Shift register unit, gate drive circuit, and display panel

Abstract

A shift register unit includes a shift register circuit, which includes a display input circuit (7) and at least two drive output circuits (5) capable of sequentially outputting display drive pulses. The drive output circuits (5) are configured to write signals provided by drive clock signal input terminals (CLKE1, CLKE2) to drive signal output terminals (OUT1, OUT2) in response to a control of an effective level signal at a pull-up node (PU). The shift register circuit also includes at least one of a first pull-up regulator circuit (VR1) and a second pull-up regulator circuit (VR2). The first pull-up regulator circuit (VR1) is connected to the pull-up node (PU), and the first pull-up regulator circuit (VR1) is configured to maintain the voltage at the pull-up node (PU) unchanged during the period when the drive output circuit (5) outputs the display drive pulse for the first output display drive pulse; the second pull-up regulator circuit (VR2) is connected to the pull-up node (PU), and the second pull-up regulator circuit (VR2) is configured to maintain the voltage at the pull-up node (PU) unchanged during the period when the drive output circuit (5) outputs the display drive pulse for the last output display drive pulse.

Description

Technical Field

[0001] This invention relates to the field of display, and in particular to a shift register unit, a gate driving circuit, and a display panel. Background Technology

[0002] The application of Active Matrix Organic Light Emitting Diode (AMOLED) panels is becoming increasingly widespread. The pixel display device of AMOLED is Organic Light-Emitting Diode (OLED). AMOLED emits light by driving thin-film transistors to generate a driving current in a saturated state, which drives the light-emitting device to emit light. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a shift register unit, comprising: a shift register circuit, the shift register circuit including:

[0004] The display input circuit is connected to the display signal input terminal and the pull-up node, and is configured to write a valid level signal to the pull-up node in response to the control of a valid level signal provided by the display signal input terminal;

[0005] At least two drive output circuits capable of sequentially outputting display drive pulses are provided. The drive output circuits are connected to the pull-up node, the drive clock signal input terminal, and the drive signal output terminal. The drive output circuits are configured to write the signal provided by the drive clock signal input terminal to the drive signal output terminal in response to the control of the effective level signal at the pull-up node.

[0006] The shift register circuit further includes at least one of a first pull-up voltage regulator circuit and a second pull-up voltage regulator circuit;

[0007] The first pull-up regulator circuit is connected to the pull-up node and is configured to maintain the voltage at the pull-up node unchanged during the period when the drive output circuit outputs the display drive pulse for the first output display drive pulse;

[0008] The second pull-up voltage regulator circuit is connected to the pull-up node and is configured to maintain the voltage at the pull-up node unchanged during the period when the drive output circuit outputs the display drive pulse for the last output display drive pulse.

[0009] In some embodiments, the first pull-up voltage regulator circuit and the second pull-up voltage regulator circuit work together to maintain the voltage at the pull-up node unchanged during the period when each drive output circuit outputs the display drive pulse.

[0010] In some embodiments, the drive output circuit includes:

[0011] The drive output sub-circuit is connected to the pull-up node, the corresponding drive clock signal input terminal, and the corresponding drive signal output terminal, and is configured to write the signal provided by the drive clock signal input terminal to the drive signal output terminal in response to the control of the effective level signal at the pull-up node.

[0012] The first end of the first capacitor is connected to the pull-up node, and the second end of the first capacitor is connected to the drive signal output terminal.

[0013] In some embodiments, during the time period when the first drive output circuit outputs a display drive pulse, m other drive output circuits sequentially start outputting display drive pulses, where m is a positive integer;

[0014] The first pull-up voltage regulator circuit includes: m first voltage regulator sub-circuits that correspond one-to-one with the drive output circuits in the m other drive output circuits;

[0015] The first voltage regulator sub-circuit is connected to the pull-up node and the corresponding first voltage regulator clock signal input terminal. The first voltage regulator sub-circuit is configured to maintain the voltage at the pull-up node unchanged when the display drive pulse output by the corresponding drive output circuit switches from the first level state to the second level state, based on the signal provided by the first voltage regulator clock signal input terminal that switches from the second level state to the first level state.

[0016] In some embodiments, the first voltage regulator sub-circuit includes: a first transmission sub-circuit and a second capacitor;

[0017] The first transmission sub-circuit is connected to the corresponding first regulated clock signal input terminal, the pull-up node and the second terminal of the second capacitor. The first transmission sub-circuit is configured to write the signal provided by the first regulated clock signal input terminal, which switches from the second level state to the first level state, to the second terminal of the second capacitor in response to the control of the effective level signal at the pull-up node when the display drive pulse output by the corresponding drive output circuit switches from the first level state to the second level state.

[0018] The first end of the second capacitor is connected to the pull-up node.

[0019] In some embodiments, the first transmission sub-circuit includes: a fifty-first transistor;

[0020] The control electrode of the fifty-first transistor is connected to the pull-up node, the first electrode of the fifty-first transistor is connected to the corresponding first regulated clock signal input terminal, and the second electrode of the fifty-first transistor is connected to the second terminal of the second capacitor.

[0021] In some embodiments, the drive output circuit includes a drive output sub-circuit and a first capacitor;

[0022] The second capacitor has the same capacitance value as the first capacitor.

[0023] In some embodiments, the shift register circuit further includes:

[0024] A pull-down control circuit, connected to a second power supply terminal, an effective level supply terminal, the pull-up node, and the pull-down node, is configured to write a voltage at the pull-down node that is inversely phase to the voltage at the pull-up node;

[0025] The first voltage regulator circuit also includes:

[0026] A first reset circuit, connected to the pull-down node, the second terminal of the second capacitor, and the fourth power supply terminal, is configured to write an invalid level signal provided by the fourth power supply terminal to the second terminal of the second capacitor in response to a valid level signal at the pull-down node.

[0027] In some embodiments, the first reset sub-circuit includes: a sixty-first transistor;

[0028] The control electrode of the sixty-first transistor is connected to the pull-down node, the first electrode of the sixty-first transistor is connected to the second terminal of the second capacitor, and the second electrode of the sixty-first transistor is connected to the second power supply terminal.

[0029] In some embodiments, during the period when the drive output circuit outputs the last display drive pulse, n other drive output circuits sequentially end the output of the display drive pulse, where n is a positive integer;

[0030] The second pull-up voltage regulator circuit includes: n second voltage regulator sub-circuits that correspond one-to-one with the drive output circuits in the n other drive output circuits;

[0031] The second voltage regulator sub-circuit is connected to the pull-up node and the corresponding second voltage regulator clock signal input terminal. The second voltage regulator sub-circuit is configured to maintain the voltage at the pull-up node unchanged when the display drive pulse output by the corresponding drive output circuit switches from the second level state to the first level state, based on the signal provided by the second voltage regulator clock signal input terminal that switches from the first level state to the second level state.

[0032] In some embodiments, the second voltage regulator sub-circuit includes: a second transmission sub-circuit and a third capacitor;

[0033] The second transmission sub-circuit is connected to the corresponding second regulated clock signal input terminal, the pull-up node and the second terminal of the third capacitor. The second transmission sub-circuit is configured to write the signal provided by the second regulated clock signal input terminal, which switches from the first level state to the second level state, to the second terminal of the third capacitor in response to the control of the effective level signal at the pull-up node when the display drive pulse output by the corresponding drive output circuit switches from the second level state to the first level state.

[0034] The first terminal of the third capacitor is connected to the pull-up node.

[0035] In some embodiments, the second transmission sub-circuit includes: a fifty-second transistor;

[0036] The control electrode of the fifty-second transistor is connected to the pull-up node, the first electrode of the fifty-second transistor is connected to the corresponding first regulated clock signal input terminal, and the second electrode of the fifty-second transistor is connected to the second terminal of the third capacitor.

[0037] In some embodiments, the drive output circuit includes a drive output sub-circuit and a first capacitor;

[0038] The third capacitor has the same capacitance value as the first capacitor.

[0039] In some embodiments, the shift register circuit further includes:

[0040] A pull-down control circuit, connected to a second power supply terminal, an effective level supply terminal, the pull-up node, and the pull-down node, is configured to write a voltage at the pull-down node that is inversely phase to the voltage at the pull-up node;

[0041] The second voltage regulator circuit also includes:

[0042] The second reset circuit is connected to the pull-down node, the second terminal of the second capacitor, and the fourth power supply terminal, and is configured to write an invalid level signal provided by the second power supply terminal to the second terminal of the second capacitor in response to the control of an effective level signal at the pull-down node.

[0043] In some embodiments, the second reset sub-circuit includes: a sixty-second transistor;

[0044] The control terminal of the sixty-second transistor is connected to the pull-down node, the first terminal of the sixty-second transistor is connected to the second terminal of the third capacitor, and the second terminal of the sixty-second transistor is connected to the second power supply terminal.

[0045] In some embodiments, the shift register further includes: at least one cascaded output circuit;

[0046] The cascaded output circuit is connected to the pull-up node, the corresponding cascaded clock signal input terminal, and the corresponding cascaded signal output terminal. The cascaded output circuit is configured to write the signal provided by the cascaded clock signal input terminal to the cascaded signal output terminal in response to the control of the pull-up node.

[0047] In some embodiments, the shift register circuit further includes:

[0048] A pull-down control circuit, connected to a second power supply terminal, an effective level supply terminal, the pull-up node, and the pull-down node, is configured to write a voltage at the pull-down node that is inversely phase to the voltage at the pull-up node;

[0049] The cascaded output circuit is also connected to the pull-down node and the second power supply terminal, and the cascaded output circuit is further configured to write an inactive level signal provided by the second power supply terminal to the cascaded signal output terminal in response to voltage control at the pull-down node.

[0050] In some embodiments, the shift register circuit further includes:

[0051] The display reset circuit is connected to the display reset signal input terminal, the second power supply terminal, and the pull-up node, and is configured to write the invalid level signal provided by the second power supply terminal to the pull-up node in response to the control of the valid level signal provided by the sensing reset signal input terminal.

[0052] The number of cascaded output circuits is two, one of which is configured to output a reset cascaded pulse, and the other is configured to output an input cascaded pulse.

[0053] In some embodiments, the cascaded output circuit configured to output the reset cascaded pulse begins outputting the reset cascaded pulse at a time earlier than the cascaded output circuit configured to output the input cascaded pulse begins outputting the input cascaded pulse.

[0054] In some embodiments, the shift register circuit further includes:

[0055] The display reset circuit is connected to the display reset signal input terminal, the second power supply terminal, and the pull-up node, and is configured to write the invalid level signal provided by the second power supply terminal to the pull-up node in response to the control of the valid level signal provided by the sensing reset signal input terminal.

[0056] A pull-down control circuit, connected to a second power supply terminal, an effective level supply terminal, the pull-up node, and the pull-down node, is configured to write a voltage at the pull-down node that is inversely phase to the voltage at the pull-up node;

[0057] The drive output sub-circuit is also connected to the pull-down node and the fourth power supply terminal, and the drive output sub-circuit is further configured to write the inactive level signal provided by the fourth power supply terminal to the drive signal output terminal in response to the control of the active level signal at the pull-down node.

[0058] In some embodiments, the number of pull-down control circuits is two, and the two pull-down control circuits are a first pull-down control circuit and a second pull-down control circuit, respectively.

[0059] The number of drop-down nodes is two, and the two drop-down nodes are the first drop-down node and the second drop-down node, respectively;

[0060] The number of effective level supply terminals is two, and the two effective level supply terminals are the first effective level supply terminal and the second effective level supply terminal, respectively.

[0061] The first pull-down control circuit is connected to the first pull-down node and the first valid level supply terminal, and the second pull-down control circuit is connected to the second pull-down node and the second valid level supply terminal;

[0062] The drive output sub-circuit is connected to both the first pull-down node and the second pull-down node. The drive output sub-circuit is configured to write the inactive level signal provided by the fourth power supply terminal to the drive signal output terminal when at least one of the first pull-down node and the second pull-down node is in an active level state.

[0063] In some embodiments, the pull-down control circuit includes: a thirty-seventh transistor, a thirty-eighth transistor, a thirty-ninth transistor, and a fortieth transistor;

[0064] The control electrode of the 37th transistor is connected to the effective level supply terminal, the first electrode of the 37th transistor is connected to the control electrode of the 37th transistor, and the second electrode of the 37th transistor is connected to the control electrode of the 38th transistor.

[0065] The control electrode of the 38th transistor is connected to the first electrode of the 40th transistor. The first electrode of the 38th transistor is connected to the effective level supply terminal. The second electrode of the 38th transistor is connected to the pull-down node.

[0066] The control terminal of the 39th transistor is connected to the pull-up node, the first terminal of the 39th transistor is connected to the pull-down node, and the second terminal of the 39th transistor is connected to the fifth power supply terminal.

[0067] The control terminal of the 40th transistor is connected to the pull-up node, and the second terminal of the 40th transistor is connected to the second power supply terminal.

[0068] In some embodiments, the pull-down control circuit further includes: a forty-first transistor, wherein the second terminal of the thirty-seventh transistor is connected to the control terminal of the thirty-eighth transistor via the forty-first transistor;

[0069] The control electrode of the forty-first transistor is connected to the control electrode of the thirty-seventh transistor, the first electrode of the forty-first transistor is connected to the second electrode of the thirty-seventh transistor, and the second electrode of the forty-first transistor is connected to the control electrode of the thirty-eighth transistor.

[0070] In some embodiments, the shift register circuit further includes: a display input auxiliary circuit, wherein the display input circuit is connected to the pull-up node through the display input auxiliary circuit, and the display input circuit and the display input auxiliary circuit are connected to a display intermediate node;

[0071] The display input auxiliary circuit is also connected to a sixth power supply terminal, a display signal input terminal, and a pull-up node. The display input auxiliary circuit is configured to write the valid level signal provided by the sixth power supply terminal to the pull-up node in response to the control of the valid level signal provided by the display signal input terminal, and to create an open circuit between the display intermediate node and the pull-up node in response to the control of the invalid level signal provided by the random signal input terminal, and to write the valid level signal provided by the sixth power supply terminal to the display intermediate node.

[0072] In some embodiments, the display input auxiliary circuit includes: a forty-second transistor and a forty-third transistor;

[0073] The control electrode of the forty-second transistor is connected to the display signal input terminal, the first electrode of the forty-second transistor is connected to the display intermediate node, and the second electrode of the forty-second transistor is connected to the pull-up node.

[0074] The control electrode of the forty-third transistor is connected to the sixth power supply terminal, the first electrode of the forty-third transistor is connected to the control electrode of the forty-third transistor, and the second electrode of the forty-third transistor is connected to the display intermediate node.

[0075] In some embodiments, the display input auxiliary circuit further includes a forty-fourth transistor, wherein the second terminal of the forty-third transistor is connected to the display intermediate node through the forty-fourth transistor;

[0076] The control electrode of the forty-fourth transistor is connected to the control electrode of the forty-third transistor, the first electrode of the forty-fourth transistor is connected to the second electrode of the forty-fourth transistor, and the second electrode of the forty-fourth transistor is connected to the display intermediate node.

[0077] In some embodiments, the shift register circuit further includes: a sensing control circuit and a sensing input circuit;

[0078] The sensing control circuit is connected to the sensing control node, the sensing signal input terminal, and the random signal input terminal. The sensing control circuit is configured to write the signal provided by the sensing signal input terminal to the sensing control node in response to the control of a valid level signal provided by the random signal input terminal.

[0079] The sensing input circuit is connected to the sensing control node, the clock control signal input terminal, the sensing intermediate node, and the pull-up node, and is configured to write a valid level signal to the sensing intermediate node in response to the control of a valid level signal at the sensing control node, and to form a path between the sensing intermediate node and the pull-up node in response to the control of a valid level signal provided by the clock control signal input terminal.

[0080] In some embodiments, the shift register circuit further includes: a sensing control leakage protection circuit;

[0081] The sensing control circuit is connected to the sensing control node through the sensing control leakage protection circuit. The sensing control leakage protection circuit is connected to the sensing control leakage protection node. The sensing control leakage protection circuit is also connected to a first power supply terminal, the sensing control node, and a random signal input terminal. The sensing control leakage protection circuit is configured to write an effective level signal provided by the first power supply terminal to the sensing control leakage protection node in response to the control of an effective level signal at the sensing control node. It is also configured to form a path between the sensing control leakage protection node and the sensing control node in response to the control of an effective level signal provided by the random signal input terminal, and to form an open circuit between the sensing control leakage protection node and the sensing control node in response to the control of an ineffective level signal provided by the random signal input terminal.

[0082] In some embodiments, the shift register circuit further includes:

[0083] A first voltage control circuit is connected to a third power supply terminal, a pull-up node, and a first voltage control node. The first voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the first voltage control node in response to the control of the effective level signal at the pull-up node.

[0084] The shift register also includes: a leakage protection circuit for sensing inputs;

[0085] The sensing input circuit is connected to the pull-up node through the sensing input leakage protection circuit. The sensing input circuit and the sensing input leakage protection circuit are connected to the sensing input leakage protection node. The sensing input leakage protection node is connected to the first voltage control node. The sensing input leakage protection node is connected to the clock control signal input terminal. The sensing input leakage protection circuit is configured to form a path between the sensing input leakage protection node and the pull-up node in response to the control of an effective level signal provided by the clock control signal input terminal, and to disconnect the circuit between the sensing input leakage protection node and the pull-up node in response to the control of an ineffective level signal provided by the clock control signal input terminal.

[0086] In some embodiments, the sensing input circuit includes:

[0087] A first input sub-circuit, connected to the sensing control node and the sensing intermediate node, is configured to write an effective level signal to the sensing intermediate node in response to the control of an effective level signal at the sensing control node.

[0088] The second input sub-circuit is connected to the sensing intermediate node and the clock control signal input terminal, and is configured to form a path between the sensing intermediate node and the pull-up node in response to the control of the valid level signal provided by the clock control signal input terminal.

[0089] The shift register unit includes two shift register circuits, and the two shift register circuits share the same sensing control circuit and the same first input sub-circuit.

[0090] In some embodiments, the shift register circuit further includes:

[0091] The display reset circuit is connected to the display reset signal input terminal, the second power supply terminal, and the pull-up node, and is configured to write the invalid level signal provided by the second power supply terminal to the pull-up node in response to the control of the valid level signal provided by the sensing reset signal input terminal.

[0092] A pull-down control circuit, connected to a second power supply terminal, an effective level supply terminal, the pull-up node, and the pull-down node, is configured to write a voltage at the pull-down node that is inversely phase to the voltage at the pull-up node;

[0093] A pull-up noise reduction circuit is connected to the second power supply terminal, the pull-up node, and the pull-down node, and is configured to write an invalid level signal provided by the second power supply terminal to the pull-up node in response to the control of an effective level signal at the pull-down node.

[0094] A global reset circuit, connected to a global reset signal input terminal, a second power supply terminal, and the pull-up node, is configured to write an invalid level signal provided by the second power supply terminal to the pull-up node in response to a valid level signal provided by the global reset signal input terminal.

[0095] The drive output sub-circuit is also connected to the pull-down node and the fourth power supply terminal, and the drive output sub-circuit is further configured to write the inactive level signal provided by the fourth power supply terminal to the drive signal output terminal in response to the control of the active level signal at the pull-down node.

[0096] In some embodiments, the shift register circuit further includes:

[0097] A first voltage control circuit is connected to a third power supply terminal, a pull-up node, and a first voltage control node. The first voltage control circuit is configured to write an effective level signal provided by the third power supply terminal to the first voltage control node in response to the control of an effective level signal at the pull-up node.

[0098] The shift register unit further includes at least one of a first leakage protection circuit, a second leakage protection circuit, and a third leakage protection circuit;

[0099] The global reset circuit is connected to the second power supply terminal through the first leakage protection circuit. The global reset circuit and the first leakage protection circuit are connected to the first leakage protection node. The first leakage protection node is connected to the first voltage control node. The first leakage protection circuit is connected to the global reset signal input terminal. The first leakage protection circuit is configured to form a path between the first leakage protection node and the second power supply terminal in response to the control of the valid level signal provided by the global reset signal input terminal, and to disconnect the circuit between the first leakage protection node and the second power supply terminal in response to the control of the invalid level signal provided by the global reset signal input terminal.

[0100] The display reset circuit is connected to the second power supply terminal through the second leakage protection circuit. The display reset circuit and the second leakage protection circuit are connected to the second leakage protection node. The second leakage protection node is connected to the first voltage control node. The second leakage protection circuit is connected to the display reset signal input terminal. The second leakage protection circuit is configured to form a path between the second leakage protection node and the second power supply terminal in response to the control of an effective level signal provided by the display reset signal input terminal, and to disconnect the circuit between the second leakage protection node and the second power supply terminal in response to the control of an ineffective level signal provided by the display reset signal input terminal.

[0101] The pull-up noise reduction circuit is connected to the second power supply terminal through the third leakage protection circuit. The pull-up noise reduction circuit and the third leakage protection circuit are connected to the third leakage protection node. The third leakage protection node is connected to the first voltage control node. The third leakage protection circuit is connected to the pull-down node. The third leakage protection circuit is configured to form a path between the third leakage protection node and the second power supply terminal in response to the control of an effective level signal at the pull-down node, and to disconnect the circuit between the third leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the pull-down node.

[0102] In a second aspect, embodiments of this disclosure provide a gate driving circuit, comprising: a plurality of shift register units as provided in the first aspect, wherein the plurality of shift register circuits included in the plurality of shift register units are cascaded.

[0103] In some embodiments, the shift register unit is the shift register unit of claim 3, and the gate drive circuit further includes: multiple clock supply signal lines capable of sequentially providing clock pulses;

[0104] The drive clock signal input terminal of the drive output circuit is connected to the corresponding clock supply signal line.

[0105] The first voltage regulator clock signal input terminal of the first voltage regulator sub-circuit is connected to the corresponding clock supply signal line;

[0106] The second voltage regulator sub-circuit's second voltage regulator clock signal input terminal is connected to the corresponding clock supply signal line.

[0107] Thirdly, embodiments of this disclosure provide a display panel, comprising: a substrate and a gate driving circuit located on the substrate, wherein the gate driving circuit employs the gate driving circuit provided in the second aspect. Attached Figure Description

[0108] Figure 1 This is a schematic diagram of the pixel circuitry within an organic light-emitting diode (OLED) display panel.

[0109] Figure 2 for Figure 1 The diagram shows a timing sequence of one type of pixel circuit.

[0110] Figure 3 This is a schematic diagram of a circuit structure for a shift register unit involved in related technologies;

[0111] Figure 4 This is a timing diagram of a shift register involved in related technologies.

[0112] Figure 5 A schematic diagram of a circuit structure for a shift register unit provided in an embodiment of this disclosure;

[0113] Figure 6A A schematic diagram of another circuit structure for a shift register unit provided in an embodiment of this disclosure;

[0114] Figure 6B for Figure 6A The diagram shows a timing diagram of one type of shift register unit.

[0115] Figure 7A A schematic diagram of another circuit structure for a shift register unit provided in an embodiment of this disclosure;

[0116] Figure 7B for Figure 7A The diagram shows a timing diagram of one type of shift register unit.

[0117] Figure 8A A schematic diagram of another circuit structure for a shift register unit provided in an embodiment of this disclosure;

[0118] Figure 8B for Figure 8A The diagram shows a timing diagram of one type of shift register unit.

[0119] Figure 9 This is a schematic diagram of a circuit structure when the pull-up voltage regulator circuit in the shift register circuit of this disclosure only includes the first voltage regulator sub-circuit;

[0120] Figure 10 This is a schematic diagram of a circuit structure in an embodiment of the present disclosure where the pull-up voltage regulator circuit in the shift register circuit includes only the second voltage regulator sub-circuit.

[0121] Figure 11 This is a schematic diagram of another circuit structure of the shift register unit in the embodiments of this disclosure;

[0122] Figure 12 This is a schematic diagram of another circuit structure of the shift register unit in the embodiments of this disclosure;

[0123] Figure 13 for Figure 12 The diagram shows a timing diagram of one type of shift register unit.

[0124] Figure 14 This is a schematic diagram of another circuit structure of the shift register unit in the embodiments of this disclosure;

[0125] Figure 15 This is a schematic diagram of another circuit structure of the shift register unit in the embodiments of this disclosure;

[0126] Figure 16This is a timing diagram of one of the two effective level supply terminals in an embodiment of this disclosure;

[0127] Figure 17 This is a schematic diagram of another circuit structure of the shift register unit in the embodiments of this disclosure;

[0128] Figure 18 This is a schematic diagram of another circuit structure of the shift register unit in the embodiments of this disclosure;

[0129] Figure 19 This is a schematic diagram of another circuit structure of the shift register unit in the embodiments of this disclosure;

[0130] Figure 20 This is a schematic diagram of another circuit structure of the shift register unit in the embodiments of this disclosure;

[0131] Figure 21 This is a schematic diagram of another circuit structure of the shift register unit in the embodiments of this disclosure;

[0132] Figure 22 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0133] Figure 23 A schematic diagram of a circuit structure for a gate driving circuit provided in an embodiment of this disclosure;

[0134] Figure 24 for Figure 23 The diagram shows a timing diagram of one type of gate drive circuit. Detailed Implementation

[0135] To enable those skilled in the art to better understand the technical solution of the present invention, a shift register unit, gate driving circuit, and gate driving method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0136] The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0137] The transistors used in this embodiment can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In this embodiment, the coupling methods of the drain and source of each transistor are interchangeable; therefore, the drain and source of each transistor in this embodiment are actually indistinguishable. Here, one of the two terminals of the transistor (excluding the control terminal, i.e., the gate) is called the drain, and the other is called the source, simply to distinguish them. The thin-film transistors used in this embodiment can be N-type transistors or P-type transistors. In this embodiment, when an N-type thin-film transistor is used, its first terminal can be the source, and its second terminal can be the drain.

[0138] In this disclosure, "effective level signal" refers to a signal that, when input to the gate electrode of a transistor, can control the transistor to conduct, and "ineffective level signal" refers to a signal that, when input to the gate electrode of a transistor, can control the transistor to cut off. For N-type transistors, a high-level signal is an effective level signal, and a low-level signal is an ineffective level signal; for P-type transistors, a low-level signal is an effective level signal, and a high-level signal is an ineffective level signal.

[0139] In the following description, an N-type transistor will be used as an example. In this case, the active level signal refers to a high-level signal, and the inactive level signal refers to a low-level signal. It is conceivable that when using a P-type transistor, the timing of the control signal needs to be adjusted accordingly. Specific details are not elaborated here, but should be within the scope of this disclosure.

[0140] Figure 1 This is a schematic diagram of the pixel circuitry within an organic light-emitting diode (OLED) display panel. Figure 2 for Figure 1 The diagram shows a timing diagram of one type of pixel circuit. Figure 1 and Figure 2 As shown, for an organic light-emitting diode display panel with external compensation function, a frame can be divided into two stages: the display driving stage and the sensing stage. In the display driving stage, each row of pixel units in the display panel completes the display driving. In the sensing stage, a certain row of pixel units in the display panel completes current extraction (i.e., sensing).

[0141] See Figure 1 As shown, the pixel circuit includes a display switching transistor QTFT (with its control electrode connected to the first gate line G1), a driving transistor DTFT, a sensing switching transistor STFT (with its control electrode connected to the second gate line G2), and a Cst. When external compensation is required for the pixel circuit, the pixel circuit includes at least the following two stages during operation: a display driving stage (including the data voltage writing process) and a sensing driving stage (including the current reading process).

[0142] During the display driving phase, the data voltage Vdata in the data line Data needs to be written to the pixel unit. During the sensing driving phase, a test voltage Vsence needs to be written to the pixel unit via the data line Data, and the electrical signal at the drain of the driving transistor is read to the signal readout line Sence via the sensing switch transistor STFT. During the current readout process, an effective level voltage needs to be written to the gate of the sensing switch transistor STFT via the corresponding second gate line G2. It should be noted that external compensation is performed on the pixel units in the OLED display panel; the specific compensation process and principle are not detailed here.

[0143] For the first gate line G1 used to control the display switching transistor QTFT and the second gate line G2 used to control the sensing switching transistor STFT, corresponding gate driving circuits are respectively configured in the peripheral area of ​​the display panel. The gate driving circuit includes multiple cascaded shift register units, which can provide driving signals to the corresponding gate lines.

[0144] Figure 3 This is a schematic diagram of a circuit structure for a shift register unit involved in related technologies. Figure 4 This is a timing diagram for a shift register involved in related technologies. For example... Figure 3 and Figure 4 As shown, the shift register unit includes a shift register circuit, which includes a preamp circuit and a drive output circuit. Both the preamp circuit and the drive output circuit are connected to the pull-up node. The preamp circuit can be used to control the voltage at the pull-up node. The drive output circuit includes a drive output sub-circuit 501 and a first capacitor C1. The first end of the first capacitor C1 is connected to the pull-up node PU, and the second end of the first capacitor C1 is connected to the corresponding drive signal output terminals OUT1 to OUT4. The drive output sub-circuit 501 includes an output transistor (not shown). The control electrode of the output transistor is connected to the pull-up node. When the voltage at the pull-up node is at an effective level, the output transistor writes the signal provided by the drive clock signal input terminal to the drive signal output terminals OUT1 to OUT4. The drive signal output terminals OUT1 to OUT4 can output corresponding drive pulses.

[0145] In related technologies, to reduce the overall space occupied by the gate drive circuit, at least two drive output circuits 5 are set in a shift register circuit. In this case, one shift register circuit can provide drive pulses for two or more gate lines. Therefore, the number of shift register circuits required in the gate drive circuit is reduced, thereby achieving the goal of reducing the overall space occupied by the gate drive circuit. See also Figure 3 As shown, Figure 3The example diagram shows a shift register circuit that includes four drive output circuits 5 and four corresponding drive signal output terminals OUT1 to OUT4.

[0146] See Figure 4 As shown, in order to ensure that the data voltage in the pixel circuit can be written accurately, the display drive pulse output by the shift register circuit needs to have a certain pulse width. At the same time, in order to ensure that all row pixel circuits can be driven within one frame, there will be some overlap between adjacent display drive pulses.

[0147] by Figure 4 As shown in the example, the four drive signal output terminals OUT1 to OUT4 output display drive pulses in sequence, and the display drive pulses output by two adjacent drive signal output terminals overlap. Figure 4 The example shows a case where the overlap ratio (the ratio of the width of the overlap portion to the pulse width of a single display drive pulse) of 50% between adjacent display drive pulses.

[0148] When the drive signal output terminals OUT1 to OUT4 output the rising and falling edges of the drive pulse, the bootstrap effect of the first capacitor C1 will have a certain impact on the voltage at the pull-up node PU. Figure 4 The situation shown in the figure is an example.

[0149] When the rising edge of the drive pulse is displayed at the first drive signal output terminal OUT1, the first capacitor C1 connected to the first drive signal output terminal OUT1 will pull up the voltage at the pull-up node PU, so that the voltage at the pull-up node PU rises.

[0150] When the rising edge of the drive pulse is displayed at the second drive signal output terminal OUT2, the first capacitor C1 connected to the second drive signal output terminal OUT2 will pull up the voltage at the pull-up node PU, so that the voltage at the pull-up node PU will rise further.

[0151] When the falling edge of the display drive pulse is output at the first drive signal output terminal OUT1, the rising edge of the display drive pulse is output synchronously at the third drive signal output terminal OUT3. The first capacitor C1 connected to the first drive signal output terminal OUT1 will pull down the voltage at the pull-up node PU, and the first capacitor C1 connected to the third drive signal output terminal OUT3 will pull up the voltage at the pull-up node PU. At this time, the voltage at the pull-up node PU remains unchanged.

[0152] When the falling edge of the display drive pulse is output at the second drive signal output terminal OUT2, the rising edge of the display drive pulse is output simultaneously at the fourth drive signal output terminal OUT4. The first capacitor C1 connected to the second drive signal output terminal OUT2 will pull down the voltage at the pull-up node PU, and the first capacitor C1 connected to the fourth drive signal output terminal OUT4 will pull up the voltage at the pull-up node PU. At this time, the voltage at the pull-up node PU remains unchanged.

[0153] When the falling edge of the drive pulse is displayed at the third drive signal output terminal OUT3, the first capacitor C1 connected to the third drive signal output terminal OUT3 will pull down the voltage at the pull-up node PU, so that the voltage at the pull-up node PU decreases.

[0154] When the falling edge of the drive pulse is displayed at the fourth drive signal output terminal OUT4, the first capacitor C1 connected to the fourth drive signal output terminal OUT will pull down the voltage at the pull-up node PU, so that the voltage at the pull-up node PU decreases.

[0155] pass Figure 4 As can be seen, during the period when the first drive signal output terminal OUT1 outputs and displays the drive pulse, the voltage at the pull-up node PU experiences one rising jump. During the period when the second drive signal output terminal OUT2 outputs and displays the drive pulse, the voltage at the pull-up node PU remains unchanged (equal to the voltage at the pull-up node PU during the latter half of the period when the first drive signal output terminal OUT1 outputs and displays the drive pulse). During the period when the third drive signal output terminal OUT3 outputs and displays the drive pulse, the voltage at the pull-up node PU remains unchanged (equal to the voltage at the pull-up node PU during the latter half of the period when the first drive signal output terminal OUT1 outputs and displays the drive pulse). During the period when the fourth drive signal output terminal OUT4 outputs and displays the drive pulse, the voltage at the pull-up node PU experiences one falling jump. Therefore, it can be seen that the voltage at the pull-up node PU when the second drive signal output terminal OUT2 outputs the drive pulse is the same as the voltage at the pull-up node PU when the third drive signal output terminal OUT3 outputs the drive pulse; however, the voltage at the pull-up node PU when the first drive signal output terminal OUT1 outputs the drive pulse and the voltage at the pull-up node PU when the fourth drive signal output terminal OUT4 outputs the drive pulse are different from the voltage at the pull-up node PU when the second (third) drive signal output terminals OUT2 and OUT3 output the drive pulse.

[0156] Furthermore, because the voltage at the pull-up node directly affects the actual waveform of the display drive pulses output by each drive signal output terminal OUT1 to OUT4, the actual waveform of the display drive pulse output by the second drive signal output terminal OUT2 is the same as that output by the third drive signal output terminal OUT3. However, the actual waveform of the display drive pulse output by the first drive signal output terminal OUT1 is different from that output by the second (third) drive signal output terminals OUT2 and OUT3, and the actual waveform of the display drive pulse output by the fourth drive signal output terminal OUT4 is different from that output by the second (third) drive signal output terminals OUT2 and OUT3. In other words, there is a problem that different drive output circuits within the same shift register circuit output different waveforms of the display drive pulses. These differences in the display drive pulse waveforms lead to variations in the driving process of the pixel circuits, ultimately resulting in "horizontal stripes" appearing on the display panel.

[0157] In practical applications, it has been found that the actual waveform of the display drive pulse output by the first output display drive pulse in the shift register circuit is different from the actual waveform of the display drive pulse output by other drive output circuits, and the actual waveform of the display drive pulse output by the last output display drive pulse in the bit register circuit is different from the actual waveform of the display drive pulse output by other drive output circuits.

[0158] Specifically, when there are two drive output circuits in the shift register circuit, the actual waveforms of the display drive pulses output by the two drive output circuits are different; when there are N drive output circuits in the shift register circuit and N is an integer greater than 2, the actual waveform of the display drive pulse output by the first drive output circuit that outputs the display drive pulse is different from the actual waveforms of the display drive pulses output by the second to Nth drive output circuits, and the actual waveform of the display drive pulse output by the Nth (last) drive output circuit that outputs the display drive pulse is different from the actual waveforms of the display drive pulses output by the first to N-1th drive output circuits.

[0159] Research and analysis revealed that the main cause of the above problem is that, in order to satisfy the requirement of partial overlap between adjacent display drive pulses, during the period when the drive output circuit of the first display drive pulse outputs the display drive pulse, other drive output circuits (e.g., the drive output circuit of the second display drive pulse output) begin to output display drive pulses (e.g., the rising edge of the display drive pulse), and the voltage at the pull-up node changes due to the bootstrap effect of the first capacitor; that is, during the period when the drive output circuit of the first display drive pulse outputs the display drive pulse, the pull-up node will jump, and the aforementioned jump in voltage at the pull-up node will cause the actual waveform of the display drive pulse output by the drive output circuit of the first display drive pulse to be different from the actual waveform of the display drive pulse output by other drive output circuits.

[0160] Similarly, during the period when the last output display drive pulse is output by the drive output circuit of the last output display drive pulse, other drive output circuits (e.g., the drive output circuit of the penultimate output display drive pulse) complete the output of display drive pulses (e.g., the falling edge of the output display drive pulse), and the voltage at the pull-up node changes through the bootstrap effect of the first capacitor; that is, during the period when the last output display drive pulse is output by the drive output circuit of the last output display drive pulse, the pull-up node will jump, and the aforementioned jump in voltage at the pull-up node will cause the actual waveform of the display drive pulse output by the drive output circuit of the last output display drive pulse to be different from the actual waveform of the display drive pulse output by other drive output circuits.

[0161] To effectively improve the technical problems existing in related technologies, such as the actual waveform of the display drive pulse output by the first output display drive pulse drive circuit in the shift register circuit being different from the actual waveform of the display drive pulse output by other drive output circuits, and / or the actual waveform of the display drive pulse output by the last output display drive pulse drive circuit in the shift register circuit being different from the actual waveform of the display drive pulse output by other drive output circuits, this disclosure provides a new shift register unit.

[0162] Figure 5 This is a schematic diagram of a circuit structure for a shift register unit provided in an embodiment of this disclosure. Figure 5 As shown, the shift register unit includes a shift register circuit, which includes: a display input circuit 7 and at least two drive output circuits 5.

[0163] The display input circuit 7 is connected to the display signal input terminal INPUT1 and the pull-up node PU. The display input circuit 7 is configured to write the valid level signal to the pull-up node PU in response to the control of the valid level signal provided by the display signal input terminal INPUT1.

[0164] The drive output circuit 501 is connected to the pull-up node PU, the corresponding drive clock signal input terminals CLKE1 and CLKE2, and the corresponding drive signal output terminals OUT1 and OUT2. The drive output circuit 501 is configured to write the signals provided by the drive clock signal input terminals CLKE1 and CLKE2 to the drive signal output terminals OUT1 and OUT2 in response to the control of the effective level signal at the pull-up node PU.

[0165] In some embodiments, the drive output circuit 5 includes a drive output sub-circuit 501 and a first capacitor C1. The drive output sub-circuit 501 is connected to a pull-up node PU, corresponding drive clock signal input terminals CLKE1 and CLKE2, and corresponding drive signal output terminals OUT1 and OUT2. The drive output circuit 501 is configured to write the signals provided by the drive clock signal input terminals CLKE1 and CLKE2 to the drive signal output terminals OUT1 and OUT2 in response to a valid level signal at the pull-up node PU. The first end of the first capacitor C1 is connected to the pull-up node PU, and the second end of the first capacitor C1 is connected to the corresponding drive signal output terminals OUT1 and OUT2.

[0166] It should be noted that the above-mentioned at least two drive output circuits 5 in the shift register circuit can output display drive pulses sequentially, and there is partial overlap between adjacent display drive pulses. The overlap ratio of adjacent display drive pulses can be pre-designed according to actual needs.

[0167] In this embodiment of the present disclosure, the shift register circuit further includes at least one of a first pull-up voltage regulator circuit VR1 and a second pull-up voltage regulator circuit VR2.

[0168] The first pull-up voltage regulator circuit VR1 is connected to the pull-up node PU. The first pull-up voltage regulator circuit VR1 is configured to maintain the voltage at the pull-up node PU unchanged during the period when the drive output circuit 5 outputs the first output display drive pulse.

[0169] The second pull-up regulator circuit VR2 is connected to the pull-up node PU. The second pull-up regulator circuit VR2 is configured to maintain the voltage at the pull-up node PU unchanged during the period when the drive output circuit 5 outputs the display drive pulse for the last output display drive pulse.

[0170] Taking a shift register circuit including a first pull-up voltage regulator circuit VR1 as an example, by setting the first pull-up voltage regulator circuit VR1, the voltage at the pull-up node PU is kept constant during the period when the drive output circuit 5 outputs the first display drive pulse. This solves the technical problem in the related technology that the actual waveform of the display drive pulse output by the drive output circuit 5 outputting the first display drive pulse is different from the actual waveform of the display drive pulse output by other drive output circuits 5 due to the voltage change at the pull-up node PU.

[0171] Similarly, when the shift register circuit includes a second pull-up voltage regulator circuit VR2, it can solve the technical problem in the related technology that the actual waveform of the display drive pulse output by the drive output circuit 5 of the last output display drive pulse is different from the actual waveform of the display drive pulse output by other drive output circuits 5 due to the voltage change at the pull-up node PU.

[0172] In some embodiments, when the shift register circuit includes both a first pull-up voltage regulator circuit VR1 and a second pull-up voltage regulator circuit VR2, the first pull-up voltage regulator circuit VR1 and the second pull-up voltage regulator circuit VR2 are jointly configured to maintain a constant voltage at the pull-up node PU during the period when each drive output circuit 5 outputs a display drive pulse. That is, during the period from the start of the first output display drive pulse from the drive output circuit 5 to the end of the last output display drive pulse from the drive output circuit 5, the voltage at the pull-up node PU can be maintained constant by the first voltage regulator circuit VR1 and the second voltage regulator circuit VR2, thereby ensuring that the actual waveforms of the display drive pulses output by each drive output circuit 5 are the same, and thus effectively solving the "horizontal stripe" problem caused by the waveform difference of the display drive pulses.

[0173] In some embodiments, the drive output sub-circuit 501 includes: a fifth transistor M5; the control electrode of the fifth transistor M5 is connected to the pull-up node PU, the first electrode of the fifth transistor M5 is connected to the corresponding drive clock signal input terminals CLKE1 and CLKE2, and the second electrode of the fifth transistor M5 is connected to the corresponding drive signal output terminals OUT1 and OUT2.

[0174] When the voltage at the pull-up node PU is at an effective level, the fifth transistor M5 is turned on, and the signals provided by the drive clock signal input terminals CLKE1 and CLKE2 are written to the corresponding drive signal output terminals OUT1 and OUT2, so that the drive signal output terminals OUT1 and OUT2 output display drive pulses; when the voltage at the pull-up node PU is at an ineffective level, the fifth transistor M5 is turned off.

[0175] Figure 6AThis is a schematic diagram of another circuit structure for a shift register unit provided in an embodiment of this disclosure. Figure 6B for Figure 6A The diagram shows a timing diagram of one type of shift register unit. Figure 6A and Figure 6B As shown, Figure 6A and Figure 6B The example given is a shift register circuit that includes two drive output circuits 5.

[0176] In some embodiments, during the time period when the first drive output circuit 5 outputs a display drive pulse, m other drive output circuits 5 sequentially start outputting display drive pulses, where m is a positive integer (m is a positive integer). Figure 6A and Figure 6B (The example given is the case where m=1); the first pull-up voltage regulator circuit VR1 includes: m first voltage regulator sub-circuits 9a corresponding one-to-one with the drive output circuits 5 in the m other drive output circuits 5; the first voltage regulator sub-circuits 9a are connected to the pull-up node PU and the corresponding first voltage regulator clock signal input terminal, and the first voltage regulator sub-circuit 9a is configured to maintain the voltage at the pull-up node PU unchanged when the display drive pulse output by the corresponding drive output circuit 5 switches from the first level state to the second level state according to the signal provided by the first voltage regulator clock signal input terminal to switch from the second level state to the first level state.

[0177] In this embodiment of the disclosure, one of the first level state and the second level state is a high level state and the other is a low level state; in the following description, the example of the pulse having a low level state as the first level state and a high level state as the second level state is used for exemplary description.

[0178] In the relevant technology, during the period when the first output display drive pulse is output by the drive output circuit 5, m other drive output circuits 5 start to output display drive pulses, that is, the rising edge of the output display drive pulse of the other m drive output circuits 5 (switching from the first level state to the second level state) is affected by the bootstrap effect of the first capacitor C1, which will cause the voltage at the pull-up node PU to rise.

[0179] In this disclosure, to prevent the voltage at the pull-up node PU from rising due to the rising edges of the outputs of the m drive output circuits 5, m first voltage regulator sub-circuits 9a, each corresponding to one of the m other drive output circuits 5, are provided in the shift register circuit. The first voltage regulator sub-circuit 9a can cancel the pull-up effect of the rising edges of the corresponding drive output circuits 5 in the m other drive output circuits 5, based on a falling edge signal (a signal that switches from the second level state to the first level state) provided by the first voltage regulator clock signal input terminal CLKF, so as to keep the voltage at the pull-up node PU constant.

[0180] In some embodiments, the first voltage regulator sub-circuit 9a includes: a first transmission sub-circuit 901 and a second capacitor C2; the first transmission sub-circuit 901 is connected to the corresponding first voltage regulator clock signal input terminal CLKF, the pull-up node PU, and the second terminal of the second capacitor C2; the first transmission sub-circuit 901 is configured to write the signal provided by the first voltage regulator clock signal input terminal CLKF, which switches from the second level state to the first level state, to the second terminal of the second capacitor C2 in response to the control of the effective level signal at the pull-up node PU when the display drive pulse output by the corresponding drive output circuit 5 switches from the first level state to the second level state; the first terminal of the second capacitor C2 is connected to the pull-up node PU.

[0181] When a rising edge is output from one of the m driving output circuits 5, causing the corresponding first capacitor C1 to pull up the voltage at the pull-up node PU, the corresponding first transmission sub-circuit 901 can be controlled to output a falling edge to the second terminal of the second capacitor C2, so as to pull down the voltage at the pull-up node PU based on the bootstrap effect of the second capacitor C2, thereby canceling the aforementioned pull-up effect and keeping the voltage at the pull-up node PU unchanged.

[0182] Therefore, the waveform provided by the first regulated clock signal input terminal CLKF connected to the first voltage regulator sub-circuit 9a can be designed according to the rising edge of the output of the above m driving output circuits 5, so as to ensure that the voltage at the pull-up node PU remains unchanged.

[0183] In some embodiments, the capacitance value of the second capacitor C2 is equal to that of the first capacitor C1. In this case, the voltage change at the falling edge output by the first voltage regulator sub-circuit 9a can be equal to the voltage change at the rising edge output by the drive output circuit 5. Therefore, the waveform of the pulse provided by the first voltage regulator clock signal input terminal CLKF to the first voltage regulator sub-circuit 9a can be the same as the waveform of the pulse provided by the drive clock signal input terminals CLKE1 and CLKE2 to the drive output circuit 5; that is, the first voltage regulator clock signal input terminal CLKF and the drive clock signal input terminals CLKE1 and CLKE2 can be connected to the same set of clock supply signal lines, thereby reducing the number of signal lines required for the gate drive circuit. See the following description for details.

[0184] In some embodiments, the first transmission sub-circuit 901 includes: a fifty-first transistor M51; the control electrode of the fifty-first transistor M51 is connected to the pull-up node PU, the first electrode of the fifty-first transistor M51 is connected to the corresponding first regulated clock signal input terminal CLKF, and the second electrode of the fifty-first transistor M51 is connected to the second terminal of the second capacitor C2.

[0185] See Figure 6B As shown, during the period when the drive output circuit 5 outputs the first output display drive pulse, the voltage at the pull-up node PU remains unchanged.

[0186] In some embodiments, during the period when the last output display drive pulse is output by the drive output circuit 5, n other drive output circuits 5 sequentially end their output display drive pulses, where n is a positive integer ( Figure 6A and Figure 6B (The example given is the case where n=1); the second pull-up voltage regulator circuit VR2 includes: n second voltage regulator sub-circuits 9b corresponding one-to-one with the drive output circuits 5 in the n other drive output circuits 5; the second voltage regulator sub-circuits 9b are connected to the pull-up node PU and the corresponding second voltage regulator clock signal input terminal CLKG, and the second voltage regulator sub-circuit 9b is configured to maintain the voltage at the pull-up node PU unchanged when the display drive pulse output by the corresponding drive output circuit 5 switches from the second level state to the first level state according to the signal provided by the second voltage regulator clock signal input terminal CLKG to switch from the first level state to the second level state.

[0187] In the relevant technology, during the period when the last output display drive pulse is output by the drive output circuit 5, n other drive output circuits 5 end to output display drive pulses. That is, the falling edge of the output display drive pulse of the other n drive output circuits 5 (switching from the second level state to the first level state) is affected by the bootstrap effect of the first capacitor C1, which will cause the voltage at the pull-up node PU to drop.

[0188] In this disclosure, to prevent the voltage at the pull-up node PU from dropping due to the falling edge output of the n drive output circuits 5, n second voltage regulator sub-circuits 9b corresponding one-to-one with the n other drive output circuits 5 are provided in the shift register circuit. The second voltage regulator sub-circuit 9b can cancel the pull-down effect of the falling edge output of the corresponding drive output circuit 5 in the n other drive output circuits 5 according to a rising edge signal (signal switching from the first level state to the second level state) provided by the second voltage regulation clock signal input terminal CLKG, so as to maintain the voltage at the pull-up node PU unchanged.

[0189] Therefore, the waveform provided by the second voltage regulator clock signal input terminal CLKG connected to the second voltage regulator sub-circuit 9b can be designed according to the falling edge of the n drive output circuits 5 above, so as to ensure that the voltage at the pull-up node PU remains unchanged.

[0190] In some embodiments, the second voltage regulator sub-circuit 9b includes: a second transmission sub-circuit 902 and a third capacitor C3; the second transmission sub-circuit 902 is connected to the corresponding second voltage regulator clock signal input terminal CLKG, the pull-up node PU, and the second terminal of the third capacitor C3; the second transmission sub-circuit 902 is configured to, in response to the control of the effective level signal at the pull-up node PU, write the signal provided by the second voltage regulator clock signal input terminal from the first level state to the second level state to the second terminal of the third capacitor C3 when the display drive pulse output by the corresponding drive output circuit 5 switches from the second level state to the first level state; the first terminal of the third capacitor C3 is connected to the pull-up node PU.

[0191] When a falling edge is output from one of the n drive output circuits 5, causing the corresponding first capacitor C1 to pull down the voltage at the pull-up node PU, the corresponding second transmission sub-circuit 902 can be controlled to output a rising edge to the second terminal of the third capacitor C3, so as to pull up the voltage at the pull-up node PU based on the bootstrap effect of the second capacitor C2, thereby canceling the aforementioned pull-down effect and keeping the voltage at the pull-up node PU unchanged.

[0192] In some embodiments, the capacitance value of the third capacitor C3 is equal to that of the first capacitor C1. In this case, the voltage change at the rising edge output by the second voltage regulator sub-circuit 9b can be equal to the voltage change at the falling edge output by the drive output circuit 5. Therefore, the waveform of the pulse provided by the second voltage regulator clock signal input terminal CLKG to the second voltage regulator sub-circuit 9b can be the same as the waveform of the pulse provided by the drive clock signal input terminals CLKE1 and CLKE2 to the drive output circuit 5; that is, the second voltage regulator clock signal input terminal CLKG and the drive clock signal input terminals CLKE1 and CLKE2 can be connected to the same set of clock supply signal lines, thereby reducing the number of signal lines required for the gate drive circuit. See the following description for details.

[0193] In some embodiments, the second transmission sub-circuit 902 includes: a fifty-second transistor M52; the control terminal of the fifty-second transistor M52 is connected to the pull-up node PU, the first terminal of the fifty-second transistor M52 is connected to the corresponding first regulated clock signal input terminal CLKF, and the second terminal of the fifty-second transistor M52 is connected to the second terminal of the third capacitor C3.

[0194] See Figure 6B As shown, the voltage at the pull-up node PU remains unchanged during the period when the drive output circuit 5 outputs the last output drive pulse.

[0195] See also Figure 6B As shown, when the voltage at the pull-up node PU remains constant during the time period when the drive output circuit 5 outputs the first display drive pulse, and the voltage at the pull-up node PU remains constant during the time period when the drive output circuit 5 outputs the last display drive pulse, then the voltage at the pull-up node PU remains constant during the time period when each drive output circuit 5 outputs the display drive pulse. That is, from the time period when the drive output circuit 5 starts outputting the display drive pulse to the time period when the drive output circuit 5 ends outputting the last display drive pulse, the voltage at the pull-up node PU remains constant, and each drive output circuit 5 can sequentially output display drive pulses with the same waveform.

[0196] Figure 7A This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure. Figure 7B for Figure 7A The diagram shows a timing diagram of one type of shift register unit. Figure 7A and Figure 7B As shown, Figure 7A and Figure 7B The example given is a shift register circuit with four drive output circuits 5, where m=1 and n=1.

[0197] Figure 8B for Figure 8A The diagram shows a timing diagram of one type of shift register unit. Figure 8A and Figure 8B As shown, Figure 8A and Figure 8B The example shown illustrates a shift register circuit comprising four drive output circuits 5, with m=2 and n=2. In this case, the overlap rate of adjacent display drive pulses is approximately 66.7%.

[0198] It should be noted that the technical solution disclosed herein does not limit the number (greater than 1) of the drive output circuits 5 in the shift register circuit, the value of m, or the value of n.

[0199] Figures 6A to 8A The diagram illustrates, by way of example, a shift register circuit that includes both a first voltage regulator circuit 9a (first pull-up voltage regulator circuit VR1) and a second voltage regulator circuit 9b (second pull-up voltage regulator circuit VR2). This is only a preferred embodiment of the present disclosure.

[0200] Figure 9 This is a schematic diagram of a circuit structure in an embodiment of the present disclosure where the pull-up regulator circuit within the shift register circuit includes only the first regulator sub-circuit. For example... Figure 9 As shown, in some embodiments, the shift register circuit may also include only the first voltage regulator circuit 9a (first pull-up voltage regulator circuit VR1). In this case, the shift register circuit has the function of maintaining the voltage at the pull-up node PU unchanged during the period when the drive output circuit 5 outputs the first output display drive pulse, which can improve the "horizontal stripe" problem to a certain extent.

[0201] Figure 10 This is a schematic diagram of a circuit structure in an embodiment of the present disclosure where the pull-up voltage regulator circuit within the shift register circuit includes only the second voltage regulator sub-circuit. For example... Figure 10 As shown, in some embodiments, the shift register circuit may also include only the second voltage regulator circuit 9b (second pull-up voltage regulator circuit VR2). In this case, the shift register circuit has the function of maintaining the voltage at the pull-up node PU unchanged during the period when the drive output circuit 5 outputs the display drive pulse of the last output display drive pulse, which can improve the "horizontal stripe" problem to a certain extent.

[0202] In practical applications, the falling edge waveform of the display drive pulse is more important. Therefore, the shift register circuit in this disclosure preferably includes at least a second pull-up voltage regulator circuit VR2.

[0203] In the following embodiments, an example is provided, which includes a shift register circuit comprising four drive output circuits 5, a first pull-up voltage regulator circuit (including a first voltage regulator sub-circuit 9a), and a second pull-up voltage regulator circuit (including a second voltage regulator sub-circuit 9b).

[0204] Figure 11 This is a schematic diagram of another circuit structure of the shift register unit in an embodiment of this disclosure. For example... Figure 11 As shown, the shift register unit includes not only the display input circuit 7, at least two drive output circuits 5, the first pull-up voltage regulator circuit VR1 and the second pull-up voltage regulator circuit VR2 in the previous embodiment, but also a display reset circuit 8 and a pull-down control circuit 11.

[0205] The display reset circuit 8 is connected to the display reset signal input terminal RST, the second power supply terminal, and the pull-up node PU. The display reset circuit 8 is configured to write an invalid level signal provided by the second power supply terminal to the pull-up node PU in response to the control of the valid level signal provided by the display reset signal input terminal RST. The display reset circuit 8 can perform a reset process on the pull-up node PU in response to the control of the signal provided by the display reset signal input terminal RST.

[0206] The pull-down control circuit 11 is connected to the second power supply terminal, the effective level supply terminal, the pull-up node PU, and the pull-down node PD. The pull-down control circuit 11 is configured to write a voltage that is opposite to the voltage at the pull-up node PU to the pull-down node PD.

[0207] The drive output sub-circuit 501 is also connected to the pull-down node PD and the fourth power supply terminal. The drive output sub-circuit 501 is also configured to write the inactive level signal provided by the fourth power supply terminal to the corresponding drive signal output terminals OUT1 to OUT4 in response to the control of the active level signal at the pull-down node PD.

[0208] In some embodiments, the first voltage regulator circuit 9a further includes a first reset circuit 903. The first reset circuit 903 is connected to the pull-down node PD, the second terminal of the second capacitor C2, and the fourth power supply terminal. The first reset circuit 903 is configured to write an invalid level signal provided by the fourth power supply terminal to the second terminal of the second capacitor C2 in response to the control of an effective level signal at the pull-down node PD. The first reset circuit 903 can reset the second terminal of the second capacitor C2.

[0209] In some embodiments, the first reset circuit 903 includes: a sixty-first transistor M61; the control terminal of the sixty-first transistor M61 is connected to the pull-down node PD, the first terminal of the sixty-first transistor M61 is connected to the second terminal of the second capacitor C2, and the second terminal of the sixty-first transistor M61 is connected to the second power supply terminal.

[0210] In some embodiments, the second voltage regulator circuit 9b further includes a second reset circuit 904; the second reset circuit 904 is connected to the pull-down node PD, the second terminal of the second capacitor C2 and the fourth power supply terminal, and the second reset circuit 904 is configured to write the inactive level signal provided by the fourth power supply terminal to the second terminal of the second capacitor C2 in response to the control of the effective level signal at the pull-down node PD.

[0211] In some embodiments, the second reset circuit 904 includes: a sixty-second transistor M62; the control terminal of the sixty-second transistor M62 is connected to the pull-down node PD, the first terminal of the sixty-second transistor M62 is connected to the second terminal of the third capacitor C3, and the second terminal of the sixty-second transistor M62 is connected to the second power supply terminal.

[0212] In some embodiments, the shift register circuit further includes: a pull-up noise reduction circuit 12; the pull-up noise reduction circuit 12 is connected to a second power supply terminal, a pull-up node PU and a pull-down node PD, and the pull-up noise reduction circuit 12 is configured to write an invalid level signal provided by the second power supply terminal to the pull-up node PU in response to the control of an effective level signal at the pull-down node PD.

[0213] In some embodiments, the shift register further includes at least one cascaded output circuit 13; the cascaded output circuit 13 is connected to a pull-up node PU, a corresponding cascaded clock signal input terminal and a corresponding cascaded signal output terminal CR, and the cascaded output circuit 13 is configured to write the signal provided by the cascaded clock signal input terminal to the cascaded signal output terminal in response to the control of the pull-up node PU.

[0214] Alternatively, the cascaded output circuit 13 is also connected to the pull-down node PD and the second power supply terminal, and the cascaded output circuit 13 is further configured to write an inactive level signal provided by the second power supply terminal to the cascaded signal output terminal CR in response to the control of the voltage at the pull-down node PD.

[0215] Figure 12 This is a schematic diagram of another circuit structure of the shift register unit in an embodiment of this disclosure. For example... Figure 12 As shown, the shift register unit in this embodiment also has the function of outputting a driving pulse for sensing. In some embodiments, the shift register circuit further includes: a sensing control circuit 1 and a sensing input circuit 2.

[0216] The sensing control circuit 1 is connected to the sensing control node H, the sensing signal input terminal and the random signal input terminal OE. The sensing control circuit 1 is configured to write the signal provided by the sensing signal input terminal INPUT2 to the sensing control node H in response to the control of the valid level signal provided by the random signal input terminal OE.

[0217] The sensing input circuit 2 is connected to the sensing control node H, the clock control signal input terminal CLKA, the sensing intermediate node N, and the pull-up node PU. It is configured to write an effective level signal to the sensing intermediate node N in response to the control of the effective level signal at the sensing control node H, and to form a path between the sensing intermediate node N and the pull-up node PU in response to the control of the effective level signal provided by the clock control signal input terminal CLKA.

[0218] In some embodiments, the shift register circuit further includes a global reset circuit 6, which is connected to the global reset signal input terminal T-RST, the second power supply terminal, and the pull-up node PU. The global reset circuit 6 is configured to write an invalid level signal provided by the second power supply terminal to the pull-up node PU in response to the control of the valid level signal provided by the global reset signal input terminal T-RST.

[0219] In some embodiments, the sensing control circuit 1 includes a first transistor M1 and a holding capacitor C0.

[0220] The control electrode of the first transistor M1 is connected to the random signal input terminal OE, the first electrode of the first transistor M1 is connected to the sensing signal input terminal INPUT2, and the second electrode of the first transistor M1 is connected to the sensing control node H.

[0221] The first terminal of capacitor C0 is connected to the sensing and control node H, and the second terminal of capacitor is connected to a constant voltage supply terminal, such as a ground terminal or a power supply terminal. Figure 12 The example diagram illustrates the case where the second terminal of the holding capacitor C0 is connected to the second power supply terminal.

[0222] In some embodiments, the sensing input circuit 2 includes a second transistor M2 and a third transistor M3.

[0223] The control electrode of the second transistor M2 is connected to the sensing control node H, and the first electrode of the second transistor M2 is connected to the clock control signal input terminal CLKA. Figure 12 The second transistor M2 is connected to the sensing intermediate node N (as shown in the figure) or the first power supply terminal (in which case no corresponding figure is given).

[0224] The control electrode of the third transistor M3 is connected to the clock control signal input terminal CLKA, the first electrode of the third transistor M3 is connected to the sensing intermediate node N, and the second electrode of the third transistor M3 is connected to the pull-up node PU.

[0225] In some embodiments, the global reset circuit 6 includes: a seventh transistor M7; the control electrode of the seventh transistor M7 is connected to the global reset signal input terminal T-RST, the first electrode of the seventh transistor M7 is connected to the pull-up node PU, and the second electrode of the seventh transistor M7 is connected to the second power supply terminal.

[0226] In some embodiments, the display input circuit 7 includes: a ninth transistor M9; the control electrode of the ninth transistor M9 is connected to the display signal input terminal INPUT1, and the first electrode of the ninth transistor M9 is connected to the first power supply terminal (…). Figure 12 (As shown in the diagram) or the display signal input terminal INPUT1 (in which case no corresponding diagram is given), the second terminal of the ninth transistor M9 is connected to the pull-up node PU.

[0227] In some embodiments, the display reset circuit 8 includes: a tenth transistor M10; the control electrode of the tenth transistor M10 is connected to the display reset signal input terminal RST, the first electrode of the tenth transistor M10 is connected to the pull-up node PU, and the second electrode of the tenth transistor M10 is connected to the second power supply terminal.

[0228] In some embodiments, the pull-down control circuit 11 includes a twelfth transistor M12 and a thirteenth transistor M13.

[0229] The control electrode of the twelfth transistor M12 is connected to the active level supply terminal, the first electrode of the twelfth transistor M12 is connected to the control electrode of the twelfth transistor M12, and the second electrode of the twelfth transistor M12 is connected to the pull-down node PD.

[0230] The control electrode of the thirteenth transistor M13 is connected to the pull-up node PU, the first electrode of the thirteenth transistor M13 is connected to the pull-down node PD, and the second electrode of the thirteenth transistor M13 is connected to the second power supply terminal.

[0231] In some embodiments, the pull-up noise reduction circuit 12 includes: a fourteenth transistor M14; the control electrode of the fourteenth transistor M14 is connected to the pull-down node PD, the first electrode of the fourteenth transistor M14 is connected to the pull-up node PU, and the second electrode of the fourteenth transistor M14 is connected to the second power supply terminal.

[0232] In some embodiments, the drive output sub-circuit 501 includes a fifth transistor M5 and a seventeenth transistor M17.

[0233] The control electrode of the fifth transistor M5 is connected to the pull-up node PU, the first electrode of the fifth transistor M5 is connected to the corresponding drive clock signal input terminals CLKE1~CLKE4, and the second electrode of the fifth transistor M5 is connected to the corresponding drive signal output terminals OUT1~OUT4.

[0234] The control electrode of the seventeenth transistor M17 is connected to the pull-down node PD. The first electrode of the seventeenth transistor M17 is connected to the corresponding drive signal output terminals OUT1 to OUT4. The second electrode of the seventeenth transistor M17 is connected to the fourth power supply terminal.

[0235] In some embodiments, the cascaded output circuit 13 includes a sixteenth transistor M16 and a nineteenth transistor M19.

[0236] The control electrode of the sixteenth transistor M16 is connected to the pull-up node PU, the first electrode of the sixteenth transistor M16 is connected to the corresponding cascaded clock signal input terminal CLKD, and the second electrode of the sixteenth transistor M16 is connected to the corresponding cascaded signal output terminal CR.

[0237] The control electrode of the nineteenth transistor M19 is connected to the pull-down node PD, the first electrode of the nineteenth transistor M19 is connected to the corresponding cascaded signal output terminal CR, and the second electrode of the nineteenth transistor M19 is connected to the second power supply terminal.

[0238] In some embodiments, a first power supply terminal provides a high-level voltage VDD1, a second power supply terminal provides a low-level voltage VGL1, a fourth power supply terminal provides a low-level voltage VGL2, and an effective level supply terminal provides a high-level voltage VDDA.

[0239] Figure 13 for Figure 12 The diagram shows a timing diagram of one type of shift register unit. Figure 13 As shown, the operation of this shift register unit includes: display driving process, sensing driving process and global reset process s1.

[0240] The display driving process includes: display input stage t1, display output stage t2, and display reset stage t3; the sensing driving process includes: sensing preparation stage p1, sensing input stage p2, sensing output stage p3, and sensing control reset stage p4.

[0241] During the display input phase t1, the display signal input terminal INPUT1 provides a high-level signal, the ninth transistor M9 is turned on, and the high-level voltage VDD1 provided by the first power supply terminal is written to the pull-up node PU through the ninth transistor M9. The pull-up node PU is in a high-level state, and correspondingly, each of the fifth transistors and the sixteenth transistor M16 is turned on.

[0242] When the pull-up node PU is in a high-level state, the thirteenth transistor M13 is turned on, and the low-level voltage VGL1 provided by the second power supply is written to the pull-down node PD through the thirteenth transistor M13. When the pull-down node PD is in a low-level state, the seventeenth transistor M17 and the nineteenth transistor M19 are both in a cut-off state.

[0243] At this time, each drive clock signal input terminal CLKE1 to CLKE4 writes a low-level signal to the drive signal output terminals OUT1 to OUT4 through the corresponding fifth transistor M5; the cascade clock signal input terminal CLKD writes a low-level signal to the cascade signal output terminal CR through the sixteenth transistor M16. That is, both the drive signal output terminals OUT1 to OUT4 and the cascade signal output terminal CR output low-level signals.

[0244] It should be noted that after entering the display input stage t1, both the 51st transistor M51 and the 52nd transistor M52 are also in the conducting state. Furthermore, before entering the display output stage t2, the rising edge of the signal provided by the first regulated clock signal input terminal CLKF will pull up the voltage at the pull-up node PU.

[0245] During the display output phase t2, the display signal input terminal INPUT1 provides a low-level signal, the ninth transistor M9 is cut off, the pull-up node PU is in a floating state and maintains the high level of the previous phase; the fifth transistor M5, the fifty-first transistor M51, and the sixteenth transistor M16 are all turned on.

[0246] Each drive clock signal input terminal CLKE1~CLKE4 sequentially provides display drive pulses to the corresponding fifth transistor M5, and each drive signal output terminal OUT1~OUT4 sequentially outputs display drive pulses.

[0247] Specifically, when the first output display drive pulse drive signal output terminal OUT1 is at the rising edge of the output display drive pulse, the first capacitor C1 connected to the first output display drive pulse drive signal output terminal OUT1 will pull up the voltage at the pull-up node PU once.

[0248] When the driving signal output terminal OUT2 of the second output display driving pulse is at the rising edge of the output display driving pulse, the first capacitor C1 connected to the driving signal output terminal OUT2 of the second output display driving pulse pulls up the voltage at the pull-up node PU; at the same time, the fifty-first transistor M51 outputs a falling edge to the second terminal of the second capacitor C2, and the second capacitor C2 pulls down the voltage at the pull-up node PU. The pull-down effect of the second capacitor C2 on the pull-up node PU cancels out the pull-up effect of the first capacitor C1 on the pull-up node PU, and the voltage at the pull-up node PU remains unchanged.

[0249] At the falling edge of the first output display drive pulse, the first capacitor C1 connected to the first output display drive pulse drive signal output terminal OUT1 pulls down the voltage at the pull-up node PU. At the same time, at the rising edge of the third output display drive pulse drive signal output terminal OUT3, the first capacitor C1 connected to the third output display drive pulse drive signal output terminal OUT3 pulls up the voltage at the pull-up node PU. The two first capacitors C1 cancel out the pull-down and pull-up effects of the pull-up node PU, and the voltage at the pull-up node PU remains unchanged.

[0250] At the falling edge of the second output display drive pulse, the first capacitor C1 connected to the second output display drive pulse drive signal output terminal OUT2 pulls down the voltage at the pull-up node PU. At the same time, at the rising edge of the fourth output display drive pulse drive signal output terminal OUT4, the first capacitor C1 connected to the fourth output display drive pulse drive signal output terminal OUT4 pulls up the voltage at the pull-up node PU. The two first capacitors C1 cancel out the pull-down and pull-up effects of the pull-up node PU, and the voltage at the pull-up node PU remains unchanged.

[0251] At the falling edge of the third output display drive pulse, the first capacitor C1 connected to the drive signal output terminal OUT3 of the third output display drive pulse pulls down the voltage at the pull-up node PU. At the same time, the fifty-second transistor M52 outputs a rising edge to the second terminal of the third capacitor C3, and the third capacitor C3 pulls up the voltage at the pull-up node PU. The pull-up effect of the third capacitor C3 on the pull-up node PU cancels out the pull-up effect of the first capacitor C1 on the pull-up node PU, and the voltage at the pull-up node PU remains unchanged.

[0252] At the falling edge of the third output display drive pulse, the first capacitor C1 connected to the drive signal output terminal OUT3 of the third output display drive pulse pulls down the voltage at the pull-up node PU. At the same time, the fifty-second transistor M52 outputs a rising edge to the second terminal of the third capacitor C3, and the third capacitor C3 pulls up the voltage at the pull-up node PU. The pull-up effect of the third capacitor C3 on the pull-up node PU cancels out the pull-up effect of the first capacitor C1 on the pull-up node PU, and the voltage at the pull-up node PU remains unchanged.

[0253] When the fourth output display drive pulse output terminal OUT4 is on the falling edge of the output display drive pulse, the first capacitor C1 connected to the fourth output display drive pulse drive signal output terminal OUT4 pulls down the voltage at the pull-up node PU.

[0254] Therefore, it can be seen that during the time period from the start of the first output display drive pulse from the start of the output display drive pulse to the end of the last output display drive pulse from the start of the output display drive pulse from the start of the output display drive pulse from the start of the output display drive pulse from the end of the output display drive pulse from the start of the output display drive pulse, the pull-up voltage regulator circuit can maintain the voltage at the pull-up node PU unchanged.

[0255] It should be noted that during the display output stage t2, the cascaded pulses provided by the cascaded clock signal input terminal CLKD are also written to the cascaded signal output terminal CR through the sixteenth transistor M16, and the cascaded signal output terminal CR outputs the cascaded pulses. The timing of the cascaded pulses output by the cascaded signal output terminal CR can be pre-designed according to actual needs, and this disclosure does not impose any restrictions on it.

[0256] After the display output phase t2 ends, the falling edge of the signal provided by the second regulated clock signal input terminal CLKG will pull down the voltage at the pull-up node PU.

[0257] During the display reset phase t3, the display reset signal input terminal RST provides a high-level signal, the tenth transistor M10 is turned on, and the low-level signal provided by the second power supply terminal is written to the pull-up node PU through the tenth transistor M10. The pull-up node PU is in a low-level state, and the fifth transistor M5 and the sixteenth transistor M16 are both turned off.

[0258] At this time, the thirteenth transistor M13 is also turned off, and the high-level voltage VDDA provided by the effective level supply terminal is written to the pull-down node PD through the twelfth transistor M12. The first pull-down node PD is in a high-level state, and the seventeenth and nineteenth transistors are both in the on state.

[0259] At this time, the low-level voltage VGL2 provided by the fourth power supply terminal is written to the corresponding drive signal output terminal OUT through the seventeenth transistor; the low-level voltage VGL2 provided by the fourth power supply terminal is written to the second terminal of the second capacitor C2 through the sixty-first transistor; the low-level voltage VGL2 provided by the fourth power supply terminal is written to the second terminal of the third capacitor C3 through the sixty-second transistor; and the low-level voltage VGL1 provided by the second power supply terminal is written to the cascaded signal output terminal CR through the nineteenth transistor. That is, each drive signal output terminal OUTOUT2 and the cascaded signal output terminal CR output a low-level signal.

[0260] Additionally, since the pull-down node PD is in a high-level state, the fourteenth transistor M14 is also turned on. The low-level voltage VGL1 provided by the second power supply is written to the pull-up node PU through the fourteenth transistor M14 to perform noise reduction processing on the pull-up node PU. At this time, the voltages across the second capacitor C2 and the third capacitor C3 are both in a low-level state.

[0261] During the sensing preparation phase p1, both the sensing signal input terminal INPUT2 and the random signal input terminal OE provide high-level signals, at which point the first transistor M1 is turned on. Since the sensing effective level supply terminal also provides a high-level signal, this high-level signal is written to the sensing control node H through the first transistor M1 to charge the sensing control node H, resulting in a high-level voltage at the sensing control node H. Correspondingly, the second transistor M2 is turned on; however, because the clock control signal input terminal CLKA provides a low-level signal, the third transistor M3 is turned off.

[0262] During the sensing input phase p2, the clock control signal input terminal CLKA provides a high-level signal, thus turning on the third transistor M3. At this time, because the voltage at the sensing control node H is high, the second transistor M2 remains on. Therefore, the high-level signal provided by the clock control signal input terminal CLKA can be written to the pull-up node PU through the second transistor M2 and the third transistor M3, meaning the voltage at the pull-up node PU is high. Correspondingly, all transistors connected to the control electrode and the pull-up node PU are turned on.

[0263] When the pull-up node PU is in a high-level state, the thirteenth transistor M13 is turned on, and the low-level voltage VGL1 passing through the second power supply terminal is written to the pull-down node PD through the thirteenth transistor M13. When the pull-down node PD is in a low-level state, all transistors connected to the control electrode of the pull-down node PD are turned off.

[0264] At this time, each drive clock signal input terminal CLKE1 to CLKE4 writes a low-level signal to the drive signal output terminals OUT1 to OUT4 through the corresponding fifth transistor M5; the cascade clock signal input terminal CLKD writes a low-level signal to the cascade signal output terminal CR through the sixteenth transistor M16. That is, both the drive signal output terminals OUT1 to OUT4 and the cascade signal output terminal CR output low-level signals.

[0265] During the sensing output phase p3, the clock control signal input terminal CLKA provides a low-level signal, so the third transistor M3 is turned off. The pull-up node PU is in a floating state and maintains the high level of the previous phase; the fifth transistor M5 and the sixteenth transistor M16 remain on.

[0266] In the initial stage of the sensing output phase p3, the signal provided by a drive clock signal input terminal (selected according to the sensing drive requirements) changes from a low level to a high level. Under the bootstrap effect of the first capacitor C1, the voltage at the pull-up node PU is pulled up to a higher level, and the drive signal output terminal corresponding to the drive clock signal input terminal outputs a high level signal, i.e., outputs a sensing drive pulse. After a period of time following the start of the sensing output phase p3, the signal provided by the aforementioned drive clock signal input terminal changes from a high level to a low level. Under the bootstrap effect of the first capacitor C1, the voltage at the pull-up node PU is pulled down to the initial high level voltage, the fifth transistor M5 remains on, and the drive signal output terminal outputs a low level signal.

[0267] It should be noted that the cascade clock signal input terminal CLKD provides a low-level signal throughout the entire sensing output stage p3. Therefore, the cascade signal output terminal CR always outputs a low-level signal throughout the entire sensing output stage p3.

[0268] During the sensing control reset phase p4, the random signal input terminal OE provides a high-level signal, and the first transistor M1 is turned on. The low-level signal provided by the sensing signal input terminal is written to the sensing control node H through the first transistor M1 to reset the sensing control node H.

[0269] During the global reset process s1, the global reset signal input terminal T-RST provides a high-level signal, the seventh transistor M7 is turned on, and the low-level voltage VGL1 provided by the second power supply terminal is written to the pull-up node PU through the seventh transistor M7 to reset the pull-up node PU.

[0270] When the pull-up node PU is in a high-level state, the high-level voltage VDDA provided by the effective level supply terminal is written to the pull-down node PD through the twelfth transistor M12. The first pull-down node PD is in a high-level state, and the seventeenth transistor M17 and the nineteenth transistor M19 are both in the on state.

[0271] In this embodiment, the order of the sensing control reset phase p4 and the global reset process s1 is not limited. For example, the sensing control reset phase p4 may precede the global reset process s1 (no corresponding figure is given), or it may be performed synchronously with the global reset process s1. Figure 13 As shown in the figure, it can also be located after the global reset process s1 (no corresponding figure is given). In the embodiments of this disclosure, it is only necessary to ensure that the sensing control reset stage p4 is located after the sensing input stage p2 and the global reset process s1 is located after the sensing output stage p3.

[0272] Figure 14This is a schematic diagram of another circuit structure of the shift register unit in an embodiment of this disclosure. For example... Figure 14 As shown, with Figure 12 The shift register unit shown is different from the one shown. Figure 14 The pull-down control circuit 11 in the shift register unit shown includes: the thirty-seventh transistor M37, the thirty-eighth transistor M38, the thirty-ninth transistor M39, and the fortieth transistor M40.

[0273] Among them, the control electrode of the thirty-seventh transistor M37 is connected to the effective level supply terminal, the first electrode of the thirty-seventh transistor M37 is connected to the control electrode of the thirty-seventh transistor M37, and the second electrode of the thirty-seventh transistor M37 is connected to the control electrode of the thirty-eighth transistor M38.

[0274] The control terminal of the thirty-eighth transistor M38 is connected to the first terminal of the fortieth transistor M40. The first terminal of the thirty-eighth transistor M38 is connected to the effective level supply terminal. The second terminal of the thirty-eighth transistor M38 is connected to the pull-down node PD.

[0275] The control terminal of the thirty-ninth transistor M39 is connected to the pull-up node PU, the first terminal of the thirty-ninth transistor M39 is connected to the pull-down node PD, and the second terminal of the thirty-ninth transistor M39 is connected to the fifth power supply terminal.

[0276] In some embodiments, the fifth power supply terminal provides a low-level voltage VGL3, where VGL3 is slightly less than the low-level voltage VGL1 provided by the second power supply terminal. For example, 0V < VGL1 - VGL3 < 0.2V. This design ensures that when both the thirty-ninth transistor M39 and the fortieth transistor M40 are in the on state, the gate-source voltage of the thirty-eighth transistor M38 remains less than 0, thus guaranteeing that the thirty-eighth transistor M38 is in the off state.

[0277] The control electrode of the 40th transistor M40 is connected to the pull-up node PU, and the second electrode of the 40th transistor M40 is connected to the second power supply terminal.

[0278] The aforementioned 37th transistor M37 to 40th transistor M40 can also be used to invert the voltage at the pull-up node PU and provide the inverted voltage to the pull-down node PD.

[0279] Further optionally, the pull-down control circuit 11 also includes: a forty-first transistor M41, the second terminal of the thirty-seventh transistor M37 being connected to the control terminal of the thirty-eighth transistor M38 through the forty-first transistor M41; the control terminal of the forty-first transistor M41 being connected to the control terminal of the thirty-seventh transistor M37; the first terminal of the forty-first transistor M41 being connected to the second terminal of the thirty-seventh transistor M37; and the second terminal of the forty-first transistor M41 being connected to the control terminal of the thirty-eighth transistor M38.

[0280] In practical applications, it has been found that when the 40th transistor M40 is in the off state and the 37th transistor M37 is in the on state, there will be a charging current with a short duration but a large current value between the control electrode of the 38th transistor M38 and the effective level supply terminal (used to charge the control electrode of the 38th transistor M38). This charging current can easily damage the 37th transistor M37, for example, by breaking it down.

[0281] To improve the above problems, in this embodiment of the present disclosure, a forty-first transistor M41 is provided between the second electrode of the thirty-seventh transistor M37 and the control electrode of the thirty-eighth transistor M38. The provision of the forty-first transistor M41 can effectively reduce the charging current between the control electrode of the thirty-eighth transistor M38 and the effective level supply terminal, so as to avoid the charging current from breaking down the thirty-seventh transistor M37.

[0282] Figure 15 This is a schematic diagram of another circuit structure of the shift register unit in an embodiment of this disclosure. Figure 16 This is a timing diagram showing the operation of two effective level supply terminals in an embodiment of this disclosure. For example... Figure 15 and Figure 16 As shown, unlike the previous embodiment where the shift register unit only includes one pull-down control circuit 11, in... Figure 15 The shift register circuit within the shift register unit of the scheme shown includes two pull-down control circuits 11.

[0283] Specifically, there are two pull-down control circuits 11, namely the first pull-down control circuit 11 and the second pull-down control circuit 11; there are two pull-down nodes, namely the first pull-down node PD1 and the second pull-down node PD2; there are two valid level supply terminals, namely the first valid level supply terminal and the second valid level supply terminal; the first pull-down control circuit 11 is connected to the first pull-down node PD1 and the first valid level supply terminal, and the second pull-down control circuit 11 is connected to the second pull-down node PD2 and the second valid level supply terminal.

[0284] The voltage supplied by the first effective level supply terminal is VDDA, and the voltage supplied by the second effective level supply terminal is VDDB. VDDA and VDDB alternately operate at effective levels. In other words, the first pull-down control circuit 11 and the second pull-down control circuit 11 work alternately. This design can effectively prevent the pull-down node PD from being in a high-voltage state for a long time, which is beneficial to improving the lifespan of the transistors whose control electrodes are connected to the pull-down nodes PD1 and PD2.

[0285] The drive output sub-circuit 501 is connected to both the first pull-down node PD1 and the second pull-down node PD2. The drive output sub-circuit 501 is configured to write the inactive level signal provided by the fourth power supply terminal to the drive signal output terminal OUT when at least one of the first pull-down node PD1 and the second pull-down node PD2 is in an active level state.

[0286] As an example, the drive output sub-circuit 501 includes not only the fifth transistor M5 and the seventeenth transistor M17 in the previous embodiment, but also the seventy-seventh transistor M77. The control electrode of the seventeenth transistor M17 is connected to the first pull-down node PD, and the control electrode of the seventy-seventh transistor M77 is connected to the second pull-down node PD.

[0287] When the shift register circuit includes a cascaded output circuit 13, the cascaded output circuit 13 is connected to both the first pull-down node PD1 and the second pull-down node PD2. The cascaded output circuit 13 is configured to write the inactive level signal provided by the second power supply terminal to the drive signal output terminal when at least one of the first pull-down node PD1 and the second pull-down node PD2 is in an active level state.

[0288] As an example, the cascaded output circuit 13 includes not only the sixteenth transistor M16 and the nineteenth transistor M19 in the previous embodiment, but also the seventy-ninth transistor M79. The control electrode of the nineteenth transistor M19 is connected to the first pull-down node PD1, and the control electrode of the seventy-ninth transistor is connected to the second pull-down node PD2.

[0289] When the shift register circuit includes a first reset sub-circuit 903, the first reset sub-circuit 903 is connected to both the first pull-down node PD1 and the second pull-down node PD2. The first reset sub-circuit 903 is configured to write the inactive level signal provided by the fourth power supply terminal to the second terminal of the second capacitor C2 when at least one of the first pull-down node PD1 and the second pull-down node PD2 is in an active level state.

[0290] As an example, the first reset circuit 903 includes not only the sixty-first transistor M61 in the previous embodiment, but also the seventy-first transistor M71. The control electrode of the sixty-first transistor M61 is connected to the first pull-down node PD1, and the control electrode of the seventy-first transistor M71 is connected to the second pull-down node PD2.

[0291] When the shift register circuit includes a second reset sub-circuit 904, the second reset sub-circuit 904 is connected to both the first pull-down node PD1 and the second pull-down node PD2. The second reset sub-circuit 904 is configured to write the inactive level signal provided by the fourth power supply terminal to the second terminal of the third capacitor C3 when at least one of the first pull-down node PD1 and the second pull-down node PD2 is in an active level state.

[0292] As an example, the second reset circuit 904 includes not only the sixty-second transistor M62 in the previous embodiment, but also the seventy-second transistor M72. The control electrode of the sixty-second transistor M62 is connected to the first pull-down node PD1, and the control electrode of the seventy-second transistor M72 is connected to the second pull-down node PD2.

[0293] When the shift register circuit includes a pull-up noise reduction circuit 12, the pull-up noise reduction circuit 12 is connected to both the first pull-down node PD1 and the second pull-down node PD2. The pull-up noise reduction circuit 12 is configured to write the effective level signal provided by the second power supply terminal to the pull-up node PU when at least one of the first pull-down node PD1 and the second pull-down node PD2 is in an effective level state.

[0294] As an example, the pull-up noise reduction circuit 12 includes not only the fourteenth transistor M14 in the previous embodiment, but also the twenty-seventh transistor M27. The control electrode of the fourteenth transistor M14 is connected to the first pull-down node PD1, and the control electrode of the twenty-seventh transistor M27 is connected to the second pull-down node PD2.

[0295] It should be noted that, Figure 15 The present invention only provides an example of each pull-down control circuit 11 including the thirty-seventh transistor M37 to the forty-first transistor M41. This example is for illustrative purposes only and does not limit the technical solution of this disclosure. In this disclosure, any circuit with voltage inversion function can be used as the pull-down control circuit 11, and will not be listed here.

[0296] Figure 17 This is a schematic diagram of another circuit structure of the shift register unit in an embodiment of this disclosure. For example... Figure 17 As shown, Figure 17The shift register circuit within the shift register unit shown includes two cascaded output circuits 13. One of the two cascaded output circuits 13 is configured to output a reset cascaded pulse, and the other is configured to output an input cascaded pulse.

[0297] In practical applications, it has been found that the part of each shift register circuit used to implement display cascading includes a display input circuit 7 and a display reset circuit 8. The display input circuit 7 is configured with a display signal input terminal INPUT1, and the display reset circuit 8 is configured with a display reset signal input terminal. The display signal input terminal INPUT1 is used to receive input cascading pulses, and the display reset signal input terminal RST is used to receive reset cascading pulses.

[0298] Therefore, for a first-level shift register circuit, it needs to provide a reset cascade pulse to a shift register circuit that precedes it in the cascade sequence (pre-set according to the cascade requirements) to control the corresponding shift register circuit to perform the corresponding display reset stage t3; at the same time, it also needs to provide a reset cascade pulse and an input cascade pulse to a shift register circuit that follows it in the cascade sequence (pre-set according to the cascade requirements) to control the corresponding shift register to perform the corresponding display input stage t1.

[0299] In related technologies, the shift register circuit is configured with at most one cascaded output circuit 13. The pulse output by the cascaded output circuit 13 serves as both a reset cascaded pulse and an input cascaded pulse. The related technology has the following problems: 1) The cascade signal output terminal of the cascade output circuit 13 needs to be connected to the display reset signal input terminal of a shift register circuit that precedes it in the cascade sequence, and also needs to be connected to the display signal input terminal INPUT1 of a shift register circuit that follows it in the cascade sequence. The load of the cascade signal output terminal is large, which is not conducive to the output of the cascade signal output terminal; 2) Since the pulse output by the cascade output circuit 13 serves as both the reset cascade pulse and the input cascade pulse, the timing design needs to consider the working process of three shift register circuits (the current shift register circuit and the two shift register circuits connected to the cascade signal output of the current shift register circuit) at the same time. In order to ensure that the shift register circuit can output the display drive pulse normally, the time period from the end of the display input stage t1 to the start of the display reset stage t3 often needs to be designed to be long. During this time period, the pull-up node PU will be in a floating state for a long time, which increases the risk of serious drift caused by the voltage at the pull-up node PU being affected by external factors (e.g., external electromagnetic field interference).

[0300] To effectively improve the above-mentioned technical problems, in this embodiment of the present disclosure, two cascaded output circuits 13 are provided in the shift register circuit. The cascaded signal output terminal CR1 of one of the two cascaded output circuits 13 is connected to the display reset signal input terminal of a shift register circuit that is cascaded before the current shift register circuit, so as to provide a reset cascaded pulse to the display reset signal input terminal of the shift register circuit. The cascaded signal output terminal CR2 of the other of the two cascaded output circuits 13 is connected to the display signal input terminal INPUT1 of a shift register circuit that is cascaded after the current shift register circuit, so as to provide an input cascaded pulse to the display signal input terminal INPUT1 of the shift register circuit.

[0301] That is, the shift register unit at this stage can output reset cascade pulses and input cascade pulses respectively, and the timing of the reset cascade pulses can be different from that of the input cascade pulses. When designing the operating timing of the shift register circuit at this stage, it is not necessary to consider the operation of the three shift register circuits (the shift register circuit at this stage and the two shift register circuits connected to the cascade signal output terminals of the shift register circuit at this stage), thus allowing for greater flexibility in timing design. Correspondingly, provided that the shift register circuit can output display drive pulses normally, the time period between the end of the display input stage t1 and the start of the display reset stage t3 can be shortened to reduce the floating time of the pull-up node PU and reduce the risk of voltage drift at the pull-up node PU. At the same time, one cascade signal output terminal CR1 and CR2 of the shift register circuit at this stage is only connected to the display reset signal input terminal or the display signal input terminal INPUT1 of other shift register circuits, thus effectively reducing the load on the cascade signal output terminal CR1 and contributing to the stable output of the cascade signal terminal.

[0302] In some embodiments, within the same shift register circuit, the cascaded output circuit 13 configured to output a reset cascaded pulse begins outputting the reset cascaded pulse before the cascaded output circuit 13 configured to output an input cascaded pulse begins outputting the input cascaded pulse. This can be controlled by configuring the signals provided by the two cascaded clock signal input terminals CLKD1 and CLKD2. This design ensures the normal operation of the shift register circuit while effectively shortening the time interval between the end of the input phase t1 and the start of the reset phase t3 during operation.

[0303] Figure 18 This is a schematic diagram of another circuit structure of the shift register unit in an embodiment of this disclosure. For example... Figure 18As shown, in some embodiments, the shift register circuit further includes: a display input auxiliary circuit 7a, the display input circuit 7 being connected to the pull-up node PU via the display input auxiliary circuit 7a, and the display input circuit 7 and the display input auxiliary circuit 7a being connected to the display intermediate node XM.

[0304] The display input auxiliary circuit 7a is also connected to the sixth power supply terminal, the display signal input terminal INPUT1, and the pull-up node PU. The display input auxiliary circuit 7a is configured to write the valid level signal provided by the sixth power supply terminal to the pull-up node PU in response to the control of the valid level signal provided by the display signal input terminal INPUT1, and to create an open circuit between the display intermediate node XM and the pull-up node PU in response to the control of the invalid level signal provided by the random signal input terminal OE, and to write the valid level signal provided by the sixth power supply terminal to the display intermediate node XM.

[0305] In some embodiments, the sixth power supply terminal provides a high-level voltage VDD2, which is equal to VDD1.

[0306] In this embodiment of the present disclosure, when the display signal input terminal INPUT1 provides a valid level signal, the display input circuit 7 and the display input auxiliary circuit 7a can simultaneously charge the pull-up node PU, so that the voltage at the pull-up node PU can be quickly pulled up, which is beneficial to the precise control of the operation process of the shift register circuit.

[0307] In some embodiments, the display input auxiliary circuit 7a includes: a forty-second transistor M42 and a forty-third transistor M43; the control electrode of the forty-second transistor M42 is connected to the display signal input terminal INPUT1, the first electrode of the forty-second transistor M42 is connected to the display intermediate node XM, and the second electrode of the forty-second transistor M42 is connected to the pull-up node PU; the control electrode of the forty-third transistor M43 is connected to the sixth power supply terminal, the first electrode of the forty-third transistor M43 is connected to the control electrode of the forty-third transistor M43, and the second electrode of the forty-third transistor M43 is connected to the display intermediate node XM.

[0308] In some embodiments, the display input auxiliary circuit 7a further includes: a forty-fourth transistor M44, the second terminal of the forty-third transistor M43 being connected to the display intermediate node XM through the forty-fourth transistor M44; the control terminal of the forty-fourth transistor M44 being connected to the control terminal of the forty-third transistor M43; the first terminal of the forty-fourth transistor M44 being connected to the second terminal of the forty-fourth transistor M44; and the second terminal of the forty-fourth transistor M44 being connected to the display intermediate node XM.

[0309] Similar to the function of reducing charging current by setting the forty-first transistor M41 described above, in this embodiment of the disclosure, by setting the forty-fourth transistor M44 between the second terminal of the forty-third transistor M43 and the display intermediate node XM, the charging current between the sixth power supply terminal and the display intermediate node XM can be effectively reduced, so as to avoid the problem of damage to the forty-third transistor M43 due to excessive charging current.

[0310] Figure 19 This is a schematic diagram of another circuit structure of the shift register unit in an embodiment of this disclosure. For example... Figure 19 As shown, when the shift register circuit includes a sensing control circuit 1 and a sensing input circuit 2, in some embodiments, the shift register circuit further includes a sensing control leakage protection circuit 3.

[0311] The sensing control circuit 1 is connected to the sensing control node H through the sensing control leakage protection circuit 3. The sensing control leakage protection circuit 3 is connected to the sensing control leakage protection node GM. The sensing control leakage protection circuit 3 is also connected to the first power supply terminal, the sensing control node H, and the random signal input terminal OE. The sensing control leakage protection circuit 3 is configured to write the valid level signal provided by the first power supply terminal to the sensing control leakage protection node GM in response to the control of the valid level signal provided by the random signal input terminal OE. It is also configured to form a path between the sensing control leakage protection node GM and the sensing control node H in response to the control of the valid level signal provided by the random signal input terminal OE, and to form an open circuit between the sensing control leakage protection node GM and the sensing control node H in response to the control of the invalid level signal provided by the random signal input terminal OE.

[0312] In some embodiments, the sensing control leakage protection circuit 3 includes an eighty-first transistor M81 and an eighty-second transistor M82.

[0313] The control electrode of the 81st transistor M81 is connected to the sensing control node H, the first electrode of the 81st transistor M81 is connected to the first power supply terminal, and the second electrode of the 81st transistor M81 is connected to the sensing input leakage protection node.

[0314] The control terminal of the 82nd transistor M82 is connected to the random signal input terminal OE, the first terminal of the 82nd transistor M82 is connected to the sensing input leakage protection node, and the second terminal of the 82nd transistor M82 is connected to the sensing control node H.

[0315] In some embodiments, the shift register circuit further includes: a first voltage control circuit 14, which is connected to a third power supply terminal, a pull-up node PU, and a first voltage control node OFF1. The first voltage control circuit 14 is configured to write the valid voltage level signal provided by the third power supply terminal to the first voltage control node OFF1 in response to the control of the valid voltage level signal at the pull-up node PU.

[0316] As an example, the effective voltage level VDD1 is provided by the third power supply terminal.

[0317] The shift register also includes: a sensing input leakage protection circuit 7'; the sensing input circuit 2 is connected to the pull-up node PU through the sensing input leakage protection circuit 7', the sensing input circuit 2 and the sensing input leakage protection circuit 2' are connected to the sensing input leakage protection node SQ1, the sensing input leakage protection node SQ1 is connected to the first control voltage node OFF1, the sensing input leakage protection circuit 2' is connected to the clock control signal input terminal, and the sensing input leakage protection circuit 2' is configured to form a path between the sensing input leakage protection node SQ1 and the pull-up node PU in response to the control of the valid level signal provided by the clock control signal input terminal CLKA, and to disconnect the sensing input leakage protection node SQ1 and the pull-up node PU in response to the control of the invalid level signal provided by the clock control signal input terminal CLKA.

[0318] In some embodiments, the first voltage control circuit 14 includes: a twentieth transistor M20; the control electrode of the twentieth transistor M20 is connected to the pull-up node PU, the first electrode of the twentieth transistor M20 is connected to the first power supply terminal, and the second electrode of the twentieth transistor M20 is connected to the first voltage control node OFF1.

[0319] In some embodiments, the sensing input leakage protection circuit 2' includes an eighth transistor M8; the control terminal of the eighth transistor M8 is connected to the clock control signal input terminal CLKA, the first terminal of the eighth transistor M8 is connected to the sensing input leakage protection node SQ1, and the second terminal of the eighth transistor M8 is connected to the pull-up node PU.

[0320] In some embodiments, the shift register circuit further includes at least one of the following: a first leakage protection circuit 15, a second leakage protection circuit 16, and a third leakage protection circuit 17;

[0321] The global reset circuit 6 is connected to the second power supply terminal through the first leakage protection circuit 15. The global reset circuit 6 and the first leakage protection circuit 15 are connected to the first leakage protection node Q1. The first leakage protection node Q1 is connected to the first voltage control node OFF1. The first leakage protection circuit 15 is connected to the global reset signal input terminal T-RST. The first leakage protection circuit 15 is configured to form a path between the first leakage protection node Q1 and the second power supply terminal in response to the control of the valid level signal provided by the global reset signal input terminal T-RST, and to disconnect the circuit between the first leakage protection node Q1 and the second power supply terminal in response to the control of the invalid level signal provided by the global reset signal input terminal T-RST.

[0322] The display reset circuit 8 is connected to the second power supply terminal through the second leakage protection circuit 16. The display reset circuit 8 and the second leakage protection circuit 16 are connected to the second leakage protection node Q2. The second leakage protection node Q2 is connected to the first voltage control node OFF1. The second leakage protection circuit 16 is connected to the display reset signal input terminal RST. The second leakage protection circuit 16 is configured to form a path between the second leakage protection node Q2 and the second power supply terminal in response to the control of the valid level signal provided by the display reset signal input terminal, and to disconnect the second leakage protection node Q2 and the second power supply terminal in response to the control of the invalid level signal provided by the display reset signal input terminal.

[0323] The pull-up noise reduction circuit 12 is connected to the second power supply terminal through the third leakage protection circuit 17. The pull-up noise reduction circuit 12 and the third leakage protection circuit 17 are connected to the third leakage protection node Q3. The third leakage protection node Q3 is connected to the first voltage control node OFF1. The third leakage protection circuit 17 is connected to the pull-down node PD. The third leakage protection circuit 17 is configured to form a path between the third leakage protection node Q3 and the second power supply terminal in response to the control of the effective level signal at the pull-down node PD, and to disconnect the circuit between the third leakage protection node Q3 and the second power supply terminal in response to the control of the ineffective level signal at the pull-down node PD.

[0324] In some embodiments, the first leakage protection circuit 15 includes a twenty-first transistor M21, the control electrode of the twenty-first transistor M21 is connected to the global reset signal input terminal T-RST, the first electrode of the twenty-first transistor M21 is connected to the first leakage protection node Q1, and the second electrode of the twenty-second transistor M22 is connected to the second power supply terminal.

[0325] In some embodiments, the first leakage protection circuit 15 includes a 22nd transistor M22, the control electrode of the 22nd transistor M22 is connected to the display reset signal input terminal, the first electrode of the 22nd transistor M22 is connected to the second leakage protection node Q2, and the second electrode of the 22nd transistor M22 is connected to the second power supply terminal.

[0326] In some embodiments, the third leakage protection circuit 17 includes: a twenty-third transistor M23, the control electrode of the twenty-third transistor M23 is connected to the first pull-down node PD, the first electrode of the twenty-third transistor M23 is connected to the third leakage protection node Q3, and the second electrode of the twenty-third transistor M23 is connected to the second power supply terminal.

[0327] It should be noted that, Figure 19 The example provided illustrates a shift register unit that simultaneously includes a first leakage protection circuit 15, a third leakage protection circuit 17, and a third leakage protection circuit 17. In practical applications, at least one of the first leakage protection circuit 15, the third leakage protection circuit 17, and the third leakage protection circuit 17 can be configured according to actual needs.

[0328] Figure 20 This is a schematic diagram of another circuit structure of the shift register unit in an embodiment of this disclosure. For example... Figure 20 As shown, in some embodiments, the shift register unit further includes a first pull-down noise reduction circuit 18 and / or a second pull-down noise reduction circuit 19.

[0329] The first pull-down noise reduction circuit 18 is connected to the pull-down node PD, the second power supply terminal, the sensing control node H, and the clock control signal input terminal. The first pull-down noise reduction circuit 18 is configured to write the ineffective level signal provided by the second power supply terminal to the pull-down node PD in response to the control of the effective level signal at the sensing control node H and the effective level signal provided by the clock control signal input terminal, so as to perform noise reduction processing on the output voltage of the pull-down node PD.

[0330] The second pull-down noise reduction circuit 19 is connected to the pull-down node PD, the second power supply terminal and the sensing signal input terminal. The second pull-down noise reduction circuit 19 is configured to write the ineffective level signal provided by the second power supply terminal to the pull-down node PD in response to the control of the effective level signal provided by the sensing signal input terminal, so as to perform noise reduction processing on the output voltage of the pull-down node PD.

[0331] In some embodiments, the first pull-down noise reduction circuit 18 includes a twenty-ninth transistor M29 and a thirtieth transistor M30, and the second pull-down noise reduction circuit 19 includes a thirty-first transistor M31.

[0332] Among them, the control terminal of the twenty-ninth transistor M29 is connected to the clock control signal input terminal, the first terminal of the twenty-ninth transistor M29 is connected to the pull-down node PD, and the second terminal of the twenty-ninth transistor M29 is connected to the first terminal of the thirtieth transistor M30.

[0333] The control electrode of the thirtieth transistor M30 is connected to the sensing control node H, and the second electrode of the thirtieth transistor M30 is connected to the second power supply terminal.

[0334] The control terminal of the thirty-first transistor M31 is connected to the second sensing signal input terminal INPUT2, the first terminal of the thirty-first transistor M31 is connected to the pull-down node PD, and the second terminal of the thirty-first transistor M31 is connected to the second power supply terminal.

[0335] Figure 21 This is a schematic diagram of another circuit structure of the shift register unit in an embodiment of this disclosure. For example... Figure 21 As shown, unlike the previous embodiment where the shift register unit included a shift register circuit, Figure 21 The shift register unit in the illustrated embodiment includes two shift register circuits, SR1 and SR2. For a description of the shift register circuits SR1 and SR2, please refer to the previous embodiments.

[0336] In some embodiments, each shift register circuit SR1, SR2 includes a sensing control circuit 1 and a sensing input circuit 2. The sensing input circuit 2 includes a first input sub-circuit 201 and a second input sub-circuit 202.

[0337] The first input sub-circuit 201 is connected to the sensing control node H and the sensing intermediate node N, and is configured to write a valid level signal to the sensing intermediate node N in response to the control of a valid level signal at the sensing control node H. The second input sub-circuit 202 is connected to the sensing intermediate node N and the clock control signal input terminal, and is configured to form a path between the sensing intermediate node N and the pull-up node PU in response to the control of a valid level signal provided by the clock control signal input terminal CLKA. As an example, the first input sub-circuit 201 includes the aforementioned second transistor M2, and the second input sub-circuit 202 includes the aforementioned third transistor M3.

[0338] In this embodiment, the two shift register circuits SR1 and SR2 share the same sensing control circuit 1 and the same first input sub-circuit 201. This design effectively reduces the number of transistors in the gate drive circuit, which helps to reduce the overall space occupied by the gate drive circuit.

[0339] Figure 22 This is a schematic diagram of another circuit structure for a shift register unit provided in an embodiment of this disclosure. (See diagram below.) Figure 22 As shown, the shift register unit includes: a shift register circuit, which includes: a display input circuit 7, a display reset circuit 8, at least one drive output circuit 5, and two cascaded output circuits 13.

[0340] The display input circuit 7 is connected to the display signal input terminal INPUT1 and the pull-up node PU. The display input circuit 7 is configured to write a valid level signal to the pull-up node PU in response to the control of the valid level signal provided by the display signal input terminal INPUT1.

[0341] The display reset circuit 8 is connected to the display reset signal input terminal RST, the second power supply terminal, and the pull-up node PU. The display reset circuit 8 is configured to write the invalid level signal provided by the second power supply terminal to the pull-up node PU in response to the control of the valid level signal provided by the sensing reset signal input terminal RST.

[0342] The drive output circuit 5 includes a drive output sub-circuit 501 and a first capacitor C1. The drive output sub-circuit 501 is connected to the pull-up node PU, the corresponding drive clock signal input terminal CLKE1, and the corresponding drive signal output terminal OUT1. The drive output sub-circuit 501 is configured to write the signal provided by the drive clock signal input terminal CLKE1 to the drive signal output terminal in response to the control of the effective level signal at the pull-up node PU. The first end of the first capacitor C1 is connected to the pull-up node PU, and the second end of the first capacitor C1 is connected to the drive signal output terminal OUT1.

[0343] The cascaded output circuit 13 is connected to the pull-up node PU, the corresponding cascaded clock signal input terminals CLKD1 and CLKD2, and the corresponding cascaded signal output terminals CR1 and CR2. The cascaded output circuit 13 is configured to write the signals provided by the cascaded clock signal input terminals CLKD1 and CLKD2 to the cascaded signal output terminals CR1 and CR2 in response to the control of the pull-up node PU. One of the two cascaded output circuits 13 is configured to output a reset cascaded pulse, and the other is configured to output an input cascaded pulse.

[0344] In some embodiments, the number of drive output circuits 5 may be greater than one, such as two or four as listed in the previous embodiments. Of course, when the number of drive output circuits 5 is greater than one, Figure 22 The shift register circuit in the shift register unit shown can be configured with the aforementioned first pull-up regulator circuit VR1 and second pull-up regulator circuit VR2.

[0345] also, Figure 22 The shift register circuit in the shift register unit shown may also selectively include at least one of the following in the previous embodiments: pull-down control circuit 11, pull-up noise reduction circuit 12, sensing control circuit 1, sensing input circuit 2, global reset circuit 6, first pull-down noise reduction circuit 18, second pull-down noise reduction circuit 19, display input auxiliary circuit 7a, and various leakage protection circuits. These will not be described in detail here.

[0346] It should be noted that some circuit structures in the above embodiments can be combined to obtain new shift register unit circuit structures, and the new shift register unit circuit structures obtained by combination should also fall within the protection scope of this disclosure.

[0347] Based on the same inventive concept, this disclosure also provides a gate driving circuit. Figure 23 This is a schematic diagram of a gate drive circuit provided in an embodiment of the present disclosure. Figure 24 for Figure 23 The diagram shows a timing diagram of one type of gate drive circuit. Figure 23 and Figure 24 As shown, the gate drive circuit includes multiple shift register units, wherein the shift register units can be the shift register units provided in any of the previous embodiments, and the multiple shift register circuits included in the multiple shift register units are cascaded; for a specific description of the shift register circuit, please refer to the content in the previous embodiments, which will not be repeated here.

[0348] Figure 23 The example diagram shows three shift register units SRU1 to SRU3, each of which includes a shift register circuit SR1 to SR3; that is, Figure 23 The example shows three shift register circuits SR1 to SR3.

[0349] In some embodiments, each pull-up regulator circuit includes the aforementioned m first regulator sub-circuits and n second regulator sub-circuits. The gate drive circuit further includes: multiple clock supply signal lines capable of sequentially providing clock pulses; the drive clock signal input terminals CLKE1 to CLKE4 of the drive output circuit are connected to the corresponding clock supply signal lines; the first regulated clock signal input terminal CLKF of the first regulator sub-circuit is connected to the corresponding clock supply signal line; and the second regulated clock signal input terminal CLKG of the second regulator sub-circuit is connected to the corresponding clock supply signal line.

[0350] As an example, there are 12 clock supply signal lines. Each shift register circuit includes 4 drive output circuits and 1 cascaded output circuit. That is, a shift register circuit has 4 drive clock signal input terminals CLKE1~CLKE4, 4 drive signal output terminals OUT1~OUT4, and 1 cascaded signal output terminal CR.

[0351] Each pull-up regulator circuit includes one first regulator sub-circuit and one second regulator sub-circuit, that is, a shift register circuit has one first regulated clock signal input terminal CLKF and one second regulated clock signal input terminal CLKG.

[0352] Among them, the four drive clock signal input terminals CLKE1~CLKE4 of the shift register circuit SR1 are connected to the clock supply signal lines CKE1~CKE4 respectively, the first regulated clock signal input terminal CLKF of the shift register circuit SR1 is connected to the clock supply signal line CKE12, and the second regulated clock signal input terminal CLKG of the shift register circuit SR1 is connected to the clock supply signal line CKE5.

[0353] The four drive clock signal input terminals CLKE1 to CLKE4 of the shift register circuit SR2 are connected to the clock supply signal lines CKE5 to CKE8, respectively. The first regulated clock signal input terminal CLKF of the shift register circuit SR2 is connected to the clock supply signal line CKE4, and the second regulated clock signal input terminal CLKG of the shift register circuit SR2 is connected to the clock supply signal line CKE9.

[0354] The four drive clock signal input terminals CLKE1 to CLKE4 of the shift register circuit SR3 are connected to the clock supply signal lines CKE9 to CKE12, respectively. The first regulated clock signal input terminal CLKF of the shift register circuit SR3 is connected to the clock supply signal line CKE8, and the second regulated clock signal input terminal CLKG of the shift register circuit SR3 is connected to the clock supply signal line CKE1.

[0355] In practical applications, the number of drive clock signal input terminals CLKE1 to CLKE4, the number of first regulated clock signal input terminals CLKF, the number of second regulated clock signal input terminals CLKG, and the number of clock supply signal lines (as well as the timing design) configured for each shift register circuit can be adjusted so that the clock supply signal lines can provide signals not only to the drive clock signal input terminals CLKE1 to CLKE4, but also to the first regulated clock signal input terminals CLKF and the second regulated clock signal input terminals CLKG, thereby effectively reducing the number of wiring connections.

[0356] Based on the same inventive concept, this disclosure also provides a display panel, wherein the display panel includes the gate driving circuit provided in the previous embodiment. For a detailed description of the gate driving circuit, please refer to the content in the previous embodiment, which will not be repeated here.

[0357] In some embodiments, the gate driving circuit is fabricated on the array substrate of the display panel using the GOA method.

[0358] Based on the same inventive concept, this disclosure also provides a display device, which includes the display panel provided in the previous embodiments. For a detailed description of the display panel, please refer to the content in the previous embodiments, which will not be repeated here.

[0359] The display device provided in this disclosure can be any product or component with display function, such as a liquid crystal display screen, wearable device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0360] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register unit, wherein, include: Shift register circuit, the shift register circuit comprising: The display input circuit is connected to the display signal input terminal and the pull-up node, and is configured to write a valid level signal to the pull-up node in response to the control of a valid level signal provided by the display signal input terminal; At least two drive output circuits capable of sequentially outputting display drive pulses are provided. The drive output circuits are connected to the pull-up node, the drive clock signal input terminal, and the drive signal output terminal. The drive output circuits are configured to write the signal provided by the drive clock signal input terminal to the drive signal output terminal in response to the control of the effective level signal at the pull-up node. The shift register circuit further includes a first pull-up voltage regulator circuit and a second pull-up voltage regulator circuit; The first pull-up regulator circuit is connected to the pull-up node and is configured to maintain the voltage at the pull-up node unchanged during the period when the drive output circuit outputs the display drive pulse for the first output display drive pulse; The second pull-up regulator circuit is connected to the pull-up node and is configured to maintain the voltage at the pull-up node unchanged during the period when the drive output circuit outputs the display drive pulse for the last output display drive pulse; The first pull-up voltage regulator circuit includes at least one first voltage regulator sub-circuit; the first voltage regulator sub-circuit includes a fifty-first transistor, a sixty-first transistor, and a second capacitor; the second terminal of the fifty-first transistor, the first terminal of the sixty-first transistor, and the second terminal of the second capacitor are connected. The second pull-up voltage regulator circuit includes at least one second voltage regulator sub-circuit; the second voltage regulator sub-circuit includes a fifty-second transistor, a sixty-second transistor, and a third capacitor; the second terminal of the fifty-second transistor, the first terminal of the sixty-second transistor, and the second terminal of the third capacitor are connected; The drive output circuit includes a drive output sub-circuit; the drive output sub-circuit includes a fifth transistor, a seventeenth transistor, and a first capacitor; the second terminal of the fifth transistor, the first terminal of the seventeenth transistor, and the second terminal of the first capacitor are connected; The control terminals of the 51st transistor, the 5th transistor, the 52nd transistor, the first terminal of the first capacitor, the first terminal of the second capacitor, and the first terminal of the third capacitor are connected to the pull-up node. The control terminals of the sixty-first transistor, the sixty-second transistor, and the seventeenth transistor are connected; The second terminals of the sixty-first transistor, the sixty-second transistor, and the seventeenth transistor are all electrically connected to the fourth power supply terminal; The first capacitor, the second capacitor, and the third capacitor have the same capacitance value.

2. The shift register unit according to claim 1, wherein, The first pull-up voltage regulator circuit and the second pull-up voltage regulator circuit are configured to maintain the voltage at the pull-up node unchanged during the period when each drive output circuit outputs the display drive pulse.

3. The shift register unit according to claim 1 or 2, wherein, The drive output circuit also includes: The drive output sub-circuit has a drive clock signal input terminal and a drive signal output terminal, and the drive output sub-circuit is configured to write the signal provided by the drive clock signal input terminal to the drive signal output terminal in response to the control of the effective level signal at the pull-up node. The second terminal of the first capacitor is connected to the drive signal output terminal.

4. The shift register unit according to claim 3, wherein, During the period when the first drive output circuit outputs the display drive pulse, m other drive output circuits sequentially start outputting display drive pulses, where m is a positive integer; The first pull-up voltage regulator circuit includes: m first voltage regulator sub-circuits that correspond one-to-one with the drive output circuits in the m other drive output circuits; The first voltage regulator sub-circuit is connected to the pull-up node and the corresponding first voltage regulator clock signal input terminal, and is configured to maintain the voltage at the pull-up node unchanged when the display drive pulse output by the corresponding drive output circuit switches from the first level state to the second level state, based on the signal provided by the first voltage regulator clock signal input terminal that switches from the second level state to the first level state.

5. The shift register unit according to claim 4, wherein, The fifty-first transistor is connected to the corresponding first regulated clock signal input terminal, the pull-up node, and the second terminal of the second capacitor. It is configured to write the signal provided by the first regulated clock signal input terminal, which switches from the second level state to the first level state, to the second terminal of the second capacitor in response to the control of the effective level signal at the pull-up node when the display drive pulse output by the corresponding drive output circuit switches from the first level state to the second level state.

6. The shift register unit according to claim 5, wherein, The first terminal of the fifty-first transistor is connected to the corresponding first regulated clock signal input terminal.

7. The shift register unit according to any one of claims 1, 2, 4 to 6, wherein, The shift register circuit also includes: A pull-down control circuit, connected to a second power supply terminal, an effective level supply terminal, the pull-up node, and the pull-down node, is configured to write a voltage at the pull-down node that is inversely phase to the voltage at the pull-up node; The control electrode of the sixty-first transistor is connected to the pull-down node, the first electrode of the sixty-first transistor is connected to the second terminal of the second capacitor, and the second electrode of the sixty-first transistor is connected to the fourth power supply terminal. It is configured to write the inactive level signal provided by the fourth power supply terminal to the second terminal of the second capacitor in response to the control of the effective level signal at the pull-down node.

8. The shift register unit according to claim 7, wherein, The second terminal of the sixty-first transistor is also connected to the second power supply terminal.

9. The shift register unit according to claim 1, wherein, During the period when the drive output circuit outputs the display drive pulse for the last output display drive pulse, n other drive output circuits sequentially end the output display drive pulse, where n is a positive integer; The second pull-up voltage regulator circuit includes: n second voltage regulator sub-circuits that correspond one-to-one with the drive output circuits in the n other drive output circuits; The second voltage regulator sub-circuit is connected to the pull-up node and the corresponding second voltage regulator clock signal input terminal. The second voltage regulator sub-circuit is configured to maintain the voltage at the pull-up node unchanged when the display drive pulse output by the corresponding drive output circuit switches from the second level state to the first level state, based on the signal provided by the second voltage regulator clock signal input terminal that switches from the first level state to the second level state.

10. The shift register unit according to claim 9, wherein, The fifty-second transistor Connected to the corresponding second regulated clock signal input terminal, the pull-up node and the second terminal of the third capacitor, configured to write the signal provided by the second regulated clock signal input terminal from the first level state to the second terminal of the third capacitor in response to the control of the effective level signal at the pull-up node when the display drive pulse output by the corresponding drive output circuit switches from the second level state to the first level state; The first terminal of the fifty-second transistor is connected to the corresponding second regulated clock signal input terminal.

11. The shift register unit according to claim 9 or 10, wherein, The shift register circuit also includes: A pull-down control circuit, connected to a second power supply terminal, an effective level supply terminal, the pull-up node, and the pull-down node, is configured to write a voltage at the pull-down node that is inversely phase to the voltage at the pull-up node; The control electrode of the sixty-second transistor is connected to the pull-down node, and the second electrode of the sixty-second transistor is connected to the second terminal of the second capacitor and the fourth power supply terminal. It is configured to write the inactive level signal provided by the fourth power supply terminal to the second terminal of the second capacitor in response to the control of the effective level signal at the pull-down node.

12. The shift register unit according to claim 11, wherein, The second terminal of the sixty-second transistor is also connected to the second power supply terminal.

13. The shift register unit according to any one of claims 1, 2, 4 to 6, 8 to 10, 12, wherein, The shift register further includes: at least one cascaded output circuit; The cascaded output circuit is connected to the pull-up node, the corresponding cascaded clock signal input terminal, and the corresponding cascaded signal output terminal. The cascaded output circuit is configured to write the signal provided by the cascaded clock signal input terminal to the cascaded signal output terminal in response to the control of the pull-up node.

14. The shift register unit according to claim 13, wherein, The shift register circuit also includes: A pull-down control circuit, connected to a second power supply terminal, an effective level supply terminal, the pull-up node, and the pull-down node, is configured to write a voltage at the pull-down node that is inversely phase to the voltage at the pull-up node; The cascaded output circuit is also connected to the pull-down node and the second power supply terminal, and the cascaded output circuit is further configured to write an inactive level signal provided by the second power supply terminal to the cascaded signal output terminal in response to voltage control at the pull-down node.

15. The shift register unit according to claim 13, wherein, The shift register circuit also includes: The display reset circuit is connected to the display reset signal input terminal, the second power supply terminal, and the pull-up node, and is configured to write the invalid level signal provided by the second power supply terminal to the pull-up node in response to the control of the valid level signal provided by the sensing reset signal input terminal. The number of cascaded output circuits is two, one of which is configured to output a reset cascaded pulse, and the other is configured to output an input cascaded pulse.

16. The shift register unit according to claim 15, wherein, The timing at which the cascaded output circuit configured to output the reset cascaded pulse begins to output the reset cascaded pulse is earlier than the timing at which the cascaded output circuit configured to output the input cascaded pulse begins to output the input cascaded pulse.

17. The shift register unit according to claim 13, wherein, The shift register circuit also includes: The display reset circuit is connected to the display reset signal input terminal, the second power supply terminal, and the pull-up node, and is configured to write the invalid level signal provided by the second power supply terminal to the pull-up node in response to the control of the valid level signal provided by the sensing reset signal input terminal. A pull-down control circuit, connected to a second power supply terminal, an effective level supply terminal, the pull-up node, and the pull-down node, is configured to write a voltage at the pull-down node that is inversely phase to the voltage at the pull-up node; The drive output sub-circuit is also connected to the pull-down node and the fourth power supply terminal, and the drive output sub-circuit is further configured to write the inactive level signal provided by the fourth power supply terminal to the drive signal output terminal in response to the control of the active level signal at the pull-down node.

18. The shift register unit according to claim 17, wherein, The number of pull-down control circuits is two, namely a first pull-down control circuit and a second pull-down control circuit; The number of drop-down nodes is two, and the two drop-down nodes are the first drop-down node and the second drop-down node; The number of effective level supply terminals is two, and the two effective level supply terminals are the first effective level supply terminal and the second effective level supply terminal, respectively. The first pull-down control circuit is connected to the first pull-down node and the first valid level supply terminal, and the second pull-down control circuit is connected to the second pull-down node and the second valid level supply terminal; The drive output sub-circuit is connected to both the first pull-down node and the second pull-down node. The drive output sub-circuit is configured to write the inactive level signal provided by the fourth power supply terminal to the drive signal output terminal when at least one of the first pull-down node and the second pull-down node is in an active level state.

19. The shift register unit according to claim 17 or 18, wherein, The pull-down control circuit includes: the thirty-seventh transistor, the thirty-eighth transistor, the thirty-ninth transistor, and the fortieth transistor; The control electrode of the 37th transistor is connected to the effective level supply terminal, the first electrode of the 37th transistor is connected to the control electrode of the 37th transistor, and the second electrode of the 37th transistor is connected to the control electrode of the 38th transistor. The control electrode of the 38th transistor is connected to the first electrode of the 40th transistor, the first electrode of the 38th transistor is connected to the effective level supply terminal, and the second electrode of the 38th transistor is connected to the pull-down node. The control electrode of the 39th transistor is connected to the pull-up node, the first electrode of the 39th transistor is connected to the pull-down node, and the second electrode of the 39th transistor is connected to the fifth power supply terminal. The control terminal of the 40th transistor is connected to the pull-up node, and the second terminal of the 40th transistor is connected to the second power supply terminal.

20. The shift register unit according to claim 19, wherein, The pull-down control circuit further includes: a forty-first transistor, wherein the second terminal of the thirty-seventh transistor is connected to the control terminal of the thirty-eighth transistor through the forty-first transistor; The control electrode of the forty-first transistor is connected to the control electrode of the thirty-seventh transistor, the first electrode of the forty-first transistor is connected to the second electrode of the thirty-seventh transistor, and the second electrode of the forty-first transistor is connected to the control electrode of the thirty-eighth transistor.

21. The shift register unit according to any one of claims 1, 2, 4 to 6, 8 to 10, 12, 14 to 18, 20, wherein, The shift register circuit further includes: a display input auxiliary circuit, the display input circuit being connected to the pull-up node through the display input auxiliary circuit, and the display input circuit and the display input auxiliary circuit being connected to the display intermediate node; The display input auxiliary circuit is also connected to a sixth power supply terminal, a display signal input terminal, and a pull-up node. The display input auxiliary circuit is configured to write the valid level signal provided by the sixth power supply terminal to the pull-up node in response to the control of the valid level signal provided by the display signal input terminal, and to create an open circuit between the display intermediate node and the pull-up node in response to the control of the invalid level signal provided by the random signal input terminal, and to write the valid level signal provided by the sixth power supply terminal to the display intermediate node.

22. The shift register unit according to claim 21, wherein, The display input auxiliary circuit includes: a forty-second transistor and a forty-third transistor; The control electrode of the forty-second transistor is connected to the display signal input terminal, the first electrode of the forty-second transistor is connected to the display intermediate node, and the second electrode of the forty-second transistor is connected to the pull-up node. The control electrode of the forty-third transistor is connected to the sixth power supply terminal, the first electrode of the forty-third transistor is connected to the control electrode of the forty-third transistor, and the second electrode of the forty-third transistor is connected to the display intermediate node.

23. The shift register unit according to claim 22, wherein, The display input auxiliary circuit further includes: a forty-fourth transistor, the second terminal of the forty-third transistor being connected to the display intermediate node through the forty-fourth transistor; The control electrode of the forty-fourth transistor is connected to the control electrode of the forty-third transistor, the first electrode of the forty-fourth transistor is connected to the second electrode of the forty-fourth transistor, and the second electrode of the forty-fourth transistor is connected to the display intermediate node.

24. The shift register unit according to any one of claims 1, 2, 4 to 6, 8 to 10, 12, 14 to 18, 20, 22, 23, wherein, The shift register circuit further includes: a sensing control circuit and a sensing input circuit; The sensing control circuit is connected to the sensing control node, the sensing signal input terminal, and the random signal input terminal. The sensing control circuit is configured to write the signal provided by the sensing signal input terminal to the sensing control node in response to the control of the valid level signal provided by the random signal input terminal. The sensing input circuit is connected to the sensing control node, the clock control signal input terminal, the sensing intermediate node, and the pull-up node, and is configured to write a valid level signal to the sensing intermediate node in response to the control of a valid level signal at the sensing control node, and to form a path between the sensing intermediate node and the pull-up node in response to the control of a valid level signal provided by the clock control signal input terminal.

25. The shift register unit according to claim 24, wherein, The shift register circuit also includes: a sensing control leakage protection circuit; The sensing control circuit is connected to the sensing control node through the sensing control leakage protection circuit. The sensing control leakage protection circuit is connected to the sensing control leakage protection node. The sensing control leakage protection circuit is also connected to a first power supply terminal, the sensing control node, and a random signal input terminal. The sensing control leakage protection circuit is configured to write an effective level signal provided by the first power supply terminal to the sensing control leakage protection node in response to the control of an effective level signal at the sensing control node. It is also configured to form a path between the sensing control leakage protection node and the sensing control node in response to the control of an effective level signal provided by the random signal input terminal, and to form an open circuit between the sensing control leakage protection node and the sensing control node in response to the control of an ineffective level signal provided by the random signal input terminal.

26. The shift register unit according to claim 24, wherein, The shift register circuit also includes: A first voltage control circuit is connected to a third power supply terminal, a pull-up node, and a first voltage control node. The first voltage control circuit is configured to write an effective level signal provided by the third power supply terminal to the first voltage control node in response to the control of an effective level signal at the pull-up node. The shift register also includes: a leakage protection circuit for sensing inputs; The sensing input circuit is connected to the pull-up node through the sensing input leakage protection circuit. The sensing input circuit and the sensing input leakage protection circuit are connected to the sensing input leakage protection node. The sensing input leakage protection node is connected to the first voltage control node. The sensing input leakage protection node is connected to the clock control signal input terminal. The sensing input leakage protection circuit is configured to form a path between the sensing input leakage protection node and the pull-up node in response to the control of an effective level signal provided by the clock control signal input terminal, and to disconnect the circuit between the sensing input leakage protection node and the pull-up node in response to the control of an ineffective level signal provided by the clock control signal input terminal.

27. The shift register unit according to claim 24, wherein, The sensing input circuit includes: A first input sub-circuit, connected to the sensing control node and the sensing intermediate node, is configured to write an effective level signal to the sensing intermediate node in response to the control of an effective level signal at the sensing control node. The second input sub-circuit is connected to the sensing intermediate node and the clock control signal input terminal, and is configured to form a path between the sensing intermediate node and the pull-up node in response to the control of the valid level signal provided by the clock control signal input terminal. The shift register unit includes two shift register circuits, and the two shift register circuits share the same sensing control circuit and the same first input sub-circuit.

28. The shift register unit according to any one of claims 1, 2, 4 to 6, 8 to 10, 12, 14 to 18, 20, 22, 23, 25 to 27, wherein, The shift register circuit also includes: The display reset circuit is connected to the display reset signal input terminal, the second power supply terminal, and the pull-up node, and is configured to write the invalid level signal provided by the second power supply terminal to the pull-up node in response to the control of the valid level signal provided by the sensing reset signal input terminal. A pull-down control circuit, connected to a second power supply terminal, an effective level supply terminal, the pull-up node, and the pull-down node, is configured to write a voltage at the pull-down node that is inversely phase to the voltage at the pull-up node; A pull-up noise reduction circuit is connected to the second power supply terminal, the pull-up node, and the pull-down node, and is configured to write an invalid level signal provided by the second power supply terminal to the pull-up node in response to the control of an effective level signal at the pull-down node. A global reset circuit, connected to a global reset signal input terminal, a second power supply terminal, and the pull-up node, is configured to write an invalid level signal provided by the second power supply terminal to the pull-up node in response to a valid level signal provided by the global reset signal input terminal. The drive output sub-circuit is also connected to the pull-down node and the fourth power supply terminal, and the drive output sub-circuit is further configured to write the inactive level signal provided by the fourth power supply terminal to the drive signal output terminal in response to the control of the active level signal at the pull-down node.

29. The shift register unit according to claim 28, wherein, The shift register circuit also includes: A first voltage control circuit is connected to a third power supply terminal, a pull-up node, and a first voltage control node. The first voltage control circuit is configured to write an effective level signal provided by the third power supply terminal to the first voltage control node in response to the control of an effective level signal at the pull-up node. The shift register circuit further includes at least one of a first leakage protection circuit, a second leakage protection circuit, and a third leakage protection circuit; The global reset circuit is connected to the second power supply terminal through the first leakage protection circuit. The global reset circuit and the first leakage protection circuit are connected to the first leakage protection node. The first leakage protection node is connected to the first voltage control node. The first leakage protection circuit is connected to the global reset signal input terminal. The first leakage protection circuit is configured to form a path between the first leakage protection node and the second power supply terminal in response to the control of the valid level signal provided by the global reset signal input terminal, and to disconnect the circuit between the first leakage protection node and the second power supply terminal in response to the control of the invalid level signal provided by the global reset signal input terminal. The display reset circuit is connected to the second power supply terminal through the second leakage protection circuit. The display reset circuit and the second leakage protection circuit are connected to the second leakage protection node. The second leakage protection node is connected to the first voltage control node. The second leakage protection circuit is connected to the display reset signal input terminal. The second leakage protection circuit is configured to form a path between the second leakage protection node and the second power supply terminal in response to the control of an effective level signal provided by the display reset signal input terminal, and to disconnect the circuit between the second leakage protection node and the second power supply terminal in response to the control of an ineffective level signal provided by the display reset signal input terminal. The pull-up noise reduction circuit is connected to the second power supply terminal through the third leakage protection circuit. The pull-up noise reduction circuit and the third leakage protection circuit are connected to the third leakage protection node. The third leakage protection node is connected to the first voltage control node. The third leakage protection circuit is connected to the pull-down node. The third leakage protection circuit is configured to form a path between the third leakage protection node and the second power supply terminal in response to the control of an effective level signal at the pull-down node, and to disconnect the circuit between the third leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the pull-down node.

30. A gate driving circuit, wherein, include: Multiple shift register units as described in any one of claims 1 to 29, wherein the multiple shift register circuits included in the multiple shift register units are cascaded.

31. The gate driving circuit according to claim 30, wherein, The shift register unit is the shift register unit of claim 4, and the gate drive circuit further includes: multiple clock supply signal lines capable of sequentially providing clock pulses; The drive clock signal input terminal of the drive output circuit is connected to the corresponding clock supply signal line; The first voltage regulator clock signal input terminal of the first voltage regulator sub-circuit is connected to the corresponding clock supply signal line.

32. The gate driving circuit according to claim 30, wherein, The shift register unit is the shift register unit of claim 9, and the gate drive circuit further includes: multiple clock supply signal lines capable of sequentially providing clock pulses; The drive clock signal input terminal of the drive output circuit is connected to the corresponding clock supply signal line; The second voltage regulator clock signal input terminal of the second voltage regulator sub-circuit is connected to the corresponding clock supply signal line.

33. A display panel, wherein, include: A substrate and a gate driving circuit located on the substrate, wherein the gate driving circuit employs any one of the gate driving circuits described in claims 30 to 32.

Images