Layout correction method, storage medium and terminal

Abstract

A layout correction method, storage medium, and terminal are disclosed. The layout correction method includes: providing an initial layout, the initial layout including several main graphics; generating several first auxiliary graphics in the initial layout using a rule-based auxiliary graphics generation method; performing iterative optical proximity correction on the main graphics, and optimizing the photolithography process window based on the auxiliary graphics during each optical proximity correction. Compared to a layout correction method based solely on rule-based insertion of sub-resolution auxiliary graphics, the photolithography process window of the layout correction is effectively improved by adding the photolithography process window optimization calculation based on the auxiliary graphics during each optical proximity correction. Compared to a layout correction method based on inversion lithography, the rule-based generation of several first auxiliary graphics and the avoidance of pixelation calculation during the photolithography process window optimization calculation based on the auxiliary graphics effectively improve the computational efficiency of the layout correction.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a layout correction method, storage medium and terminal. Background Art

[0002] Integrated circuit manufacturing is a complex process with rapid technological advancements. A key parameter characterizing integrated circuit manufacturing technology is the minimum feature size, or critical dimension (CD). As CDs shrink, even down to the nanometer level, it is precisely this reduction in CDs that makes it possible to place millions of devices on a single chip.

[0003] Photolithography is the driving force behind the development of integrated circuit manufacturing processes and is also one of the most complex technologies. Compared to other individual manufacturing technologies, improvements in photolithography are of great significance to the development of integrated circuits. Before the photolithography process begins, the pattern must first be copied onto a mask using a specific device. The photolithography equipment then generates light of a specific wavelength to copy the pattern structure on the mask onto the silicon wafer used to produce the chip. However, due to the shrinking size of semiconductor devices, distortion occurs during the process of transferring the pattern to the silicon wafer. Failure to eliminate this distortion can lead to the failure of the entire manufacturing process. Therefore, to address this issue, the mask can be subjected to optical proximity correction (OPC). Optical proximity correction involves pre-processing the photolithography mask before lithography, performing pre-modification so that the amount of compensation is just enough to compensate for the optical proximity effect caused by the exposure system.

[0004] However, there are still many problems with layout correction in the existing technology. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a layout correction method, storage medium and terminal to improve the lithography process window and calculation efficiency of layout correction.

[0006] To solve the above problems, the technical solution of the present invention provides a method for correcting a layout, comprising: providing an initial layout, wherein the initial layout includes several main graphics; using a rule-based auxiliary graphics generation method to generate several first auxiliary graphics in the initial layout, so that the initial layout forms an intermediate layout; performing iterative optical proximity correction on the main graphics, and performing optimization calculations on the lithography process window based on the auxiliary graphics during each optical proximity correction process, so that the intermediate layout forms a corrected layout.

[0007] Optionally, the method for performing optimization calculation of the photolithography process window based on the auxiliary pattern includes: adjusting the shape and position of the first auxiliary pattern.

[0008] Optionally, the method for adjusting the shape of the first auxiliary graphic includes: adjusting one or both of the length and width of the first auxiliary graphic.

[0009] Optionally, the method for adjusting the position of the first auxiliary pattern includes: adjusting the spacing between the first auxiliary pattern and the main pattern, or adjusting the spacing between adjacent first auxiliary patterns.

[0010] Optionally, the method for performing optimization calculation of the photolithography process window based on auxiliary patterns further includes: generating a plurality of second auxiliary patterns in the intermediate layout.

[0011] Optionally, both the first auxiliary graphic and the second auxiliary graphic are sub-resolution auxiliary graphics.

[0012] Optionally, the optical proximity correction includes: fragmented optical proximity correction.

[0013] Optionally, the method of performing the fragmented optical proximity correction on the main graphic includes: dividing each side length of the main graphic into a plurality of correction line segments; and translating each of the correction line segments along a direction perpendicular to the correction line segment.

[0014] Optionally, an evaluation function based on edge placement error guides the iterative correction direction of the fragmented optical proximity correction.

[0015] Optionally, an evaluation function based on the photolithography process variation bandwidth guides the iterative operation direction of the optimization operation of the photolithography process window.

[0016] Correspondingly, the technical solution of the present invention further provides a storage medium on which computer instructions are stored, and when the computer instructions are executed, the steps of the method described in any one of the above technical solutions are executed.

[0017] Correspondingly, the technical solution of the present invention also provides a terminal, including a memory and a processor, wherein the memory stores computer instructions that can be run on the processor, and when the processor runs the computer instructions, the steps of the method described in any one of the above technical solutions are executed.

[0018] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0019] In the layout correction method of the technical solution of the present invention, a rule-based auxiliary pattern generation method is used to generate several first auxiliary patterns in the initial layout, and during each optical proximity correction, an optimization calculation of the lithography process window is performed based on the auxiliary patterns. Compared with a layout correction method based solely on rule-based insertion of sub-resolution auxiliary patterns, the addition of an optimization calculation based on the auxiliary patterns during each optical proximity correction effectively improves the lithography process window of the layout correction. Compared with a layout correction method based on inversion lithography, the rule-based generation of several first auxiliary patterns and the avoidance of pixelated calculations during the auxiliary pattern-based lithography process window optimization calculation effectively improve the computational efficiency of the layout correction.

[0020] Furthermore, the optical proximity correction includes a fragmented optical proximity correction. Using the fragmented optical proximity correction to correct the main pattern avoids the use of a pixelated calculation method compared to layout correction methods based on inversion lithography, thereby further improving the calculation efficiency of layout correction. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 1 is a flow chart of a method for correcting a layout according to an embodiment of the present invention;

[0022] Figures 2 to 6 1 is a structural diagram of each step of the layout correction method in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] As described in the background art, there are still many problems with layout correction in the prior art, which will be described in detail below.

[0024] To increase pattern contrast during optical proximity correction (OPC), a target pattern and a sub-resolution assist feature (SRAF) are typically formed on a mask. The SRAF is a surrounding pattern that creates an optical proximity effect on the target pattern and is not formed on the wafer after exposure. Examples of SRAFs include stripes and boxes. In the prior art, an image plane is typically selected in the middle of the photoresist layer to collect wafer data. This is used to calibrate an OPC model for the main pattern. This calibrated model is then used to simulate exposure of the main pattern under normal conditions and the SRAF under overexposure conditions.

[0025] Currently, there are two general methods for inserting sub-resolution auxiliary graphics in the industry. One method is a rule-based insertion method. The process is generally to obtain a fixed rule for inserting sub-resolution auxiliary graphics through designed experiments, and the sub-resolution auxiliary graphics are inserted before running the optical proximity correction. The other method is to use inverse lithography technology (ILT) to obtain a liberalized rule for inserting sub-resolution auxiliary graphics during the operation. Among them, after the sub-resolution auxiliary graphics are inserted based on the rule, the main graphics are subjected to fragmented optical proximity correction iterative processing, and the shape and position of the sub-resolution auxiliary graphics are not changed during the fragmented optical proximity correction process. Based on inverse lithography technology, the main graphics and sub-resolution auxiliary graphics are pixelated and calculated, and multiple cost functions are used to correct the main graphics and sub-resolution auxiliary graphics. During the correction process, the sub-resolution auxiliary graphics will move in pixels.

[0026] However, the former layout correction method has limited ability to improve the lithography process window, but has a fast run time. The latter layout correction method can significantly improve the lithography process window, but the run time is too long.

[0027] On this basis, the present invention provides a layout correction method, storage medium, and terminal. These methods utilize a rule-based auxiliary pattern generation method to generate a plurality of first auxiliary patterns within the initial layout, and perform a photolithography process window optimization calculation based on the auxiliary patterns during each optical proximity correction. Compared to layout correction methods that solely insert sub-resolution auxiliary patterns based on rules, the addition of a photolithography process window optimization calculation based on the auxiliary patterns during each optical proximity correction effectively improves the photolithography process window of the layout correction. Compared to layout correction methods based on inversion lithography, the use of a rule-based method to generate the plurality of first auxiliary patterns and the avoidance of pixelated calculations during the photolithography process window optimization calculation based on the auxiliary patterns effectively improve the computational efficiency of layout correction.

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Figure 1 1 is a flow chart of a method for correcting a layout according to an embodiment of the present invention, comprising:

[0030] Step S101, providing an initial layout, wherein the initial layout includes a plurality of main graphics;

[0031] Step S102, generating a plurality of first auxiliary graphics in the initial layout using a rule-based auxiliary graphics generation method, so that the initial layout forms an intermediate layout;

[0032] Step S103 , performing an iterative optical proximity correction process on the main pattern, and performing an optimization calculation of the photolithography process window based on the auxiliary pattern during each optical proximity correction process, so that the intermediate layout forms a corrected layout.

[0033] The steps of the layout correction method are described in detail below with reference to the accompanying drawings.

[0034] Figures 2 to 6 1 is a structural diagram of each step of the layout correction method in an embodiment of the present invention.

[0035] Please refer to Figure 2 , providing an initial layout, which includes several main graphics 100.

[0036] It should be noted that, in this embodiment, the main pattern 100 is a pattern that can be exposed and developed onto a photoresist in a subsequent manufacturing process, and forms a pattern corresponding to an actual functional device on a wafer.

[0037] Please refer to Figure 3 , a rule-based auxiliary pattern generation method is used to generate a plurality of first auxiliary patterns 101 in the initial layout, so that the initial layout forms an intermediate layout.

[0038] It should be noted that the first auxiliary patterns 101 are inserted between the main patterns 100 using a rule-based auxiliary pattern (SRAF) generation method. This method uses empirically preset configuration rules, taking into account the position and shape of the gaps between the main patterns 100, as well as the number and corresponding positions of the first auxiliary patterns 101 to be inserted. After the first auxiliary patterns 101 are generated, the position between the first auxiliary patterns 101 and the main pattern 100 is detected; based on the detection results, the position and size of the first auxiliary patterns 101 are further adjusted.

[0039] In this embodiment, the first auxiliary pattern 101 is a Sub-Resolution Assist Feature (SRAF). A sub-resolution assist feature is a commonly used optical proximity correction method. By adding it near the main pattern 100 in the layout, it imparts the characteristics of dense patterns to even isolated and sparse patterns, thereby improving light intensity distribution and enhancing imaging quality. However, due to the small line width of the sub-resolution assist feature, the intensity of diffracted light at this feature is lower than the sensitivity threshold of the photoresist on the substrate (e.g., a silicon wafer), preventing the sub-resolution assist feature from being imaged.

[0040] Please refer to Figure 4 , performing optical proximity correction iterative processing on the main pattern 100, and performing optimization calculation of the photolithography process window based on the auxiliary pattern during each optical proximity correction process, so that the intermediate layout forms a corrected layout.

[0041] A rule-based auxiliary pattern generation method is used to generate a plurality of first auxiliary patterns 101 in the initial layout, and during each optical proximity correction, an optimization calculation of the lithography process window is performed based on the auxiliary patterns. Compared to a layout correction method based solely on rule-based insertion of sub-resolution auxiliary patterns, the addition of an optimization calculation based on the auxiliary patterns during each optical proximity correction effectively improves the lithography process window of the layout correction. Compared to a layout correction method based on inversion lithography, the rule-based generation of the plurality of first auxiliary patterns 101 avoids pixel-based calculations during the auxiliary pattern-based lithography process window optimization calculation, effectively improving the computational efficiency of the layout correction.

[0042] In this embodiment, the method for performing the optimization calculation of the photolithography process window based on the auxiliary pattern includes: adjusting the shape and position of the first auxiliary pattern 101 .

[0043] Please continue to refer to Figure 4 In this embodiment, the method of adjusting the shape of the first auxiliary graphic 101 includes: adjusting one or both of the length and width of the first auxiliary graphic 101.

[0044] Please continue to refer to Figure 4 In this embodiment, the method for adjusting the position of the first auxiliary graphic 101 includes: adjusting the spacing between the first auxiliary graphic 101 and the main graphic 100, or adjusting the spacing between adjacent first auxiliary graphics 101.

[0045] Please continue to refer to Figure 4In this embodiment, the method for optimizing the photolithography process window based on auxiliary patterns further includes: generating a plurality of second auxiliary patterns 102 in the intermediate layout.

[0046] In this embodiment, the second auxiliary pattern 102 is also a sub-resolution auxiliary pattern.

[0047] In this embodiment, the optical proximity correction adopts a fragmented optical proximity correction. Using the fragmented optical proximity correction to correct the main pattern 100 avoids the use of a pixelated calculation method compared to a layout correction method based on inversion lithography, thereby further improving the calculation efficiency of the layout correction.

[0048] In this embodiment, the method for performing the fragmented optical proximity correction on the main graphic 100 includes: dividing each side length of the main graphic 100 into a plurality of correction line segments (not labeled); and translating each of the correction line segments along a direction perpendicular to the correction line segment.

[0049] In this embodiment, the method of dividing each side of the main figure 100 into a plurality of correction line segments includes: setting a plurality of segmentation points (not shown) on each side of the main figure 100, and each adjacent segmentation point forms a correction line segment.

[0050] In this embodiment, an edge placement error (EPE cost function) is used to guide the iterative correction direction of the fragmented optical proximity correction, wherein the edge placement error cost function is:

[0051]

[0052] Among them, EPE n is the edge placement error corresponding to each of the correction line segments.

[0053] Please refer to Figure 5 In this embodiment, the method for obtaining the edge placement error of each correction line segment includes: obtaining an exposure pattern 103 corresponding to the main pattern 100 after the fragmented optical proximity correction; and comparing the exposure pattern 103 with the main pattern 100 in the initial layout to obtain the edge placement error. The two measurement points P1 for the edge placement error are the center point of each correction line segment in the main pattern 100 and a point on the exposure pattern 103 perpendicular to the correction line segment. The distance between the two measurement points P1 is the edge placement error.

[0054] It should be noted that, since the smaller the value of the edge placement error is, the higher the matching degree between the exposure pattern 103 and the main pattern 100 is, the value of the evaluation function of the edge placement error needs to be gradually reduced after each iterative process of optical proximity correction.

[0055] In this embodiment, the iterative operation direction of the optimization operation of the lithography process window is guided by an evaluation function based on the lithography process variation bandwidth (PV band cost function), wherein the evaluation function of the lithography process variation bandwidth is:

[0056]

[0057] Among them, PVband n is the photolithography process variation bandwidth corresponding to each correction line segment.

[0058] Please refer to Figure 6 In this embodiment, the method for obtaining the photolithography process variation bandwidth for each correction line segment includes: obtaining two worst-case exposure patterns of the main pattern 100 under deviating-from-optimal exposure conditions after the segmented optical proximity correction, namely, a first worst-case exposure pattern 104 under positive deviating-from-optimal exposure conditions and a second worst-case exposure pattern 105 under negative deviating-from-optimal exposure conditions; and comparing the first worst-case exposure pattern 104 with the second worst-case exposure pattern 105 to obtain the photolithography process variation bandwidth. The two measurement points P2 for the photolithography process variation bandwidth are the center point of each correction line segment in the main pattern 100 and points on the first worst-case exposure pattern 104 and the second worst-case exposure pattern 105 perpendicular to the correction line segment. The distance between the two measurement points P2 is the photolithography process variation bandwidth.

[0059] It should be noted that, since the smaller the value of the lithography process variation bandwidth is, the higher the lithography process window is, the value of the evaluation function of the lithography process variation bandwidth needs to be gradually reduced after each optimization operation of the lithography process window.

[0060] Correspondingly, an embodiment of the present invention further provides a storage medium on which computer instructions are stored. When the computer instructions are executed, the steps of the method described in any one of the above embodiments are executed.

[0061] Correspondingly, an embodiment of the present invention further provides a terminal, including a memory and a processor, wherein the memory stores computer instructions that can be run on the processor, and when the processor runs the computer instructions, the steps of the method described in any one of the above embodiments are executed.

[0062] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for correcting a layout, characterized in that: include: Providing an initial layout, wherein the initial layout includes a plurality of main graphics; Generating a plurality of first auxiliary graphics in the initial layout using a rule-based auxiliary graphics generation method, so that the initial layout forms an intermediate layout; The main pattern is subjected to an iterative optical proximity correction process, and during each optical proximity correction process, an optimization calculation of the photolithography process window is performed based on the auxiliary pattern, so that the intermediate layout forms a corrected layout.

2. The method for correcting a layout according to claim 1, wherein: The method for optimizing the photolithography process window based on the auxiliary pattern includes adjusting the shape and position of the first auxiliary pattern.

3. The method for correcting a layout according to claim 2, wherein: The method of adjusting the shape of the first auxiliary pattern includes adjusting one or both of a length and a width of the first auxiliary pattern.

4. The method for correcting a layout according to claim 2, wherein: The method for adjusting the position of the first auxiliary pattern includes: adjusting the distance between the first auxiliary pattern and the main pattern, or adjusting the distance between adjacent first auxiliary patterns.

5. The method for correcting a layout according to claim 2, wherein: The method for performing optimization calculation of the photolithography process window based on auxiliary patterns further includes: generating a plurality of second auxiliary patterns in the intermediate layout.

6. The method for correcting a layout according to claim 5, wherein: Both the first auxiliary pattern and the second auxiliary pattern are sub-resolution auxiliary patterns.

7. The method for correcting a layout according to claim 1, wherein: The optical proximity correction includes: fragmented optical proximity correction.

8. The method for correcting a layout according to claim 7, wherein: The method for performing the fragmented optical proximity correction on the main graphic includes: dividing each side length of the main graphic into a plurality of correction line segments; and performing translation processing on each correction line segment along a direction perpendicular to the correction line segment.

9. The method for correcting a layout according to claim 8, wherein: An evaluation function based on edge placement error guides the iterative correction direction of the segmented optical proximity correction.

10. The method for correcting a layout according to claim 1, wherein: An evaluation function based on the photolithography process variation bandwidth guides the iterative operation direction of the optimization operation of the photolithography process window.

11. A storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed, the steps of the method according to any one of claims 1 to 10 are executed.

12. A terminal comprising a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, characterized in that: When the processor runs the computer instructions, the steps of the method according to any one of claims 1 to 10 are performed.

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