A low-power neuron circuit supporting multiple coding modes

Abstract

This invention relates to a low-power neuron circuit supporting multiple encoding methods. The neuron circuit includes a two-stage sensitive amplifier structure and corresponding logic control circuitry. Specifically, the input pulse signal generates an enable signal for the first-stage sensitive amplifier through delay control. The first-stage sensitive amplifier compares the neuron membrane capacitance potential Vmem with the first-stage threshold voltage Vrefs to determine whether to generate an enable signal for the second-stage sensitive amplifier. The output of the second-stage sensitive amplifier generates an output pulse signal through an SR latch. Further, the output pulse signal controls the resetting of the neuron based on the current input configuration signal. Compared with existing technologies, this invention has the advantages of low power consumption and support for multiple encoding methods.

Description

Technical Field

[0001] This invention relates to the field of neuronal circuits, and in particular to a low-power neuronal circuit that supports multiple encoding methods. Background Technology

[0002] Deep learning, based on artificial neural networks, has demonstrated wide applications across various fields. However, high-performance learning algorithms rely on extremely large network sizes and massive storage and computational costs. Therefore, while pursuing high-performance AI chips, the industry has proposed spiking neural networks, which more closely resemble biological behavioral characteristics. Spiking neural networks use relatively sparse pulse signals for transmission and computation, offering greater potential for improving the energy efficiency of algorithms.

[0003] As a key component of spiking neural networks, neurons produce different responses to input pulses based on different dynamic models. Current spiking neural networks generally employ a simple LIF (Leakage, Integration, Pulse Firing) model as the behavioral characteristics of neurons. In terms of implementation, while neurons based on digital circuit design can accommodate a variety of flexible behavioral models, they have higher circuit area overhead and greater circuit control complexity than analog neurons.

[0004] Neurons implemented using purely analog circuits face challenges in design and power consumption as the complexity of neuron functionality increases. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low-power neuron circuit that supports multiple encoding methods.

[0006] The objective of this invention can be achieved through the following technical solutions:

[0007] This invention provides a low-power neuron circuit that supports multiple encoding methods. The neuron circuit includes a two-stage sensitive amplifier structure and corresponding logic control circuitry, specifically:

[0008] The input pulse signal generates an enable signal for the first-stage sensitive amplifier through delay control. The first-stage sensitive amplifier compares the potential Vmem of the neuron membrane capacitance with the threshold voltage Vrefs of the first-stage sensitive amplifier to determine whether to generate an enable signal for the second-stage sensitive amplifier.

[0009] When the enable signal of the second-stage sensitive amplifier is valid, the second-stage sensitive amplifier compares the potential Vmem of the neuron membrane capacitance with the second-stage threshold voltage Vref. The output of the second-stage sensitive amplifier is stored through the SR latch and determines whether to generate an output pulse signal. The output pulse signal and the input configuration signal are controlled by the logic control circuit to control the reset behavior of the neuron.

[0010] Preferably, the threshold voltage Vrefs of the first sensitive amplifier is lower than the threshold voltage Vref of the second sensitive amplifier.

[0011] Preferably, the neuron circuit further includes an input configuration signal that controls the Leaky behavior of the neuron through a logic control circuit; wherein, the Leaky behavior of the neuron is characterized by multiple sets of gate voltage adjustable transmission gates, and the time constant for the neuron membrane potential to recover to Vb under the action of an external power supply can be flexibly configured; the enabling and shielding of the Leaky behavior of the neuron is regulated by the input configuration signal.

[0012] Preferably, the control logic of the neuron circuit is as follows:

[0013] The interface between the neuron circuit and the external circuit includes an input pulse terminal, a potential terminal of the membrane capacitor, and an output pulse terminal.

[0014] When the input pulse terminal generates a pulse signal, the external synaptic circuit performs an integration operation on the potential node of the membrane capacitor, causing a certain potential rise or fall; after the integration operation is completed, the sensitive amplifier is triggered to compare the membrane potential and the threshold voltage, and to determine whether the neuron has fired a pulse.

[0015] Preferably, the input configuration signals include a global reset signal Reset, an on-chip training enable signal Train, and an encoding control signal Type; the output signals of the logic control circuit include OnR and Leak_en signals;

[0016] When the global reset signal Reset is valid, the membrane potential is reset to Vb, and the output pulse signal is low.

[0017] When the on-chip training enable signal Train is active, the Leak_en signal shuts down the Leaky circuit M0, thus blocking the Leaky behavior of the neuron.

[0018] The encoding control signal Type determines the encoding method of the current neural network.

[0019] Preferably, the encoding method includes frequency encoding and time encoding.

[0020] Preferably, the frequency encoding method is as follows: under the frequency encoding system, after the neuron fires a pulse, its membrane potential is immediately reset and it waits for the next input pulse signal.

[0021] Preferably, the time encoding method is as follows: under the time encoding system, after the neuron fires a pulse, it will block the input pulse signal for a period of time and wait for the global reset signal Reset to wake it up.

[0022] Preferably, the shielding of the input pulse signal during the subsequent period is specifically controlled by switch W0 and pull-down transistor N0.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] 1) The two-stage sensitive amplifier structure enables the neuron circuit to maintain low power consumption in networks containing sparse events.

[0025] 2) By configuring external signals, this neuron circuit can respond to pulse signals with two different encoding methods;

[0026] 3) During on-chip training of the network, the control logic circuit inside the neuron will adjust the LIF behavior to assist the external circuit in updating the weights. Attached Figure Description

[0027] Figure 1 The diagram shows the structure of a LIF neuron circuit based on a two-stage sensitive amplifier.

[0028] Figure 2 A schematic diagram of key signal waveforms under frequency coding configuration;

[0029] Figure 3 A schematic diagram of the key signal waveforms under time-coding configuration;

[0030] Figure 4 This diagram illustrates a power consumption comparison between a traditional neuron circuit and this circuit under different weight sparsity conditions. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0032] Example

[0033] This embodiment presents a low-power neuron circuit that supports multiple encoding schemes. By configuring external signals, the neuron circuit can respond to pulse signals with two different encoding schemes; a two-stage sensitive amplifier structure enables the neuron circuit to maintain low power consumption in networks containing sparse events; furthermore, during on-chip training of the network, the control logic circuitry inside the neuron adjusts the LIF behavior, assisting the external circuitry in updating the weights.

[0034] The neuron circuit consists of a two-stage sensitive amplifier structure S0-S1 and a corresponding logic control circuit M1. The input pulse ispike signal generates an enable signal CLK for the first-stage sensitive amplifier S0 through delay control. S0 compares the potential Vmem of the neuron membrane capacitance Cmem with a small threshold voltage Vrefs to determine whether to generate an enable signal for the second-stage sensitive amplifier S1.

[0035] The output of the second-stage sensitive amplifier S1 generates an output pulse oSpike through the SR latch M2. Finally, the oSpike signal, along with the input configuration signals Train, Type, and Reset, is processed by the logic control circuit M1 to generate the OnR signal, which controls the reset of the neuron (pull-up transistor P0).

[0036] The transistor constituting the sensitive amplifier S1 has a larger size than S0; the offset voltage of S1 is lower than that of S0; and the power consumption of S1 is greater than that of S0. The representation of neuronal Leaky behavior is composed of multiple sets of gate-voltage-adjustable transmission gates T0-T1. External input configuration signals Train and Type can enable and disable neuronal Leaky behavior. Furthermore, under the influence of external power supplies LP and LN, the time constant for the neuronal membrane potential to recover to Vb can be flexibly configured.

[0037] Control method: The interface between this neuron circuit and the external circuit is manifested at the input pulse iSpike terminal, the Vmem terminal of the Cmem membrane capacitor, and the output pulse oSpike terminal. When iSpike generates a pulse signal, the external synaptic circuit performs an integration operation on the Vmem node of the Cmem membrane capacitor, causing a certain potential rise and fall. After the integration operation is completed, the CLK signal is enabled, controlling a two-stage sensitive amplifier to compare the membrane potential Vmem with the threshold voltage and determine whether the neuron should fire a pulse (fire operation).

[0038] Among them, the input configuration signal Reset is a global reset signal. When this signal is valid, the membrane potential Vmem is reset to Vb, and the oSpike output is low. The input configuration signal Train is an on-chip training enable signal. When this signal is valid, the Leak_en signal turns off the Leaky circuit M0, blocking the Leaky behavior of the neuron. The input configuration signal Type is a 1-bit encoding control signal. This signal determines the encoding method of the current neural network: in the frequency encoding system, after the neuron fires, its membrane potential Vmem is immediately reset and waits for the next input pulse iSpike; in the time encoding system, after the neuron fires, it blocks the input pulse iSpike for a period of time (controlled by switch W0 and pull-down transistor N0) and waits for the Reset signal to wake it up.

[0039] The two-stage sensitive amplifier structure of the neuron circuit can meet the low-power requirements of sparse network operation. By setting the value of Vrefs to be less than the threshold voltage Vref for neuron firing pulses, the circuit only activates the low-power sensitive amplifier S0 when most pulses are not fired (membrane potential Vmem does not reach Vrefs). Compared with a neuron circuit composed of a single stage S1, this structure has higher energy efficiency in overall network operation. In addition, the low quiescent power of the sensitive amplifier also gives this neuron circuit a significant advantage compared with analog neuron circuits composed of operational amplifiers.

[0040] The introduction of input configuration signals increases the flexibility of this neuron circuit in network applications. While supporting two different encoding methods, it also provides some reference value for the future development of on-chip learning of spiking neural networks.

[0041] Figure 1 The structure diagram of the LIF neuron circuit based on a two-stage sensitive amplifier is given; Figure 2 A waveform diagram of the key signal under frequency encoding is given; Figure 3 A waveform diagram of the key signal under the time-coding configuration is given; Figure 4 The power consumption of traditional neural circuits and this circuit is compared under different weight sparsity conditions.

[0042] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low-power neuron circuit supporting multiple encoding methods, characterized in that, The neuron circuit includes a two-stage sensitive amplifier structure and corresponding logic control circuitry, specifically: The input pulse signal generates an enable signal for the first-stage sensitive amplifier through delay control. The first-stage sensitive amplifier compares the potential Vmem of the neuron membrane capacitance with the first-stage threshold voltage Vrefs to determine whether to generate an enable signal for the second-stage sensitive amplifier. When the enable signal of the second-stage sensitive amplifier is valid, the second-stage sensitive amplifier compares the potential Vmem of the neuron membrane capacitance with the second-stage threshold voltage Vref. The output of the second-stage sensitive amplifier is stored through the SR latch and determines whether to generate an output pulse signal. The output pulse signal and the input configuration signal are controlled by the logic control circuit to control the reset behavior of the neuron. The control logic of the neuron circuit is specifically as follows: The interface between the neuron circuit and the external circuit includes an input pulse terminal, a potential terminal of the membrane capacitor, and an output pulse terminal. When the input pulse terminal generates a pulse signal, the external synaptic circuit performs an integration operation on the potential node of the membrane capacitor, causing it to generate a certain potential rise or fall. After the integration operation is completed, the sensitive amplifier is triggered to compare the membrane potential and the threshold voltage and to determine whether the neuron has fired a pulse. The input configuration signals include a global reset signal Reset, an on-chip training enable signal Train, and an encoding control signal Type; the output signals of the logic control circuit include OnR and Leak_en signals. When the global reset signal Reset is valid, the membrane potential is reset to Vb, and the output pulse signal is low. When the on-chip training enable signal Train is active, the Leak_en signal shuts down the Leaky circuit M0, thus blocking the Leaky behavior of the neuron. The encoding control signal Type determines the encoding method of the current neural network; The encoding methods include frequency encoding and time encoding; The frequency encoding method is as follows: In the frequency encoding system, after the neuron fires a pulse, its membrane potential is immediately reset and it waits for the next input pulse signal to arrive. The time encoding method is as follows: In the time encoding system, after the neuron fires a pulse, it will block the input pulse signal for a period of time and wait for the global reset signal Reset to wake it up.

2. The low-power neuron circuit supporting multiple encoding methods according to claim 1, characterized in that, The transistor size of the second-stage sensitive amplifier is larger than that of the first-stage sensitive amplifier, and the power consumption of the second-stage sensitive amplifier is greater than that of the first-stage sensitive amplifier; the offset voltage of the second-stage sensitive amplifier is lower than that of the first-stage sensitive amplifier.

3. A low-power neuron circuit supporting multiple encoding methods according to claim 1, characterized in that, The threshold voltage Vrefs of the first-stage sensitive amplifier is lower than the threshold voltage Vref of the second-stage sensitive amplifier.

4. A low-power neuron circuit supporting multiple encoding methods according to claim 1, characterized in that, The neuron circuit also includes an input configuration signal that controls the neuron's Leaky behavior via a logic control circuit; wherein, the neuron's Leaky behavior is characterized by multiple sets of gate voltage adjustable transmission gates, and the time constant for the neuron's membrane potential to recover to Vb under the action of an external power supply can be flexibly configured; the enabling and disabling of the neuron's Leaky behavior is regulated by the input configuration signal.

5. A low-power neuron circuit supporting multiple encoding methods according to claim 1, characterized in that, The input pulse signal is shielded for a period of time thereafter, specifically controlled by switch W0 and pull-down transistor N0.

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