Classification method and related device of quantum graph neural network based on hardware adaptation

Abstract

The embodiment of the present application discloses a classification method and related device based on a hardware-adapted quantum graph neural network, the method includes transferring the node information and edge information of the graph into the hardware-adapted quantum graph neural network to realize the classification of the graph, the hardware-adapted quantum graph neural network includes a first variational quantum circuit for extracting node features according to the node information and a second variational quantum circuit for extracting edge features according to the edge information, the node features and the edge features are used to classify the graph, and the first variational quantum circuit and the second variational quantum circuit are connected by a direct product and a weakly coupled bit gate. The use of the embodiment of the present application is conducive to fully adapting to real quantum chips and solving large-scale graph classification problems.

Description

Technical Field

[0001] The present invention relates to the field of quantum computing technology, and in particular to a classification method and related devices of quantum graph neural networks based on hardware adaptation. Background Art

[0002] Graph classification is the task of classifying nodes or subgraphs in graph structured data. It has wide applications in many fields, such as social network analysis, bioinformatics, recommendation systems, and network security. Machine learning algorithms for solving graph classification problems are mainly based on feature extraction and traditional classifiers, including support vector machines, random forests, K-nearest neighbor algorithms, and graph kernel methods. However, due to the inability to efficiently utilize the structural information of the graph, these methods are unable to cope with large-scale, complex topology graph classification problems.

[0003] The potential exponential acceleration advantage of quantum computing has given people great hope for breaking through the bottleneck of classical machine learning, and has become a very promising method for solving big data classification problems in the future. However, the efficient combination of machine learning and quantum computing cannot be achieved overnight. The design and production of quantum computers are very complex. Fault-tolerant quantum computers can fully utilize the computing power advantages of quantum computing, but they still have a long way to go before they mature. The number of bits in current quantum computers is limited, and the current quantum machine learning algorithms have only been verified by small-scale simulation experiments on real quantum machines, and have encountered difficulties in expanding to medium-scale or even large-scale experiments. Summary of the invention

[0004] The embodiments of the present application provide a classification method and related devices of a quantum graph neural network based on hardware adaptation, which are conducive to fully adapting to real quantum chips and solving large-scale graph classification problems.

[0005] The first aspect of the embodiment of the present application provides a classification method of a quantum graph neural network based on hardware adaptation, the method comprising:

[0006] The node information and edge information of the graph are passed into a hardware-adapted quantum graph neural network to achieve graph classification. The hardware-adapted quantum graph neural network includes a first variational quantum circuit for extracting node features based on the node information and a second variational quantum circuit for extracting edge features based on the edge information. The node features and the edge features are used to classify the graph. The first variational quantum circuit and the second variational quantum circuit are connected via a direct product and a weakly coupled bit gate.

[0007] Based on the above scheme, the first variational quantum circuit and the second variational quantum circuit are connected through direct products and weakly coupled bit gates, which increases the separability of the first variational quantum circuit and the second variational quantum circuit, so that the first variational quantum circuit and the second variational quantum circuit can be run on different real quantum computers. This distributed processing method is conducive to breaking through the limitation of the number of bits in current real quantum computers, fully adapting to real quantum chips, and solving large-scale graph classification problems.

[0008] In combination with the first aspect, in some descriptions of the first aspect, the first variational quantum circuit includes a node data encoding circuit and a node feature extraction circuit, and the second variational quantum circuit includes an edge data encoding circuit and an edge feature extraction circuit;

[0009] Among them, the node data encoding circuit and the edge data encoding circuit are connected through a direct product and a weakly coupled bit gate; and / or, the node feature encoding circuit and the edge feature encoding circuit are connected through a direct product and a weakly coupled bit gate.

[0010] In combination with the first aspect, in certain descriptions of the first aspect, the hardware-adapted quantum graph neural network also includes a dedicated simulated circuit, which is used to update node features layer by layer and capture the interactions and connection relationships between nodes. The dedicated simulated circuit is also internally connected through direct products and weakly coupled bit gates.

[0011] In combination with the first aspect, in some descriptions of the first aspect, the first quantum circuit includes a first quantum logic gate and a second quantum logic gate acting on a first quantum bit set, the second quantum circuit includes a third quantum logic gate and a fourth quantum logic gate acting on a second quantum bit set, the first quantum logic gate and the third quantum logic gate have the same action sequence, the second quantum logic gate and the fourth quantum logic gate have the same action sequence, and the weakly coupled bit gates each act on a quantum bit in the first quantum bit set and the second quantum bit set;

[0012] Wherein, the first quantum circuit is a node data encoding circuit, and the second quantum circuit is an edge data encoding circuit;

[0013] And / or, the first quantum circuit is a node feature extraction circuit, and the second quantum circuit is an edge feature extraction circuit;

[0014] And / or, the first quantum circuit is a first sub-proposed circuit inside the dedicated proposed circuit, and the second quantum circuit is a second sub-proposed circuit inside the dedicated proposed circuit.

[0015] In combination with the first aspect, in some descriptions of the first aspect, the method further includes:

[0016] Circuit cutting is performed according to the weakly coupled bit gate to obtain the first quantum circuit and the second quantum circuit, wherein the quantum state of the quantum bit at the cutting position is ρ=<0|ρ|0>|0><0|+<1|ρ|1>|1><1|.

[0017] In combination with the first aspect, in some descriptions of the first aspect, before the node information and edge information of the graph are transmitted to the hardware-adapted quantum graph neural network to implement graph classification, the method further includes:

[0018] The node information of the graph is compressed by using the T-distributed random neighbor embedding algorithm to obtain compressed node information; and the edge information of the graph is compressed by using the spectral clustering algorithm to obtain compressed edge information;

[0019] And / or, performing a sparse operation on the structural data of the graph through random sampling, threshold screening and maximum degree restriction technology to obtain a graph with reduced structural data, wherein the structural data of the graph includes node information and edge information.

[0020] In combination with the first aspect, in some descriptions of the first aspect, the step of transferring the node information and edge information of the graph to the hardware-adapted quantum graph neural network to implement graph classification includes:

[0021] The node information and edge information of the graph are passed into the hardware-adapted quantum graph neural network to obtain the target node features output by the hardware-adapted quantum graph neural network;

[0022] Globally aggregating the target node features according to the readout function to obtain the global features of the graph;

[0023] The global features of the graph are input into a multi-layer perceptron, and the graph is classified according to the prediction value output by the multi-layer perceptron.

[0024] A second aspect of an embodiment of the present application provides a classification device based on a quantum graph neural network adapted by hardware, the device comprising:

[0025] A classification unit is used to pass the node information and edge information of the graph into a hardware-adapted quantum graph neural network to achieve graph classification. The hardware-adapted quantum graph neural network includes a first variational quantum circuit for extracting node features based on the node information and a second variational quantum circuit for extracting edge features based on the edge information. The node features and the edge features are used to classify the graph. The first variational quantum circuit and the second variational quantum circuit are connected via a direct product and a weakly coupled bit gate.

[0026] A third aspect of the embodiments of the present application provides an electronic device, including: a processor and a memory;

[0027] The processor is connected to the memory, wherein the memory is used to store a computer program, and the processor is used to call the computer program to execute the method in the first aspect of the embodiment of the present application.

[0028] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. The computer program includes program instructions. When the program instructions are executed by a processor, the method in the first aspect of the embodiment of the present application is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 An example system block diagram of a classification method based on a quantum graph neural network adapted for hardware according to an embodiment of the present application is shown;

[0031] Figure 2 A schematic diagram of the structure of a variational quantum circuit included in a quantum graph neural network provided by one embodiment of the present application is shown;

[0032] Figure 3 A schematic diagram of a process flow of a classification method of a quantum graph neural network based on hardware adaptation provided by an embodiment of the present application is shown;

[0033] Figure 4 A schematic diagram of the structure of a quantum circuit connected by direct product and weakly coupled bit gates provided by an embodiment of the present application is shown;

[0034] Figure 5 A schematic diagram of the structure of a quantum graph neural network connected by direct product and weakly coupled bit gates provided by one embodiment of the present application is shown;

[0035] Figure 6 A schematic diagram of the structure of a classification device based on a quantum graph neural network adapted by hardware provided in one embodiment of the present application is shown;

[0036] Figure 7 A schematic diagram of the structure of a computer device provided in one embodiment of the present application is shown. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0038] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches that drive the functions of a classical computer. If there are n bits of data, there are 2n possible classical states, and one state is represented at a time.

[0039] Quantum computers use quantum processors that operate on data represented by quantum bits, also known as qubits. A qubit can represent the classical binary state "0", "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can represent both the "0" and "1" states at the same time. For example, if there are n bits of data, then 2 n Quantum states can be represented simultaneously. Further, qubits in superposition can be related to each other, known as entanglement, where the state of one qubit (whether it is 1 or 0 or both) can depend on the state of another qubit, and more information can be encoded within the two entangled qubits. Based on the principles of superposition and entanglement, qubits can enable quantum computers to perform functions that may be relatively complex and time-consuming for classical computers.

[0040] Please refer to Figure 1 , which shows an example system block diagram of a classification method based on hardware adaptation of a quantum graph neural network provided by an embodiment of the present application. System 100 may be a hybrid computing system including a combination of one or more quantum computers, quantum systems and / or classical computers. Figure 1 In the example shown, system 100 may include a quantum system 110 and a classical computer 120. In one embodiment, quantum system 110 and classical computer 120 may be configured to communicate via one or more of a wired connection and / or a wireless connection (e.g., a wireless network). Quantum system 110 may include a quantum chipset consisting of one or more quantum chips, which includes various hardware components for processing data encoded in quantum bits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chip from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that may degrade the performance of the quantum chip. Classical computer 120 may be electronically integrated with quantum system 110 via any suitable wired and / or wireless electronic connection.

[0041] exist Figure 1 In the example shown, quantum system 110 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, such as quantum gate operations, manipulate the quantum states of quantum bits to evolve and / or entangle. Figure 1 In the example embodiment shown, the quantum system 110 may include a measurement and control integrated machine 111, an interface 112, and a quantum chip 113. In some embodiments, all or part of each of the measurement and control integrated machine 111, the interface 112, and the quantum chip 113 may be located in a cryogenic environment to help perform quantum operations. The quantum chip 113 may be any hardware capable of processing information using quantum states. The hardware may include a plurality of qubits and a device for coupling or entanglement of the qubits so as to process information using quantum states. Qubits may include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip may include a set of quantum logic gates configured to perform quantum logic operations on qubits stored in a quantum register. The quantum gate may include one or more single-qubit gates, dual-qubit gates, and / or other multi-qubit gates.

[0042] The measurement and control integrated machine 111 can be any combination of digital computing devices capable of performing quantum computing (e.g., executing quantum circuits) in combination with the interface 112. The digital computing device may include a digital processor and memory for storing and executing quantum instructions using the interface 112. The digital computing device may also include a communication protocol device for receiving instructions and sending the results of the quantum computing performed to a classical computer. In addition, the digital computing device may also include a communication interface with an interface 112. In one embodiment, the measurement and control integrated machine 111 may be configured to receive classical instructions (e.g., from a classical computer 120) and convert the classical instructions into measurement and control instructions for the interface 112. The measurement and control instructions provided to the interface 112 by the measurement and control integrated machine 111 may be, for example, digital signals indicating which quantum gates in the quantum gate need to act on the quantum bit to perform a specific function. The interface 112 may be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses), which may be used to apply quantum gates on the quantum bit to manipulate the interaction between the quantum bits.

[0043] The interface 112 may be a classical-quantum interface, including a device combination capable of receiving instructions from the measurement and control integrated machine 111 and converting the instructions into a device for implementing quantum operations. In one embodiment, the interface 112 may convert instructions from the measurement and control integrated machine 111 into a drive signal that can drive or manipulate a quantum bit, and / or act on a quantum gate on the quantum bit. In addition, the interface 112 may be configured to convert a signal received from the quantum chip 113 into a digital signal that can be processed and transmitted by the measurement and control integrated machine 111. The devices included in the interface 112 may include, but are not limited to, a digital-to-analog converter, an analog-to-digital converter, a waveform generator, an attenuator, an amplifier, an optical fiber, a laser, and a filter. The interface 112 may further include a circuit component configured to measure a plurality of quantum bits after the quantum gate acts, wherein the measurement may produce a result represented by a classical bit. Each measurement performed by the interface 112 may be read out to a device connected to the quantum system 110, such as a classical computer 120. The plurality of measurement results provided by the interface 112 may represent a probabilistic result.

[0044] The classical computer 120 can include hardware components such as a processor and a storage device (e.g., including a memory device and a classical register) for processing data encoded in classical bits. In one embodiment, the classical computer 120 can be configured to provide various control signals, instructions, and data encoded in classical bits to the quantum system 110. Further, the quantum state measured by the quantum system 110 can be read out by the classical computer 120, and the classical computer 120 can store the measured quantum state as a classical bit in a classical register. In one embodiment, the classical computer 120 can be any suitable combination of computer executable hardware and / or computer executable software capable of executing a preparation module 121 to perform quantum computing using data stored in a data storage module 122 as part of the construction and calculation. The data storage module 122 can be a repository for data to be analyzed using a quantum computing algorithm and the results of the analysis. The preparation module 121 can be a program or module capable of preparing classical data from the data storage module 122 as part of a quantum circuit implementation. The preparation module 121 can be instantiated as part of a larger algorithm, such as a function call of an application programming interface (API), or by parsing hybrid classical-quantum computing into aspects of quantum and classical computing. For example, the preparation module 121 can generate instructions for creating a quantum circuit using quantum gates. In an embodiment, such instructions can be stored by the measurement and control integrated machine 111, and components of the interface 112 can be instantiated to execute, so that the quantum operation of the quantum gate can be performed on the quantum chip 113.

[0045] The classical computer 120 may be a laptop computer, a desktop computer, a vehicle integrated computer, a smart mobile device, a tablet device, and / or any other suitable classical computing device. Additionally or alternatively, the classical computer 120 may also be operated as part of a cloud computing service model, such as software as a service (SaaS), platform as a service (PaaS), or infrastructure as a service (IaaS). The classical computer 120 may also be located in a cloud computing deployment model, such as a private cloud, a community cloud, a public cloud, or a hybrid cloud.

[0046] At present, there are some quantum machine learning algorithms for solving graph classification problems. They mainly map traditional machine learning algorithms into corresponding quantized versions, including Quantum Graph Kernel Method (QGKM), Quantum Graph Convolutional Neural Networks (QGCN) and Quantum Graph Neural Networks (QGNNs).

[0047] The patent with publication number CN115238852A discloses a quantum graph neural network and a method for implementing a quantum graph neural network. Please refer to Figure 2 , Figure 2 The schematic diagram of the structure of the variational quantum circuit included in the quantum graph neural network provided by one embodiment of the present application is shown. The variational quantum circuit includes a pair of circuits, and a first set of revolving gates (R x (θ1), R x (θ2), R x (θ3) and R x (θ4), R x (θ4), R x (θ6)), the first type of parameter used to characterize the node characteristic data is expressed in the form of the rotation angle of the first set of revolving doors. A controlled door (CR x (α1) and CR x (α2)), the controlled door arranged on one of the pair of lines is controlled by the other line, and the second type of parameter characterizing the edge feature data is expressed in the form of the rotation angle of the controlled door. A second set of revolving doors (R x (β1), R x (β2), R x (β3) and R x (β4), R x (β5), R x(β6)), the weight of the linear function that aggregates the node feature data of the adjacent nodes at both ends of each edge and the edge feature data of the edge itself, is expressed in the form of the rotation angle of the second set of revolving doors. Among them, θ1~θ6 and α1~α2 can be but not actively optimized, and β1~β6 need to be actively optimized.

[0048] The technical solution is used in the same variable quantum circuit to first pass through the first set of revolving doors (R x (θ1), R x (θ2), R x (θ3) and R x (θ4), R x (θ5), R x (θ6)) encodes the node information and then passes through the controlled gate (CR x (α1) and CR x (α2)) to encode the side information and finally pass through the second set of revolving doors (R x (β1), R x (β2), R x (β3) and R x (β4), R x (β5), R x (β6)) Extract node features and edge features.

[0049] This technical solution has the following disadvantages: first, encoding node information and edge information simultaneously in the same variational quantum circuit can save the number of bits, but it will increase the circuit depth, leading to the accumulation of logic gate errors, thereby reducing the accuracy of classification; second, encoding node information and edge information simultaneously in the same variational quantum circuit, the two different information are mixed together, which may lead to failure to converge, so it is impossible to determine the second set of revolving gates (R x (β1), R x (β2), R x (β3) and R x (β4), R x (β5), R x (β6)); Third, even if the optimal parameters can be obtained, the node features and edge features finally measured are entangled and cannot be separated and purified. Based on this, the present application provides a classification method based on hardware-adapted quantum graph neural network (Hardware-Adapt QGNN, HAQGNN).

[0050] Please refer to Figure 3 , which shows a flow chart of a classification method of a quantum graph neural network based on hardware adaptation provided by an embodiment of the present application. The method can be applied to a computer device, which refers to an electronic device with data calculation and processing capabilities. The method may include the following steps:

[0051] Step 301: The node information and edge information of the graph are passed into a hardware-adapted quantum graph neural network to realize graph classification. The hardware-adapted quantum graph neural network includes a first variational quantum circuit for extracting node features according to the node information and a second variational quantum circuit for extracting edge features according to the edge information. The node features and the edge features are used to classify the graph. The first variational quantum circuit and the second variational quantum circuit are connected via a direct product and a weakly coupled bit gate.

[0052] Among them, in graph structured data, nodes and edges are the basic components, which together constitute the data structure of the graph.

[0053] Nodes usually represent entities in a graph, such as users in a social network, atoms in a molecular structure, etc. Each node can carry certain attribute information, which is called node attributes or node information. Node information can be a scalar value, vector, or other form of data. Node information can be used to describe the characteristics of the node itself. For example, in a social network, a node may represent a person, so the node information may include information such as age, gender, and occupation. In some cases, a node may also have a label for classification tasks. For example, in a chemical molecule graph, nodes may represent different types of atoms, and each atom has a specific label to identify its type.

[0054] Edges represent connections or relationships between nodes. Edges can also carry attribute information, which is called edge attributes or edge information. Edge information can be used to describe the characteristics of the relationship between two nodes. For example, in a social network, an edge can represent the friendship between two people. Edge information may include information such as the strength of friendship and the frequency of interaction. Edges can also have weights, which represent the importance of the edge or the strength of the relationship between two nodes. In many application scenarios, the weight of an edge is very important information. For example, in the shortest path problem, the weight of an edge can represent the distance or cost.

[0055] The weakly coupled bit gate is a two-bit gate without variable parameters, for example, a CZ gate, a CNOT gate, a SWAP gate, etc.

[0056] Based on the above scheme, it can be seen that in the present application, the first variational quantum circuit is used to extract node features according to the node information, and the second variational quantum circuit is used to extract edge features according to the edge information. Two different variational quantum circuits are used to extract node features and edge features respectively, which can reduce the number of logic gates in a single variational quantum circuit, thereby reducing the depth of the variational quantum circuit, minimizing the accumulation of logic gate errors, thereby improving the accuracy of classification, and being more friendly to real quantum computers; secondly, two different variational quantum circuits are used to extract node features and edge features respectively, which facilitates the separate training of the two variational quantum circuits and is conducive to quickly determining the optimal value of the variable parameter; finally, two different variational quantum circuits are used to extract node features and edge features respectively, which facilitates the separation and purification of node features or edge features in the later stage.

[0057] At the same time, in order to further adapt to the characteristics of fewer quantum bits in real quantum computers, the first variational quantum circuit and the second variational quantum circuit are connected through direct products and weakly coupled bit gates, which increases the separability of the first variational quantum circuit and the second variational quantum circuit, so that the first variational quantum circuit and the second variational quantum circuit can be run on different real quantum computers. This distributed processing method is conducive to breaking through the limitations on the number of bits in current real quantum computers, fully adapting to real quantum chips, and solving large-scale graph classification problems.

[0058] In combination with the first aspect, in some descriptions of the first aspect, the first variational quantum circuit includes a node data encoding circuit and a node feature extraction circuit, and the second variational quantum circuit includes an edge data encoding circuit and an edge feature extraction circuit;

[0059] Among them, the node data encoding circuit and the edge data encoding circuit are connected through a direct product and a weakly coupled bit gate; and / or, the node feature encoding circuit and the edge feature encoding circuit are connected through a direct product and a weakly coupled bit gate.

[0060] Furthermore, the graph structure data G = (V, E) can be mapped to the quantum state |ψ G >, where V and E represent the node set and edge set of the graph structure data respectively. The node information of each node can be mapped to the quantum state |v>, and the edge information of each edge can be mapped to the quantum state |e>. The initial quantum state of the graph structure data can be expressed as:

[0061]

[0062] The above operations are based on the tensor product property of quantum states, which allows all node information or all edge information to be represented by quantum states and then directly producted into a quantum state to represent the node information corresponding to the node set or the edge information corresponding to the edge set. At the same time, it also allows different information (node ​​information and edge information) of graph structure data to be mapped to different quantum state spaces, and finally the tensor product operation is used to directly product various types of information into a quantum state representation. This method is naturally distributed and friendly, and is compatible with real quantum computers.

[0063] The data encoding circuit is used to encode the classical node information v and edge information e into quantum states |ψ G >, using the quantum state |ψ G > to represent node information and edge information. The encoding method can be Figure 2 The angle encoding method in the embodiment may also be an amplitude encoding method or other encoding methods. The angle encoding method is not limited to Figure 2 R in the embodiment x Door, can also be R y or R z .

[0064] Among them, the feature extraction circuit is used to encode the quantum state of node information or edge information |ψ G >Evolution, the quantum logic gate U(θ) determined by the optimal rotation parameter θ obtained through training is transformed from the quantum state |ψ G > extract features and discard redundant and invalid information for classification, thereby obtaining node features or edge features, which are represented by another quantum state |ψ(θ)>=U(θ)|ψ G >To indicate.

[0065] In order to extract the required target features from the output quantum state |ψ(θ)>, the observable O is introduced v and O e , corresponding to the nodes and edges of the graph respectively:

[0066]

[0067] By estimating the expected values ​​of these observables, we can obtain the node feature f v and edge feature f e .

[0068] Among them, feature encoding circuits can be connected through direct products and weakly coupled bit gates, feature extraction circuits can be connected through direct products and weakly coupled bit gates, or both can be connected through direct products and weakly coupled bit gates. This method can increase the separability of the circuits, allowing for distributed processing of the circuits, which is conducive to breaking through the current limit on the number of bits in real quantum computers, fully adapting to real quantum chips, and solving large-scale graph classification problems.

[0069] In combination with the first aspect, in certain descriptions of the first aspect, the hardware-adapted quantum graph neural network also includes a dedicated simulated circuit, which is used to update node features layer by layer and capture the interactions and connection relationships between nodes. The dedicated simulated circuit is also internally connected through direct products and weakly coupled bit gates.

[0070] Among them, the node characteristics of the dedicated proposed line are updated according to the following formula:

[0071]

[0072] in, and Respectively represent the node features of node v and node u in the l-th layer QGNN, |ψ> e U represents the connection relationship between node v and node u, and N(v) is the set of neighbor nodes of node v. (l) is a quantum circuit used to update the quantum state of the node. After l layers of updates, the final feature representation of each node can be obtained

[0073] Based on the above scheme, the dedicated proposed circuit can update node features layer by layer, capture the interaction and connection relationship between nodes, so that the obtained features can better restore the original graph structure data, so that when the classification is performed according to the features, the results are more accurate. In addition, the dedicated proposed circuit can also be connected through direct products and weakly coupled bit gates to increase the separability of the dedicated proposed circuit, so that the circuit can be distributedly processed, which is conducive to breaking through the current limit on the number of bits in real quantum computers and fully adapting to real quantum chips.

[0074] In combination with the first aspect, in some descriptions of the first aspect, the first quantum circuit includes a first quantum logic gate and a second quantum logic gate acting on a first quantum bit set, the second quantum circuit includes a third quantum logic gate and a fourth quantum logic gate acting on a second quantum bit set, the first quantum logic gate and the second quantum logic gate have the same action timing, the third quantum logic gate and the fourth quantum logic gate have the same action timing, and each weakly coupled bit gate acts on a quantum bit in the first quantum bit set and the second quantum bit set;

[0075] Wherein, the first quantum circuit is a node data encoding circuit, and the second quantum circuit is an edge data encoding circuit;

[0076] And / or, the first quantum circuit is a node feature extraction circuit, and the second quantum circuit is an edge feature extraction circuit;

[0077] And / or, the first quantum circuit is a first sub-proposed circuit inside the dedicated proposed circuit, and the second quantum circuit is a second sub-proposed circuit inside the dedicated proposed circuit.

[0078] like Figure 4 As shown, Figure 4 A schematic diagram of the structure of a quantum circuit connected by direct product and weakly coupled bit gates provided by an embodiment of the present application is shown. The first quantum circuit includes a first quantum logic gate U1 and a second quantum logic gate U3 acting on a first quantum bit set, and the second quantum circuit includes a third quantum logic gate U2 and a fourth quantum logic gate U4 acting on a second quantum bit set. The first quantum logic gate U1 and the third quantum logic gate U2 have the same action sequence, and the second quantum logic gate U3 and the fourth quantum logic gate U4 have the same action sequence. The weakly coupled bit gate ( Figure 4 The first quantum circuit may be a node data encoding circuit, and the second quantum circuit may be an edge data encoding circuit; and / or, the first quantum circuit may be a node feature extraction circuit, and the second quantum circuit may be an edge feature extraction circuit; and / or, the first quantum circuit may be a first sub-designed circuit inside a dedicated design circuit, and the second quantum circuit may be a second sub-designed circuit inside a dedicated design circuit. Figure 5 A schematic diagram of the structure of a quantum graph neural network connected by direct product and weakly coupled bit gates provided by an embodiment of the present application is shown. Figure 5 In the embodiment, the data encoding circuit, feature extraction circuit and dedicated proposed circuit are connected to each other through direct product and weakly coupled bit gates.

[0079] Based on the above scheme, different from Figure 2 The prior art in Figure 2 Although there is also a two-door CR x (α1) and CR x (α2), but the role of the double gate is to encode the side information, and the role of the double gate in this application is to connect two different lines; secondly, the positions of the two in the line are also different. The double gate in this application is located between the two lines, while Figure 2The double gate in is located after one of the circuits (node ​​information encoding circuit), or it constitutes a circuit itself (edge ​​information encoding circuit). This application can increase the splitability of the circuit, so that the circuit can be distributed and processed, which is conducive to breaking through the current limit on the number of bits in real quantum computers, fully adapting to real quantum chips, and solving large-scale graph classification problems.

[0080] In combination with the first aspect, in some descriptions of the first aspect, the method further includes:

[0081] Circuit cutting is performed according to the weakly coupled bit gate to obtain the first quantum circuit and the second quantum circuit, wherein the quantum state of the quantum bit at the cutting position is ρ=<0|ρ|0>|0><0|+<1|ρ|1>|1><1|.

[0082] When performing distributed processing on quantum circuits, it is necessary to cut the quantum circuits according to the positions of the weakly coupled bit gates. After cutting, the quantum state preparation and circuit operation of each sub-quantum circuit are performed separately, and then the results obtained from each operation are spliced ​​to obtain the final calculation result. Among them, the complete quantum channel splitting form is:

[0083] ρ=1 / 2[Tr(ρI)I+Tr(ρX)X+Tr(ρY)Y+Tr(ρZ)Z],

[0084] In the above formula, ρ represents the quantum state of the cutting bit position, and I, X, Y, and Z represent the observation matrix that ensures the completeness of the channel at the cutting position. Research has found that under the condition of meeting specific circuits and data structures, the above complete quantum channel can be simplified to:

[0085] ρ=<0|ρ|0>|0><0|+<1|ρ|1>|1><1|.

[0086] Based on the above scheme, under the premise of ensuring channel completeness, the number of channels is compressed exponentially, and the sampling complexity is reduced from O(4 k ) is reduced to O(1), and the number of sampling times required to recover the complete data can be reduced by reducing the completeness of the quantum channel. Through non-redundant sampling, the embodiment of the present application has the lowest algorithm complexity and the highest output data stability and fidelity.

[0087] In combination with the first aspect, in some descriptions of the first aspect, before the node information and edge information of the graph are transmitted to the hardware-adapted quantum graph neural network to implement graph classification, the method further includes:

[0088] The node information of the graph is compressed by using the T-distributed random neighbor embedding algorithm to obtain compressed node information; and the edge information of the graph is compressed by using the spectral clustering algorithm to obtain compressed edge information;

[0089] And / or, performing a sparse operation on the structural data of the graph through random sampling, threshold screening and maximum degree restriction technology to obtain a graph with reduced structural data, wherein the structural data of the graph includes node information and edge information.

[0090] Among them, the t-Distributed Stochastic Neighbor Embedding (t-SNE) algorithm is a nonlinear dimensionality reduction technique used to map high-dimensional data to lower dimensions for visualization. The cost function of the t-SNE algorithm can be expressed as:

[0091] C=∑ i KL(P i ||Q i )=∑ i ∑ j p j|i log(p j|i / p ji ),

[0092] Among them, KL(P i ||Q i ) is the KL divergence of node i, and the conditional probability p j|i represents the probability that node i chooses node j as a neighbor in the original graph structure, p ji is the probability between node i and node j in the low-dimensional space after dimensionality reduction by the t-SNE algorithm.

[0093] Among them, the spectral clustering algorithm is a clustering method based on the spectral graph theory in graph theory. It is mainly used to deal with problems that are difficult to solve with traditional clustering algorithms (such as K-means), especially when the data points are distributed in non-convex shapes or complex structures. The cost function of the spectral clustering algorithm can be expressed as:

[0094]

[0095] Among them, C i represents the i-th subgraph, x u and x v Represents the feature vector of node u and node v, and m is the number of subgraphs that need to be divided in the end.

[0096] Based on the above scheme, before the node information and edge information are passed into HAQGNN, the number of nodes is compressed by the t-SNE algorithm, and the number of edges is compressed by the spectral clustering algorithm. The number of nodes or edges in the graph can be reduced by deleting redundant nodes or edges, merging similar nodes or edges, etc., thereby reducing the number of bits used in the quantum graph neural network and saving hardware resources.

[0097] Furthermore, while reducing graph data, we can also introduce distributed computing-friendly ideas, perform sparse operations on graph structure data through random sampling, threshold screening, and maximum degree limit, and focus on optimizing nodes and edges that have no valid information and hinder distributed implementation. Finally, we output distributed-friendly reduced graph structure data.

[0098] In combination with the first aspect, in some descriptions of the first aspect, the step of transferring the node information and edge information of the graph to the hardware-adapted quantum graph neural network to implement graph classification includes:

[0099] The node information and edge information of the graph are passed into the hardware-adapted quantum graph neural network to obtain the target node features output by the hardware-adapted quantum graph neural network;

[0100] Globally aggregating the target node features according to the readout function to obtain the global features of the graph;

[0101] The global features of the graph are input into a multi-layer perceptron, and the graph is classified according to the prediction value output by the multi-layer perceptron.

[0102] In the field of graph neural networks and machine learning, the readout function refers to a function used to aggregate node features in a graph. Its function is to aggregate all node features in the graph into a vector representation of a fixed length, so that it can represent the information of the entire graph. For example:

[0103]

[0104] Among them, h G is the global feature of the graph, It is the target node feature output by the lth layer.

[0105] Among them, Multilayer Perceptron (MLP) is a feedforward neural network, which consists of an input layer, one or more hidden layers and an output layer. Each layer consists of multiple neurons (or nodes), and the neurons between adjacent layers are fully connected, which means that each neuron is connected to all neurons in the next layer, which can fit complex nonlinear relationships. For example:

[0106]

[0107] in, is the predicted value.

[0108] Figure 6 The schematic diagram of the structure of a classification device based on a hardware-adapted quantum graph neural network provided by an embodiment of the present application is shown. The device includes:

[0109] A classification unit 601 is used to pass the node information and edge information of the graph into a hardware-adapted quantum graph neural network to achieve graph classification. The hardware-adapted quantum graph neural network includes a first variational quantum circuit for extracting node features based on the node information and a second variational quantum circuit for extracting edge features based on the edge information. The node features and the edge features are used to classify the graph. The first variational quantum circuit and the second variational quantum circuit are connected via a direct product and a weakly coupled bit gate.

[0110] Figure 7 A structural schematic diagram of a computer device provided by an embodiment of the present application is shown, including a memory and a processor, the memory stores a computer program, and the processor implements the functions of a computer system of a classification method of a quantum graph neural network based on hardware adaptation in any of the above-mentioned embodiments when executing the computer program.

[0111] An embodiment of the present application also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a computer, the computer performs the functions of a computer system of the classification method based on hardware-adapted quantum graph neural network in any of the above embodiments.

[0112] An embodiment of the present application also provides a computer program product comprising instructions, which, when executed by a computer, enables the computer to perform the functions of a computer system of the classification method based on hardware-adapted quantum graph neural network in any of the above embodiments.

[0113] It should be understood that the specific examples in this application are only intended to help those skilled in the art to better understand the embodiments of the present application, rather than to limit the scope of the present invention.

[0114] It can be understood that in the various implementations of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of the present application.

[0115] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0116] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms of "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0117] It can be understood that the processor of the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method implementation can be completed by the hardware integrated logic circuit or software instructions in the processor. The above processor can be a general processor, a digital signal processor (DigitalSignal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiment of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor are combined and executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0118] It is understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0119] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0120] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0121] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0122] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0123] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0124] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of each implementation method of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0125] The above are only specific embodiments of the present application, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A classification method based on hardware-adapted quantum graph neural network, characterized in that: The method comprises: The node information and edge information of the graph are transmitted to a hardware-adapted quantum graph neural network to realize the classification of the graph, wherein the hardware-adapted quantum graph neural network includes a first variational quantum circuit for extracting node features according to the node information and a second variational quantum circuit for extracting edge features according to the edge information, wherein the node features and the edge features are used to classify the graph, and the first variational quantum circuit and the second variational quantum circuit are connected via a direct product and a weakly coupled bit gate; the weakly coupled bit gate is a two-bit gate without variable parameters; Wherein, the first variational quantum circuit is a node data encoding circuit, and the second variational quantum circuit is an edge data encoding circuit; And / or, the first variational quantum circuit is a node feature extraction circuit, and the second variational quantum circuit is an edge feature extraction circuit; And / or, the first variant quantum circuit is a first sub-planned circuit inside a dedicated planned circuit, and the second variant quantum circuit is a second sub-planned circuit inside a dedicated planned circuit.

2. The method according to claim 1, characterized in that The first variational quantum circuit includes a node data encoding circuit and a node feature extraction circuit, and the second variational quantum circuit includes an edge data encoding circuit and an edge feature extraction circuit; Among them, the node data encoding circuit and the edge data encoding circuit are connected through a direct product and a weakly coupled bit gate; and / or, the node feature extraction circuit and the edge feature extraction circuit are connected through a direct product and a weakly coupled bit gate.

3. The method according to claim 2, characterized in that The hardware-adapted quantum graph neural network also includes a dedicated simulated circuit, which is used to update node features layer by layer and capture the interactions and connection relationships between nodes. The dedicated simulated circuit is also internally connected through direct products and weakly coupled bit gates.

4. The method according to claim 3, characterized in that The first variational quantum circuit includes a first quantum logic gate and a second quantum logic gate acting on a first quantum bit set, and the second variational quantum circuit includes a third quantum logic gate and a fourth quantum logic gate acting on a second quantum bit set, the first quantum logic gate and the third quantum logic gate have the same action timing, the second quantum logic gate and the fourth quantum logic gate have the same action timing, and each weakly coupled bit gate acts on a quantum bit in the first quantum bit set and the second quantum bit set.

5. The method according to claim 4, characterized in that The method further comprises: According to the weakly coupled bit gate, circuit cutting is performed to obtain the first variational quantum circuit and the second variational quantum circuit, wherein the quantum state of the quantum bit at the cutting position is .

6. The method according to any one of claims 1 to 5, characterized in that: Before the node information and edge information of the graph are transmitted to the hardware-adapted quantum graph neural network to realize the classification of the graph, the method further includes: The node information of the graph is compressed by using the T-distributed random neighbor embedding algorithm to obtain compressed node information; and the edge information of the graph is compressed by using the spectral clustering algorithm to obtain compressed edge information; And / or, performing a sparse operation on the structural data of the graph through random sampling, threshold screening and maximum degree restriction technology to obtain a graph with reduced structural data, wherein the structural data of the graph includes node information and edge information.

7. The method according to any one of claims 1 to 5, characterized in that: The step of transferring the node information and edge information of the graph to the hardware-adapted quantum graph neural network to achieve graph classification includes: The node information and edge information of the graph are passed into the hardware-adapted quantum graph neural network to obtain the target node features output by the hardware-adapted quantum graph neural network; Globally aggregating the target node features according to the readout function to obtain the global features of the graph; The global features of the graph are input into a multi-layer perceptron, and the graph is classified according to the prediction value output by the multi-layer perceptron.

8. A classification device based on a hardware-adapted quantum graph neural network, characterized in that: The device comprises: A classification unit, used for transferring the node information and edge information of the graph into a hardware-adapted quantum graph neural network to realize the classification of the graph, wherein the hardware-adapted quantum graph neural network includes a first variational quantum circuit for extracting node features according to the node information and a second variational quantum circuit for extracting edge features according to the edge information, wherein the node features and the edge features are used to classify the graph, and the first variational quantum circuit and the second variational quantum circuit are connected via a direct product and a weakly coupled bit gate; the weakly coupled bit gate is a two-bit gate without variable parameters; Wherein, the first variational quantum circuit is a node data encoding circuit, and the second variational quantum circuit is an edge data encoding circuit; And / or, the first variational quantum circuit is a node feature extraction circuit, and the second variational quantum circuit is an edge feature extraction circuit; And / or, the first variant quantum circuit is a first sub-planned circuit inside a dedicated planned circuit, and the second variant quantum circuit is a second sub-planned circuit inside a dedicated planned circuit.

9. An electronic device, characterized in that: include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to call the computer program to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the method according to any one of claims 1 to 7 is executed.

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