Storage unit, memory and access method thereof, preparation method, and electronic device

Abstract

The present application provides a storage unit, a memory, an access method thereof, a preparation method, and an electronic device. The storage unit includes a first transistor and a second transistor; the first transistor is configured as a read transistor; the second transistor is configured as a write transistor; wherein the first transistor includes a first gate, a second gate, a first electrode, and a second electrode; the first transistor has two different threshold voltages, one threshold voltage corresponding to the first gate and the other threshold voltage corresponding to the second gate; the second transistor includes a third gate, a third electrode, and a fourth electrode; the first gate and the second gate are connected, and connected to the fourth electrode; the first electrode is connected to a read word line, and the second electrode is connected to a read bit line; the third gate is connected to a write word line, and the third electrode is connected to a write bit line. The present application can realize the storage and reading of various information.

Description

Technical Field

[0001] The present application relates to the field of memory, and more specifically, to a storage unit, a memory, an access method thereof, a preparation method thereof, and an electronic device. Background Art

[0002] Currently, DRAM (dynamic random access memory) scaling has reached a bottleneck. To achieve highly integrated DRAM devices, various new DRAM technologies have emerged, with oxide semiconductor DRAM and multi-bit DRAM memory being key areas of focus.

[0003] Traditional 2T0C DRAM memory can only store two types of information, "1" and "0", and cannot meet the future development direction of multi-bit DRAM memory. Summary of the Invention

[0004] The present application provides a storage unit, a memory, an access method thereof, a preparation method, and an electronic device.

[0005] In a first aspect, an embodiment of the present application provides a memory cell, comprising a first transistor and a second transistor;

[0006] The first transistor is configured as a read transistor;

[0007] The second transistor is configured as a write transistor;

[0008] The first transistor includes a first gate, a second gate, a first electrode, and a second electrode; the first transistor has two different threshold voltages, one threshold voltage corresponding to the first gate and the other threshold voltage corresponding to the second gate; the second transistor includes a third gate, a third electrode, and a fourth electrode;

[0009] The first gate of the first transistor is connected to the second gate of the first transistor, and is also connected to the fourth electrode of the second transistor; the fourth electrode serves as a storage node for storing a written storage signal;

[0010] A first electrode of the first transistor is connected to a read word line, and a second electrode of the first transistor is connected to a read bit line;

[0011] The third gate of the second transistor is connected to the write word line, and the third electrode of the second transistor is connected to the write bit line;

[0012] a second transistor, configured to be turned on based on a first voltage of the write word line during a write operation, so that a storage signal on the write bit line is written into the storage node;

[0013] The first transistor is used to apply a fixed voltage on the read word line during a read operation, and is in a fully conductive, semi-conductive or closed state based on the relationship between the storage signal stored in the storage node and two different threshold voltages, and reads the storage signal by sensing different current values ​​or voltage values ​​on the read bit line.

[0014] In a second aspect, an embodiment of the present application provides a memory, comprising a plurality of storage units as described above, a plurality of write word lines, a plurality of write bit lines, a plurality of read word lines, and a plurality of read bit lines;

[0015] Multiple storage units are distributed in an array;

[0016] The third gate of the second transistor of each memory cell in a row of memory cells is connected to a write word line, and the first electrode of the first transistor of each memory cell in a row of memory cells is connected to a read word line;

[0017] The third electrode of the second transistor of each memory cell in a column of memory cells is connected to a write bit line, and the second electrode of the first transistor of each memory cell in a column of memory cells is connected to a read bit line;

[0018] Memory cells in different rows correspond to different write word lines and different read word lines;

[0019] Memory cells in different columns correspond to different write bit lines and different read bit lines.

[0020] In a third aspect, an embodiment of the present application provides an electronic device comprising the memory as described above.

[0021] In a fourth aspect, an embodiment of the present application provides a method for reading and writing a storage unit, comprising:

[0022] Write operation phase: applying a first voltage to the write word line to turn on the second transistor and write the storage signal into the storage node through the write bit line;

[0023] Read operation phase: A fixed voltage is applied to the read word line, and based on the relationship between the storage signal stored in the storage node and two different threshold voltages, the first transistor is placed in a fully-on, half-on or off state, and the storage signal is read by sensing different current values ​​or voltage values ​​on the read bit line.

[0024] In a fifth aspect, an embodiment of the present application provides a method for accessing a memory, comprising:

[0025] Write operation phase: applying a first voltage to the write word line in a row of memory cells to be accessed, so that the second transistors in the row of memory cells are turned on, and writing a storage signal into the storage nodes of the row of memory cells through all write bit lines connected to the row of memory cells;

[0026] Read operation phase: A fixed voltage is applied to the read word line, and based on the relationship between the storage signal stored in the storage node and two different threshold voltages, the first transistor is placed in a fully-on, half-on or off state, and the written storage signal is read by sensing different current values ​​or voltage values ​​on the read bit line.

[0027] In a sixth aspect, an embodiment of the present application provides a method for preparing a memory, comprising:

[0028] providing a substrate;

[0029] forming a second gate, a second gate dielectric layer, a first semiconductor layer, a first gate dielectric layer and a first gate in sequence on one side of the substrate;

[0030] On the first gate, forming a fourth electrode, a third electrode, a second semiconductor layer, a third gate dielectric layer and a third gate in sequence;

[0031] forming a first electrode and a second electrode on the substrate on which the third gate is formed;

[0032] wherein the area of ​​the first gate is different from the area of ​​the second gate; and / or,

[0033] The material of the first gate is different from the material of the second gate; and / or,

[0034] The thickness of the first gate is different from the thickness of the second gate; and / or,

[0035] The thickness of the first gate dielectric layer is different from the thickness of the second gate dielectric layer.

[0036] The technical solutions provided in the embodiments of the present application have at least the following beneficial effects:

[0037] The memory cell provided in an embodiment of the present application includes two transistors, one of which is a read transistor and the other is a write transistor. The read transistor is a dual-gate transistor, and the two gates of the read transistor are connected and connected to one electrode of the write transistor. The read transistor has two different threshold voltages. During a write operation, the write transistor is turned on based on the first voltage of the write word line, so that the storage signal on the write bit line is written to the storage node. During a read operation, a fixed voltage is applied to the read word line, and based on the relationship between the storage signal stored in the node in the memory cell and the two different threshold voltages, the read transistor is in a fully conductive, half-conductive or closed state, and the storage signal is read by sensing different current values ​​or voltage values ​​on the read bit line. That is, by reading the three states of the fully conductive, half-conductive and closed transistor, the memory cell can realize the storage and reading of multiple (multi-bit) information.

[0038] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0040] Figure 1 A circuit schematic diagram of a storage unit provided in an embodiment of the present application;

[0041] Figure 2-Figure 9 A schematic diagram of the structure of different preparation processes in a method for preparing a memory provided in an embodiment of the present application; wherein, Figure 4b for Figure 4a Schematic diagram of the cross section along the dotted line AA, Figure 4c for Figure 4a Schematic cross-section along dotted line BB; Figure 5b for Figure 5a Schematic diagram of the cross section along the dotted line AA, Figure 5c for Figure 5a Schematic cross-section along dotted line BB; Figure 8b for Figure 8a Schematic diagram of the cross section along the dotted line AA, Figure 8c for Figure 8a Schematic cross section along the dotted line BB.

[0042] Figure 10 A flowchart of a memory access method provided in an embodiment of the present application;

[0043] Figure 11 A schematic diagram of the circuit structure of the memory provided in an embodiment of the present application.

[0044] Reference numerals:

[0045] 100-substrate, 101-second gate, 102-second gate dielectric layer, 103-first semiconductor layer, 104-first gate dielectric layer, 105-first gate, 106-first insulating dielectric layer, 106a-first sub-insulating dielectric layer, 106b-second sub-insulating dielectric layer, 107-fourth electrode, 108-second insulating dielectric layer, 109-third electrode, 110-third insulating dielectric layer, 111-second semiconductor layer, 112-third gate dielectric layer, 113-third gate, 114-first electrode, 115-second electrode. DETAILED DESCRIPTION

[0046] The present application is described in detail below. Examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components having the same or similar functions. In addition, if the detailed description of the known technology is not necessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0047] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0048] It will be understood by those skilled in the art that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and / or" used herein includes all or any units and all combinations of one or more associated listed items.

[0049] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0050] The embodiment of the present application provides a memory, such as Figure 11 As shown, the memory includes a memory array; the memory array includes a plurality of memory cells, a plurality of write word lines WWL (WWL1, WWL2 ... WWLn), a plurality of write bit lines WBL (WBL1, WBL2 ... WBLn), a plurality of read word lines RWL (RWL1, RWL2 ... RWLn), and a plurality of read bit lines RBL (RBL1, RBL2 ... RBLn). Each memory cell includes a first transistor T1 and a second transistor T2 connected thereto.

[0051] A plurality of memory cells are distributed in an array; the third gate of the second transistor of each memory cell in a row of memory cells is connected to a write word line, and the first electrode of the first transistor of each memory cell in a row of memory cells is connected to a read word line; the third electrode of the second transistor of each memory cell in a column of memory cells is connected to a write bit line, and the second electrode of the first transistor of each memory cell in a column of memory cells is connected to a read bit line; memory cells in different rows correspond to different write word lines and different read word lines; memory cells in different columns correspond to different write bit lines and different read bit lines.

[0052] Specifically, such as Figure 1 As shown, the memory cell includes a first transistor T1 and a second transistor T2. The first transistor T1 is configured as a read transistor, and the second transistor T2 is configured as a write transistor.

[0053] The first transistor T1 is a dual-gate transistor, and the second transistor T2 is a single-gate transistor. The first transistor T1 includes a first gate, a second gate, a first electrode, and a second electrode. The first transistor T1 has two different threshold voltages, one of which corresponds to the first gate and the other corresponds to the second gate. The second transistor T2 includes a third gate, a third electrode, and a fourth electrode.

[0054] Specifically, the first gate and second gate of the first transistor T1 are connected, and are also connected to the fourth electrode of the second transistor T2, which serves as a storage node for storing a written storage signal. The first electrode of the first transistor T1 is connected to the read word line RWL, and the second electrode of the first transistor T1 is connected to the read bit line RBL. The third gate of the second transistor T2 is connected to the write word line WWL, and the third electrode of the second transistor T2 is connected to the write bit line WBL.

[0055] The second transistor T2 is configured to be turned on based on a first voltage of the write word line during a write operation, so that a storage signal on the write bit line is written into the storage node.

[0056] The first transistor T1 is used to apply a fixed voltage to the read word line during a read operation, and is in a fully conductive, semi-conductive or closed state based on the relationship between the storage signal stored in the storage node and two different threshold voltages, and reads the storage signal by sensing different current values ​​or voltage values ​​on the read bit line.

[0057] It should be noted that the first transistor T1 has two different threshold voltages, one of which corresponds to the first gate and the other corresponds to the second gate. That is, the first transistor T1 includes two channels, the first gate controls the on / off state of one of the channels (one of which has a threshold voltage corresponding to the first gate), and the second gate controls the on / off state of the other channel (the other threshold voltage corresponds to the second gate). It can also be simply understood that the first transistor T1 includes two separate transistors, which have little or no effect on each other, and each separate transistor has a threshold voltage.

[0058] In the present application, the two poles of the same transistor, one of which is the source and the other is the drain. For example, the "first pole" of the first transistor T1 specifically refers to the source of the transistor, and the "second pole" specifically refers to the drain of the transistor. Of course, those skilled in the art should know that the "first pole" and the "second pole" are interchangeable, that is, the "first pole" specifically refers to the drain of the transistor, and the "second pole" specifically refers to the source of the transistor. The "third pole" of the second transistor T2 specifically refers to the source of the transistor, and the "fourth pole" specifically refers to the drain of the transistor. Of course, those skilled in the art should know that the "third pole" and the "fourth pole" are interchangeable, that is, the "third pole" specifically refers to the drain of the transistor, and the "fourth pole" specifically refers to the source of the transistor.

[0059] A memory provided by an embodiment of the present application includes a memory array; the memory array includes multiple memory cells, each of which includes two transistors, one of which is a read transistor and the other is a write transistor. The read transistor is a dual-gate transistor, with the two gates of the read transistor connected and connected to one electrode of the write transistor. The read transistor has two different threshold voltages. During a write operation, the write transistor is turned on based on a first voltage of a write word line, allowing the stored signal on the write bit line to be written to the storage node. During a read operation, a fixed voltage is applied to the read word line, and based on the relationship between the stored signal stored at the node in the memory cell and the two different threshold voltages, the read transistor is placed in a fully on, half-on, or off state. The stored signal is read by sensing different current values ​​or voltage values ​​on the read bit line. In other words, by switching the read transistor to the fully on, half-on, and off states, the memory cell can store and read multiple types of information, for example, three types of information. During a read operation, the conduction state of the channel can be controlled to read the information according to the different stored information. For example, when the stored information is the first type of information, both channels of the reading transistor are in a closed state, the reading transistor is in a closed state, and the current value or voltage value on the read bit line is 0; when the stored information is the second type of information, one of the two channels of the reading transistor is in an open state, and the other channel is in a closed state, the reading transistor is in a semi-conducting state, and the current value or voltage value on the read bit line is a first current value or a first voltage value; when the stored information is the third type of information, both channels of the reading transistor are in an open state, the reading transistor is in a fully conductive state, and the current value or voltage value on the read bit line is a second current value or a second voltage value. In this way, the storage and reading of three types of information can be realized, the multi-bit storage function of the 2T0C memory is realized, and the integration of the memory is increased.

[0060] In some embodiments, as Figure 9 As shown, the first transistor T1 and the second transistor T2 are stacked in a direction perpendicular to the substrate 100 , and the first transistor T1 is close to the substrate 100 , while the second transistor T2 is far away from the substrate 100 .

[0061] In some embodiments, as Figure 9 As shown, the first transistor T1 further includes a first semiconductor layer 103. The first gate 105 of the first transistor T1 is located on the side of the first semiconductor layer 103 away from the substrate 100, and the second gate 101 of the first transistor T1 is located on the side of the first semiconductor layer 103 close to the substrate 100; the first electrode 114 of the first transistor T1 and the second electrode 115 of the first transistor T1 are located on both sides of the perpendicular bisector of the first semiconductor layer 103, and the first electrode 114 and the second electrode 115 are respectively connected to the first semiconductor layer 103. Figure 9As can be seen from the figure, the cross-sectional shape of the first semiconductor layer 103 is a square wave shape, thereby forming a square wave channel.

[0062] In some embodiments, as Figure 9 As shown, the first semiconductor layer 103 includes a first sub-semiconductor layer and a second sub-semiconductor layer, the first sub-semiconductor layer is close to the first gate 105, and the second sub-semiconductor layer is close to the second gate 101; the first gate 105 controls the conduction and closing of the first channel corresponding to the first sub-semiconductor layer, and the second gate 101 controls the conduction and closing of the second channel corresponding to the second sub-semiconductor layer; the turn-on voltages of the first channel and the second channel are different, so that the first transistor T1 has two different threshold voltages.

[0063] In some embodiments, as Figure 9 As shown, the area of ​​the first gate 105 is different from the area of ​​the second gate 101; and / or, the material of the first gate 105 is different from the material of the second gate 101; and / or, along the direction perpendicular to the substrate 100, the thickness of the first gate 105 is different from the thickness of the second gate 101.

[0064] Specifically, in the embodiment of the present application, the first gate 105 and the second gate 101 are made of different materials, have different areas, and different thicknesses, so that the first gate 105 and the second gate 101 have different work functions, thereby making the two threshold voltages of the read transistor different.

[0065] Alternatively, as Figure 9 As shown, the area of ​​the first gate 105 is larger than that of the second gate 101, and the first gate 105 covers the second gate 101; the thickness of the first gate 105 is greater than that of the second gate 101. Of course, the area of ​​the first gate 105 can also be smaller than that of the second gate 101, and the thickness of the first gate 105 can be smaller than that of the second gate 101, as long as the read transistor can have two different threshold voltages.

[0066] In some embodiments, as Figure 9 As shown, the first transistor T1 further includes a first gate dielectric layer 104 and a second gate dielectric layer 102. The first gate dielectric layer 104 is located between the first gate electrode 105 and the first semiconductor layer 103; the second gate dielectric layer 102 is located between the second gate electrode 101 and the first semiconductor layer 103. The thickness of the first gate dielectric layer 104 is different from that of the second gate dielectric layer 102, so that the read transistor has two different threshold voltages.

[0067] Alternatively, as Figure 9As shown, the thickness of the first gate dielectric layer 104 is greater than that of the second gate dielectric layer 102. Of course, the thickness of the first gate dielectric layer 104 may also be less than that of the second gate dielectric layer 102, as long as the read transistor has two different threshold voltages.

[0068] In some embodiments, as Figure 9 As shown, the second transistor T2 further includes a second semiconductor layer 111 and a third gate dielectric layer 112. The third electrode 109 and the fourth electrode 107 are stacked and insulated perpendicular to the substrate 100. The second semiconductor layer 111 extends perpendicular to the substrate 100 and is connected to the third electrode 109 and the fourth electrode 107. The channel of the second semiconductor layer 111 is a vertical channel. The third gate electrode 113 extends perpendicular to the substrate 100, and the third gate dielectric layer 112 is located between the third gate electrode 113 and the second semiconductor layer 111.

[0069] In some embodiments, the memory device of the present invention further includes a first sub-insulating dielectric layer 106a and a second sub-insulating dielectric layer 106b. The first sub-insulating dielectric layer 106a is located between the first electrode 114 and the first gate 105. The second sub-insulating dielectric layer 106b is located between the second electrode 115 and the first gate 105.

[0070] In some embodiments, the memory device of the present invention further includes a second insulating dielectric layer 108 and a third insulating dielectric layer 110. The second insulating dielectric layer 108 is located between the fourth electrode 107 and the third electrode 109. The third insulating dielectric layer 110 is located on a side of the third electrode 109 away from the substrate 100.

[0071] In a specific embodiment, the first electrode 114 can serve as part of the read word line RWL, the second electrode 115 can serve as part of the read bit line RBL, the third electrode 10 can serve as part of the write bit line WBL, and the third gate 113 can serve as part of the write word line WWL, thereby simplifying the memory structure process of the 2T0C and saving space, thereby improving the integration level.

[0072] In some embodiments of the present application, when both transistors are n-type transistors, the material of the first semiconductor layer 103 and the second semiconductor layer 111 includes a metal oxide semiconductor material. The metal oxide material can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 1E-15A to 1E-10A), where 1E-15A refers to 10 to the power of -15 amperes, and 1E-10A refers to 10 to the power of -10 amperes, thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and other materials, as long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0073] In some embodiments of the present application, the metal in the metal oxide semiconductor material includes at least one of indium, tin, zinc, aluminum, and gallium.

[0074] Based on the same inventive concept, an embodiment of the present application provides an electronic device, including the memory provided by any of the above embodiments. The electronic device may include a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a smart mobile terminal.

[0075] The electronic device provided in the embodiment of the present application has the same inventive concept and the same beneficial effects as the previous embodiments. The contents not shown in detail in the electronic device can be referred to the previous embodiments and will not be repeated here.

[0076] Based on the same inventive concept, an embodiment of the present application provides a method for reading and writing a storage unit, comprising:

[0077] Write operation phase: applying a first voltage to the write word line to turn on the second transistor and write the storage signal into the storage node through the write bit line;

[0078] Read operation phase: A fixed voltage is applied to the read word line, and based on the relationship between the storage signal stored in the storage node and two different threshold voltages, the first transistor is placed in a fully-on, half-on or off state, and the storage signal is read by sensing different current values ​​or voltage values ​​on the read bit line.

[0079] In some embodiments, the read operation phase may specifically include:

[0080] A fixed voltage is applied to the read word line. When the storage signals stored in the storage nodes are both less than two threshold voltages, the first channel and the second channel of the first transistor are both closed, and the current value or voltage value sensed on the read bit line is 0, and the storage signal read and written is the first storage signal.

[0081] A fixed voltage is applied to the read word line. When the storage signal stored in the storage node is between two threshold voltages, one of the first channel and the second channel of the first transistor is turned on. Then, a current value or a voltage value on the read bit line is sensed to be a first current value or a first voltage value, and the storage signal read and written is a second storage signal.

[0082] A fixed voltage is applied to the read word line. When the storage signals stored in the storage nodes are greater than two threshold voltages, the first channel and the second channel of the first transistor are both turned on, and the current value or voltage value sensed on the read bit line is the second current value or the second voltage value, and the storage signal read and written is the third storage signal.

[0083] The reading and writing method of the storage unit provided in the embodiment of the present application has the same inventive concept and the same beneficial effects as the previous embodiments. The contents not shown in detail in the reading and writing method of the storage unit can be referred to the previous embodiments and will not be repeated here.

[0084] Based on the same inventive concept, the embodiment of the present application provides a method for accessing a memory, such as Figure 10 As shown, the access method includes:

[0085] S11: write operation phase: applying a first voltage to the write word line in a row of memory cells to be accessed, so that the second transistors in the row of memory cells are turned on, and writing a storage signal into the storage nodes of the row of memory cells through all write bit lines connected to the row of memory cells;

[0086] S12: Read operation phase: a fixed voltage is applied to the read word line, and based on the relationship between the storage signal stored in the storage node and two different threshold voltages, the first transistor is placed in a fully-on, half-on or off state, and the written storage signal is read by sensing different current values ​​or voltage values ​​on the read bit line.

[0087] In some embodiments, after the write operation phase is completed, a second voltage (off voltage) is applied to the write word line in a row of memory cells so that all the second transistors are turned off.

[0088] The following describes in detail the memory access method with reference to a specific example.

[0089] Writing information: Apply a high-level voltage to the write word line WWL in a row of memory cells to turn on the write transistor, and write a storage signal to a row of memory cells through the write bit line WBL. The storage signal can be the first storage signal (information 0), the second storage signal (information 1), or the third storage signal (information 2).

[0090] Reading information: Apply a fixed voltage to the read word line RWL and sense different current values ​​or voltage values ​​on the read bit line RBL to read the written storage signal.

[0091] Specifically, a fixed voltage is applied to the read word line RWL. When the current value on the read bit line RBL is sensed to be 0, the first channel and the second channel of the read transistor are both closed, and the storage signal read and written is the first storage signal (i.e., information 0). At this time, the voltage value of the first storage signal is less than the two threshold voltages.

[0092] A fixed voltage is applied to the read word line RWL. When the current value or voltage value on the read bit line RBL is sensed to be a first current value, one of the first channel and the second channel of the read transistor is turned on, and the storage signal read and written is the second storage signal (i.e., information 1). At this time, the voltage value of the second storage signal is between the two threshold voltages.

[0093] A fixed voltage is applied to the read word line RWL. When the current value on the read bit line RBL is sensed to be the second current value, the first channel and the second channel of the read transistor are both turned on, and the storage signal read and written is the third storage signal (i.e., information 2). At this time, the voltage value of the second storage signal is greater than the two threshold voltages.

[0094] The first current value is greater than 0 and less than the second current value. Figure 1 The truth table of the 2T0C memory cell shown is as follows:

[0095] Store signal Reading the dual threshold voltage of the transistor Reading the state of the transistor 0V (information 0) 0.5V / 1.5V closure 1V (Information 1) 0.5V / 1.5V Half-open (half-conduction) 2V (Information 2) 0.5V / 1.5V Fully open (full conduction)

[0096] Based on the same inventive concept, an embodiment of the present application provides a method for preparing a memory, the method comprising:

[0097] S21: providing a substrate;

[0098] S22: forming a second gate, a second gate dielectric layer, a first semiconductor layer, a first gate dielectric layer and a first gate in sequence on one side of the substrate;

[0099] S23: forming a fourth electrode, a third electrode, a second semiconductor layer, a third gate dielectric layer and a third gate in sequence on the first gate;

[0100] S24: forming a first electrode and a second electrode on the substrate on which the third gate is formed.

[0101] Specifically, a second gate electrode, a second gate dielectric layer, a first semiconductor layer, a first gate dielectric layer, and a first gate electrode are sequentially formed on one side of the substrate through a patterning process. Subsequently, a fourth electrode, a third electrode, a second semiconductor layer, a third gate dielectric layer, and a third gate electrode are sequentially formed through a patterning process, and finally, a first electrode and a second electrode are formed. The first gate electrode has an area different from that of the second gate electrode, and / or the material of the first gate electrode is different from that of the second gate electrode, and / or the thickness of the first gate electrode is different from that of the second gate electrode, and / or the thickness of the first gate dielectric layer is different from that of the second gate electrode. This allows the first transistor (reading transistor) to correspond to two different threshold voltages, enabling the storage and reading of multiple types of information.

[0102] The preparation method of the memory provided in the embodiment of the present application is relatively simple. By first forming the two gate electrodes and the semiconductor layer of the read transistor, then forming the write transistor, and finally forming the two poles of the read transistor, the read transistor and the write transistor are arranged up and down and stacked, which can achieve a more compact space, save area, and facilitate high-density integration and manufacturing.

[0103] The following combination Figure 2-Figure 9 A manufacturing process of a memory in one embodiment of the present application is described in detail.

[0104] Specifically, such as Figure 2 As shown, a metal film is deposited on a substrate 100, and then an etching process is performed to form a second gate 101. The deposition method may be PVD (Physical Vapor Deposition).

[0105] like Figure 3 As shown, a gate oxide film and a metal oxide semiconductor film are sequentially deposited, and then an etching process is performed to form a second gate dielectric layer 102 and a first semiconductor layer 103. The deposition method can be ALD (Atomic Layer Deposition). ALD deposition technology can achieve better step coverage of the deposited material and more uniform gate dielectric layer and channel.

[0106] like Figure 4a 、 Figure 4b and Figure 4c As shown, a gate oxide film is deposited, and then a first gate dielectric layer 104 is formed by an etching process. The deposition method can be ALD (Atomic Layer Deposition). Optionally, the thickness and area of ​​the first gate dielectric layer 104 are different from the thickness and area of ​​the second gate dielectric layer 102, so that the two threshold voltages of the read transistor can be different. Furthermore, it can be seen from the figure that the thickness of the first gate dielectric layer 104 is greater than the thickness of the second gate dielectric layer 102, and the area of ​​the first gate dielectric layer 104 is greater than the area of ​​the second gate dielectric layer 102.

[0107] like Figure 5a 、 Figure 5b and Figure 5c As shown, a metal film is deposited, and then the first gate 105 is formed by an etching process. The deposition method can be PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition) and other methods. Optionally, the materials, areas and thicknesses of the first gate 105 and the second gate 101 can be different, so that the first gate 105 and the second gate 101 have different work functions, which can make the two threshold voltages of the reading transistor different. Furthermore, it can be seen from the figure that the area of ​​the first gate 105 is larger than the area of ​​the second gate 101, and the thickness of the first gate 105 is greater than the thickness of the second gate 101.

[0108] like Figure 6 As shown, an insulating dielectric film is deposited to form a first insulating dielectric layer 106. For example, an SOD (Spin-on Dielectrics) process can be used to spin-coat an insulating dielectric material such as SiO2 (silicon dioxide), which has a good filling effect. A CMP (Chemical Mechanical Polishing) process is then used to planarize the surface. After planarization, the first gate 105 is exposed, and the surface of the first insulating dielectric layer 106 is flush with the surface of the first gate 105.

[0109] like Figure 7 As shown, metal films and insulating dielectric films are alternately deposited in sequence, and an etching process is performed to form the fourth electrode 107, the second insulating dielectric layer 108, the third electrode 109, and the third insulating dielectric layer 110. This deposition method can use PVD (Physical Vapor Deposition), which can reduce costs.

[0110] like Figure 8a 、 Figure 8b and Figure 8cAs shown, a through hole is formed by etching to terminate the fourth electrode 107. Then, a metal oxide semiconductor film, a gate oxide film, and a metal film are sequentially deposited in the through hole to form a second semiconductor layer 111, a third gate dielectric layer 112, and a third gate electrode 113. This deposition method can adopt ALD (Atomic Layer Deposition). ALD deposition technology can achieve better step coverage of the deposited material, more uniform gate dielectric layer and channel, and has advantages such as strong hole filling capability.

[0111] like Figure 9 As shown, a portion of the first insulating dielectric layer 106 is removed by an etching process to form two through holes, which expose the first semiconductor layer 103, and a metal film is deposited in the two through holes to form a first pole 114 and a second pole 115, as well as a first sub-insulating dielectric layer 106a and a second sub-insulating dielectric layer 106b, respectively. The memory is then completed.

[0112] By adopting the embodiments of the present application, at least the following beneficial effects can be achieved:

[0113] A memory provided by an embodiment of the present application includes a memory array; the memory array includes a plurality of memory cells, each memory cell including two transistors, one of which is a read transistor and the other is a write transistor. The read transistor is a dual-gate transistor, with the two gates of the read transistor connected and connected to one electrode of the write transistor. The read transistor has two different threshold voltages, thereby enabling the storage and reading of multiple types of information, for example, enabling the storage and reading of three types of information. During a read operation, the conduction state of the channel can be controlled according to the different stored information to read the information. For example, when storing the first type of information, both channels of the read transistor are in a closed state, the read transistor is in an off state, and the current value or voltage value on the read bit line is 0; when storing the second type of information, one of the two channels of the read transistor is in an open state and the other channel is in a closed state, the read transistor is in a half-conducting state, and the current value or voltage value on the read bit line is a first current value or a first voltage value; when storing the third type of information, both channels of the read transistor are in an open state, the read transistor is in a fully conductive state, and the current value or voltage value on the read bit line is a second current value or a second voltage value.

[0114] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0115] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0116] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0117] The above description is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A storage unit, characterized in that: including a first transistor and a second transistor; The first transistor is configured as a read transistor; The second transistor is configured as a write transistor; The first transistor includes a first gate, a second gate, a first electrode, and a second electrode; the first transistor has two different threshold voltages, one threshold voltage corresponds to the first gate, and the other threshold voltage corresponds to the second gate; the second transistor includes a third gate, a third electrode, and a fourth electrode; The first gate of the first transistor is connected to the second gate of the first transistor, and is also connected to the fourth electrode of the second transistor; the fourth electrode serves as a storage node for storing a written storage signal; A first electrode of the first transistor is connected to a read word line, and a second electrode of the first transistor is connected to a read bit line; The third gate of the second transistor is connected to the write word line, and the third electrode of the second transistor is connected to the write bit line; The second transistor is configured to be turned on based on a first voltage of the write word line during a write operation, so that a storage signal on the write bit line is written into the storage node; The first transistor is used to apply a fixed voltage on the read word line during a read operation, and is in a fully conductive, semi-conductive or closed state based on the relationship between the storage signal stored in the storage node and two different threshold voltages, and reads the storage signal by sensing different current values ​​or voltage values ​​on the read bit line.

2. The storage unit according to claim 1, wherein The first transistor and the second transistor are stacked in a direction perpendicular to a substrate, with the first transistor close to the substrate and the second transistor far away from the substrate.

3. The storage unit according to claim 2, wherein: The first transistor further includes a first semiconductor layer; The first gate is located on a side of the first semiconductor layer away from the substrate, and the second gate is located on a side of the first semiconductor layer close to the substrate; The first electrode and the second electrode are located on both sides of a perpendicular bisector of the first semiconductor layer, and the first electrode and the second electrode are connected to the first semiconductor layer respectively.

4. The storage unit according to claim 3, wherein: The first semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer, the first sub-semiconductor layer is close to the first gate, and the second sub-semiconductor layer is close to the second gate; The first gate controls the on / off state of a first channel corresponding to the first sub-semiconductor layer, and the second gate controls the on / off state of a second channel corresponding to the second sub-semiconductor layer.

5. The storage unit according to claim 4, wherein: The area of ​​the first gate is different from the area of ​​the second gate; and / or, The material of the first gate is different from the material of the second gate; and / or, The thickness of the first gate is different from the thickness of the second gate. The storage unit according to claim 5 , wherein: The area of ​​the first gate is greater than the area of ​​the second gate, and the first gate covers the second gate; and / or, The thickness of the first gate is greater than the thickness of the second gate.

7. The storage unit according to claim 4, wherein: The first transistor further includes: a first gate dielectric layer, located between the first gate and the first semiconductor layer; a second gate dielectric layer, located between the second gate and the first semiconductor layer; The thickness of the first gate dielectric layer is different from the thickness of the second gate dielectric layer.

8. The storage unit according to claim 7, wherein: The thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer.

9. The storage unit according to claim 3, wherein: The second transistor further includes a second semiconductor layer and a third gate dielectric layer; Along a direction perpendicular to the substrate, the third pole and the fourth pole are stacked and insulated; The second semiconductor layer extends in a direction perpendicular to the substrate and is connected to the third electrode and the fourth electrode respectively; The third gate extends in a direction perpendicular to the substrate, and the third gate dielectric layer is located between the third gate and the second semiconductor layer.

10. A memory, characterized in that: comprising a plurality of memory cells according to any one of claims 1 to 9, a plurality of write word lines, a plurality of write bit lines, a plurality of read word lines, and a plurality of read bit lines; Multiple storage units are distributed in an array; The third gate of the second transistor of each memory cell in a row of memory cells is connected to a write word line, and the first electrode of the first transistor of each memory cell in a row of memory cells is connected to a read word line; The third electrode of the second transistor of each memory cell in a column of memory cells is connected to a write bit line, and the second electrode of the first transistor of each memory cell in a column of memory cells is connected to a read bit line; Memory cells in different rows correspond to different write word lines and different read word lines; Memory cells in different columns correspond to different write bit lines and different read bit lines.

11. An electronic device, characterized in that: Comprising the memory as claimed in claim 10.

12. A method for reading and writing a storage unit according to any one of claims 1 to 9, characterized in that: include: Write operation phase: applying a first voltage to the write word line to turn on the second transistor and write the storage signal into the storage node through the write bit line; Read operation phase: A fixed voltage is applied to the read word line, and based on the relationship between the storage signal stored in the storage node and two different threshold voltages, the first transistor is placed in a fully-on, half-on or off state, and the storage signal is read by sensing different current values ​​or voltage values ​​on the read bit line.

13. The method for reading and writing a storage unit according to claim 12, wherein: The read operation phase specifically includes: Applying a fixed voltage to the read word line, when the storage signals stored in the storage node are both less than the two threshold voltages, the first channel and the second channel of the first transistor are both closed, and the current value or voltage value sensed on the read bit line is 0, and the storage signal read or written is the first storage signal; Applying a fixed voltage to the read word line, when the storage signal stored in the storage node is between the two threshold voltages, one of the first channel and the second channel of the first transistor is turned on, and a current value or a voltage value on the read bit line is sensed as the first current value or the first voltage value, and the storage signal read or written is the second storage signal; A fixed voltage is applied to the read word line. When the storage signals stored in the storage nodes are greater than the two threshold voltages, the first channel and the second channel of the first transistor are both turned on, and the current value or voltage value sensed on the read bit line is the second current value or the second voltage value, and the storage signal read and written is the third storage signal.

14. A method for accessing a memory according to claim 10, characterized in that: include: Write operation phase: applying a first voltage to the write word line in a row of memory cells to be accessed, so that the second transistors in the row of memory cells are turned on, and writing a storage signal into the storage nodes of the row of memory cells through all write bit lines connected to the row of memory cells; Read operation phase: A fixed voltage is applied to the read word line, and based on the relationship between the storage signal stored in the storage node and two different threshold voltages, the first transistor is placed in a fully-on, half-on or off state, and the written storage signal is read by sensing different current values ​​or voltage values ​​on the read bit line.

15. A method for preparing a memory cell according to any one of claims 1 to 9, characterized in that: include: providing a substrate; forming a second gate, a second gate dielectric layer, a first semiconductor layer, a first gate dielectric layer and a first gate in sequence on one side of the substrate; On the first gate, forming a fourth electrode, a third electrode, a second semiconductor layer, a third gate dielectric layer and a third gate in sequence; forming a first electrode and a second electrode on the substrate on which the third gate is formed; wherein the area of ​​the first gate is different from the area of ​​the second gate; and / or, The material of the first gate is different from the material of the second gate; and / or, The thickness of the first gate is different from the thickness of the second gate; and / or, The thickness of the first gate dielectric layer is different from the thickness of the second gate dielectric layer.

16. The method for preparing a memory cell according to claim 15, wherein: The method of sequentially forming a second gate, a second gate dielectric layer, a first semiconductor layer, a first gate dielectric layer and a first gate on one side of the substrate comprises: Depositing a metal film and forming a second gate through an etching process; Depositing a gate oxide film and a metal oxide semiconductor film in sequence, and forming a second gate dielectric layer and a first semiconductor layer by an etching process; Depositing a gate oxide film and forming a first gate dielectric layer through an etching process; A metal film is deposited and a first gate is formed by an etching process.

17. The method for preparing a memory cell according to claim 16, wherein: The fourth electrode, the third electrode, the second semiconductor layer, the third gate dielectric layer and the third gate are sequentially formed on the first gate, including: depositing an insulating dielectric film to form a first insulating dielectric layer; Alternately depositing metal films and insulating dielectric films, and forming a fourth electrode, a second insulating dielectric layer, a third electrode, and a third insulating dielectric layer through an etching process; forming a through hole by an etching process and exposing the fourth electrode; A metal oxide semiconductor film, a gate oxide film and a metal film are sequentially deposited in the through hole to form a second semiconductor layer, a third gate dielectric layer and a third gate.

18. The method for preparing a memory cell according to claim 17, wherein: The forming of the first pole and the second pole comprises: removing a portion of the first insulating dielectric layer by an etching process to form two through holes, wherein both through holes expose the first semiconductor layer; Metal films are deposited in both through holes to form a first electrode and a second electrode respectively.

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