Voltage configuration method for storage array

Abstract

This disclosure provides a voltage configuration method for a memory array, applicable to the field of circuit technology. The method includes: configuring the write word line and the write bit line to a first voltage in response to a read operation, such that the write transistor is in a turned-off state; configuring the read bit line to a second voltage, the second voltage being greater than the first voltage; determining a selection state of the read word line of the memory array, the selection state indicating whether a memory cell associated with the read word line performs a read operation; and configuring the voltage of the read word line according to the selection state and the second voltage to control the conduction state of the read transistor.

Description

Technical Field

[0001] This disclosure relates to the field of circuit technology, and more specifically to a voltage configuration method for a memory array. Background Technology

[0002] Embedded dynamic random access memory (eDRAM) is a design that integrates DRAM into a system-on-a-chip. Typically, each eDRAM cell consists of a capacitor and a transistor, resulting in high storage density.

[0003] In the traditional 2T1C read scheme, VDD is applied to the read word line of the selected row and VSS is applied to the read bit line. VSS is applied to the unselected row. At this time, the read transistor of the 2T1C cell that stores "1" in the unselected row is in the open state, resulting in an additional leakage path. A large current will appear on the read bit line of the 2T1C cell that stores "0" in the selected row, resulting in additional power consumption and read error. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a voltage configuration method for a storage array.

[0005] According to a first aspect of this disclosure, a voltage configuration method for a memory array is provided. The memory array includes a plurality of memory cells, each memory cell including a write transistor, a memory node, and a read transistor. A first terminal of the write transistor is connected to a write bit line, and a second terminal of the write transistor is connected to a write word line. A first terminal of the memory node is connected to a third terminal of the write transistor, and a second terminal of the memory node is grounded. A first terminal of the read transistor is connected to a read word line, and a second terminal is connected to a third terminal of the memory node. A third terminal of the read transistor is connected to a read bit line. The method includes: configuring the write word line and the write bit line to a first voltage in response to a read operation, such that the write transistor is in a turned-off state; configuring the read bit line to a second voltage, the second voltage being greater than the first voltage; determining a selection state of the read word line of the memory array, the selection state indicating whether a read operation is performed on the memory cell associated with the read word line; and configuring the voltage of the read word line according to the selection state and the second voltage to control the on state of the read transistor.

[0006] According to embodiments of this disclosure, voltage configuration of a read word line based on a selected state and a second voltage includes: configuring the read word line to a third voltage when the selected state indicates that the memory cell associated with the read word line is not performing a read operation, so that the read transistor is in a turned-off state, wherein the third voltage is the same as the second voltage.

[0007] According to embodiments of this disclosure, when a read operation is performed on a memory cell associated with a read word line, the read word line is configured with a fourth voltage to turn on the read transistor, wherein the second voltage is greater than the fourth voltage.

[0008] According to embodiments of this disclosure, the method further includes: configuring read word lines and read bit lines to a second voltage and configuring write word lines to a fifth voltage, the fifth voltage being greater than the second voltage, in response to a write operation, such that read transistors are in a turned-off state and write transistors are in a turned-on state; determining the type of data to be written, the type of data being characterized by the direction of charge flow between the write bit lines and the memory nodes in the memory cells associated with the write bit lines; and configuring the voltage of the write bit lines according to the type of data to be written.

[0009] According to embodiments of this disclosure, voltage configuration of the write bit line based on the type of data being written includes configuring the write bit line to a second voltage when the type of data being written indicates that charge flows from the write bit line to the storage node.

[0010] According to embodiments of this disclosure, when the type of data being written indicates that charge flows from the write bit line to the storage node, the charge is stored from the write bit line to the storage node, thereby increasing the voltage value of the storage node.

[0011] According to embodiments of this disclosure, configuring the voltage of the write bit line according to the type of data to be written further includes: configuring the write bit line to a sixth voltage when the type of data to be written indicates that charge flows from the storage node to the write bit line, wherein the sixth voltage is less than the second voltage.

[0012] According to embodiments of this disclosure, when the type of data being written indicates that charge flows from the storage node to the write bit line, the charge is released from the storage node to the write bit line, thereby reducing the voltage value of the storage node.

[0013] According to embodiments of this disclosure, the write line is configured with a fifth voltage to improve the data retention time of the storage array.

[0014] According to embodiments of this disclosure, both the write transistor and the read transistor are complementary metal-oxide-semiconductor transistors or indium gallium zinc oxide thin-film transistors.

[0015] According to embodiments of this disclosure, when the memory array responds to a read operation, the write word line and the write bit line are configured with a first voltage to turn off the write transistor; the read bit line is configured with a second voltage, which is greater than the first voltage; the selection state of the read word line of the memory array is determined, the selection state indicating whether the memory cell associated with the read word line performs a read operation; and the voltage of the read word line is configured according to the selection state and the second voltage to control the conduction state of the read transistor. By determining whether the memory cell associated with the read word line performs a read operation to determine the voltage configuration of the read word line and control the conduction state of the read transistor, leakage caused by the read transistor always being in the conduction state is avoided. This eliminates the leakage path during memory array readout, thereby reducing readout power consumption and readout error. Attached Figure Description

[0016] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram of a storage array according to an embodiment of the present disclosure is shown;

[0018] Figure 2 A flowchart illustrating a voltage configuration method for a memory array according to an embodiment of the present disclosure is shown schematically.

[0019] Figure 3 A schematic diagram of a storage array under a read operation according to an embodiment of the present disclosure is shown.

[0020] Figure 4 A flowchart illustrating a voltage configuration method for a memory array under a write operation according to an embodiment of the present disclosure is shown schematically. Detailed Implementation

[0021] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0023] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0024] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0025] Embodiments of this disclosure provide a voltage configuration method for a memory array. In response to a read operation, the write word line and the write bit line are configured to a first voltage so that the write transistor is in a turned-off state; the read bit line is configured to a second voltage, which is greater than the first voltage; a selection state of the read word line of the memory array is determined, the selection state indicating whether the memory cell associated with the read word line performs a read operation; and the voltage of the read word line is configured according to the selection state and the second voltage to control the conduction state of the read transistor.

[0026] Figure 1 A schematic diagram of a storage array according to an embodiment of the present disclosure is shown; Figure 2 A flowchart illustrating a voltage configuration method for a memory array according to an embodiment of the present disclosure is shown schematically.

[0027] According to a first aspect of this disclosure, a method for configuring the voltage of a storage array is provided. For example... Figure 1 As shown, the above-mentioned memory array includes multiple memory cells. Each memory cell includes a write transistor N1, a memory node SN, and a read transistor N2. The first end of the write transistor N1 is connected to the write bit line, and the second end of the write transistor N1 is connected to the write word line. The first end of the memory node SN is connected to the third end of the write transistor N1, and the second end of the memory node SN is grounded. The first end of the read transistor N2 is connected to the read word line, and the second end is connected to the third end of the memory node SN. The third end of the read transistor N2 is connected to the read bit line.

[0028] like Figure 2 As shown, the voltage configuration method for the storage array includes operations S210~S240.

[0029] In operation S210, when the memory array responds to a read operation, the write word line and write bit line are configured to a first voltage so that the write transistor is turned off.

[0030] In operation S220, the read bit line is configured to a second voltage, which is greater than the first voltage;

[0031] In operation S230, the selected state of the read word line of the storage array is determined. The selected state indicates whether the storage cell associated with the read word line is performing a read operation.

[0032] In operation S240, the voltage of the read word line is configured according to the selected state and the second voltage to control the conduction state of the read transistor.

[0033] According to embodiments of this disclosure, the memory array may be a 2T1C eDRAM array or a 2T0C eDRAM memory array.

[0034] According to embodiments of this disclosure, both write transistor N1 and read transistor N2 can be transistors used in dynamic random access memory (DRAM) and static random access memory (SRAM).

[0035] According to embodiments of this disclosure, the storage node SN can be a capacitor used to store written data.

[0036] According to embodiments of this disclosure, a Write Bit Line (WBL) is a wire in an SRAM memory array used for writing data, storing and transmitting data bits.

[0037] According to embodiments of this disclosure, a Write Word Line (WWL) is a control signal line in an SRAM memory array used to select a specific row. When the Write Word Line is set to a high level, the write transistor N1 connected to the Write Word Line will be turned on.

[0038] According to embodiments of this disclosure, a read bit line (RBL) is a wire in an SRAM memory array used for reading data, storing and transmitting data bits.

[0039] According to embodiments of this disclosure, the Read Word Line (RWL) is a control signal line in an SRAM memory array used to select a specific row. When the Read Word Line is set to a high level, the read transistor N2 connected to the Read Word Line will be turned on.

[0040] According to embodiments of this disclosure, a read operation is used to read data by turning on the read transistor N2.

[0041] According to embodiments of this disclosure, the first voltage can be a low voltage VSS, where VSS generally refers to the negative ground or zero potential point of the circuit, that is, the write word line and write bit line are configured to 0V.

[0042] According to embodiments of this disclosure, the second voltage can be a high voltage VDD, which can be configured according to actual needs, for example, the read bit line can be configured to 0.9V.

[0043] According to an embodiment of this disclosure, when the storage array responds to a read operation, WWL and WBL are set to VSS, and RBL is set to VDD. Since WWL is set to VSS, write transistor N1 is turned off to avoid read errors caused by the operation of write transistor N1 during the read operation.

[0044] According to embodiments of this disclosure, since the storage array is provided with multiple sets of storage cells consisting of "write transistor N1 - storage node SN - read transistor N2", when performing a read operation, the data on the storage cell of the selected row is read by controlling the selection state of RWL.

[0045] According to an embodiment of this disclosure, the conduction state of the read transistor N2 is controlled based on the voltage difference between the voltage value of the read word line in the memory cell corresponding to the selected state and the second voltage.

[0046] According to embodiments of this disclosure, when the memory array responds to a read operation, the write word line and the write bit line are configured with a first voltage to turn off the write transistor; the read bit line is configured with a second voltage, which is greater than the first voltage; the selection state of the read word line of the memory array is determined, the selection state indicating whether the memory cell associated with the read word line performs a read operation; and the voltage of the read word line is configured according to the selection state and the second voltage to control the conduction state of the read transistor. By determining whether the memory cell associated with the read word line performs a read operation to determine the voltage configuration of the read word line and control the conduction state of the read transistor, leakage caused by the read transistor always being in the conduction state is avoided. This eliminates the leakage path during memory array readout, thereby reducing readout power consumption and readout error.

[0047] According to embodiments of this disclosure, voltage configuration of the read line is performed based on a selected state and a second voltage, including:

[0048] When the selected state indicates that the memory cell associated with the read word line is not performing a read operation, the read word line is configured to a third voltage to turn off the read transistor, wherein the third voltage is the same as the second voltage.

[0049] According to an embodiment of this disclosure, when RWL is not selected, i.e., the memory cell associated with the read word line does not perform a read operation, RWL is configured to a third voltage VDD (e.g., 0.9V) that is the same as the second voltage. At this time, since both RWL and RBL are high voltages and have the same voltage value, there is no voltage difference between the first and third terminals of the read transistor, so no current flows in the read transistor, and the read transistor is in the off state with no current flowing.

[0050] According to embodiments of this disclosure, when a read operation is performed on a memory cell associated with a read word line, the read word line is configured with a fourth voltage to turn on the read transistor, wherein the second voltage is greater than the fourth voltage.

[0051] According to an embodiment of this disclosure, when RWL is selected, i.e., when a read operation is performed on the memory cell associated with the read word line, RWL is configured to the fourth voltage VSS (0V). At this time, RWL is a low voltage, RBL is a high voltage, there is a voltage difference between the first and third terminals of the read transistor, and current flows from RBL to RWL through the read transistor, i.e., the read transistor is in the on state.

[0052] Figure 3 A schematic diagram of a storage array under a read operation according to an embodiment of the present disclosure is shown.

[0053] According to embodiments of this disclosure, such as Figure 3 As shown, when the unselected row RWL is configured as VDD and RBL is configured as VDD, the read transistor N2 of the memory cell corresponding to the unselected row is in the off state regardless of whether the memory node SN is "1" or "0". Therefore, unnecessary leakage paths are eliminated, thereby reducing read power consumption and read error.

[0054] Figure 4 A flowchart illustrating a voltage configuration method for a memory array under a write operation according to an embodiment of the present disclosure is shown schematically.

[0055] According to embodiments of this disclosure, such as Figure 4 As shown, the above method also includes operations S410~S430.

[0056] In operation S410, when the memory array responds to a write operation, the read word line and read bit line are configured to a second voltage, and the write word line is configured to a fifth voltage, which is greater than the second voltage, so that the read transistor is in the off state and the write transistor is in the on state.

[0057] In operation S420, the type of data to be written is determined, which characterizes the direction of charge flow between the write bit line and the memory node in the memory cell associated with the write bit line.

[0058] When operating the S430, the voltage of the write bit line is configured according to the type of data being written.

[0059] According to embodiments of this disclosure, a write operation is used to write data to a storage node by turning on a write transistor.

[0060] According to embodiments of this disclosure, the fifth voltage may be VDDH, which has a higher voltage value than the second voltage VDD, for example, it may be configured as 1.1V.

[0061] According to embodiments of this disclosure, the write operation type includes "1" and "0", where "1" means the storage node stores high-voltage data and "0" means the storage node stores low-voltage data.

[0062] According to embodiments of this disclosure, for data at different levels, the WBL needs to adaptively adjust the configured voltage value to achieve the writing of data at different voltages.

[0063] According to embodiments of this disclosure, voltage configuration of the write bit line based on the type of data being written includes configuring the write bit line to a second voltage when the type of data being written indicates that charge flows from the write bit line to the storage node.

[0064] According to embodiments of this disclosure, when the type of data being written indicates that charge flows from the write bit line to the storage node, the charge is stored from the write bit line to the storage node, thereby increasing the voltage value of the storage node.

[0065] According to an embodiment of this disclosure, when the type of data being written represents the storage node storing charge, i.e., the charge flows from the write bit line to the storage node, the WBL is configured to a high voltage VDD. At this time, since the WBL is high voltage and the storage node is grounded, the charge flows from the WBL to the storage node, thereby increasing the voltage value of the storage node.

[0066] According to embodiments of this disclosure, configuring the voltage of the write bit line according to the type of data being written further includes:

[0067] When the type of data being written represents the flow of charge from the storage node to the write bit line, the write bit line is configured with a sixth voltage, where the sixth voltage is less than the second voltage.

[0068] According to embodiments of this disclosure, when the type of data being written indicates that charge flows from the storage node to the write bit line, the charge is released from the storage node to the write bit line, thereby reducing the voltage value of the storage node.

[0069] According to embodiments of this disclosure, when the type of data being written indicates that the storage node releases charge, i.e., the charge flows from the storage node to the write bit line, the WBL is configured to a low voltage VSS (sixth voltage). At this time, since the WBL is a low voltage and the storage node is a high voltage, the charge is released from the storage node to the write bit line, thereby reducing the voltage value of the storage node.

[0070] According to embodiments of this disclosure, the write line is configured with a fifth voltage to improve the data retention time of the storage array.

[0071] According to embodiments of this disclosure, by configuring the write line to the fifth voltage VDDH to increase the voltage at which the storage node is written, the retention time of the stored data is increased, enabling the circuit to retain the stored data for a long time without loss.

[0072] According to embodiments of this disclosure, both the write transistor and the read transistor are complementary metal-oxide-semiconductor transistors or indium gallium zinc oxide thin-film transistors.

[0073] According to embodiments of this disclosure, the method is not limited to 2T1C memory arrays, but is also applicable to 2T0C memory arrays; wherein the read transistors and write transistors in the memory cells of 2T0C and 2T1C are not limited to CMOS transistors (complementary metal-oxide-semiconductor transistors), but can also be applied to IGZO transistors (indium gallium zinc oxide thin film transistors), and can be selected according to actual needs.

[0074] According to embodiments of this disclosure, an integrated circuit chip incorporating the memory array of this disclosure can be obtained through front-end design, back-end design, and wafer fabrication of digital and analog circuits, wherein the process technology used is 28nm.

[0075] According to embodiments of this disclosure, in actual chip testing, during write operations, the WWL voltage is set to 1.1V, and the WBL voltage is set to 0.9V or 0V depending on the type of data being written; during read operations, the RWL voltage for the selected row is set to 0V, the RBL voltage is set to 0.9V, and the RWL voltage for the unselected row is set to 0.9V. Compared to the traditional 2T1C array current readout voltage configuration scheme, the embodiment of this disclosure reduces readout power consumption by 1.49 times and increases read margin by 1.67 times, thereby reducing readout error.

[0076] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0077] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A voltage configuration method for a storage array, characterized in that, The storage array includes multiple storage cells, each storage cell including a write transistor, a storage node, and a read transistor. A first terminal of the write transistor is connected to a write bit line, and a second terminal of the write transistor is connected to a write word line. A first terminal of the storage node is connected to a third terminal of the write transistor, and a second terminal of the storage node is grounded. A first terminal of the read transistor is connected to a read word line, and a second terminal is connected to a third terminal of the storage node. The third terminal of the read transistor is connected to a read bit line. The method includes: In response to a read operation, the write word line and the write bit line are configured to a first voltage so that the write transistor is turned off. The read bit line is configured with a second voltage, which is greater than the first voltage; Determine the selection state of the read word line of the storage array, wherein the selection state indicates whether the storage cell associated with the read word line performs the read operation; Based on the selected state and the second voltage, the voltage of the read word line is configured to control the conduction state of the read transistor; The step of configuring the voltage of the word reading line according to the selected state and the second voltage includes: When the selected state indicates that the memory cell associated with the read word line does not perform the read operation, the read word line is configured to a third voltage to turn off the read transistor, wherein the third voltage is the same as the second voltage; When the selected state indicates that the memory cell associated with the read word line is performing the read operation, the read word line is configured with a fourth voltage to turn on the read transistor, wherein the second voltage is greater than the fourth voltage.

2. The method according to claim 1, characterized in that, The method further includes: In response to a write operation, the read word line and the read bit line are configured to the second voltage, and the write word line is configured to the fifth voltage, which is greater than the second voltage, so that the read transistor is in the off state and the write transistor is in the on state. The type of data to be written is determined, wherein the type of data to be written characterizes the direction of charge flow between the write bit line and the memory node in the memory cell associated with the write bit line; The voltage of the write bit line is configured according to the type of data to be written.

3. The method according to claim 2, characterized in that, The step of configuring the voltage of the write bit line according to the type of the written data includes: When the type of data being written indicates that the charge flows from the write bit line to the memory node, the write bit line is configured to the second voltage.

4. The method according to claim 3, characterized in that, When the type of data being written indicates that the charge flows from the write bit line to the storage node, the charge is stored from the write bit line to the storage node, causing the voltage value of the storage node to increase.

5. The method according to claim 3, characterized in that, The step of configuring the voltage of the write bit line according to the type of the written data further includes: When the type of data being written indicates that the charge flows from the storage node to the write bit line, the write bit line is configured with a sixth voltage, wherein the sixth voltage is less than the second voltage.

6. The method according to claim 5, characterized in that, When the type of data being written indicates that the charge flows from the storage node to the write bit line, the charge is released from the storage node to the write bit line, thereby reducing the voltage value of the storage node.

7. The method according to claim 2, characterized in that, Configure the write line to the fifth voltage to improve the data retention time of the storage array.

8. The method according to claim 1, characterized in that, Both the write transistor and the read transistor are complementary metal-oxide-semiconductor transistors or indium gallium zinc oxide thin-film transistors.

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