A data processing method and a data processing device

Abstract

The present application discloses a data processing method and a data processing device. In this method, the data processing device extends the puncturing range of each first codeword from the parity bits to the information bits and the parity bits, rather than only performing puncturing processing on the parity bits of each first codeword. Therefore, it is beneficial to search for appropriate puncturing positions and reduce the post-error correction bit error rate of FEC codewords.

Description

[0001] This application is a divisional application. The application number of the original application is 202211607442.3, the original application date is December 14, 2022, and the entire content of the original application is incorporated herein by reference. Technical Field

[0002] Embodiments of this application relate to the field of communications, and in particular, to a data processing method and a data processing device. Background Art

[0003] In a passive optical network (PON) access system, with the continuous increase in network capacity requirements and customer experience requirements, the flexible configuration of customer rates has become an important technical point in the PON system. Flexible rate configuration can maximize the utilization of channel conditions to optimize the overall network capacity, and at the same time can optimize the network experience of each user. Adjusting the rate through flexible forward error coding (Flex FEC) is an easy-to-implement method, usually achieved by puncturing and shortening the system standard codewords. However, for the PON system, the system has performance requirements at a very low post-correction bit error rate (<1e-12), so the FEC needs to maintain relatively good performance after puncturing and there should be no error floor. Therefore, selecting a suitable puncturing method is a key issue in the design of high-throughput Flex FEC.

[0004] In the traditional technology, multiple check bits are selected from the check bits of the FEC codeword for puncturing processing to obtain the punctured FEC codeword.

[0005] However, the number of check bits of each FEC codeword is limited, it is not easy to find suitable puncturing check bits, which is likely to affect the post-correction bit error rate of the FEC codeword. Summary of the Invention

[0006] This application provides a data processing method and a data processing device for reducing the post-correction bit error rate of FEC codewords.

[0007] In a first aspect, this application provides a data processing method. This data processing method can be executed by a data processing device or by components of a data processing device (such as components like a processor, a chip, or a chip system). Taking the data processing device as an example, the data processing device obtains a first data stream. The first data stream is a data stream that has undergone FEC encoding, and the first data stream includes multiple first codewords. Then, the data processing device performs puncturing processing on the information bits and check bits of each first codeword in the first data stream respectively to obtain a second data stream including multiple second codewords, and the length of each second codeword is less than the length of each first codeword.

[0008] In this embodiment, since the data processing device extends the puncturing range of each first codeword from the parity bits to the information bits and the parity bits, rather than only performing puncturing processing on the parity bits of each first codeword. Therefore, it is beneficial to search for appropriate puncturing positions and reduce the post-correction error rate of the FEC codewords.

[0009] In a possible implementation manner, the data processing device performs puncturing processing on the information bits and the parity bits of each first codeword in the first data stream respectively, or performs puncturing processing on the information bits of each first codeword in the first data stream, to obtain a second data stream including a plurality of second codewords, including: the data processing device obtains h first puncturing positions and g second puncturing positions corresponding to each first codeword, each first puncturing position indicating a plurality of bits in the information bits of the first codeword, and each second puncturing position indicating a plurality of bits in the parity bits of the first codeword; where the sum of h and g is equal to w, h is an integer greater than 0, g is an integer greater than or equal to 0, and w is an integer greater than 1. Then, the data processing device excludes the bits indicated by the h first puncturing positions and the bits indicated by the g second puncturing positions corresponding to each first codeword from each first codeword, to obtain a plurality of second codewords.

[0010] In this implementation manner, it is proposed that the data processing device can obtain h first puncturing positions and g second puncturing positions for each first codeword, and then, the data processing device performs puncturing processing on the first codeword based on the foregoing h first puncturing positions and g second puncturing positions. If the sum of the number of the first puncturing positions and the number of the second puncturing positions of each first codeword is equal to a fixed value (for example, the foregoing w), the data processing device can adjust the ratio between the first puncturing positions selected in the information bits and the second puncturing positions selected in the parity bits, and further search for appropriate puncturing positions to reduce the post-correction error rate of the FEC codewords.

[0011] In a possible implementation manner, w is the number of puncturing positions that need to be excluded in the standard puncturing processing. Exemplarily, w = 7. The number of puncturing positions that need to be excluded in the standard puncturing processing, that is, the number of puncturing positions that need to be excluded in the puncturing mode of only puncturing the parity bits. For example, in the prior art, the puncturing mode of only puncturing the parity bits needs to select w puncturing positions in the parity bits of the first codeword, while the solution of this application is to select w puncturing positions in the information bits and the parity bits of the first codeword. Since the number of puncturing positions in the information bits of the first codeword is increased and the number of puncturing positions in the parity bits of the first codeword is reduced, and the total number of puncturing positions for a first codeword remains unchanged, therefore, in reducing the post-correction error rate of the FEC codewords, it is beneficial to keep the code rate unchanged.

[0012] In another possible implementation, w is related to the post-correction error rate and the FEC codeword transmission rate. It can also be understood that w is the optimal solution that can improve the FEC codeword transmission rate while ensuring the post-correction error rate.

[0013] In a possible implementation, the first puncturing positions of any two first codewords in the first data stream are the same, and / or, the second puncturing positions of any two first codewords in the first data stream are the same.

[0014] In a possible implementation, the first puncturing position and / or the second puncturing position are related to the number of iterative calculations. For example, the first puncturing position and / or the second puncturing position of the same first codeword are the puncturing positions that enable all the extrinsic information of all the parity check equations of the second codeword corresponding to the first codeword to be updated after one iterative calculation. Therefore, it is beneficial for the second codeword to only require a relatively small number of iterative calculations during the decoding process, improving the decoding efficiency of the second codeword by the receiving device.

[0015] In a possible implementation, the first data stream includes a plurality of first codewords each having a length of (L + T) bits. The first L bits of the first codeword are information bits, and the last T bits of the first codeword are parity bits, where L is an integer greater than 0, and T is an integer greater than 0. The data processing device performs puncturing processing on the information bits and parity bits of each first codeword in the first data stream respectively, or performs puncturing processing on the information bits of each first codeword in the first data stream, to obtain a second data stream including a plurality of second codewords, including: the data processing device excludes P bits from the information bits of the first L bits of each first codeword, and excludes Q bits from the parity bits of the last T bits of each first codeword, to obtain a plurality of second codewords, each second codeword including K bits of punctured information bits and M bits of punctured parity bits, where K = L - P, M = T - Q, the sum of P and Q is equal to w times r, r is the number of bits to be excluded at each puncturing position, r is an integer greater than 0, w is an integer greater than 0, P is an integer greater than 0, Q is an integer greater than or equal to 0, K is an integer greater than 0, and M is an integer greater than 0.

[0016] In a possible implementation, the h first puncturing positions include h columns of information-bit code blocks and the g second puncturing positions include g columns of parity-bit code blocks. Each first codeword includes e columns of information-bit code blocks and f columns of parity-bit code blocks. Each column of code blocks includes at least one bit. The data processing device performs puncturing processing on the information bits and parity bits of each codeword in the first data stream respectively, or performs puncturing processing on the information bits of each of the first codewords in the first data stream, to obtain a second data stream including multiple second codewords, including: The data processing device obtains the identifiers of each column of information-bit code blocks in the h columns of information-bit code blocks and the identifiers of each column of parity-bit code blocks in the g columns of parity-bit code blocks; then, the data processing device excludes the h columns of information-bit code blocks from the e columns of information-bit code blocks based on the identifiers of the h columns of information-bit code blocks, and excludes the g columns of parity-bit code blocks from the f columns of parity-bit code blocks based on the identifiers of the g columns of parity-bit code blocks, to obtain a second codeword. e is an integer greater than 1, f is an integer greater than 1, h is an integer greater than 0, and g is an integer greater than or equal to 0. Optionally, the sum of h and g is equal to w.

[0017] In this implementation, the data processing device can convert the first codeword into a set of multiple columns of code blocks by simulating an iterative decoding algorithm, and then determine the first puncturing positions and the second puncturing positions in units of one column of code blocks, which is beneficial to quickly and efficiently determine each of the first puncturing positions and each of the second puncturing positions.

[0018] In a possible implementation, the parity-check matrix of the second codeword corresponds to multiple layers of parity-check equations. The variable nodes in each layer of parity-check equations of the parity-check matrix of the second codeword can obtain extrinsic information after the first iterative calculation, and the extrinsic information is used to decode the parity-check equations corresponding to the variable nodes related to the extrinsic information in the second codeword.

[0019] In a possible implementation, there is at least one shortened frame in the first data stream, and the length of the information bits of the last first codeword of the shortened frame is less than the length of the information bits of the other first codewords of the frame; the data processing device obtains the first data stream, including: The data processing device performs zero-padding processing on each shortened frame in the data stream to be encoded, to obtain a data stream to be encoded with zero-padding processing; then, the data processing device performs FEC encoding processing on the data stream to be encoded with zero-padding processing, to obtain an encoded data stream; then, the data processing device performs shortening processing on each frame with zero-padding processing in the encoded data stream, to obtain the first data stream.

[0020] In a possible implementation, there is at least one frame in the first data stream that has been shortened. The length of the information bits of the last first codeword in the shortened frame is equal to (L - S), where S is an integer greater than 0 and less than L. Obtaining the first data stream includes: obtaining a data stream to be encoded, the data stream to be encoded includes multiple data blocks of length L and at least one shortened data block of length less than L, and the shortened data block is the last data block of a frame; supplementing S zero bits after each shortened data block in the data stream to be encoded to obtain a zero-supplemented data stream to be encoded; performing FEC encoding processing on the zero-supplemented data stream to be encoded with L bits as one encoding block to obtain an encoded data stream; deleting S zero bits from the information bits of the last encoding block of the frame in the encoded data stream to obtain the first data stream.

[0021] In a possible implementation, the first data stream further includes at least one shortened first codeword of length (L - S + T) bits. The first (L - S) bits of the shortened first codeword are information bits, and the last T bits of the shortened first codeword are parity bits. L is an integer greater than 0, and T is an integer greater than 0. The data processing device performs puncturing processing on the information bits and parity bits of each first codeword in the first data stream respectively, or performs puncturing processing on the information bits of each first codeword in the first data stream to obtain a second data stream including multiple second codewords, including: the data processing device excludes P' bits from the information bits of the first (L - S) bits of the shortened first codeword, and excludes Q bits from the parity bits of the last T bits of the shortened first codeword to obtain a shortened second codeword. The shortened second codeword includes K' bits of punctured information bits and M bits of punctured parity bits, where K' = L - S - P', M = T - Q, the sum of P' and Q is equal to w times r, r is the number of bits to be excluded at each puncturing position, r is an integer greater than 0, w is an integer greater than 0, P' is an integer greater than 0, Q is an integer greater than or equal to 0, K' is an integer greater than 0, and M is an integer greater than 0.

[0022] In a second aspect, the present application provides a data processing device, which includes:

[0023] An acquisition module, configured to acquire a first data stream, where the first data stream is an FEC-encoded data stream, and the first data stream includes multiple first codewords;

[0024] A puncturing processing module, configured to perform puncturing processing on the information bits and parity bits of each first codeword in the first data stream respectively, or perform puncturing processing on the information bits of each first codeword in the first data stream to obtain a second data stream including multiple second codewords, and the length of each second codeword is less than the length of each first codeword.

[0025] Optionally, the obtaining module includes an FEC encoding module, and the FEC encoding module is configured to perform FEC encoding on the data stream to be encoded to obtain the first data stream.

[0026] In a possible implementation manner, the obtaining module is specifically configured to obtain h first puncturing positions and g second puncturing positions corresponding to each first codeword, each first puncturing position indicating multiple bits in the information bits of the first codeword, each second puncturing position indicating multiple bits in the parity bits of the first codeword, the sum of h and g being equal to w, h being an integer greater than 0, g being an integer greater than or equal to 0, and w being an integer greater than 1; the puncturing processing module is specifically configured to exclude the bits indicated by the h first puncturing positions and the bits indicated by the g second puncturing positions corresponding to each first codeword from each first codeword to obtain multiple second codewords.

[0027] In a possible implementation manner, w is the number of puncturing positions that need to be excluded in standard puncturing processing. Exemplarily, w = 7.

[0028] In a possible implementation manner, w is related to the post-correction error rate and the FEC codeword transmission rate.

[0029] In a possible implementation manner, the first puncturing positions of any two first codewords in the first data stream are the same, and / or, the second puncturing positions of any two first codewords in the first data stream are the same.

[0030] In a possible implementation manner, the first puncturing position and / or the second puncturing position is related to the number of times of iterative calculation.

[0031] In a possible implementation manner, the first puncturing position and / or the second puncturing position of the same first codeword are the puncturing positions that enable all the extrinsic information of all the parity equations corresponding to the second codeword corresponding to the first codeword to be updated after one iterative calculation.

[0032] In a possible implementation manner, the first data stream includes multiple first codewords each having a length of (L + T) bits, the first L bits of the first codeword being information bits, and the last T bits of the first codeword being parity bits, L being an integer greater than 0, and T being an integer greater than 0. The puncturing processing module is specifically configured to exclude P bits from the information bits of the first L bits of each first codeword, and exclude Q bits from the parity bits of the last T bits of each first codeword to obtain multiple second codewords, each second codeword including K bits of punctured information bits and M bits of punctured parity bits, K = L - P, M = T - Q, the sum of P and Q being equal to w times r, r being the number of bits to be excluded for each puncturing position, r being an integer greater than 0, w being an integer greater than 0, P being an integer greater than 0, Q being an integer greater than or equal to 0, K being an integer greater than 0, and M being an integer greater than 0.

[0033] In a possible implementation manner, the h first punching positions include h columns of information bit code blocks, and the g second punching positions include g columns of parity bit code blocks. Each first codeword includes e columns of information bit code blocks and f columns of parity bit code blocks. Each column of code blocks includes at least one bit;

[0034] The obtaining module is specifically configured to obtain the identifiers of each column of information bit code blocks in the h columns of information bit code blocks and the identifiers of each column of parity bit code blocks in the g columns of parity bit code blocks;

[0035] The punching processing module is specifically configured to exclude the h columns of information bit code blocks from the e columns of information bit code blocks based on the identifiers of the h columns of information bit code blocks, and exclude the g columns of parity bit code blocks from the f columns of parity bit code blocks based on the identifiers of the g columns of parity bit code blocks, to obtain a second codeword. e is an integer greater than 1, f is an integer greater than 1, h is an integer greater than 0, and g is an integer greater than or equal to 0. Optionally, the sum of h and g is equal to w.

[0036] In a possible implementation manner, the parity check matrix of the second codeword corresponds to multiple layers of parity check equations. The variable nodes in each layer of parity check equations of the parity check matrix of the second codeword can obtain extrinsic information after the first iterative calculation, and the extrinsic information is used to decode the parity check equations corresponding to the variable nodes related to the extrinsic information in the second codeword.

[0037] In a possible implementation manner, there is at least one frame subjected to shortening processing in the first data stream. The length of the information bits of the last first codeword of the frame subjected to shortening processing is less than the length of the information bits of the other first codewords of the frame. The data processing device further includes a zero-padding processing module; the zero-padding processing module is configured to perform zero-padding processing on each frame subjected to shortening processing in the data stream to be encoded to obtain a data stream to be encoded with zero-padding; the FEC encoding module is configured to perform FEC encoding processing on the data stream to be encoded with zero-padding to obtain an encoded data stream; the shortening processing module is configured to perform shortening processing on each frame subjected to zero-padding processing in the encoded data stream to obtain the first data stream.

[0038] In a possible implementation, there is at least one shortened frame in the first data stream. The length of the information bits of the last first codeword in the shortened frame is equal to (L - S), where S is an integer greater than 0 and less than L; an acquisition module for acquiring a data stream to be encoded, the data stream to be encoded includes multiple data blocks with a length of L and at least one shortened data block with a length less than L, and the shortened data block is the last data block of a frame; a zero-padding processing module for padding S zero bits after each shortened data block in the data stream to be encoded to obtain a zero-padded data stream to be encoded; an FEC encoding module for performing FEC encoding processing on the zero-padded data stream to be encoded with L bits as one encoding block to obtain an encoded data stream; a shortening processing module for deleting S zero bits from the information bits of the last encoding block of the frame in the encoded data stream to obtain the first data stream.

[0039] In a possible implementation, the first data stream further includes at least one shortened first codeword with a length of (L - S + T) bits. The first (L - S) bits of the shortened first codeword are information bits, and the last T bits of the shortened first codeword are parity bits. L is an integer greater than 0, and T is an integer greater than 0. A puncturing processing module is specifically configured to exclude P' bits from the information bits of the first (L - S) bits of the shortened first codeword, and exclude Q bits from the parity bits of the last T bits of the shortened first codeword to obtain a shortened second codeword. The shortened second codeword includes K' bits of punctured information bits and M bits of punctured parity bits, where K' = L - S - P', M = T - Q, the sum of P' and Q is equal to w times r, r is the number of bits to be excluded at each puncturing position, r is an integer greater than 0, w is an integer greater than 0, P' is an integer greater than 0, Q is an integer greater than or equal to 0, K' is an integer greater than 0, and M is an integer greater than 0.

[0040] It should be noted that the specific implementation manners and beneficial effects of this aspect are similar to some of the implementation manners in the previous first aspect. For details, please refer to the specific implementation manners and their beneficial effects of the first aspect, which will not be elaborated here.

[0041] In a third aspect, the present application provides a data processing device, which includes a processor and a transceiver; the transceiver is configured to receive the first data stream and send the second data stream; the processor is configured to execute some or all of the steps of any one of the methods in the first aspect above.

[0042] In a fourth aspect, the present application provides a chip, which includes at least one logic circuit and an input / output interface; the input / output interface is configured to input the first data stream and output the second data stream; the logic circuit is configured to execute some or all of the steps of any one of the methods in the first aspect above.

[0043] In a fifth aspect, the present application provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by hardware, it can implement some or all of the steps of any one of the methods in the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application.

[0045] Figure 1 FIG. is a schematic diagram of a communication system applied to an embodiment of the present application;

[0046] Figure 2 FIG. is a schematic diagram of the data transmission process in the traditional technology;

[0047] Figure 3 FIG. is a flowchart of a data processing method in the present application;

[0048] Figure 4A FIG. is an example diagram of a frame structure involved in the data processing method in the present application;

[0049] Figure 4B FIG. is another example diagram of a frame structure involved in the data processing method in the present application;

[0050] Figure 5 FIG. is an example diagram of the comparison result of the punching method in the present application and the punching method in the traditional technology;

[0051] Figure 6 FIG. is another flowchart of the data processing method in the present application;

[0052] Figure 7A FIG. is an example diagram of the first punching position and the second punching position in the first codeword of the present application;

[0053] Figure 7B FIG. is another example diagram of the first punching position and the second punching position in the first codeword of the present application;

[0054] Figure 8 FIG. is an example diagram of the convergence comparison of the punching mode of the present application and the punching mode of the traditional solution;

[0055] Figure 9 FIG. is an example diagram of the performance comparison of the punching mode of the present application and the punching mode of the traditional solution;

[0056] Figure 10 FIG. is a schematic diagram of an embodiment of a data processing device in the present application;

[0057] Figure 11 This is a schematic diagram of another embodiment of the data processing device in the present application. Detailed implementation manners

[0058] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0059] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above accompanying drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0060] It should be understood that the term "and / or" herein is only a relationship describing associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0061] Figure 1 This is a schematic diagram of a communication system applied in the embodiments of the present application. As Figure 1 shown, the communication system includes a transmitting end 01, a receiving end 02, and a channel transmission medium 03. Taking the PON system as an example, the transmitting end 01 and the receiving end 02 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission, and the channel transmission medium 03 can be an optical fiber. Optionally, the transmitting end 01, the receiving end 02, and the channel transmission medium 03 in the communication system can support bidirectional transmission or unidirectional transmission, and specific details are not limited herein.

[0062] As Figure 2As shown in the figure, it is a schematic diagram of the data transmission process in the prior art. In the process of transmitting a data stream from the transmitting end 01 to the receiving end 02, the transmitting end 01 is used to perform forward error correction coding (flexible forward error coding, FEC) on the original data stream to obtain a data stream containing multiple FEC codewords before puncturing. Then, the transmitting end 01 performs puncturing on the parity bits of the FEC codewords before puncturing to obtain a data stream containing multiple FEC codewords after puncturing. Then, the transmitting end 01 transmits the data stream after puncturing to the receiving end 02 through the channel transmission medium 03. After receiving the aforementioned data stream after puncturing, the receiving end 02 performs decoding processing on the data stream to obtain the original data stream. In this process, since the transmitting end 01 only performs puncturing on the parity bits of the FEC codewords, it is not easy to find suitable puncturing parity bits, so it is easy to affect the post-correction error rate of the FEC codewords in the decoding process of the receiving end 02.

[0063] In response to this, the present application provides a data processing method. This data processing method adopts a new puncturing mode, which is conducive to searching for suitable puncturing positions and reducing the post-correction error rate of FEC codewords. The following will be combined with Figure 3 for introduction:

[0064] As Figure 3 shown, it is the main process of the data processing method provided by the present application. The data processing device involved in this method can be located in the aforementioned transmitting end 01. Specifically, the data processing device will perform the following steps:

[0065] Step 301, the data processing device obtains a first data stream including multiple first codewords, and the first data stream is a data stream after FEC coding.

[0066] Among them, each first codeword includes an information bit and a parity bit. For example, the first few bits of the first codeword are information bits, and the last few bits of the first codeword are parity bits. Generally, the parity bit is determined by the FEC encoder based on the information bit. The FEC encoder can be located in the aforementioned data processing device, or in other processing chips or functional modules outside the aforementioned data processing device, which is not limited here.

[0067] It should be noted that the FEC coding involved in the present application can be a coding method based on a low-density parity-check code (LDPC), or other types of FEC coding methods, which are not limited in the present application. For example, in the flexible FEC (Flexible FEC, Flex FEC) coding scenario in 50GPON, the FEC coding is LDPC coding; in other scenarios, the FEC coding can be other types of FEC coding methods.

[0068] In a possible implementation, the first data stream is processed by FEC encoding, but the first data stream is not processed by shortening. For example, the data processing device includes an FEC encoder, and the data processing device performs FEC encoding processing on the data stream to be encoded based on the FEC encoder and outputs the first data stream. In this case, the first data stream only includes the first codewords that have not been processed by shortening, and the lengths of each first codeword in the first data stream are the same.

[0069] Exemplarily, Figure 4A FIG. is an example diagram of the processing procedure for the data processing device to obtain the first data stream that has not been processed by shortening. As Figure 4A shown, the lengths of each data block in the data stream to be encoded are the same. Taking the data stream to be encoded including multiple data blocks with a length of L as an example. The data processing device encodes the data block with a length of L into information bits, adds parity bits with a length of T, and obtains the first data stream. Among them, the lengths of each first codeword in the first data stream are the same, and each first codeword includes information bits with a length of L and parity bits with a length of T. Among them, L is an integer greater than 0, and T is an integer greater than 0.

[0070] In another possible implementation, the first data stream is not only processed by FEC encoding, but the first data stream is also processed by shortening. For example, the data stream to be encoded obtained by the data processing device not only includes multiple data blocks with a length of L but also includes at least one shortened data block with a length less than L. The data processing device first performs zero-padding processing on each shortened data block in the data stream to be encoded so that the length of each data block in the data stream to be encoded after zero-padding processing is L. Then, the data processing device performs FEC encoding processing on the data stream to be encoded after zero-padding processing based on the FEC encoder and outputs the encoded data stream. Then, the data processing device shortens the information bits of the codewords that have been zero-padded in the encoded data stream to obtain the first data stream including multiple first codewords. In this case, there is at least one codeword in the first data stream that has been processed by shortening, and the length of the codeword that has been processed by shortening is less than the lengths of other codewords. That is to say, there are at least two different lengths of first codewords in the first data stream.

[0071] Exemplarily, taking the data stream to be encoded having at least one shortened data block (hereinafter referred to as the shortened data block) as an example. As Figure 4B shown, the shortened data block (for example, Figure 4BThe data block n') in it is located at the last data block of a frame, and the length of the last data block of this frame is less than the lengths of other data blocks in the frame. Taking the length of the last data block (i.e., the shortened data block) in the frame as (L - S) bits and the lengths of other data blocks in the frame as L bits, where S is an integer greater than 0 and less than L. The data processing device supplements S zero bits after each shortened data block (e.g., Figure 4B the data block n') in the data stream to be encoded, obtaining the data stream to be encoded with zero bits supplemented. At this time, the length of each data block in the data stream to be encoded after zero-bit supplementation is L bits. For example, the data block n' with a length of (L - S) bits becomes the data block n with a length of L bits after zero-bit supplementation. Then, the data processing device encodes the data block with a length of L into information bits and adds parity bits with a length of T, obtaining an encoded data stream containing multiple encoded blocks. Then, the data processing device deletes S zero bits from the information bits of the last encoded block (e.g., Figure 4B the encoded block n) of the frame that has been zero-bit supplemented in the encoded data stream, obtaining a first data stream containing first codewords of at least two different lengths. For example, in the obtained first data stream, the length of the information bits of the last first codeword in some frames is (L - S) bits, while the length of the information bits of other first codewords in this frame is L bits.

[0072] It should be noted that not every last codeword in each frame of the first data stream after shortening processing has been shortened. It is possible that only the last codewords of some frames have been shortened. This application does not limit the number of shortened first codewords included in the first data stream.

[0073] Step 302, the data processing device performs puncturing processing on the information bits and parity bits of each first codeword in the first data stream respectively, or performs puncturing processing on the information bits of each first codeword in the first data stream, obtaining a second data stream containing multiple second codewords.

[0074] In a possible implementation manner, the data processing device selects multiple bits in the information bits of each first codeword for puncturing processing, that is, excludes (or deletes) the aforementioned multiple bits from the information bits of this first codeword, and selects multiple bits in the parity bits of each first codeword for puncturing processing, that is, excludes (or deletes) the aforementioned multiple bits from the parity bits of this first codeword, obtaining a second codeword. Among them, the length of the information bits of the second codeword is less than the length of the information bits of the first codeword, and the length of the parity bits of the second codeword is less than the length of the parity bits of the first codeword. The length of each second codeword is less than the length of each first codeword.

[0075] In another possible implementation, the data processing device selects multiple bits in the information bits of each first codeword for puncturing, that is, excludes (or deletes) the aforementioned multiple bits from the information bits of the first codeword to obtain a second codeword. Wherein, the length of the information bits of the second codeword is less than the length of the information bits of the first codeword, and the length of the parity bits of the second codeword is equal to the length of the parity bits of the first codeword. The length of each second codeword is less than the length of each first codeword.

[0076] The following is an introduction with examples:

[0077] In a possible example, the first data stream only includes multiple first codewords with a length of (L + T) bits. The first L bits of the first codeword are information bits, and the last T bits of the first codeword are parity bits. Wherein, L is an integer greater than 0, and T is an integer greater than 0. As Figure 4A shown, the data processing device excludes P bits from the information bits of the first L bits of each of the first codewords, and excludes Q bits from the parity bits of the last T bits of each of the first codewords to obtain multiple second codewords. Wherein, each second codeword includes K bits of punctured information bits and M bits of punctured parity bits, K = L - P, M = T - Q, the sum of P and Q is equal to w times r, r is the number of bits to be excluded at each puncturing position, r is an integer greater than 0, w is an integer greater than 0, P is an integer greater than 0, Q is an integer greater than or equal to 0, K is an integer greater than 0, and M is an integer greater than 0.

[0078] In another possible example, the first data stream not only includes multiple first codewords with a length of (L + T) bits, but also includes at least one shortened first codeword with a length of (L - S + T) bits. The first (L - S) bits of the shortened first codeword are information bits, and the last T bits of the shortened first codeword are parity bits. Wherein, L is an integer greater than 0, and T is an integer greater than 0. As Figure 4B shown, the data processing device excludes P' bits from the information bits of the first (L - S) bits of the shortened first codeword, and excludes Q bits from the parity bits of the last T bits of the shortened first codeword to obtain a shortened second codeword. Wherein, the shortened second codeword includes K' bits of punctured information bits and M bits of punctured parity bits, K' = L - S - P', M = T - Q, the sum of P' and Q is equal to w times r, r is the number of bits to be excluded at each puncturing position, r is an integer greater than 0, w is an integer greater than 0, P' is an integer greater than 0, Q is an integer greater than or equal to 0, K' is an integer greater than 0, and M is an integer greater than 0.

[0079] It should be noted that the last codeword of each frame in the first data stream may be a shortened codeword. If the position of the shortening process coincides with the position of the puncturing process, then the shortening process is performed and the information bit part that does not coincide is punctured. Since puncturing and shortening are two independent steps, there is no need to introduce a judgment on whether the puncturing position coincides with the shortening position during actual operation, and the processing complexity will not be increased. That is to say, whether there is a shortened first codeword in the first data stream or not, the data processing device can puncture the information bits and parity bits of the first codeword respectively, or only puncture the information bits of the first codeword.

[0080] In this embodiment, since the puncturing range is expanded, that is, the puncturing process range is extended to the information bits of each first codeword, rather than only puncturing the parity bits of each first codeword. Therefore, it is beneficial to search for a suitable puncturing position and reduce the post-correction error rate of the FEC codeword.

[0081] In addition, compared with the traditional technology, without increasing the number of punctured bits, information bit puncturing is added to the traditional puncturing method, and parity bit puncturing is reduced. Figure 5 For example, in the traditional technology, the number of punctured bits is (Q + P) bits. The traditional puncturing method only punctures (Q + P) bits in the parity bits. The puncturing method proposed in this application punctures P bits in the information bits and Q bits in the parity bits. Wherein, P is an integer greater than 0, and Q is an integer greater than or equal to 0. Therefore, the length of the codeword after puncturing in the traditional scheme is the same as the length of the codeword after puncturing in the scheme of this application. For example, both are (K + M) bits. Also, since the FEC decoder at the receiving end will recover all the bits of the codeword, that is, it can recover the information bits deleted during the puncturing process. Therefore, compared with the traditional scheme, the number of information bits transmitted by a single codeword in the scheme of this application is both L, and the code rate is both L / (K + M). Therefore, the scheme of this embodiment can ensure the code rate while reducing the post-correction error rate of the FEC codeword.

[0082] Next, the data processing method provided by this application will be further introduced in combination with Figure 6 After obtaining the first data stream, the data processing device will perform puncturing processing in the following manner:

[0083] Step 601, the data processing device obtains h first puncturing positions and g second puncturing positions corresponding to each first codeword in the first data stream.

[0084] Among them, each first punching position indicates multiple bits in the information bits of the first codeword, and each second punching position indicates multiple bits in the parity bits of the first codeword. The number of bits indicated by any two of the h first punching positions is the same. For example, the data processing device obtains h first punching positions, and each first punching position indicates a bits, where h is an integer greater than 0, and a is an integer greater than 0. The number of bits indicated by any two of the g second punching positions is the same. For example, the data processing device obtains g second punching positions, and each second punching position indicates b bits, where g is an integer greater than or equal to 0, and b is an integer greater than 0. The number of bits indicated by a first punching position and the number of bits indicated by a second punching position may be the same or different. For example, in the foregoing example, a may be equal to b, or a may not be equal to b, and the present application does not limit this.

[0085] Optionally, the sum of the number of first punching positions and the number of second punching positions of each first codeword is equal to w, where w is an integer greater than 1. For example, for a first codeword, the number of first punching positions is h, and the number of second punching positions is g. A total of h + g = w punching positions are punched on this first codeword. Among them, w is an integer greater than 0, h is an integer greater than 0, and g is an integer greater than or equal to 0.

[0086] Exemplarily, w is related to the post-correction error rate and the FEC codeword transmission rate. It can also be understood that w is the optimal solution that can improve the FEC codeword transmission rate while ensuring the post-correction error rate.

[0087] Exemplarily, w is the number of punching positions that need to be excluded in the standard punching process. For example, in the prior art, the punching pattern that only punches the parity bits needs to select w punching positions in the parity bits of the first codeword, while the solution of the present application is to select w punching positions in the information bits and parity bits of the first codeword.

[0088] For example, w = 7 means that generally 7 punching positions are selected in the 50GPON standard punching process. For example, h = 1, g = 6; or h = 2, g = 5; or h = 3, g = 4; or h = 4, g = 3; or h = 5, g = 2; or h = 6, g = 1. That is to say, compared with the prior art in which 7 punching positions are selected in the check bits of the first codeword for punching processing, the solution of the present application selects h punching positions in the information bits of the first codeword and g punching positions in the check bits of the first codeword, and a total of h + g = 7 punching positions are selected on the first codeword for punching processing. Since the number of punching positions in the information bits of the first codeword is increased and the number of punching positions in the check bits of the first codeword is reduced, while the total number of punching positions for a first codeword remains unchanged, therefore, the post-error correction bit error rate of the FEC codeword is reduced, which is beneficial to keeping the code rate unchanged.

[0089] In a possible implementation manner, each first codeword in the first data stream may be arranged in a rectangle as shown in Figure 7A wherein each of the first codewords includes e columns of information bit blocks and f columns of check bit blocks, and each column of the code blocks includes at least one bit. Wherein, e is an integer greater than 1, and f is an integer greater than 1. Generally, the number of bits included in different code blocks is the same, however, there may also be a case where the number of bits included in two columns of code blocks is different, which is not limited in the present application. Taking Figure 7A as an example, the foregoing h first punching positions may be h columns of information bit blocks with identifiers h1, h2, h3, h4, and h5 in the information bits of the first codeword in Figure 7A , and the foregoing g second punching positions may be g columns of check bit blocks with identifiers g1 and g2 in the check bits of the first codeword in Figure 7A . Wherein, h is an integer greater than 0, and g is an integer greater than or equal to 0. Optionally, the sum of h and g is equal to w. w can be understood as the number of columns of code blocks to be excluded in the standard punching process.

[0090] It should be noted that the first punching position and / or the second punching position may be determined by the data processing device based on an algorithm or manually configured, and specific details are not limited herein. The first punching position and the second punching position obtained by the data processing device satisfy at least one of the following constraints:

[0091] A possible constraint example is that the first punching position and the second punching position are related to the construction of the check matrix of the first codeword. For example, the data processing device determines the first punching position and the second punching position of the first codeword based on the pre-configured punching positions.

[0092] Another possible example of a constraint is that the first punching position and the second punching position are related to the number of iterations of the iterative calculation. The first punching position and the second punching position obtained by the data processing device are beneficial for the second codeword to only require a relatively small number of iterative calculations during the decoding process, improving the decoding efficiency of the receiving device for the second codeword. For example, the first punching position and the second punching position of the same first codeword are the punching positions such that all the extrinsic information of all the check nodes of the second codeword corresponding to the first codeword can be updated after one iteration calculation. Among them, one iteration calculation means that the receiving device completes the calculation of the extrinsic information of all the check nodes once according to the check relationship of the check matrix when decoding the second codeword.

[0093] Exemplarily, the data processing device can determine the check matrix of the first codeword based on the first codeword. Each layer of the check matrix of the first codeword corresponds to a check equation, that is, the check matrix of the first codeword corresponds to multiple layers of check equations. For example, if the first codeword includes e columns of information bit blocks and f columns of check bit blocks, then the check matrix of the first codeword includes f rows of check equations. There is an association relationship between the foregoing multiple layers of check equations. Each of the check equations includes multiple variable nodes. The data processing device can search for the foregoing first punching position and second punching position based on theoretical calculation, fast convergence, or simulation experiments, etc. If the first punching position and the second punching position searched by the data processing device can enable the variable nodes in each layer of the check equation of the check matrix of the second codeword to obtain extrinsic information after the first iteration calculation, and the extrinsic information is used to decode the check equation corresponding to the variable node related to the extrinsic information in the second codeword. That is to say, the first punching position and the second punching position can enable the extrinsic information to be transmitted to all the information bits participating in this check during the first iteration in the decoding process.

[0094] Exemplarily, when each row of the f - row check equations of the first codeword with (e + f) columns satisfies the following conditions, the second codeword obtained after the punching process satisfies the foregoing constraint:

[0095] At most 1 bit is punched in the first row;

[0096] Among the bits punched in the second row, the number of bits not participating in the check of the first row does not exceed 1;

[0097] Among the bits punched in the third row, the number of bits not participating in the check of any of the first and second rows does not exceed 1;

[0098] Among the bits punched in the fourth row, the number of bits not participating in the check of any of the first, second, and third rows does not exceed 1;

[0099] …

[0100] Among the bits punched in the f - th row, the number of bits not participating in the check of any of the previous (f - 1) rows does not exceed 1.

[0101] It should be noted that in practical applications, the data processing device can also use other algorithms to determine the first punching position and the second punching position that meet the foregoing constraints, which will not be enumerated one by one here.

[0102] Step 602, the data processing device excludes the bits indicated by the h first punching positions corresponding to the first codeword and the bits indicated by the g second punching positions from each first codeword, and obtains a second data stream including a plurality of second codewords.

[0103] In a possible implementation manner, the bits indicated by the h first punching positions corresponding to the first codeword are the bits corresponding to the h column information bit code blocks, and the bits indicated by the g second punching positions corresponding to the first codeword are the bits corresponding to the g column check bit code blocks. The data processing device excludes the h column information bit code blocks from the e column information bit code blocks based on the identifiers of the h column information bit code blocks, and, excludes the g column check bit code blocks from the f column check bit code blocks based on the identifiers of the g column check bit code blocks, to obtain the second codeword. Taking Figure 7A as an example, the data processing device excludes the h column information bit code blocks from the e column information bit code blocks of the first codeword based on the h column information bit code blocks with identifiers h1, h2, h3, h4, and h5; in addition, the data processing device excludes the g column check bit code blocks from the f column check bit code blocks of the first codeword based on the g column check bit code blocks with identifiers g1 and g2, to obtain the second codeword.

[0104] Exemplarily, taking a codeword with 7 columns punched (256 bits are punched in each column, and a total of 1792 bits are punched) according to the 50GPON standard, and the FEC encoder is an LDPC encoder as an example. As Figure 7B shown, the first codeword includes 69 column code blocks, where columns 1 to 57 of the first codeword are information bit code blocks, and columns 58 to 69 are check bit code blocks. If each column includes 256 bits, then the 57 column information bit code blocks of the first codeword are 57×256 = 14592 bits, the 12 column check bit code blocks of the first codeword are 12×256 = 3072 bits, and the code length of the first codeword is 15872. If the data processing device determines to perform punching processing on a total of 5 column information bit code blocks in columns 22, 23, 42, 52, and 57 of the information bits of each first codeword and a total of 2 column check bit code blocks in columns 60 and 64 of the check bits of each first codeword, then the data processing device will determine the following parameters:

[0105] The number of information bits to be punched P = h×256 = 5×256 = 1280 bits;

[0106] The number of check bits to be punched Q = g×256 = 2×256 = 512 bits;

[0107] The number of information bits after punching K = (e - h)×256 = (57 - 5)×256 = 52×256 = 13312 bits;

[0108] The number of check bits M after punching is M = (f - g) × 256 = (12 - 2) × 256 = 10 × 256 = 2560 bits;

[0109] The length N of the second codeword transmitted in the channel is N = K + M = 13312 + 2560 = 15872 bits;

[0110] The codeword rate R of the second codeword is R = (K + P) / N = (13312 + 1280) / 15872 = 14592 / 15872 ≈ 0.9194.

[0111] The data processing device performs encoding according to the above parameters through an LDPC encoder. Specifically, as Figure 7B shown, based on the 14592 information bits received, the data processing device generates 3072 = 512 + 2560 check bits after encoding, and then performs punching on the positions corresponding to [22 23 42 52 57 60 64]. Finally, there are 13312 information bits and 2560 check bits left, a total of 15872 bits. Then the data processing device generates a physical frame according to the obtained second codeword and Figure 4A sends it.

[0112] As Figure 8 shown, it is a comparison diagram of the punching positions of the foregoing Figure 7B shown example and the traditional punching method. The solution of the traditional technology is to punch 7 columns from the 12-column check bit block of the first codeword; while the solution provided by this application is to punch 7 columns from all 69 columns. In this example, the dark shadow indicates the code block that can transfer extrinsic information to the punching position in the first iteration, and the light shadow indicates the code block that cannot transfer extrinsic information. If punching is performed according to the solution of the traditional technology, in the best case, there are still two rows (i.e., the first row and the third row) of check equations that cannot transfer extrinsic information in the first iteration, while using the solution of this application, all positions can transfer extrinsic information in the first iteration. Therefore, the solution provided by this application has a faster convergence speed and better performance.

[0113] In addition, error code simulations of Gaussian channels are performed on the two examples shown in Figure 8 , and the simulation results are as shown in Figure 9 . Among them, Figure 9 the abscissa of the broken line graph shown is the signal-to-noise ratio (SNR), and the ordinate is the error correction error rate after decoding. It can be seen from the average number of iterations of the two punching methods at different SNR points as shown in Table 1 below.

[0114] Table 1

[0115]

[0116] Compared with the traditional punching method, at the operating point of the system, the average number of decoding iterations is reduced, and the performance is about 0.05 dB better than the existing punching mode. Moreover, the advantage is more obvious at 1e-12. Therefore, the punching method provided in this application is beneficial to ensuring the code rate while reducing the post-error correction rate of the FEC codeword, and is beneficial for the receiving end to use fewer iterative calculations during the decoding process, reducing the processing power consumption of the receiving end hardware.

[0117] As Figure 10 shown, it is a schematic structural diagram of a data processing device 10 provided in this embodiment. It should be understood that the data processing device 10 in the foregoing Figure 3 or Figure 6 corresponding method embodiment can be based on the structure in this embodiment. The data processing device 10 can be Figure 10 or Figure 1 or Figure 2 the transmitting end 01. For example, in an optical communication scenario, the data processing device 10 can be devices such as an optical line terminal (OLT), an optical network unit (ONU), or an optical network terminal (ONT). In addition, the data processing device 10 can also be a functional module, an integrated circuit, or a chip in the transmitting end 01. For example, in an optical communication scenario, the data processing device 10 can be a functional module, an integrated circuit, or a chip in devices such as OLT, ONU, and ONT. For example, the data processing device can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) in devices such as OLT, ONU, and ONT, which is not limited here.

[0118] As Figure 10 shown, the data processing device 10 includes an acquisition module 1001 and a punching processing module 1002. Among them, the acquisition module 1001 is used to acquire a first data stream, the first data stream is a data stream encoded by FEC, and the first data stream includes a plurality of first codewords; the punching processing module 1002 is used to perform punching processing on the information bits and check bits of each first codeword in the first data stream respectively, or perform punching processing on the information bits of each first codeword in the first data stream to obtain a second data stream including a plurality of second codewords, and the length of each second codeword is less than the length of each first codeword.

[0119] Optionally, the obtaining module 1001 includes an FEC encoding module 10011, and the FEC encoding module 10011 is configured to perform FEC encoding on the data stream to be encoded to obtain the first data stream.

[0120] In a possible implementation, the obtaining module 1001 is specifically configured to obtain h first puncturing positions and g second puncturing positions corresponding to each first codeword, each first puncturing position indicating multiple bits in the information bits of the first codeword, each second puncturing position indicating multiple bits in the parity bits of the first codeword, the sum of h and g being equal to w, h being an integer greater than 0, g being an integer greater than or equal to 0, and w being an integer greater than 1; the puncturing processing module 1002 is specifically configured to exclude the bits indicated by the h first puncturing positions and the bits indicated by the g second puncturing positions corresponding to each first codeword from each first codeword to obtain a plurality of second codewords.

[0121] In a possible implementation, w is the number of puncturing positions that need to be excluded in standard puncturing processing. Exemplarily, w = 7.

[0122] In a possible implementation, w is related to the post-correction error rate and the FEC codeword transmission rate.

[0123] In a possible implementation, the first puncturing positions of any two first codewords in the first data stream are the same, and / or the second puncturing positions of any two first codewords in the first data stream are the same.

[0124] In a possible implementation, the first puncturing position and / or the second puncturing position is related to the number of iterations of iterative calculation.

[0125] In a possible implementation, the first puncturing position and / or the second puncturing position of the same first codeword are the puncturing positions such that all the extrinsic information of all the parity equations of the second codeword corresponding to the first codeword can be updated after one iteration of calculation.

[0126] In a possible implementation, the first data stream includes a plurality of first codewords each having a length of (L + T) bits. The first L bits of the first codeword are information bits, and the last T bits of the first codeword are parity bits. L is an integer greater than 0, and T is an integer greater than 0. The puncturing processing module 1002 is specifically configured to exclude P bits from the information bits of the first L bits of each first codeword, and exclude Q bits from the parity bits of the last T bits of each first codeword, so as to obtain a plurality of second codewords. Each second codeword includes K bits of punctured information bits and M bits of punctured parity bits, where K = L - P, M = T - Q, the sum of P and Q is equal to w times r, r is the number of bits to be excluded at each puncturing position, r is an integer greater than 0, w is an integer greater than 0, P is an integer greater than 0, Q is an integer greater than or equal to 0, K is an integer greater than 0, and M is an integer greater than 0.

[0127] In a possible implementation, the foregoing h first puncturing positions include h columns of information bit code blocks, and the foregoing g second puncturing positions include g columns of parity bit code blocks. Each first codeword includes e columns of information bit code blocks and f columns of parity bit code blocks, and each column of code blocks includes at least one bit. The obtaining module 1001 is specifically configured to obtain the identifiers of each column of information bit code blocks in the h columns of information bit code blocks and the identifiers of each column of parity bit code blocks in the g columns of parity bit code blocks. The puncturing processing module 1002 is specifically configured to exclude the h columns of information bit code blocks from the e columns of information bit code blocks based on the identifiers of the h columns of information bit code blocks, and exclude the g columns of parity bit code blocks from the f columns of parity bit code blocks based on the identifiers of the g columns of parity bit code blocks, so as to obtain a second codeword. e is an integer greater than 1, f is an integer greater than 1, h is an integer greater than 0, and g is an integer greater than or equal to 0. Optionally, the sum of h and g is equal to w.

[0128] In a possible implementation, the parity check matrix of the second codeword corresponds to multiple layers of parity check equations. The variable nodes in each layer of the parity check equations of the parity check matrix of the second codeword can obtain extrinsic information after the first iterative calculation, and the extrinsic information is used to decode the parity check equations corresponding to the variable nodes related to the extrinsic information in the second codeword.

[0129] In a possible implementation, there is at least one frame in the first data stream that has been shortened. The length of the information bits of the last first codeword of the shortened frame is less than the length of the information bits of the other first codewords of the frame. The data processing device further includes a zero-padding processing module 10012. The zero-padding processing module 10012 is configured to perform zero-padding processing on each shortened frame in the data stream to be encoded, so as to obtain a data stream to be encoded that has been zero-padded. The FEC encoding module 10011 is configured to perform FEC encoding processing on the data stream to be encoded that has been zero-padded, so as to obtain an encoded data stream. The shortening processing module 10013 is configured to perform shortening processing on each frame in the encoded data stream that has been zero-padded, so as to obtain the first data stream.

[0130] In a possible implementation, there is at least one shortened frame in the first data stream. The length of the information bits of the last first codeword of the shortened frame is equal to (L - S), where S is an integer greater than 0 and less than L; an acquisition module 1001, configured to acquire a data stream to be encoded, the data stream to be encoded includes a plurality of data blocks with a length of L and at least one shortened data block with a length less than L, and the shortened data block is the last data block of a frame; a zero-padding processing module 10012, configured to supplement S zero bits after each shortened data block in the data stream to be encoded, to obtain the data stream to be encoded after zero-padding processing; an FEC encoding module 10011, configured to perform FEC encoding processing on the data stream to be encoded after zero-padding processing with L bits as one encoding block, to obtain an encoded data stream; a shortening processing module 10013, configured to delete S zero bits from the information bits of the last encoding block of the frame in the encoded data stream, to obtain the first data stream.

[0131] In a possible implementation, the first data stream further includes at least one shortened first codeword with a length of (L - S + T) bits. The first (L - S) bits of the shortened first codeword are information bits, and the last T bits of the shortened first codeword are parity bits. L is an integer greater than 0, and T is an integer greater than 0. A puncturing processing module 1002 is specifically configured to exclude P' bits from the information bits of the first (L - S) bits of the shortened first codeword, and exclude Q bits from the parity bits of the last T bits of the shortened first codeword, to obtain a shortened second codeword. The shortened second codeword includes K' bits of punctured information bits and M bits of punctured parity bits, where K' = L - S - P', M = T - Q, the sum of P' and Q is equal to w times r, r is the number of bits to be excluded at each puncturing position, r is an integer greater than 0, w is an integer greater than 0, P' is an integer greater than 0, Q is an integer greater than or equal to 0, K' is an integer greater than 0, and M is an integer greater than 0.

[0132] The rest can refer to the above Figure 3 or Figure 6 the method of the data processing device in the corresponding embodiment, which will not be elaborated here.

[0133] As Figure 11 shown, it is a schematic structural diagram of another data processing device 110 provided in this embodiment. It should be understood that the data processing device in the foregoing Figure 3 or Figure 6 corresponding method embodiment can be based on the structure of the data processing device 110 shown in this embodiment. As Figure 11 shown Figure 11As shown, the data processing device 110 may include a processor 1101 and a transceiver 1102, and the processor 1101 is coupled to the transceiver 1102.

[0134] Among them, the aforementioned processor 1101 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor 1101 may refer to a single processor or may include multiple processors, and specific details are not limited here.

[0135] Among them, the aforementioned transceiver 1102 may also be referred to as a transceiver unit, a transceiver, a transceiver device, etc. Optionally, the devices in the transceiver unit for implementing the receiving function may be regarded as the receiving unit, and the devices in the transceiver unit for implementing the sending function may be regarded as the sending unit, that is, the transceiver unit includes a receiving unit and a sending unit. The receiving unit may also be referred to as a receiver, an input port, a receiving circuit, etc., and the sending unit may be referred to as a transmitter, a transmitter, or a transmitting circuit, etc.

[0136] Optionally, the data processing device 110 further includes a memory 1103. Among them, the processor 1101 is coupled to the memory 1103. The memory 1103 is mainly used to store software programs and data. The memory 1103 can exist independently and be connected to the processor 1101. Optionally, the memory 1103 can be integrated with the processor 1101, for example, integrated within one or more chips. Among them, the memory 1103 can store the program code for implementing the technical solution of the embodiment of the present application and is controlled by the processor 1101 to execute. Various computer program codes executed can also be regarded as the driver programs of the processor 1101. The memory 1103 can include volatile memory, such as random-access memory (RAM); the memory can also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD) or solid-state drive (SSD); the memory 1103 can also include a combination of the above types of memories. The memory 1103 can refer to a single memory or can include multiple memories. Exemplarily, the memory 1103 is used to store various data. For example, at least one first punching position and at least one second punching position. For another example, the identifiers of the h-column information-bit code blocks and the g-column parity-bit code blocks in the first codeword. Specifically, please refer to the relevant introduction in the foregoing embodiments, and details are not described herein again.

[0137] In one implementation, the memory 1103 stores computer-readable instructions, and the computer-readable instructions include multiple software modules. For example, the acquisition module 1001, punching processing module 1002, FEC encoding module 10011, zero-padding processing module 10012, shortening processing module 10013, etc. introduced above. Specifically, please refer to the relevant description in the foregoing Figure 10 and details are not described herein again. Figure 10

[0138] In addition, the present application provides a computer program product, which includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are fully or partially generated. For example, to implement as described above Figure 3 or Figure 6Methods related to the data processing device therein. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from a website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can store or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a digital versatile disc (DVD)), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0139] In addition, the present application also provides a computer-readable storage medium storing a computer program, which is executed by a processor to implement the method related to the data processing device as described above Figure 3 or Figure 6 the method related to the data processing device therein.

[0140] It should be understood that in various embodiments of the present application, the magnitudes of the serial numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0141] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

Claims

1. A data processing method, characterized in that, Including: Obtain a first data stream, where the first data stream is a data stream that has been forward error correction (FEC) encoded. The first data stream includes a plurality of first codewords, and the first codewords are binary LDPC codewords; Perform puncturing processing on the information bits and parity bits of each of the first codewords in the first data stream respectively to obtain a second data stream including a plurality of second codewords. The length of each second codeword is less than the length of each first codeword. The puncturing positions of the same first codeword are the puncturing positions such that the extrinsic information of all the parity equations corresponding to the second codeword obtained from the first codeword can be updated after one iteration calculation; Output the second data stream.

2. The method according to claim 1, wherein The performing puncturing processing on the information bits and parity bits of each of the first codewords in the first data stream respectively to obtain a second data stream including a plurality of second codewords includes: Obtain h first puncturing positions and g second puncturing positions corresponding to each first codeword. Each first puncturing position indicates a plurality of bits in the information bits of the first codeword, and each second puncturing position indicates a plurality of bits in the parity bits of the first codeword. h is an integer greater than 0, g is an integer greater than or equal to 0, and the sum of h and g is equal to w, where w is an integer greater than 1; Exclude the bits indicated by the h first puncturing positions and the bits indicated by the g second puncturing positions from each of the first codewords to obtain the plurality of second codewords.

3. The method according to claim 1, characterized in that The first puncturing positions of any two of the first codewords in the first data stream are the same.

4. The method according to any one of claims 1 to 3, characterized in that, The first data stream includes a plurality of first codewords of length (L + T) bits. The first L bits of the first codeword are information bits, and the last T bits of the first codeword are parity bits. L is an integer greater than 0, and T is an integer greater than 0; The performing puncturing processing on the information bits and parity bits of each of the first codewords in the first data stream respectively to obtain a second data stream including a plurality of second codewords includes: Exclude P bits from the information bits of the first L bits of each first codeword, and exclude Q bits from the parity bits of the last T bits of each first codeword to obtain a plurality of the second codewords. Each second codeword includes K bits of punctured information bits and M bits of punctured parity bits. P is an integer greater than 0, Q is an integer greater than or equal to 0, K is an integer greater than 0, and M is an integer greater than 0.

5. The method according to claim 4, characterized in that, The parity check matrix of the second codeword corresponds to multiple layers of parity equations. The variable nodes in each layer of the parity equations of the parity check matrix of the second codeword can obtain extrinsic information after the first iteration calculation, and the extrinsic information is used to decode the parity equations corresponding to the variable nodes related to the extrinsic information in the second codeword.

6. The method according to any one of claims 1 to 3, characterized in that There is at least one shortened frame in the first data stream; The obtaining the first data stream includes: Perform zero-padding processing on each shortened frame in the data stream to be encoded to obtain a data stream to be encoded with zero-padding processed; Perform FEC encoding processing on the data stream to be encoded with zero-padding processed to obtain the first data stream.

7. The method according to claim 1, characterized in that The first codeword includes an information-bit code block and a parity-bit code block.

8. The method according to claim 7, wherein The first codeword includes an information-bit code block of 57 bits and a parity-bit code block of 12 columns.

9. The method according to claim 1, characterized in that, The obtaining of the first data stream includes: Performing forward error correction (FEC) encoding on the original data stream to obtain a plurality of first data streams each including the first codeword.

10. The method according to claim 9, wherein The FEC encoding is a low-density parity-check code or a flexible FEC encoding.

11. The method according to claim 9, characterized in that The method further includes: Determining a parity-check matrix of the first codeword based on the first codeword.

12. A data processing device, characterized in that, Comprising a processor and a transceiver; The transceiver is configured to receive a first data stream and output a second data stream; The processor is configured to execute the method according to any one of claims 1 to 11.

13. A chip, characterized in that, Comprising at least one logic circuit and an input / output interface; The input / output interface is configured to input a first data stream and output a second data stream; The logic circuit is configured to execute the method according to any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that, Storing instructions which, when run on a computer, cause the computer to execute the method according to any one of claims 1 to 11.

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