Frequency-adaptive single-photon detection system

Abstract

The present application provides a frequency adaptive single-photon detection system, which relates to the field of weak light detection technology. The frequency adaptive single-photon detection system includes: a frequency adaptive generation circuit for providing the gating frequency required by the avalanche diode, including a first phase-locked loop unit and a second phase-locked loop unit; an extremely narrowband interference circuit for extracting the avalanche signal generated by the avalanche diode, and adaptively adjusting the center frequency to suppress the capacitive response caused by the gating signal in the avalanche signal. The extremely narrowband interference circuit includes: a varactor diode for changing the center frequency of the extremely narrowband interference circuit according to the frequency of the gating signal; a voltage-controlled attenuator for balancing the attenuation change of the varactor diode to maintain the suppression effect of the extremely narrowband interference circuit. Based on an external reference signal, the phase-locked loop technology is used to generate the gating frequency required by the avalanche diode, and the center frequency of the extremely narrowband interference circuit is adaptively adjusted to match it, so that the extremely narrowband interference circuit remains in the optimal working state.

Description

Technical Field

[0001] The present application relates to the field of weak light detection technology, and in particular to a frequency adaptive single photon detection system. Background Art

[0002] In recent years, single-photon detectors based on semiconductor InGaAs / InP avalanche photodiodes (APDs) have played a vital role in the demand for weak-light sensing and detection in fields such as quantum communications, space communications, LiDAR, bioimaging, and national defense. In particular, with the rapid development of quantum information, APDs have become an indispensable module in practical quantum communication networks due to their advantages such as small size, low cost, low power consumption, and lack of cryogenic refrigeration.

[0003] The APD single-photon detector module based on an extremely narrowband interferometer circuit has a high degree of integration and is only 8.8 × 6 × 2 cm in size. 3 Although the size is small, it still faces the problem of requiring an external signal generator to generate a 1.25 GHz gating signal for the APD single-photon detector. This greatly increases the cost of the APD single-photon detector and limits its application scenarios.

[0004] Furthermore, in high-speed quantum communication networks, APD single-photon detectors (APDs) often use gating signals to achieve rapid avalanche and quenching, improving detection efficiency and count rates. However, due to the parasitic capacitance of the avalanche photodiode and its circuitry, the capacitive response of the gating signal can mask the photon-induced avalanche signal. Therefore, post-processing circuitry that effectively eliminates the capacitive response and extracts the weak avalanche signal is crucial.

[0005] In the prior art, APD single-photon detectors typically use post-processing circuits to eliminate capacitive response and extract weak avalanche signals. Post-processing circuits include ultra-narrowband interferometry circuits with fixed delays and ultra-narrowband interferometry circuits with adjustable frequency.

[0006] Existing fixed-delay, ultra-narrowband interferometry circuit technology can effectively eliminate the fundamental frequency and higher harmonic frequencies of the capacitance response of the gate signal at the APD output. It is unaffected by the operating state of the APD device itself and can stably provide a wide and continuous frequency domain passband to process avalanche narrow pulse signals. It has minimal impact on the signal-to-noise ratio, pulse waveform, and jitter of avalanche narrow pulse signals, and significantly optimizes the detection efficiency, afterpulse, and temporal resolution of single-photon detectors. However, the center frequency of this fixed-delay, ultra-narrowband interferometry circuit technology is not adjustable, limiting its use.

[0007] Existing frequency-adjustable ultra-narrowband interferometer circuit technology can passively adjust the center frequency within a certain frequency range, but it cannot automatically adjust to the input external frequency, which affects the suppression effect. When facing frequency differences between different external microwave signal sources, the ultra-narrowband interferometer circuit cannot operate optimally, reducing the suppression effect on the gate signal and affecting the performance of the entire APD single-photon detector. Summary of the Invention

[0008] In order to solve at least one of the above problems, the present application proposes a frequency adaptive single photon detection system.

[0009] According to the first aspect of the present application, at least one embodiment of the present application provides a frequency-adaptive single-photon detection system, including: a frequency-adaptive generation circuit, connected to an avalanche diode, for providing the gating frequency required by the avalanche diode, including: a first phase-locked loop unit, for receiving an external reference signal and generating a first operating frequency according to the frequency of the external reference signal; a second phase-locked loop unit, connected to the first phase-locked loop unit, for correcting the first operating frequency to generate the gating frequency; an extremely narrowband interference circuit, connected to the avalanche diode, for extracting the avalanche signal generated by the avalanche diode, and adaptively adjusting the center frequency according to the frequency of the gating signal to suppress the capacitive response caused by the gating signal in the avalanche signal, the extremely narrowband interference circuit including: a varactor diode, for changing the center frequency of the extremely narrowband interference circuit according to the frequency of the gating signal; a voltage-controlled attenuator, for balancing the attenuation change of the varactor diode to maintain the suppression effect of the extremely narrowband interference circuit.

[0010] For example, in some embodiments of the present application, the first phase-locked loop unit includes: a first voltage-controlled oscillator, used to generate a first output signal according to the frequency of the external reference signal; a first level conversion circuit, connected to the first voltage-controlled oscillator, used to receive the first output signal and generate a first feedback signal according to the frequency difference between the first output signal and the external reference signal; a first phase-locked loop, connected to the first level conversion circuit, used to receive the first feedback signal and generate a first error signal according to the phase difference between the external reference signal and the first feedback signal; a first low-pass filter, connected to the first phase-locked loop and the first voltage-controlled oscillator respectively, used to filter out noise in the first error signal, generate a first error voltage, and output it to the first voltage-controlled oscillator; wherein, the first voltage-controlled oscillator is also used to adjust the frequency of the first output signal according to the first error voltage to generate the first operating frequency.

[0011] For example, in some embodiments of the present application, when the frequency difference between the first output signal and the external reference signal is constant, the phase difference between the external reference signal and the first feedback signal is zero, and the first phase-locked loop is locked to keep the frequency difference between the frequency of the first output signal of the first voltage-controlled oscillator and the frequency of the external reference signal constant, thereby generating the first operating frequency.

[0012] For example, in some embodiments of the present application, the first phase-locked loop unit further includes: a first balun connected between the first phase-locked loop and the first level conversion circuit, and configured to transmit the first feedback signal to the first phase-locked loop.

[0013] For example, in some embodiments of the present application, the second phase-locked loop unit includes: a second voltage-controlled oscillator, used to receive the first operating frequency and generate a second output signal; a second level conversion circuit, connected to the second voltage-controlled oscillator, used to receive the second output signal and generate a second feedback signal according to the difference between the frequency of the second output signal and the first operating frequency; a second phase-locked loop, connected to the second level conversion circuit, used to receive the second feedback signal and generate a second error signal according to the phase difference between the first operating frequency and the second feedback signal; a second low-pass filter, connected to the second phase-locked loop and the second voltage-controlled oscillator respectively, used to filter out noise in the second error signal, generate a second error voltage, and output it to the second voltage-controlled oscillator; wherein the second voltage-controlled oscillator is also used to adjust the frequency of the second output signal according to the second error voltage to generate a second operating frequency, that is, the gating frequency.

[0014] For example, in some embodiments of the present application, when the difference between the frequency of the second output signal and the first operating frequency is constant, the phase difference between the first operating frequency and the second feedback signal is zero, and the second phase-locked loop is locked to keep the frequency difference between the frequency of the second output signal of the second voltage-controlled oscillator and the first operating frequency constant, thereby generating the second operating frequency.

[0015] For example, in some embodiments of the present application, the second phase-locked loop unit further includes: a second balun connected between the second phase-locked loop and the second level conversion circuit, and configured to transmit the second feedback signal to the second phase-locked loop.

[0016] For example, in some embodiments of the present application, it also includes: a first single-pole double-throw switch, wherein the input end of the first single-pole double-throw switch is used to receive the external reference signal, and the first output end is connected to the first phase-locked loop unit; a transmission unit, connected to the second output end of the first single-pole double-throw switch, and used to transmit the external reference signal; a second single-pole double-throw switch, wherein the first input end of the second single-pole double-throw switch is connected to the second phase-locked loop unit, and the second input end is connected to the transmission unit.

[0017] For example, in some embodiments of the present application, the first single-pole double-throw switch and the second single-pole double-throw switch are configured as follows: when the external reference signal is less than the required gating frequency of the avalanche diode, the first output end of the first single-pole double-throw switch is connected to the first phase-locked loop unit, the second output end is disconnected from the transmission unit, and the first input end of the second single-pole double-throw switch is connected to the second phase-locked loop unit, and the second input end is disconnected from the transmission unit; when the external reference signal is equal to the required gating frequency of the avalanche diode, the second output end of the first single-pole double-throw switch is connected to the transmission unit, the first output end is disconnected from the first phase-locked loop unit, the second input end of the second single-pole double-throw switch is connected to the transmission unit, and the first input end is disconnected from the second phase-locked loop unit; when the frequency adaptive single-photon detection system is powered off, the first single-pole double-throw switch is disconnected from the first phase-locked loop unit and the transmission unit, and the second single-pole double-throw switch is disconnected from the second phase-locked loop unit and the transmission unit.

[0018] For example, in some embodiments of the present application, the transmission unit includes: a first delay line, connected to the second output end of the first single-pole double-throw switch to receive the external reference signal; and a third balun, connected to the first delay line and the second input end of the second single-pole double-throw switch, respectively, to transmit the external reference signal.

[0019] For example, in some embodiments of the present application, it also includes: a fourth balun, connected between the first phase-locked loop unit and the second phase-locked loop unit, for transmitting the first operating frequency to the second phase-locked loop unit; a second delay line, connected to the second phase-locked loop unit; a fifth balun, connected to the second delay line and the first input end of the second single-pole double-throw switch, for transmitting the gating frequency.

[0020] For example, in some embodiments of the present application, it also includes: an amplifier, connected to the second single-pole double-throw switch, for amplifying the external reference signal or the second operating frequency; a filter, connected to the amplifier, for filtering out frequencies other than the amplified external reference signal or the second operating frequency to obtain a specific frequency signal.

[0021] For example, some embodiments of the present application further include: a programmable logic unit connected to the second phase-locked loop unit, used to dynamically compile the second phase-locked loop unit to modify the second output signal.

[0022] Through the above-mentioned example embodiments, the present application provides a frequency-adaptive single-photon detection system, which uses phase-locked loop technology to generate the gating signal frequency required by the APD single-photon detector, that is, the gating frequency provided above or the external reference signal. After inputting it into the avalanche diode APD, an avalanche signal is generated. The extremely narrowband interference circuit compares the frequency of the avalanche signal with the center frequency of the extremely narrowband interference circuit, and dynamically adjusts the control voltage on the varactor diode in the extremely narrowband interference circuit to adjust the center frequency of the extremely narrowband interference circuit, so that the center frequency of the extremely narrowband interference circuit is aligned with the frequency of the gating signal in the avalanche signal, so that the extremely narrowband interference circuit is always maintained in the optimal working state, effectively eliminating the capacitive response caused by the gating signal, and improving the performance of the APD single-photon detector.

[0023] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] By describing in detail exemplary embodiments thereof with reference to the accompanying drawings, the above and other objects, features and advantages of the present application will become more apparent. The drawings described below are only some embodiments of the present application, and are not intended to limit the present application.

[0025] Figure 1 A schematic diagram illustrating a frequency adaptive single photon detection system according to an exemplary embodiment is shown;

[0026] Figure 2a A waveform diagram showing an input reference signal and an output signal of a frequency adaptive generation circuit according to an exemplary embodiment;

[0027] Figure 2b Another waveform diagram showing an exemplary input reference signal and an output signal of the frequency adaptive generation circuit;

[0028] Figure 3 A schematic diagram of an extremely narrowband interferometer circuit according to an exemplary embodiment is shown. DETAILED DESCRIPTION

[0029] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the drawings represent like or similar parts, and thus repeated description thereof will be omitted.

[0030] The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of these specific details, or other methods, components, materials, devices, etc. may be employed. In these cases, well-known structures, methods, devices, implementations, materials or operations will not be shown or described in detail.

[0031] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0032] The terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0033] Those skilled in the art will understand that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present application, and therefore cannot be used to limit the scope of protection of the present application.

[0034] Figure 1 A schematic diagram of a frequency adaptive single-photon detection system is shown according to an exemplary embodiment.

[0035] like Figure 1As shown, the frequency-adaptive single-photon detection system includes a frequency-adaptive generation circuit 10, an avalanche diode 20, and an ultra-narrowband interferometer circuit 30. The frequency-adaptive generation circuit 10 is connected to the avalanche diode 20 to provide the gate frequency required by the avalanche diode. The ultra-narrowband interferometer circuit 30 is connected to the avalanche diode 20 to extract the avalanche signal generated by the avalanche diode 20 and adaptively adjust the center frequency based on the frequency of the gate signal in the avalanche signal to suppress the capacitive response caused by the gate signal.

[0036] like Figure 1 As shown, the frequency adaptive generation circuit 10 includes a first phase-locked loop unit 101 and a second phase-locked loop unit 102 .

[0037] The first phase-locked loop unit 101 is configured to receive an external reference signal and, based on the external reference signal, generate a first operating frequency for the ultra-narrowband interferometer circuit 101. The second phase-locked loop unit 102 is connected to the first phase-locked loop unit 101 and is configured to modify the first operating frequency to generate a second operating frequency, i.e., the gating frequency.

[0038] According to an example embodiment, the first phase-locked loop unit 101 includes a first phase-locked loop 1011 , a first low-pass filter 1012 , a first voltage-controlled oscillator 1013 , a first level conversion circuit 1014 , and a first balun 1015 .

[0039] The first phase-locked loop (PLL) 1011 is configured to receive an external reference signal CLK In. The first voltage-controlled oscillator (VCO) 1013 is configured to generate a first output signal based on the frequency of the external reference signal. A first level shifter (LVCO) 1014 is connected to the first VCO 1013 and configured to receive the first output signal and generate a first feedback signal based on the frequency difference between the first output signal and the external reference signal. The first phase-locked loop (PLL) 1011 is configured to receive the first feedback signal and generate a first error signal based on the phase difference between the external reference signal and the first feedback signal. A first low-pass filter (LPF) 1012 is connected to the first PLL 1011 and the first VCO 1013, respectively, and configured to filter out high-frequency noise from the first error signal, generate a first error voltage, and output the first error voltage to the first VCO 1013. The first VCO 1013 adjusts the frequency of the first output signal based on the first error voltage to generate a first operating frequency. The first balun 1015 is connected between the first phase-locked loop 1011 and the first level conversion circuit 1014 , and is configured to transmit the first feedback signal to the first phase-locked loop 1011 .

[0040] According to an example embodiment, when the frequency difference between the first output signal and the external reference signal is constant, the phase difference between the external reference signal and the first feedback signal is zero, and the first phase-locked loop 1011 is locked to keep the frequency difference between the frequency of the first output signal of the first voltage-controlled oscillator 1012 and the frequency of the external reference signal constant, thereby generating a first operating frequency.

[0041] When an external reference signal enters the adaptive frequency generation circuit, the phase-locked loop (PLL) is initially unlocked. The frequency of the output signal generated by the voltage-controlled oscillator (VCO) differs from the frequency of the external reference signal, generating a feedback signal to the PLL. The PLL compares the phase difference between the external reference signal and the feedback signal to generate an error signal. This error signal is filtered through a low-pass filter to remove high-frequency noise and generate an error voltage. This error voltage adjusts the output frequency of the VCO. As long as the error signal is present, the error voltage changes until the VCO's output frequency gradually approaches the frequency of the input signal. At this point, the phase difference approaches zero, and the error signal also approaches zero, indicating that the PLL is locked. The frequency difference between the VCO's output frequency and the input signal maintains a stable phase relationship. Once locked, the PLL continuously adjusts the VCO's frequency to maintain a constant phase difference between the external reference signal and the feedback signal, allowing it to quickly adapt even if the external reference signal's frequency changes.

[0042] According to an example embodiment, the second phase-locked loop unit 102 includes a second phase-locked loop 1021 , a second low-pass filter 1022 , a second voltage-controlled oscillator 1023 , a second level conversion circuit 1024 , and a second balun 1025 .

[0043] The second phase-locked loop (PLL) 1021 is configured to receive a first operating frequency. The second voltage-controlled oscillator (VCO) 1023 is configured to generate a second output signal based on the first operating frequency. A second level shifter (LVCO) 1024 is connected to the second VCO 1023 and configured to receive the second output signal and generate a second feedback signal based on the difference between the frequency of the second output signal and the first operating frequency. The second phase-locked loop (PLL) 1021 is connected to the second level shifter (LVCO) 1024 and configured to receive the second feedback signal and generate a second error signal based on the phase difference between the first operating frequency and the second feedback signal. A second low-pass filter (LPF) 1022 is connected to the second PLL 1021 and the second VCO 1023, respectively, and configured to filter out high-frequency noise from the second error signal, generate a second error voltage, and output the second error voltage to the second VCO 1023. The second VCO 1023 adjusts the frequency of the second output signal based on the second error voltage to generate a second operating frequency, i.e., a gated frequency. The second balun 1025 is connected between the second phase-locked loop 1021 and the second level conversion circuit 1024 , and is configured to transmit the second feedback signal to the second phase-locked loop 1021 .

[0044] According to an example embodiment, when the difference between the frequency of the second output signal and the first operating frequency is constant, the phase difference between the first operating frequency and the second feedback signal is zero, and the second phase-locked loop 1021 is locked to keep the frequency difference between the frequency of the second output signal of the second voltage-controlled oscillator 1022 and the first operating frequency constant, thereby generating the second operating frequency, i.e., the gated frequency RF Out.

[0045] This application utilizes a two-stage cascaded phase-locked loop (PLL) to generate the gate frequency required by the avalanche diode 20 through progressive locking. To stabilize the generated frequency, a voltage-controlled crystal oscillator (VCXO) can be used in the first PLL unit. VCXOs have a narrower tuning range and can be used in applications with narrower loop bandwidths. This narrower loop bandwidth helps purify the noise of the reference source, requiring only minor voltage adjustments to correct for deviations, allowing for use as the reference frequency for the second-stage PLL. Furthermore, VCXOs have a lower broadband noise floor, allowing for wide-ranging adjustments.

[0046] Figure 2a A waveform diagram shows the input reference signal and the output signal of the frequency adaptive generation circuit of an exemplary embodiment. After powering on, the frequency adaptive generation circuit generates an initially set gated frequency signal. The initial phase difference between the input reference signal and the gated signal is constant and can be further fine-tuned.

[0047] For example, Figure 2a A waveform diagram showing that the phase difference between the input reference signal and the gate signal maintains a first phase difference; Figure 2b A waveform diagram showing that the phase difference between the input reference signal and the gate signal maintains a second phase difference.

[0048] According to an example embodiment, the frequency adaptive generation circuit further includes: a first single-pole double-throw switch 104 , a transmission unit 105 , and a second single-pole double-throw switch 106 .

[0049] The first single-pole double-throw switch 104 has an input terminal for receiving an external reference signal, and a first output terminal connected to the first phase-locked loop unit 101. The transmission unit 105 is connected to the second output terminal of the first single-pole double-throw switch 104 for transmitting the external reference signal. The second single-pole double-throw switch 106 has a first input terminal connected to the second phase-locked loop unit 102, and a second input terminal connected to the transmission unit 105.

[0050] According to an example embodiment, the first single-pole double-throw switch 104 and the second single-pole double-throw switch 106 are configured as:

[0051] When the external reference signal is less than the required gating frequency of the avalanche diode 20, the first output terminal of the first single-pole double-throw switch 104 is connected to the first phase-locked loop unit 101, and the second output terminal is disconnected from the transmission unit 105. The first input terminal of the second single-pole double-throw switch 106 is connected to the second phase-locked loop unit 102, and the second input terminal is disconnected from the transmission unit 105.

[0052] When the external reference signal is equal to the desired gating frequency of the avalanche diode 20, the second output terminal of the first single-pole double-throw switch 104 is connected to the transmission unit 105, and the first output terminal is disconnected from the first phase-locked loop unit 101; the second input terminal of the second single-pole double-throw switch 106 is connected to the transmission unit 105, and the first input terminal is disconnected from the second phase-locked loop unit 102;

[0053] When the frequency adaptive generation circuit 10 is powered off, the first SPDT switch 104 is disconnected from the first PLL unit 101 and the transmission unit 105 , and the second SPDT switch 106 is disconnected from the second PLL unit 102 and the transmission unit 105 .

[0054] According to some embodiments, the required gating frequency of the avalanche diode 20 can be set independently, for example, 1.25 GHz, but the present application is not limited thereto.

[0055] According to an example embodiment, the transmission unit 105 includes a first delay line 1051 and a third balun 1052 .

[0056] The first delay line 1051 is connected to the second output terminal of the first SPDT switch 104 to receive the external reference signal. The third balun 1052 is connected to the first delay line 1051 and the second input terminal of the second SPDT switch 106 to transmit the external reference signal.

[0057] According to an example embodiment, the frequency adaptive generation circuit 10 further includes a fourth balun 1071 , a second delay line 1072 , a fifth balun 1073 , an amplifier 1081 , a filter 1082 , and a programmable logic unit 109 .

[0058] The fourth balun 1071 is connected between the first phase-locked loop unit 101 and the second phase-locked loop unit 102 and is configured to transmit the first operating frequency to the second phase-locked loop unit. The second delay line 1072 is connected to the second phase-locked loop unit 102. The fifth balun 1073 is connected to the second delay line 1072 and the first input terminal of the second single-pole double-throw switch 106, respectively, and is configured to transmit the gating frequency.

[0059] Amplifier 1081 is connected to second SPDT switch 106 for amplifying the external reference signal or the second operating frequency. Filter 1082 is connected to amplifier 1081 for filtering out frequencies other than the amplified external reference signal or the second operating frequency to obtain a signal of a specific frequency.

[0060] The programmable logic unit 109 is connected to the second phase-locked loop unit 102 and is used to dynamically compile the second phase-locked loop unit 102 to modify the second output signal.

[0061] Single-photon detectors used in the 1550nm communications band are primarily based on semiconductor InGaAs / InP materials. To suppress post-pulse noise and improve the photon count rate of InGaAs / InP-based APDs, gate-driven avalanche photodiodes are often used to reduce avalanche charge and post-avalanche recovery time. However, due to parasitic capacitance within the avalanche photodiode and circuitry, the capacitive response of the gate signal can mask the photon-induced avalanche signal. Therefore, this capacitive response must be effectively eliminated.

[0062] Figure 3 A schematic diagram of an extremely narrowband interferometer circuit according to an exemplary embodiment is shown.

[0063] like Figure 3 As shown, the ultra-narrowband interferometer circuit is used to extract the avalanche signal generated by the avalanche diode and adaptively adjusts the center frequency to match the frequency of the gate signal in the avalanche signal, thereby suppressing the capacitive response caused by the gate signal. The ultra-narrowband interferometer circuit includes two 9:1 power couplers (CPLs) 3011 and 3012, a voltage-controlled attenuator (VCA) 302, a surface acoustic wave filter (SAW) 303, a temperature sensor (DTS) 304, a varactor 305, an inductor 3061, a capacitor 3062, and two 50 Ω resistors.

[0064] The ultra-narrowband interferometer circuit adaptively adjusts its center frequency to match the frequency of the avalanche signal (APD raw signal) using the following operating principles: a surface acoustic wave (SAW) filter filters out the fundamental wave in the avalanche signal. Then, in response to the generated interference signal through a transmission capacitor under a gated signal, the control voltage of the varactor diode is adjusted to achieve real-time compensation for the SAW filter's changing group delay, thereby changing the center frequency of the ultra-narrowband interferometer circuit. Furthermore, the attenuation changes of the varactor diode are balanced by adjusting the voltage-controlled attenuator on the other interferometer arm to maintain the suppression effect of the ultra-narrowband interferometer circuit.

[0065] This application is based on an external reference signal and uses phase-locked loop technology to generate the gating signal frequency required for the APD single-photon detector, that is, the gating frequency or external reference signal provided above; after inputting it into the avalanche diode APD, an avalanche signal is generated; the extremely narrowband interference circuit compares the frequency of the gating signal in the avalanche signal with the center frequency of the extremely narrowband interference circuit, and dynamically adjusts the control voltage on the varactor diode in the extremely narrowband interference circuit to adjust the center frequency of the extremely narrowband interference circuit, so that the center frequency of the extremely narrowband interference circuit is aligned with the frequency of the gating signal in the avalanche signal, so that the extremely narrowband interference circuit always remains in the optimal working state, effectively eliminating the capacitive response caused by the gating signal, and improving the performance of the APD single-photon detector.

[0066] This technical solution is applicable to the field of single-photon detection. Based on different input reference signal frequencies, it realizes dynamic adjustment of the operating frequency of the APD single-photon detector post-processing circuit - the ultra-narrowband interferometer circuit, so that the ultra-narrowband interferometer circuit always keeps the capacitance response caused by the gate signal in the avalanche signal of the avalanche diode in the best suppression state, further improving the overall performance of the APD single-photon detector.

[0067] It should be clearly understood that this application describes how to form and use specific examples, but this application is not limited to any details of these examples. On the contrary, based on the teaching of the content disclosed in this application, these principles can be applied to many other embodiments.

[0068] Furthermore, it should be noted that the aforementioned figures are merely illustrative of the processes included in the methods according to exemplary embodiments of the present application and are not intended to be limiting. It is readily understood that the processes illustrated in the aforementioned figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0069] While the exemplary embodiments of the present application have been specifically illustrated and described above, it should be understood that the present application is not limited to the detailed structures, configurations, or implementations described herein; rather, the present application is intended to encompass various modifications and equivalent configurations within the spirit and scope of the appended claims.

Claims

1. A frequency-adaptive single-photon detection system, characterized in that: include: The frequency adaptive generation circuit is connected to the avalanche diode and is used to provide the gate frequency required by the avalanche diode, including: a first phase-locked loop unit, configured to receive an external reference signal and generate a first operating frequency according to a frequency of the external reference signal; a second phase-locked loop unit, connected to the first phase-locked loop unit, and configured to modify the first operating frequency to generate the gate frequency; An extremely narrowband interference circuit is connected to the avalanche diode and is used to extract the avalanche signal generated by the avalanche diode and adaptively adjust the center frequency according to the frequency of the gate signal in the avalanche signal to suppress the capacitive response caused by the gate signal. The extremely narrowband interference circuit includes: a varactor diode, configured to change the center frequency of the extremely narrowband interference circuit according to the frequency of the gating signal; A voltage-controlled attenuator is used to balance the attenuation variation of the varactor diode to maintain the suppression effect of the extremely narrowband interference circuit.

2. The frequency adaptive single photon detection system according to claim 1, wherein: The first phase-locked loop unit includes: a first voltage-controlled oscillator, configured to generate a first output signal according to the frequency of the external reference signal; a first level conversion circuit, connected to the first voltage-controlled oscillator, configured to receive the first output signal and generate a first feedback signal according to a frequency difference between the first output signal and the external reference signal; a first phase-locked loop, connected to the first level conversion circuit, configured to receive the first feedback signal and generate a first error signal according to a phase difference between the external reference signal and the first feedback signal; a first low-pass filter, connected to the first phase-locked loop and the first voltage-controlled oscillator, respectively, for filtering out noise in the first error signal, generating a first error voltage, and outputting the first error voltage to the first voltage-controlled oscillator; The first voltage-controlled oscillator is further configured to adjust the frequency of the first output signal according to the first error voltage to generate the first operating frequency.

3. The frequency adaptive single photon detection system according to claim 2, wherein: When the frequency difference between the first output signal and the external reference signal is constant, the phase difference between the external reference signal and the first feedback signal is zero, and the first phase-locked loop is locked to keep the frequency difference between the frequency of the first output signal of the first voltage-controlled oscillator and the frequency of the external reference signal constant, thereby generating the first operating frequency.

4. The frequency adaptive single photon detection system according to claim 2, wherein: The first phase-locked loop unit further includes: The first balun is connected between the first phase-locked loop and the first level conversion circuit, and is used to transmit the first feedback signal to the first phase-locked loop.

5. The frequency adaptive single photon detection system according to claim 1, wherein: The second phase-locked loop unit includes: a second voltage-controlled oscillator, configured to receive the first operating frequency and generate a second output signal; a second level conversion circuit, connected to the second voltage-controlled oscillator, configured to receive the second output signal and generate a second feedback signal according to a difference between a frequency of the second output signal and the first operating frequency; a second phase-locked loop, connected to the second level conversion circuit, configured to receive the second feedback signal and generate a second error signal according to a phase difference between the first operating frequency and the second feedback signal; a second low-pass filter, connected to the second phase-locked loop and the second voltage-controlled oscillator, respectively, for filtering out noise in the second error signal, generating a second error voltage, and outputting the second error voltage to the second voltage-controlled oscillator; The second voltage-controlled oscillator is further configured to adjust the frequency of the second output signal according to the second error voltage to generate a second operating frequency, ie, the gate frequency.

6. The frequency adaptive single photon detection system according to claim 5, wherein: When the difference between the frequency of the second output signal and the first operating frequency is constant, the phase difference between the first operating frequency and the second feedback signal is zero, and the second phase-locked loop is locked to keep the frequency difference between the frequency of the second output signal of the second voltage-controlled oscillator and the first operating frequency constant, thereby generating the second operating frequency.

7. The frequency adaptive single photon detection system according to claim 5, wherein: The second phase-locked loop unit further includes: The second balun is connected between the second phase-locked loop and the second level conversion circuit, and is used to transmit the second feedback signal to the second phase-locked loop.

8. The frequency adaptive single photon detection system according to claim 5, wherein: Also includes: a first single-pole double-throw switch, wherein an input end of the first single-pole double-throw switch is used to receive the external reference signal, and a first output end is connected to the first phase-locked loop unit; a transmission unit connected to the second output end of the first single-pole double-throw switch, and configured to transmit the external reference signal; A second single-pole double-throw switch, wherein a first input end of the second single-pole double-throw switch is connected to the second phase-locked loop unit, and a second input end of the second single-pole double-throw switch is connected to the transmission unit.

9. The frequency adaptive single photon detection system according to claim 8, wherein: The first single-pole double-throw switch and the second single-pole double-throw switch are configured as follows: When the external reference signal is less than the required gating frequency of the avalanche diode, the first output terminal of the first single-pole double-throw switch is connected to the first phase-locked loop unit, and the second output terminal is disconnected from the transmission unit; the first input terminal of the second single-pole double-throw switch is connected to the second phase-locked loop unit, and the second input terminal is disconnected from the transmission unit; When the external reference signal is equal to the required gating frequency of the avalanche diode, the second output terminal of the first single-pole double-throw switch is connected to the transmission unit, the first output terminal is disconnected from the first phase-locked loop unit, and the second input terminal of the second single-pole double-throw switch is connected to the transmission unit, and the first input terminal is disconnected from the second phase-locked loop unit; When the frequency adaptive single-photon detection system is powered off, the first single-pole double-throw switch is disconnected from the first phase-locked loop unit and the transmission unit, and the second single-pole double-throw switch is disconnected from the second phase-locked loop unit and the transmission unit.

10. The frequency adaptive single photon detection system according to claim 8, wherein: The transmission unit includes: a first delay line connected to the second output terminal of the first single-pole double-throw switch to receive the external reference signal; A third balun is connected to the first delay line and the second input end of the second single-pole double-throw switch respectively to transmit the external reference signal.

11. The frequency adaptive single photon detection system according to claim 8, wherein: Also includes: a fourth balun, connected between the first phase-locked loop unit and the second phase-locked loop unit, and configured to transmit the first operating frequency to the second phase-locked loop unit; a second delay line connected to the second phase-locked loop unit; A fifth balun is connected to the second delay line and the first input end of the second single-pole double-throw switch, and is used to transmit the gating frequency.

12. The frequency adaptive single photon detection system according to claim 8, wherein: Also includes: an amplifier, connected to the second single-pole double-throw switch, and configured to amplify the external reference signal or the second operating frequency; The filter is connected to the amplifier and is used to filter out the amplified external reference signal or frequencies other than the second operating frequency to obtain a specific frequency signal.

13. The frequency adaptive single photon detection system according to claim 5, wherein: Also includes: A programmable logic unit is connected to the second phase-locked loop unit and is used to dynamically compile the second phase-locked loop unit to modify the second output signal.

Images