A DMA system and data transfer method

Abstract

This application discloses a DMA system and a data transfer method to improve the data transfer efficiency of the DMA system. The DMA system includes a read instruction splitting module, a write instruction splitting module, a read instruction splitting cache module communicatively connected to the read instruction splitting module and the write instruction splitting module, and an arbitrator communicatively connected to the read instruction splitting module and the write instruction splitting module, the arbitrator including a read arbitrator and a write arbitrator. The DMA system provided by this solution enables pipelined processing of instructions, allowing write instruction processing to begin immediately upon reading back the target data, thereby improving the efficiency of write instruction execution and shortening the time cycle required for reading and writing data, thus improving the data transfer efficiency of direct memory access.

Description

Technical Field

[0001] This application relates to the field of direct memory access and data transfer, and more particularly to a DMA system and a data transfer method. Background Technology

[0002] Direct memory access, also known as direct cache access (DMA), can be applied in microcontroller units (MCUs). A DMA system is a device used to implement data transfer.

[0003] In practical applications, due to limitations in the architecture and bus protocol of DMA systems, for peripheral requests, the DMA system often needs to first perform a read operation, and then, after reading the data to be transferred, perform a write operation based on the read data. In this data transfer process, the read and write operations are executed linearly, resulting in low data transfer efficiency, and it is necessary to wait for the bus transfer feedback to be valid before executing the next transfer.

[0004] How to improve the data transfer efficiency of DMA systems is the technical problem that this application aims to solve. Summary of the Invention

[0005] The purpose of this application is to provide a DMA system and a data transfer method to improve the data transfer efficiency of the DMA system.

[0006] In a first aspect, embodiments of this application provide a DMA system, which is communicatively connected to a bus matrix. The DMA system includes: a read instruction splitting module, a write instruction splitting module, a read instruction splitting cache module communicatively connected to the read instruction splitting module and the write instruction splitting module, and an arbitrator communicatively connected to the read instruction splitting module and the write instruction splitting module, wherein the arbitrator includes a read arbitrator and a write arbitrator.

[0007] The read instruction splitting module splits the acquired peripheral request into read instructions and instructs the read arbitrator to perform read arbitration on the split read instructions. If the read arbitrator reports that the read arbitration is valid, the target read instruction with valid read arbitration is stored in the read instruction splitting cache module. The peripheral request is used to request to read data from the first position and write it to the second position.

[0008] The read arbitrator is used to perform read arbitration and send the target read command that is valid through the read arbitration to the bus matrix through the host interface to read the target data from the first position;

[0009] The write instruction splitting module, after reading the target data, obtains the target read instruction from the read instruction splitting cache module and performs write instruction splitting, instructing the write arbitrator to perform write arbitration on the split write instruction;

[0010] The write arbitrator is used to perform write arbitration and, according to the valid write instruction, send the target data to the bus matrix through the host interface to write the target data to the second location.

[0011] Secondly, embodiments of this application provide a data transfer method applied to a DMA system, comprising:

[0012] Obtain a peripheral device request, the peripheral device request being used to request to read data from a first location and write it to a second location;

[0013] The peripheral device request is split using the read instruction splitting module;

[0014] The read arbitrator executes read arbitration on the split read instructions.

[0015] The target read instruction that is valid for read arbitration is stored in the read instruction splitting cache module, and the target read instruction is sent to the bus matrix through the host interface to read the target data from the first position;

[0016] If the target data has been read, the write instruction splitting module performs write instruction splitting on the target read instruction in the read instruction splitting cache module;

[0017] Write arbitration is performed on the split write commands using a write arbitrator;

[0018] According to the write instruction that is valid in the write arbitration, the target data is sent to the bus matrix through the host interface to write the target data to the second position.

[0019] Thirdly, embodiments of this application provide an electronic device including a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the method as described in the second aspect.

[0020] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method as described in the second aspect.

[0021] Fifthly, embodiments of this application provide a computer program product including a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of the method as described in the second aspect.

[0022] In this embodiment, the DMA system includes a read instruction splitting module, a write instruction splitting module, a read instruction splitting cache module communicatively connected to the read instruction splitting module and the write instruction splitting module, and an arbitrator communicatively connected to the read instruction splitting module and the write instruction splitting module. The arbitrator includes a read arbitrator and a write arbitrator. The read instruction splitting module can request a peripheral device to perform read instruction splitting and instruct the read arbitrator to arbitrate the split read instructions. If the read arbitration is valid, the target read instruction is stored in the read instruction splitting cache module. This allows the write instruction splitting module to know that a split read instruction with valid read arbitration exists. Once the target data is read back through the split read instruction, the write instruction splitting module can start executing the write instruction splitting without waiting for all data to be read back. The arbitrator includes a read arbitrator and a write arbitrator, which can support the simultaneous execution of read arbitration and write arbitration functions. The DMA system provided by this solution can implement pipelined processing of instructions. It can start executing write instructions on the target data as soon as the target data is read back, thereby improving the execution efficiency of write instructions on the target data, shortening the time cycle required for reading and writing data, and thus improving the data transfer efficiency of direct memory access. Attached Figure Description

[0023] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0024] Figure 1a This is a schematic diagram of the data transfer process of a DMA system based on a related technology in one embodiment of this application;

[0025] Figure 1b This is a schematic diagram of a communication connection scenario of a DMA system in one embodiment of this application;

[0026] Figure 1c This is one of the structural schematic diagrams of a DMA system in one embodiment of this application;

[0027] Figure 1d This is a comparative schematic diagram of the data transfer process of a DMA system in one embodiment of this application;

[0028] Figure 2 This is a second schematic diagram of the structure of a DMA system in one embodiment of this application;

[0029] Figure 3 This is the third schematic diagram of the structure of a DMA system in one embodiment of this application;

[0030] Figure 4 This is the fourth schematic diagram of the structure of a DMA system in one embodiment of this application;

[0031] Figure 5 This is the fifth schematic diagram of the structure of a DMA system in one embodiment of this application;

[0032] Figure 6 This is a schematic diagram of the task-level splitting granularity of a DMA system in one embodiment of this application;

[0033] Figure 7 This is a schematic diagram of the read / write instruction processing flow of a DMA system in one embodiment of this application;

[0034] Figure 8 This is one of the flowcharts illustrating a data transfer method in one embodiment of this application;

[0035] Figure 9 This is a second flowchart illustrating a data transfer method in one embodiment of this application. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. The drawing numbers in this application are only used to distinguish the various steps in the solution and are not used to limit the execution order of the various steps. The specific execution order is subject to the description in the specification.

[0037] In practical applications, DMA systems can transfer data between different peripherals and different memories; that is, they can read data from one location and write the read data to another location. In related technologies, DMA systems need to execute a read instruction first, and then execute a write instruction after reading the data to be transferred.

[0038] See Figure 1aIn a DMA system based on related technologies, the data transfer process of the DMA system is illustrated. Based on a peripheral request, the DMA system first performs read instruction splitting, requests arbitration on the split read instructions, and after the arbitration is valid, performs bus transfer on the read instructions to read the data to be transferred. After reading back the data to be transferred, the system performs write instruction splitting, requests arbitration on the split write instructions, and after the arbitration is valid, performs bus transfer on the write instructions to write the read-back data.

[0039] based on Figure 1a As shown in the flowchart, the DMA system needs to execute the read instruction first, read back the data, and then perform the splitting and writing of the write instruction. This linear sequential processing method results in low transfer efficiency for the DMA system, often requiring multiple cycles to achieve a single effective data transfer. This processing method is limited by the architecture of the DMA system itself, making it difficult to improve efficiency.

[0040] To address the problems existing in the prior art, embodiments of this application provide a DMA system, where DMA is an IP core (Intellectual Property Core) in a chip, such as... Figure 1b As shown, the DMA system provided in this embodiment is communicatively connected to a bus matrix. Optionally, the bus matrix can communicate with a central processing unit (CPU) and multiple peripherals. The bus matrix is ​​used to implement communication connections between peripherals, the CPU, and the DMA system. The DMA system can read and write data through the buses in the bus matrix. The peripherals specifically refer to various auxiliary devices or modules connected to the processor (CPU) within the chip.

[0041] like Figure 1c As shown, the DMA system provided in this application embodiment includes: a read instruction splitting module, a write instruction splitting module, a read instruction splitting cache module communicatively connected to the read instruction splitting module and the write instruction splitting module, and an arbitrator communicatively connected to the read instruction splitting module and the write instruction splitting module, wherein the arbitrator includes a read arbitrator and a write arbitrator.

[0042] The read instruction splitting module splits the acquired peripheral request into read instructions and instructs the read arbitrator to perform read arbitration on the split read instructions. If the read arbitrator reports that the read arbitration is valid, the target read instruction with valid read arbitration is stored in the read instruction splitting cache module. The peripheral request is used to request to read data from the first position and write it to the second position.

[0043] The peripheral request is a request initiated by the peripheral device to perform data read / write operations. The read instruction splitting module is used to split read instructions from these peripheral requests. The splitting process can be performed according to preset rules and granularity. After splitting the read instruction, the read instruction splitting module requests the read arbitrator to perform read arbitration on the split read instruction. The read arbitrator can perform arbitration based on preset read arbitration rules, such as determining the validity of parameters like the address of the read instruction and selecting the channel to execute the read instruction.

[0044] After the read arbitrator reports the valid read arbitration result to the read instruction splitting module, the read arbitrator stores the valid read instruction into the read instruction splitting cache module so that the write instruction splitting module can perform the relevant write instruction operations on the read data.

[0045] The read arbitrator is used to perform read arbitration and send the target read command that is valid through the read arbitration to the bus matrix through the host interface to read the target data from the first position.

[0046] Specifically, the first location refers to the data read location specified by the target read instruction. In practical applications, this first location can be a designated storage location of a peripheral device or memory connected to the aforementioned bus matrix. In this embodiment, the target data to be transferred is obtained by reading the target data at the first location. This target data is temporarily stored in the cache of the DMA system and then called when a write instruction is executed subsequently, thereby writing the target data to the second location, thus realizing the transfer of the target data from the first location to the second location.

[0047] After the arbiter determines that a read command is valid, the valid read command is executed through the host interface, and data is read by transmitting it to the bus matrix. The read data can be stored in the data buffer through the arbiter for subsequent write commands.

[0048] The write instruction splitting module, after reading the target data, obtains the target read instruction from the read instruction splitting cache module and performs write instruction splitting, instructing the write arbitrator to perform write arbitration on the split write instruction.

[0049] In this solution, the write instruction splitting module can retrieve the target read instruction from the read instruction splitting cache module to execute the write instruction splitting, provided that the target data has been read and the corresponding split read instruction is stored in the read instruction splitting cache module. Correspondingly, instruction splitting can be performed according to preset splitting rules and granularity; the specific splitting rules for the aforementioned read and write instructions can be set according to actual needs.

[0050] After the write command is split into write commands, the write command splitting module requests the write arbitrator to perform write arbitration on the split write commands. This includes determining whether the address and other parameters of the write command are valid, and arbitrarily selecting the channel to execute the write command.

[0051] The write arbitrator is used to perform write arbitration and, according to the valid write instruction, send the target data to the bus matrix through the host interface to write the target data to the second location.

[0052] Specifically, the second location refers to the data write location specified by the target write instruction. In practical applications, this second location can be a designated storage location of a peripheral device or memory connected to the aforementioned bus matrix. In this embodiment, the target data that has been pre-read is retrieved, and the target data is written to the second location according to the target write instruction, thereby transferring the target data from the first location to the second location.

[0053] In this DMA system, the arbitrator includes a write arbitrator and a read arbitrator. The read and write arbitrators can perform arbitration in parallel, enabling separate arbitration for reads and writes. When the DMA system has multiple channels, the read and write arbitrators can specifically select the highest-priority channel based on the descriptor configuration and the fixed priority of each channel, thereby initiating the transmission. During arbitration, if two channels have the same fixed priority, a round-robin approach can be used for arbitration. With a large number of read and write instructions, the DMA system provided in this application can perform read and write arbitration in parallel. The parallel execution of read and write arbitration functions significantly improves the instruction arbitration efficiency in the DMA system.

[0054] In this scheme, the data read back by the read command can be temporarily stored in the data cache. Each channel in the DMA system is configured with a corresponding data cache, and the data caches corresponding to different channels can be independent of each other.

[0055] In one application scenario, a read command might require reading a significant amount of data. A linear read-write approach would necessitate reading all the data before executing the write command splitting, arbitration, and transmission. In this solution, the write command splitting module, with the target data stored in the data cache, can retrieve the split read command from the read command splitting cache module to continue splitting and arbitrating the write command. This eliminates the need to wait for all data requested by the peripheral device to be read before processing the write command. Compared to the linear approach of completing data readback before writing, this DMA system can begin splitting and arbitrating the write command after reading a portion of the data, allowing for rapid writing of the already read data from the data cache. Simultaneously, the splitting, arbitration, and transmission of the write command can be executed concurrently, improving write command processing efficiency without affecting data readback based on read commands. This ensures the read data is written to the required location as quickly as possible, shortening the overall data read / write time and effectively improving overall data read / write efficiency.

[0056] See Figure 1d A rectangle represents one clock cycle, and the contents of the rectangle represent the steps executed within that clock cycle, from left to right, indicating the steps executed sequentially by the DMA. Related DMA systems often employ a linear processing approach, first splitting, arbitrating, and transferring read instructions. Only after the data to be read or written has been transferred can the splitting, arbitrating, and transferring of write instructions be performed. Assuming that each instruction splitting, arbitrating, and transferring consumes one clock cycle, then based on the linear processing approach, completing one data read / write operation requires sequentially executing these steps, thus consuming six clock cycles.

[0057] In comparison, the DMA system of this scheme can implement pipelined processing for each module. During the processing of read instructions, the read instruction splitting module can split the first read instruction in the first clock cycle (i.e., read instruction split 1) and split the second read instruction in the second clock cycle, thereby continuously performing pipelined splitting processing on multiple read instructions. Correspondingly, the read arbitrator arbitrates the first split read instruction in the second clock cycle (i.e., read request arbitration 1) and arbitrates the second split read instruction in the third clock cycle, thereby continuously arbitrating multiple split read instructions. Accordingly, read instruction transmission also adopts the above-mentioned pipelined processing method. Compared with the DMA systems of related technologies that execute read and write instructions, this scheme adopts a pipelined processing method, which can efficiently pipeline multiple read instructions, and has a higher read instruction processing efficiency than existing technologies.

[0058] Correspondingly, the DMA system in this scheme can also employ a pipelined approach when processing write instructions to improve processing efficiency. Specifically, the write instruction splitting in this scheme is executed only when the target data has been read back and the corresponding split read instruction is stored in the aforementioned read instruction splitting cache module. That is, once a portion of the input to be written (i.e., the target data) has been read back, writing can begin on the read-back target data, thus quickly writing the target data to the required location without waiting for all data to be read back.

[0059] The DMA system provided in this application includes a read instruction splitting cache module for storing split read instructions that have passed read arbitration. This facilitates the write instruction splitting module in quickly executing write instruction processing after reading the target data, thereby writing the target data to the required location as quickly as possible. Furthermore, since the read and write instruction splitting modules are independent of each other, and the read and write arbitration modules are also independent, the read instruction processing function and the write instruction processing function can be implemented in parallel. Therefore, there is no need to wait for one cycle to complete before entering the next cycle, enabling pipelined operation and effectively improving the transmission efficiency of the DMA system.

[0060] In practical applications, peripheral requests may require data read / write operations between memory locations, between peripherals, or between a peripheral and a memory. The DMA system provided in this application employs a pipelined approach during data read / write processing, allowing read and write instructions to be processed in parallel. Compared to the linear processing of read / write instructions in related technologies, the DMA system in this application can effectively improve efficiency by 20% in memory-to-memory mode, and by 50% in memory-to-memory mode with multiple AHB bus master interfaces.

[0061] Based on the solution provided in the above embodiment, optionally, Figure 2 As shown, the DMA system further includes a bus control module and a bus selector communicatively connected to the arbitrator and the bus control module. The bus control module includes multiple host interfaces and instruction cache modules corresponding to each of the multiple host interfaces.

[0062] The arbitrator is used to send a valid target instruction to the bus selector, the target instruction including the target read instruction and / or the target write instruction;

[0063] The bus selector is used to determine the target host interface for executing the target instruction from multiple host interfaces, and to store the target instruction in the instruction cache module corresponding to the target host interface;

[0064] The bus control module is used to execute instructions from the corresponding instruction cache module through the host interface.

[0065] The arbitrator arbitrates the commands and then sends the valid command to the bus selector. Specifically, read commands are arbitrated by the read arbitrator, and the valid read command is sent to the bus selector after successful arbitration. Similarly, write commands are arbitrated by the write arbitrator, and the valid write command is sent to the bus selector after successful write arbitration.

[0066] After receiving a valid arbitration command, the bus selector can determine the host interface to transmit the command based on information such as the address in the command, and then send the command to the address indicated by the address through the host interface.

[0067] A bus matrix enables interconnection between multiple devices. The DMA system in this solution communicates with the bus matrix via a host interface, thereby enabling command transmission and reception as well as data transfer. The DMA system can be configured with one or more host interfaces. With multiple host interfaces configured, different host interfaces can connect to different buses in the bus matrix. The bus selector can determine which host interface to transmit a validly arbitrated command for execution based on information such as the command's address.

[0068] The bus control module includes one or more host interfaces. Each host interface is configured with an instruction cache module, which stores the instructions to be sent by the corresponding host interface. After the bus selector sends a valid, arbitrated instruction to one of the host interfaces of the bus control module, if the host interface is idle, it can perform a conversion process matching the bus protocol on the received instruction and then send the converted instruction to the bus. If the host interface is busy when it receives the instruction, for example, while processing other instructions, it can first store the instruction in the instruction cache of that host interface. If there are many instructions to be processed, they can be sequentially arranged in the instruction cache of the host interface so that the host interface can process multiple instructions in the instruction cache in sequence.

[0069] The bus control module can be used to perform bus conversion of instructions according to the bus protocol. That is, if an instruction needs to be sent to the AHB bus, it will be converted to a protocol compatible with the AHB bus before being sent through the host interface. In practical applications, it can also be converted to AXI or other types of buses.

[0070] The solution provided in this application allows the arbitrator to transmit valid arbitration instructions to the bus control module via a bus selector. Without waiting for instruction execution to complete, the arbitrator can continuously perform arbitration, effectively improving arbitration efficiency. In cases where the bus control module includes multiple host interfaces, each host interface is configured with a corresponding instruction cache module. After the bus selector determines the host interface to execute the instruction, it can send the instruction to the instruction cache of that host interface for storage, enabling the host interface to process the instructions in the corresponding instruction cache module in an orderly manner. This solution efficiently implements instruction caching by storing instructions to be transmitted through an instruction cache module corresponding to the host interface, preventing instruction transmission efficiency from affecting the arbitrator's arbitration efficiency, thereby improving the overall instruction transmission efficiency.

[0071] Based on the solution provided in the above embodiment, optionally, Figure 3 As shown, the DMA system also includes a data control module that is communicatively connected to the read instruction splitting module, the write instruction splitting module, and the arbitrator;

[0072] The read arbitrator is also used to store the target data read from the first position into the data control module;

[0073] The write instruction splitting module is specifically used to, when the target data exists in the data control module, obtain the target read instruction from the read instruction splitting cache module and perform write instruction splitting, and instruct the write arbitrator to perform write arbitration on the split write instruction.

[0074] In this embodiment, the data control module is connected to the read instruction splitting module, the write instruction splitting module, and the arbitrator. The read instruction splitting module sends the split read instructions to the read arbitrator to request read arbitration. After the read arbitration is valid and the target data is read back via the read instruction, the arbitrator stores the read target data in the data control module. The target data stored in the data control module can be accessed by the write instruction splitting module and sent to the bus via the arbitrator to write the target data to the desired location.

[0075] Based on the solution provided in the above embodiment, optionally, Figure 4 As shown, the data control module includes a data type conversion submodule and a data caching submodule;

[0076] The data caching submodule is used to store the target data;

[0077] The data bit width conversion submodule is used to convert the bit width of the target data into the bit width of the bus matrix.

[0078] In this embodiment, the data control module includes a data caching submodule and a data type conversion submodule. The data caching submodule stores the target data read back based on read instructions, so that the target data is provided when data writing is performed. The data type conversion submodule can be used to perform bit width conversion on the target data, for example, Figure 4 The document illustrates two data type conversion submodules: a narrow-to-wide data conversion module and a wide-to-narrow data conversion module. These submodules can perform data type conversion based on the difference between the actual bit width of the target data and the bus matrix bit width, ensuring that the bit width of the target data in the output bus meets the matrix bit width rules.

[0079] Based on the solution provided in the above embodiments, the data caching submodule includes a first-in-first-out storage module;

[0080] The read instruction splitting module is further configured to identify whether the storage space of the first-in-first-out storage module meets the preset data reading conditions before performing read instruction splitting on the acquired peripheral request, and to perform read instruction splitting on the acquired peripheral request if the conditions are met.

[0081] In this embodiment of the application, the data cache submodule in the data control module is specifically a first-in-first-out (FIFO) storage module, which can also be called a FIFO (First Input First Output) memory, and can perform ordered processing of data that enters in an orderly manner in a first-in-first-out order.

[0082] Before splitting the read instruction, the read instruction splitting module first checks the available storage space of the first-in-first-out (FIFO) memory module. Only when it is determined that there is enough space in the FIFO memory to accommodate the target data to be read back will the read instruction splitting process begin, thus avoiding the problem that there is not enough space to store the target data to be read back.

[0083] For example, the preset data read condition can specifically refer to the available storage space in the FIFO memory being greater than or equal to a preset capacity value. Alternatively, the capacity value required for the target data to be read back can be determined first based on the read instruction, and the preset data read condition can specifically refer to the available storage space in the FIFO memory being greater than or equal to the capacity value required for the target data.

[0084] Based on the solution provided in the above embodiment, optionally, Figure 5 As shown, the DMA system includes multiple DMA channels, and the DMA system also includes:

[0085] The request control module receives a peripheral request initiated by the peripheral device, determines the target DMA channel for processing the peripheral request based on the mapping relationship, and instructs the target DMA channel to process the peripheral request.

[0086] In this embodiment, the request control module can be communicatively connected to the read instruction splitting module. The request control module receives peripheral requests initiated by the peripheral device and determines the DMA channel used to process the peripheral request according to a mapping relationship. DMA systems often have multiple channels, and the mapping relationship between DMA channels and peripheral requests can be restricted through pre-configuration. Based on this mapping relationship, the request control module can select a target DMA channel from the multiple DMA channels to process the peripheral request. Then, the DMA performs subsequent processing on the peripheral request through the target DMA channel.

[0087] In addition, after receiving a peripheral request, the request control module can also be used to determine the enable status of the DMA system to ensure that the DMA system is in a state that can process peripheral requests.

[0088] The solution provided in this application embodiment ensures that peripheral requests are processed through the matching DMA channel and controls the enable state of the DMA system, thereby effectively improving the processing efficiency of the DMA system for peripheral requests.

[0089] Based on the solution provided in the above embodiments, optionally, the read arbitrator is specifically used for:

[0090] A first channel for executing the target read instruction is determined based on preset read arbitration rules;

[0091] The target read command, which is valid for read arbitration, is sent to the bus matrix via the host interface through the first channel to read target data from the first position.

[0092] The target data is stored in the data cache corresponding to the first channel.

[0093] In a DMA system with multiple channels, the aforementioned request control module determines which DMA channel to split the peripheral request based on the mapping relationship. In this scheme, the read arbitrator is also used to determine which DMA channel to use for reading back the target data, thereby improving the efficiency of executing read instructions.

[0094] Based on the solution provided in the above embodiments, optionally, the write instruction splitting module is specifically used for:

[0095] When the read instruction splitting cache module is in a non-empty state and the amount of data stored in the data cache corresponding to the first channel meets the preset data writing conditions, the target read instruction is obtained from the read instruction splitting cache module and the write instruction splitting is performed.

[0096] The write arbitrator is instructed to perform write arbitration on the split write commands.

[0097] In this embodiment, the write instruction splitting module determines whether to begin executing write instruction splitting based on the storage state of the read instruction splitting cache module and the amount of data in the data cache. A non-empty read instruction splitting cache module indicates the existence of a valid split read instruction after read arbitration. The data cache corresponding to the first channel can specifically be a data cache sub-module corresponding to the first channel within the data control module. If the amount of data stored in this data cache meets preset data writing conditions, it indicates that the data cache has stored data to support the execution of write instructions. In this case, the write instruction splitting module can determine that there is an executed split read instruction and data that can be written, thus allowing it to begin executing write instruction splitting. Specifically, it retrieves the split read instruction from the read instruction splitting cache module to execute subsequent write instruction splitting processing.

[0098] The solution provided in this application can determine whether write instruction splitting can begin by considering both read instructions and read-back data, effectively improving the effectiveness of subsequent write instruction execution after reading back data.

[0099] Based on the solution provided in the above embodiments, optionally, the write arbitrator is further configured to send information for executing the target write instruction to the bus control module through the bus selector;

[0100] Specifically, the bus control module is used to read the data to be written from the data buffer corresponding to the first channel according to the information of the target write instruction, and to perform conversion on the data to be written according to the bus protocol and send it to the bus matrix through the host interface to write the data to be written to the second position. The data to be written includes at least a portion of the target data.

[0101] In this step, the write arbitrator sends information to the bus selector for executing the target write instruction. This information, which may include parameters such as address, is used to implement the target write instruction. This information is then sent to the bus control module via the bus selector. The bus control module performs a conversion on the write data according to the bus protocol and sends it to the bus matrix to execute the write instruction, thereby writing the target data to the desired second location.

[0102] Based on the solution provided in the above embodiments, optionally, the read instruction splitting module is specifically used to perform read instruction splitting according to a first preset task granularity, and the write instruction splitting module is specifically used to perform write instruction splitting according to a second preset task granularity.

[0103] In this embodiment, the granularity of the splitting can be set according to actual needs. The first preset task granularity and the second preset task granularity can be the same or different, that is, the granularity of read instruction splitting and write instruction splitting can be the same or different. For example... Figure 6 As shown, Single or Burst granularity can be used to split the instructions into granularities suitable for execution.

[0104] In practical applications, task-level splitting rules can be flexibly set. Taking the AHB bus as an example, it can be set to split according to the bus Burst, and the specific splitting granularity of the Burst can be flexibly set according to actual needs, such as splitting according to the number of transactions. Alternatively, it can be set to split according to the bus Single, that is, splitting according to the number of transactions one by one.

[0105] Task-level splitting allows for flexible setting of the amount of data executed within a single clock cycle, enabling single-cycle transfer volume control. After splitting, AHB bus Bus transfers and AHB bus Single transfers can be executed according to the split granularity. For example, if splitting by Bus, a group of data transfers can be executed within one clock cycle, which may contain multiple consecutive instructions. If splitting by Single, a single instruction transfer can be executed within one clock cycle.

[0106] Below, as Figure 7 As shown, this solution will be explained in detail with an example.

[0107] The read instruction process is as follows (e.g.) Figure 7 Left side):

[0108] Step 1: Through the peripheral request module, the peripheral request is routed to the corresponding DMA channel. Specifically, a channel for instruction splitting can be selected from multiple DMA channels according to a preset mapping relationship.

[0109] Step 2: Wait for the peripheral device request to be valid. Specifically, the DMA system can check its own enable status to determine if it is in a normal state. If the request is invalid, for example, if the DMA system is in a disabled state, an enable command can be used to control the DMA state change. If other anomalies cause the DMA system to be in an abnormal state, it can enter a waiting state for transmission.

[0110] Step 3: The read instruction splitting module determines whether the data FIFO module has enough space to store the data to be read back. If the space is insufficient, it can enter a waiting state for transmission.

[0111] Step 4: If the data space is sufficient to store the read data, then start executing the read instruction splitting and initiate a read arbitration request to the read arbitrator based on the split read instruction.

[0112] Step 5: After the read arbitrator returns a valid channel arbitration result, write the split read instruction into the read instruction split buffer.

[0113] Step 6: After the arbitrator's arbitration is successful, the corresponding channel information is transmitted to the bus control module via the bus selector. This information may include parameters such as the read address and read mode, which support the implementation of read commands.

[0114] Step 7: When the bus control module determines that it is in a non-busy state, it can convert the above-mentioned information into a form that conforms to the bus protocol and transmit it to the bus.

[0115] Step 8: The data read back from the host interface of the bus control module is returned to the read arbitrator module according to the bus selector. The read arbitrator module then returns the data to the aforementioned channel's data buffer based on the channel information.

[0116] The write instruction splitting process is as follows (e.g.) Figure 7 (Right side):

[0117] Step 1: The write instruction splitting module starts splitting write instructions once it confirms that the read instruction splitting cache is not empty and that there is enough data in the data cache.

[0118] Step 2: Send the instructions and arbitration request information extracted from the write instructions to the write arbitrator module.

[0119] Step 3: Wait for the write arbitrator to arbitrate successfully. The arbitrator will then transmit the write command and address information to the bus control module through the bus selection module.

[0120] Step 4: The bus control module will retrieve cached data from the aforementioned data cache based on the information transmitted by the write arbitrator, and convert it into the corresponding bus protocol for transmission onto the bus to execute data writing.

[0121] In the DMA system provided in this application embodiment, the read instruction splitting module can be used to request a peripheral device to perform read instruction splitting and instruct the read arbitrator to arbitrate the split read instruction. If the read arbitration is valid, the target read instruction is stored in the read instruction splitting cache module. This allows the write instruction splitting module to know that a split read instruction with valid read arbitration already exists. Once the target data is read back through the split read instruction, the write instruction splitting module can begin executing the write instruction splitting without waiting for all data to be read back. The arbitrator includes a read arbitrator and a write arbitrator, which can support simultaneous execution of read and write arbitration functions. The DMA system provided by this solution enables pipelined processing of instructions. Upon reading back the target data, write instruction processing can begin on the target data, thereby improving the efficiency of write instruction execution and shortening the time cycle required for reading and writing data, thus improving the data transfer efficiency of direct memory access.

[0122] To address the problems existing in related technologies, embodiments of this application also provide a data transfer method applied to a DMA system, such as... Figure 8 As shown, it includes the following steps:

[0123] S81: Obtain peripheral device request, the peripheral device request being used to request to read data from a first location and write it to a second location;

[0124] S82: Perform read instruction splitting on the peripheral device request through the read instruction splitting module;

[0125] S83: Perform read arbitration on the split read command through the read arbitrator;

[0126] S84: Store the target read instruction that is valid for read arbitration into the read instruction splitting cache module, and send the target read instruction to the bus matrix through the host interface to read the target data from the first position;

[0127] S85: If the target data has been read, the write instruction splitting module performs write instruction splitting on the target read instruction in the read instruction splitting cache module;

[0128] S86: Perform write arbitration on the split write instructions through the write arbitrator;

[0129] S87: Based on the write instruction that is valid for write arbitration, the target data is sent to the bus matrix through the host interface to write the target data to the second position.

[0130] Specifically, the execution entity in this application embodiment may be a DMA system, which includes a read instruction splitting module, a write instruction splitting module, a read instruction splitting cache module, and an arbitrator, which includes a read arbitrator and a write arbitrator.

[0131] The aforementioned peripheral request is initiated by the peripheral device and can be used to implement data read and write requests. During the process of splitting the read instruction for the peripheral request, the splitting can be performed according to preset rules and granularity. After splitting the read instruction, the read arbitrator can perform arbitration based on preset read arbitration and rules, such as determining whether the address and other parameter information of the read instruction are valid, and arbitrarily selecting the channel to execute the read instruction.

[0132] After the arbitration result is valid, on the one hand, the valid read instruction is stored in the read instruction splitting cache module so that the write instruction splitting module can perform the relevant write instruction operations on the read data. On the other hand, the valid read instruction is executed through the host interface, thereby performing data reading by transmitting it to the bus matrix. The read data can be stored in the data cache for subsequent execution of write instructions.

[0133] If the target data has been read and the corresponding split read instruction is stored in the read instruction splitting cache module, write instruction splitting is performed on the target read instruction in the read instruction splitting cache module. Accordingly, instruction splitting can be performed according to preset splitting rules and granularity, and the specific splitting rules for the above read and write instructions can be set according to actual needs.

[0134] After the write instructions are split into parts, write arbitration is performed on them. This includes determining the validity of parameters such as the address of the write instructions and selecting the channel to execute the write instructions through arbitration.

[0135] In one application scenario, a DMA system can have multiple channels. The read arbitrator and write arbitrator are used to select the highest-priority channel based on the descriptor configuration and the fixed priority of each channel, thereby initiating the transfer. During arbitration, if two channels have the same fixed priority, a round-robin approach can be used for arbitration. With a large number of read and write instructions, this solution can perform read and write arbitration in parallel. The parallel execution of read and write arbitration functions significantly improves instruction arbitration efficiency.

[0136] The solution provided by the embodiments of this application can implement pipelined processing of instructions, and can start executing write instructions on the target data as soon as the target data is read back, thereby improving the execution efficiency of write instructions on the target data, shortening the time cycle required for reading and writing data, and thus improving the data transfer efficiency of direct memory access.

[0137] Based on the solution provided in the above embodiment, optionally, Figure 9 As shown, after step S84 above, that is, after sending the target read instruction to the bus matrix through the host interface to read target data from the first position, the method further includes:

[0138] S91: Store the target data in the data cache;

[0139] Wherein, when the target data has been read, the write instruction splitting module performs write instruction splitting on the target read instruction in the read instruction splitting cache module, including:

[0140] S92: When the read instruction splitting cache module is in a non-empty state and the amount of data stored in the data cache meets the preset data writing conditions, the write instruction splitting module performs write instruction splitting on the target read instruction in the read instruction splitting cache module.

[0141] In this scheme, data read back by read commands can be temporarily stored in a data cache. For example, in a DMA system with multiple channels, each channel is configured with a corresponding data cache, and the data caches for different channels can be independent of each other.

[0142] In one application scenario, a read command might need to retrieve a significant amount of data. A linear read-write approach would require retrieving all data before the write command can be split, arbitrated, and transmitted. This solution, however, allows for write command splitting and arbitration of the read command splitting cache module once the target data is stored in the data cache. This eliminates the need to wait for all data requested by the peripheral device to be read before processing the write command. Compared to the linear approach of retrieving data first and then writing it, this solution allows for write command splitting and arbitration to begin after a portion of the data has been read, enabling the rapid writing of the already retrieved data from the data cache. Simultaneously with the target data writing, write command splitting, arbitration, and transmission can also be performed, improving write command processing efficiency without affecting read-based data retrieval. This ensures the read data is written to the required location as quickly as possible, shortening the overall data read / write time and effectively improving overall data read / write efficiency.

[0143] In practical applications, peripheral requests may require data read / write operations between memory locations, between peripherals, or between a peripheral and a memory. The solution provided in this application employs a pipelined approach in the data read / write processing, allowing read and write instructions to be processed in parallel. Compared to the linear processing of read / write instructions in related technologies, this solution can effectively improve efficiency by 20% in memory-to-memory mode, and by 50% in memory-to-memory mode with multiple AHB bus master interfaces.

[0144] Preferably, this application embodiment also provides a data transfer device, and the modules in the device provided in this application embodiment can implement the method steps provided in the above method embodiments. Furthermore, the device provided in this application embodiment can achieve the technical effects achievable by the above method embodiments.

[0145] Preferably, this application embodiment also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements the various processes of the above-described data transfer method embodiment and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0146] This application also provides a computer-readable storage medium storing a computer program. When executed by a processor, this computer program implements the various processes of the above-described data transfer method embodiment and achieves the same technical effect. To avoid repetition, it will not be described again here. The computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0147] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. The computer program is operable to cause a computer to perform some or all of the steps of the above-described data transfer method embodiment and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0148] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0149] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.

[0150] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0151] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0152] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0153] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0154] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0155] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0156] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0157] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A DMA system, characterized in that, The DMA system is communicatively connected to a bus matrix. The DMA system includes: a read instruction splitting module, a write instruction splitting module, a read instruction splitting cache module communicatively connected to the read instruction splitting module and the write instruction splitting module, and an arbitrator communicatively connected to the read instruction splitting module and the write instruction splitting module. The arbitrator includes a read arbitrator and a write arbitrator. The read instruction splitting module splits the acquired peripheral request into read instructions and instructs the read arbitrator to perform read arbitration on the split read instructions. If the read arbitrator reports that the read arbitration is valid, the target read instruction with valid read arbitration is stored in the read instruction splitting cache module. The peripheral request is used to request to read data from the first position and write it to the second position. The read arbitrator is used to perform read arbitration and send the target read command that is valid through the read arbitration to the bus matrix through the host interface to read the target data from the first position; The write instruction splitting module, after reading the target data, obtains the target read instruction from the read instruction splitting cache module and performs write instruction splitting, instructing the write arbitrator to perform write arbitration on the split write instruction; The write arbitrator is used to perform write arbitration and, according to the valid write instruction, send the target data to the bus matrix through the host interface to write the target data to the second location.

2. The DMA system as described in claim 1, characterized in that, It also includes a bus control module and a bus selector communicatively connected to the arbitrator and the bus control module. The bus control module includes multiple host interfaces and instruction cache modules corresponding to the multiple host interfaces respectively. The arbitrator is used to send a valid target instruction to the bus selector, the target instruction including the target read instruction and / or the target write instruction; The bus selector is used to determine the target host interface for executing the target instruction from multiple host interfaces, and to store the target instruction in the instruction cache module corresponding to the target host interface; The bus control module is used to execute instructions from the corresponding instruction cache module through the host interface.

3. The DMA system as described in claim 2, characterized in that, It also includes a data control module that is communicatively connected to the read instruction splitting module, the write instruction splitting module and the arbitrator; The read arbitrator is also used to store the target data read from the first position into the data control module; The write instruction splitting module is specifically used to, when the target data exists in the data control module, obtain the target read instruction from the read instruction splitting cache module and perform write instruction splitting, and instruct the write arbitrator to perform write arbitration on the split write instruction.

4. The DMA system as described in claim 3, characterized in that, The data control module includes a data type conversion submodule and a data caching submodule; The data caching submodule is used to store the target data; The data type conversion submodule is used to convert the bit width of the target data into the bit width of the bus matrix.

5. The DMA system as described in claim 4, characterized in that, The data caching submodule includes a first-in-first-out storage module; The read instruction splitting module is further configured to identify whether the storage space of the first-in-first-out storage module meets the preset data reading conditions before performing read instruction splitting on the acquired peripheral request, and to perform read instruction splitting on the acquired peripheral request if the conditions are met.

6. The DMA system as described in claim 4, characterized in that, The DMA system includes multiple DMA channels, and the DMA system also includes: The request control module receives a peripheral request initiated by the peripheral device, determines the target DMA channel for processing the peripheral request based on the mapping relationship, and instructs the target DMA channel to process the peripheral request.

7. The DMA system as described in claim 6, characterized in that, The arbitrator is specifically used for: A first channel for executing the target read instruction is determined based on preset read arbitration rules; The target read command, which is valid for read arbitration, is sent to the bus matrix via the host interface through the first channel to read target data from the first position. The target data is stored in the data cache corresponding to the first channel.

8. The DMA system as described in claim 7, characterized in that, The write instruction splitting module is specifically used for: When the read instruction splitting cache module is in a non-empty state and the amount of data stored in the data cache corresponding to the first channel meets the preset data writing conditions, the target read instruction is obtained from the read instruction splitting cache module and the write instruction splitting is performed. The write arbitrator is instructed to perform write arbitration on the split write commands.

9. The DMA system as described in claim 8, characterized in that, The write arbitrator is also used to send information for executing the target write instruction to the bus control module through the bus selector; Specifically, the bus control module is used to read the data to be written from the data buffer corresponding to the first channel according to the information of the target write instruction, and to perform conversion on the data to be written according to the bus protocol and send it to the bus matrix through the host interface to write the data to be written to the second position. The data to be written includes at least a portion of the target data.

10. The DMA system according to any one of claims 1 to 9, characterized in that, The read instruction splitting module is specifically used to split multiple read instructions that conform to a first preset task granularity from the peripheral device request, and the write instruction splitting module is specifically used to split multiple write instructions that conform to a second preset task granularity from the peripheral device request.

11. A data transfer method, characterized in that, Applied to DMA systems, including: Obtain a peripheral device request, the peripheral device request being used to request to read data from a first location and write it to a second location; The peripheral device request is split using the read instruction splitting module; The read arbitrator executes read arbitration on the split read instructions. The target read instruction that is valid for read arbitration is stored in the read instruction splitting cache module, and the target read instruction is sent to the bus matrix through the host interface to read the target data from the first position; If the target data has been read, the write instruction splitting module performs write instruction splitting on the target read instruction in the read instruction splitting cache module; Write arbitration is performed on the split write commands using a write arbitrator; According to the write instruction that is valid in the write arbitration, the target data is sent to the bus matrix through the host interface to write the target data to the second position.

12. The method as described in claim 11, characterized in that, After sending the target read instruction to the bus matrix via the host interface to read target data from the first position, the method further includes: The target data is stored in a data cache; Wherein, when the target data has been read, the write instruction splitting module performs write instruction splitting on the target read instruction in the read instruction splitting cache module, including: When the read instruction splitting cache module is in a non-empty state and the amount of data stored in the data cache meets the preset data writing conditions, the write instruction splitting module performs write instruction splitting on the target read instruction in the read instruction splitting cache module.

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