A data access pattern-aware soft-hard collaborative dynamic graph processing device

Abstract

The application discloses a data access mode-aware soft and hard cooperative dynamic graph processing device, and belongs to the field of graph computation optimization, and comprises: a memory controller, which is used for reading graph structure data and update edge data into an on-chip memory and buffering the graph structure data in a graph structure buffer; a priority scheduler, which is used for identifying vertices with a degree higher than a threshold value in the update edge data and edges connected to the vertices as high-priority data, permanently residing in a high-priority on-chip buffer, and identifying the remaining vertices and the connected edges as low-priority data, buffering the low-priority data in a low-priority on-chip buffer; and an update edge distributor, which is used for reading the update edge data from the high-priority on-chip buffer and the low-priority on-chip buffer, and distributing the update edge data into N groups according to the ID of a source vertex and respectively distributing the update edge data to N graph update processing units; wherein the graph update processing unit is used for inserting the received update edge data into the graph structure data. The application can improve the update efficiency of a dynamic graph.

Description

Technical Field

[0001] This invention belongs to the field of graph computation optimization, and more specifically, relates to a hardware-software collaborative dynamic graph processing device with data access pattern awareness. Background Technology

[0002] In today's information society, data is growing at an astonishing rate, especially complex network structures such as social networks, recommendation systems, and Internet of Things (IoT) networks. This data is typically represented in the form of graphs. Taking social networks as an example, each social network user can be considered a node in the graph. These nodes can contain users' personal information, such as username, avatar, age, and gender. Social relationships between users (such as friendships and following relationships) can be represented by edges. For example, if user A follows user B, there will be an edge in the graph pointing from A to B. Friendships between users change over time; new friendships create new edges, and broken existing relationships result in the deletion of edges. The dynamic nature and scale of graph data present unprecedented challenges to data processing technologies.

[0003] Dynamic graph computation typically involves graph update operations on the graph structure, i.e., inserting new edge data into the graph data, and performing graph analysis operations such as BFS and PageRank on the updated graph. Existing solutions use PMA-based or tree-based structures to store the graph structure. With PMA-based structures, gaps exist between the data stored in the array, requiring element shifting during insertion or deletion to avoid altering the entire data structure after each insertion or deletion. However, since vertices and edges share an array, conflicts arise between different updates. Furthermore, insufficient gaps lead to significant data movement overhead, resulting in inefficient graph updates. Tree-based structures typically use a search tree to support fast queries and optimize non-leaf or leaf nodes. However, their structural characteristics still result in discontinuous data storage. Traversing all vertices and edges during graph analysis incurs significant random access overhead, compromising graph analysis efficiency.

[0004] The solutions mentioned above either suffer from poor data locality and high computational complexity in dynamic graph analysis, or require significant overhead to search and move data, making it impossible to achieve efficient graph analysis and graph updates simultaneously. Summary of the Invention

[0005] To address the shortcomings and improvement needs of existing technologies, this invention provides a data access mode-aware, hardware-software collaborative dynamic graph processing device. Its purpose is to propose a new processing architecture to improve the update efficiency of dynamic graphs, taking into account their dynamic nature and scalability.

[0006] To achieve the above objectives, the present invention provides a data access pattern-aware hardware-software collaborative dynamic graph processing device, comprising: a memory controller, a priority scheduler, a low-priority on-chip cache, a high-priority on-chip cache, a graph structure cache, an update edge allocator, and N graph update processing units; N≥2;

[0007] The memory controller is used to read the graph structure data and the update edge data of the current update batch stored in off-chip memory into on-chip memory, and cache the graph structure data in the graph structure cache; the update edge data includes the edges of the graph structure to be inserted, each edge is represented by the source vertex and destination vertex it connects to, and each vertex has a unique ID;

[0008] A priority scheduler is used to update edge data where the degree is higher than the threshold. λ The vertices and edges connected to these vertices are identified as high-priority data and permanently reside in the high-priority on-chip cache, while the remaining vertices and edges connected to them are identified as low-priority data and cached in the low-priority on-chip cache according to the preset cache replacement strategy.

[0009] The edge update allocator is used to read update edge data from the high-priority on-chip cache and the low-priority on-chip cache, and divide the update edge data into N groups according to the ID of the source vertex, and allocate them to N graph update processing units respectively.

[0010] The graph update processing unit is used to perform graph update operations to insert the received update edge data into the graph structure data.

[0011] Furthermore, the threshold Degree λ The calculation methods include:

[0012] Vertices with a degree lower than a preset threshold λ in the updated edge data are identified as low-degree vertices, and the remaining vertices are identified as height vertices.

[0013] according to Calculate the threshold Degree λ ;

[0014] Where b represents the size of the current update batch, y represents the total number of edges connected to the low-degree vertices, and x represents the total number of edges connected to the high-degree vertices.

[0015] Furthermore, the graph update processing unit is also used to perform preprocessing operations before performing the graph update operation; the preprocessing operations include:

[0016] Sort the received updated edge data according to the destination vertex ID.

[0017] Furthermore, the preprocessing operations also include:

[0018] Remove redundant edges from the received updated edge data.

[0019] Furthermore, the updated edge data is divided into N groups according to the ID of the source vertex, including:

[0020] For each source vertex, perform the ID mod N operation, and group the edges connected to source vertices with the same operation result into the same group;

[0021] Here, mod represents the modulo operation.

[0022] Furthermore, the graph structure data is stored in the graph structure cache in the form of a hierarchical index; the hierarchical index includes: a vertex block array, a regular array, a redundant index array, and a hierarchical index tree;

[0023] The vertex block array includes V vertex blocks that correspond one-to-one with the V vertices in the graph structure data. Each vertex block is indexed by the vertex ID and includes L+1 slots; V is the number of vertices in the graph structure data.

[0024] For the i-th vertex block in the vertex block array, its first slot is used to store the degree of the i-th vertex. i If 0 ≤ Degree i If L ≤ L, then all destination vertices corresponding to the i-th vertex are stored in the i-th vertex block; otherwise, the L-1 destination vertices corresponding to the i-th vertex are stored in the 2nd to Lth slots of the i-th vertex block, and the remaining destination vertices are stored in the next-level structure, with the L+1th slot of the i-th vertex block storing a pointer to that next-level structure; if L <Degree i If L ≤ L + A, then the next level structure is a regular array; if L + A ≤ Degree i If the degree is less than or equal to L+M, then the next level structure is a redundant index array; if the degree is less than or equal to L+M, then the next level structure is a redundant index array. i If L+M, then the next level structure is a hierarchical index tree;

[0025] A regular array is used to store at most A vertices;

[0026] The redundant index array consists of an index array and a gap array. The gap array is used to store up to M vertices. The gap array consists of one or more storage blocks of equal size. Vertices are stored in the gap array in order of their IDs. The ID of the first vertex in each storage block is stored in the index array in order.

[0027] The hierarchical index tree is a tree structure, where its internal nodes are learning nodes and its leaf nodes are redundant index arrays or ordinary arrays; the learning nodes include a machine learning model and a learning index array; the machine learning model is used to predict the position of a vertex in the corresponding learning index array based on the ID of the vertex; the learning index array includes one or more entry blocks of equal size, and the vertices are stored in order in the learning index array according to their IDs;

[0028] The entries in the entry block include four types: unused type, edge type, block type, and pointer type; among them, the entries of the unused type are free entries, the entries of the edge type are the entries storing the destination vertex, the entries of the block type are the entries in the entry block where data movement has occurred and there are no child nodes, and the entries of the pointer type are the entries in the entry block with child nodes;

[0029] Among them, L, A, and M are all positive integers, and A < M.

[0030] Furthermore, the graph update operation includes:

[0031] For the edge (v, u) to be inserted, obtain the degree Degree of its source vertex v and the vertex block where the source vertex v is located. If 0 ≤ Degree ≤ L, then execute the vertex block insertion step; if L < Degree ≤ L + A, then execute the ordinary array insertion step; if L + A < Degree ≤ L + M, then execute the redundant array insertion step; if Degree > L + M, then execute the hierarchical index tree insertion step;

[0032] The vertex block insertion step includes:

[0033] Judge whether there is remaining space in the current vertex block. If so, insert the destination vertex u into the current vertex block; otherwise, create an ordinary array for the current vertex block, and store the destination vertex u and the data in the current vertex block after merging them in the current vertex block and the created ordinary array;

[0034] The ordinary array insertion step includes:

[0035] Judge whether there is remaining space in the current ordinary array. If so, insert the destination vertex u into the current ordinary array; otherwise, upgrade the current ordinary array to a redundant index array and clear the current ordinary array;

[0036] The redundant index array insertion step includes:

[0037] (S1) Determine the storage block in the gap array where the destination vertex u should be inserted according to the index array in the current redundant index array. If there is remaining space in this storage block, insert the destination vertex u into this storage block in order and update the index array, and the redundant index array insertion step ends; if there is no remaining space in this storage block, then go to (S2);

[0038] (S2) If there is remaining space in the gap array, calculate the total distance of data movement after inserting the destination vertex u in sequence, and go to (S3); if there is no remaining space in the gap array, go to (S4);

[0039] (S3) If the total data movement distance Distance≤Distance_Max, then insert the destination vertex u into the sequential insertion gap array, and the redundant index array insertion step ends; if Distance>Distance_Max, and the total space of the gap array has not reached M, then proceed to (S5); if Distance>Distance_Max, and the total space of the gap array has reached M, then proceed to (S6).

[0040] (S4) If the total space of the gap array has not reached M, then proceed to (S5); if the total space of the gap array has reached M, then proceed to (S6).

[0041] (S5) After expanding the gap array by one storage block, merge the data in the gap array together with the destination vertex u and distribute them evenly in each storage block, and update the index array. The redundant index array insertion step ends.

[0042] (S6) Upgrade the current redundant index array to a hierarchical index tree, clear the current redundant index array, and the redundant index array insertion step ends.

[0043] Where Distance_Max is a preset distance threshold;

[0044] The steps for inserting a hierarchical index tree include:

[0045] (T1) Set the root node of the current level index tree as the current node;

[0046] (T2) If the current node is a learning node, then use the machine learning model of the current node to predict the position p of the target vertex u in the learning index array, and proceed to step (T3); if the current node is a redundant index array, then execute the redundant index array insertion step, and the hierarchical index tree insertion step ends; if the current node is a normal array, then execute the normal array insertion step, and the hierarchical index tree insertion step ends.

[0047] (T3) Determine the entry type corresponding to position p. If it is an unused type, insert the destination vertex u into the entry at position p and update the entry type to edge type. If it is an edge type, proceed to (T4); if it is a block type, proceed to (T4); if it is a pointer type, proceed to the next level node and proceed to (T2).

[0048] (T4) If there is remaining space in the current entry block, insert the destination vertex u into the current entry block in order, and set the type of each entry in the current entry block to block type; otherwise, create a normal array for the current entry block, merge the data of the destination vertex u and the current entry block and store it in the created normal array, set the pointer of the created normal array in the current entry block, and set the type of each entry in the current entry block to pointer type.

[0049] Furthermore, the vertex block size is an integer multiple of the cache line size.

[0050] Furthermore, the default cache replacement strategy is any one of FIFO, LRU, or LFU.

[0051] Furthermore, the memory controller is also used to transfer the graph structure data to off-chip memory after each graph update processing unit has completed the graph update operation.

[0052] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0053] (1) In this invention, the priority scheduler treats the vertices with higher degrees and the edges connected to them in the updated edge data as high-priority data and permanently stores them in a high-priority on-chip cache. Based on the data locality of dynamic graphs, high-priority data is accessed frequently. By permanently storing this data in the cache, it can be quickly retrieved when performing graph update operations and subsequent graph analysis operations. This achieves data access pattern awareness, which is beneficial to improving the efficiency of graph update and graph analysis operations. The update edge allocator divides the updated edge data into N different groups and allocates them to N graph update processing units, thus decomposing the graph update task. Utilizing the hardware parallelism of the N graph update processing units, the efficiency of graph updates can be effectively improved. Overall, the dynamic graph processing device provided by this invention, based on data access pattern awareness and hardware parallelism, can effectively improve the update efficiency of dynamic graphs and is beneficial to improving the efficiency of subsequent graph analysis operations.

[0054] (2) In a preferred embodiment of the present invention, a threshold value (Degree) for distinguishing between high-priority data and low-priority data is adaptively calculated based on the degree of each vertex in the updated edge data. λ Specifically, first, based on a preset threshold λ, high-degree vertices and low-degree vertices are identified, and then according to... Calculate the average degree of the vertices with the highest degree as the threshold. λIn the final identified high-priority data, the degree of the vertices is higher than the average degree of the height vertices. Since the graph structure used to represent practical applications follows a power-law distribution, that is, there are many low-degree vertices and few high-degree vertices, this invention can accurately identify useful data and permanently reside it in the high-priority on-chip cache through this identification method.

[0055] (3) In a preferred embodiment of the present invention, the graph update processing unit sorts the received update edge data according to the destination vertex ID before performing the graph update operation. On the one hand, the orderliness of the update edge data can reduce the number of moves when inserting the update edge data, thereby reducing the data movement overhead. On the other hand, the orderliness of the update edge data is compatible with graph analysis algorithms such as TC, which is beneficial to improving the efficiency of subsequent graph analysis operations.

[0056] (4) In a preferred embodiment of the present invention, the graph update processing unit removes redundant update edge data before performing the graph update operation, thereby avoiding useless operations and further reducing the update overhead.

[0057] (5) In a preferred embodiment of the present invention, the graph structure data is stored in the form of a hierarchical index. Based on this storage method, vertices with different degrees will have different storage forms. For vertices with high degrees, a tree structure is used for storage, which is beneficial to improving update efficiency. For vertices with low degrees, an array-type structure is used for storage, which can ensure the locality of data and is beneficial to improving graph analysis efficiency. Correspondingly, when inserting and updating edges, a combination of horizontal expansion and vertical expansion is adopted, which effectively reduces data movement overhead. At the same time, based on the index array in the redundant index data and the machine learning model in the learning index array, the storage location of the data can be quickly located, which effectively reduces search overhead and can simultaneously achieve efficient graph update operations and graph analysis operations.

[0058] (6) In a preferred embodiment of the present invention, in the first-level vertex block array of the hierarchical index, the size of the data block corresponding to each vertex is an integer multiple of the cache line size, thereby enabling the source vertex and its corresponding destination vertex (i.e., neighboring nodes) to be loaded into the cache simultaneously, thereby effectively reducing the number of cache swaps, reducing overhead and improving access efficiency. Attached Figure Description

[0059] Figure 1 This is an architecture diagram of a hardware-software collaborative dynamic graph processing device for data access mode awareness, provided in an embodiment of the present invention.

[0060] Figure 2 A schematic diagram of a dynamic graph representation method for a hierarchical index provided in an embodiment of the present invention;

[0061] Figure 3 A flowchart of the graph update operation provided in this embodiment of the invention;

[0062] Figure 4 A schematic diagram illustrating an example of redundant index array insertion provided in an embodiment of the present invention;

[0063] Figure 5 This is a schematic diagram illustrating an example of inserting a learning index array according to an embodiment of the present invention. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0065] In this invention, the terms "first," "second," etc. (if present) in the invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0066] To improve the update efficiency of dynamic graphs, this invention provides a data access pattern-aware, hardware-software co-processing dynamic graph processing device. It employs hardware-software collaboration to identify high-priority and low-priority data based on vertex degree, permanently residing high-priority data in an on-chip cache, thus achieving data access pattern awareness. Simultaneously, it decomposes and distributes dynamic graph update tasks to multiple graph update processing units, leveraging the parallelism of these units to effectively improve the update efficiency. Building upon this, it further implements an efficient dynamic graph storage and update method, achieving efficient search and data movement while ensuring data locality and neighbor ordering, and effectively adjusting the distance of data movement, thereby achieving efficient dynamic graph updates and dynamic graph analysis.

[0067] Based on the above ideas, in one embodiment of the present invention, a data access mode-aware hardware-software collaborative dynamic graph processing device is provided, such as... Figure 1 As shown, it includes: a memory controller, a priority scheduler, a low-priority on-chip cache, a high-priority on-chip cache, a graph structure cache, an update edge allocator, and N graph update processing units; N≥2.

[0068] In this embodiment, the memory controller is used to read the graph structure data and the update edge data of the current update batch stored in the off-chip memory into the on-chip memory, and cache the graph structure data in the graph structure cache;

[0069] It is easy to understand that graph structure data is used to represent applications such as social networks, recommendation systems, and Internet of Things (IoT) networks. Accordingly, this embodiment can effectively improve the update and analysis efficiency of these applications. The updated edge data includes the edges of the graph structure to be inserted. Each edge is represented by its source vertex and destination vertex, for example, it can be represented as (v, u), where v represents the source vertex and u represents the destination vertex; each vertex has a unique ID.

[0070] In this embodiment, the priority scheduler is used to update edge data where the degree is higher than the threshold Degree. λ Vertices and edges connected to these vertices are identified as high-priority data and permanently reside in the high-priority on-chip cache. The remaining vertices and edges are identified as low-priority data and cached in the low-priority on-chip cache according to the preset cache replacement strategy.

[0071] Based on the data locality of dynamic graphs, high-priority data is accessed frequently. By permanently residing this data in the cache, it can be quickly retrieved when performing graph update operations and subsequent graph analysis operations. This achieves data access pattern awareness, which helps improve the efficiency of graph update and graph analysis operations.

[0072] Due to the limited on-chip cache capacity, in order to ensure that useful data resides permanently in the high-priority cache, a threshold (Degree) is used to distinguish between high-priority and low-priority data. λ The setting of the degree threshold is extremely important. Traditional solutions often directly set a threshold, classifying vertices with degrees higher than the threshold and their connected edges as high-priority data. However, graph structures used to represent real-world applications often follow a power-law distribution, meaning there are many low-degree vertices and few high-degree vertices. Traditional identification methods cannot effectively identify high-priority data. To address this problem, this embodiment proposes an adaptive threshold calculation method based on updating the degree of each vertex in the edge data. λ Specifically, in this embodiment, the threshold Degree λ The calculation methods include:

[0073] Vertices with a degree lower than a preset threshold λ in the updated edge data are identified as low-degree vertices, and the remaining vertices are identified as height vertices.

[0074] according to Calculate the threshold Degree λ ;

[0075] Where b represents the size of the current update batch, y represents the total number of edges connected to the low-degree vertices, and x represents the total number of edges connected to the high-degree vertices.

[0076] Based on the above identification method, in the high-priority data finally identified in this embodiment, the degree of the vertices is higher than the average degree of the vertices with height, thereby accurately identifying useful data to be permanently stored in the high-priority on-chip cache.

[0077] Meanwhile, the identified low-priority data is quite large, and it cannot all reside in the low-priority cache. Instead, it must be cached based on a preset cache replacement strategy. To improve cache replacement efficiency, this embodiment preferably uses lightweight cache replacement strategies such as FIFO, LRU, and LFU.

[0078] In this embodiment, the edge update allocator is used to read update edge data from the high-priority on-chip cache and the low-priority on-chip cache, and divide the update edge data into N groups according to the ID of the source vertex, and allocate them to N graph update processing units respectively.

[0079] In this embodiment, the edge update allocator divides the edge update data into N groups and distributes them to N graph update processing units, thereby decomposing the update task.

[0080] Optionally, in this embodiment, the method by which the edge update allocator divides the edge update data into N groups according to the ID of the source vertex specifically includes:

[0081] For each source vertex, perform the ID mod N operation, and group the edges connected to source vertices with the same operation result into the same group;

[0082] Here, mod represents the modulo operation.

[0083] In this embodiment, the graph update processing unit is used to perform graph update operations to insert the received update edge data into the graph structure data. Since the update edge data involved in the graph update operations performed by each graph update processing unit does not overlap, N graph update processing units can perform graph update operations in parallel, effectively improving the efficiency of graph updates.

[0084] To further improve efficiency and reduce overhead, in a preferred embodiment, the graph update processing unit is further configured to perform a preprocessing operation before performing the graph update operation; the preprocessing operation includes:

[0085] Sort the received updated edge data according to the destination vertex ID.

[0086] By sorting the target vertices, the orderliness of the updated edge data can be guaranteed. On the one hand, the orderliness of the updated edge data can reduce the number of moves when inserting updated edge data, thereby reducing data movement overhead. On the other hand, the orderliness of the updated edge data is compatible with graph analysis algorithms such as TC, which is conducive to improving the efficiency of subsequent graph analysis operations.

[0087] Considering that some redundancy may exist in the updated edge data during actual graph update operations, in order to avoid useless operations and further reduce overhead, in this embodiment, the preprocessing operations performed by the graph update processing unit before executing the graph update operation further include:

[0088] Remove redundant edges from the received updated edge data.

[0089] The number of graph update processing units, N, is often set to a power of 2. In practical applications, it can be set according to the actual computing resources of the system.

[0090] In this embodiment, the memory controller is also used to transfer the graph structure data to off-chip memory after each graph update processing unit has completed the graph update operation.

[0091] To further improve the efficiency of dynamic graph updates and simultaneously achieve efficient graph analysis operations, this embodiment proposes a hierarchical indexed graph structure data storage format and a corresponding locality-aware dynamic graph update mechanism. In the hierarchical indexed graph structure data storage format, vertex data is stored in a vertex block array, a regular array, a redundant index array, or a hierarchical index tree, based on the degree of the vertices in the dynamic graph. In the locality-aware dynamic graph data update mechanism, during graph data updates, data movement is standardized to effectively adjust the distance the data moves within the data structure, minimizing memory access overhead during the graph update process. After the memory controller reads the graph structure data from off-chip memory into the graph structure cache, the graph structure data is stored in the graph structure cache in the form of a hierarchical index. When the graph update processing unit performs graph update operations, it specifically follows the locality-aware dynamic graph update mechanism.

[0092] Specifically, such as Figure 2 As shown, in this embodiment, the hierarchical index includes: a vertex block array, a normal array, a redundant index array, and a hierarchical index tree;

[0093] The vertex block array includes V vertex blocks that correspond one-to-one with the V vertices in the graph structure data. Each vertex block is indexed by the vertex ID and includes L+1 slots; V is the number of vertices in the graph structure data.

[0094] For the i-th vertex block in the vertex block array, its first slot is used to store the degree of the i-th vertex. i If 0 ≤ Degree i If L ≤ L, then all destination vertices corresponding to the i-th vertex are stored in the i-th vertex block; otherwise, the L-1 destination vertices corresponding to the i-th vertex are stored in the 2nd to Lth slots of the i-th vertex block, and the remaining destination vertices are stored in the next-level structure, with the L+1th slot of the i-th vertex block storing a pointer to that next-level structure; if L <Degreei If L ≤ L + A, then the next level structure is a regular array; if L + A ≤ Degree i If the degree is less than or equal to L+M, then the next level structure is a redundant index array; if the degree is less than or equal to L+M, then the next level structure is a redundant index array. i If L+M, then the next level structure is a hierarchical index tree;

[0095] A regular array is used to store at most A vertices;

[0096] The redundant index array consists of an index array and a gap array. The gap array is used to store up to M vertices. The gap array consists of one or more storage blocks of equal size. Vertices are stored in the gap array in order of their IDs. The ID of the first vertex in each storage block is stored in the index array in order.

[0097] The hierarchical index tree is a tree structure, with internal nodes being learning nodes and leaf nodes being redundant index arrays or ordinary arrays. The learning node includes a machine learning model and a learning index array. The machine learning model is used to predict the position of a vertex in the corresponding learning index array based on the vertex's ID. The learning index array includes one or more blocks of entries of equal size, and vertices are stored in the learning index array in order of their IDs.

[0098] The entries in an entry block include four types: unused type, edge type, block type, and pointer type. Among them, unused type entries are free entries, edge type entries are entries that store the destination vertex, block type entries are entries in an entry block where data has been moved and there are no child nodes, and pointer type entries are entries in an entry block where there are child nodes.

[0099] Where L, A, and M are all positive integers, and A <M。

[0100] In practical applications, the machine learning model in the learning node can adopt models such as linear regression (LR). These models can approximate the cumulative distribution function (CDF) when making predictions, thus effectively predicting the position of a key value in an ordered array.

[0101] In hierarchical indexed graph data storage, vertices with different degrees will have different storage formats. For vertices with high degrees, a tree structure is used to improve update efficiency; for vertices with low degrees, an array structure is used to ensure data locality and improve graph analysis efficiency.

[0102] As a preferred embodiment, in this embodiment, the size of each vertex block is the size of a cache line, so that the source vertex and its corresponding destination vertex (i.e., neighbor node) can be loaded into the cache simultaneously, effectively reducing the number of cache exchanges, reducing overhead, and improving access efficiency. In some other embodiments of the present invention, the size of each vertex block can also be set to an integer multiple of the cache line size.

[0103] Based on the hierarchical index-based storage form of graph structure data, as Figure 3 shown, in this embodiment, the graph update operations performed by the graph update processing unit include:

[0104] For the edge (v, u) to be inserted, obtain the degree Degree of its source vertex v and the vertex block where the source vertex v is located. If 0 ≤ Degree ≤ L, perform the vertex block insertion step; if L < Degree ≤ L + A, perform the ordinary array insertion step; if L + A < Degree ≤ L + M, perform the redundant array insertion step; if Degree > L + M, perform the hierarchical index tree insertion step.

[0105] The vertex block insertion step includes:

[0106] Judge whether there is remaining space in the current vertex block. If so, insert the destination vertex u into the current vertex block; otherwise, create an ordinary array for the current vertex block, and store the merged data of the destination vertex u and the data in the current vertex block in the current vertex block and the created ordinary array.

[0107] The ordinary array insertion step includes:

[0108] Judge whether there is remaining space in the current ordinary array. If so, insert the destination vertex u into the current ordinary array; otherwise, upgrade the current ordinary array to a redundant index array and clear the current ordinary array;

[0109] It is easy to understand that upgrading the current ordinary data to a redundant index array specifically means that after creating a new redundant index array, store the data in the current ordinary array and the destination vertex u in the storage format of the redundant index array, and modify the pointer pointing to the current ordinary array to point to the created redundant index array;

[0110] The redundant index array insertion step includes:

[0111] (S1) Determine the storage block in the gap array where the destination vertex u should be inserted according to the index array in the current redundant index array. If there is remaining space in this storage block, insert the destination vertex u into this storage block in order and update the index array, and the redundant index array insertion step ends; if there is no remaining space in this storage block, go to (S2);

[0112] (S2) If there is remaining space in the gap array, calculate the total distance of data movement after inserting the destination vertex u in sequence, and go to (S3); if there is no remaining space in the gap array, go to (S4);

[0113] In this embodiment, the total distance of data movement refers to the sum of the distances moved by each data after insertion, and its upper limit is the preset distance threshold Distance_Max;

[0114] (S3) If the total data movement distance Distance ≤ Distance_Max, then insert the destination vertex u into the sequential insertion gap array, and the redundant index array insertion step ends; at this time, inserting the destination vertex u will cause data movement between storage blocks.

[0115] If Distance > Distance_Max, and the total space of the gap array has not reached M, then proceed to (S5) to expand the redundant index array.

[0116] If Distance > Distance_Max, and the total space of the gap array reaches M, then proceed to (S6);

[0117] This embodiment determines whether to perform inter-block data movement based on both the data movement distance and the total space of the gap array, thus avoiding excessive data movement overhead.

[0118] (S4) If the total space of the gap array does not reach M, then proceed to (S5) to expand the redundant index array; if the total space of the gap array reaches M, then proceed to (S6).

[0119] (S5) After expanding the gap array by one storage block, merge the data in the gap array together with the destination vertex u and distribute them evenly in each storage block, and update the index array. The redundant index array insertion step ends.

[0120] In this embodiment, after each expansion of the redundant index array, the data is merged and evenly distributed across the storage blocks, thereby reducing the number of data movements in subsequent insertion operations.

[0121] (S6) Upgrade the current redundant index array to a hierarchical index tree, clear the current redundant index array, and the redundant index array insertion step ends.

[0122] What is easy to understand is that upgrading the current redundant index array to a hierarchical index tree specifically means that after creating a new hierarchical index tree, the data in the current redundant index array and the destination vertex u are stored according to the storage format of the hierarchical index tree, and the pointer to the current redundant index array is modified to point to the created hierarchical index tree.

[0123] The steps for inserting a hierarchical index tree include:

[0124] (T1) Set the root node of the current level index tree as the current node;

[0125] (T2) If the current node is a learning node, then use the machine learning model of the current node to predict the position p of the target vertex u in the learning index array, and proceed to step (T3); if the current node is a redundant index array, then execute the redundant index array insertion step, and the hierarchical index tree insertion step ends; if the current node is a normal array, then execute the normal array insertion step, and the hierarchical index tree insertion step ends.

[0126] (T3) Determine the entry type corresponding to position p. If it is an unused type, insert the destination vertex u into the entry at position p and update the entry type to edge type. If it is an edge type, proceed to (T4); if it is a block type, proceed to (T4); if it is a pointer type, proceed to the next level node and proceed to (T2).

[0127] (T4) If there is remaining space in the current entry block, insert the destination vertex u into the current entry block in order, and set the type of each entry in the current entry block to block type; otherwise, create a normal array for the current entry block, merge the data of the destination vertex u and the current entry block and store it in the created normal array, set the pointer of the created normal array in the current entry block, and set the type of each entry in the current entry block to pointer type.

[0128] Based on the above update mechanism, when inserting and updating edges, a combination of horizontal and vertical expansion is adopted, which effectively reduces data movement overhead. At the same time, based on the index array in the redundant index data and the machine learning model in the learned index array, the storage location of the data can be quickly located, which effectively reduces search overhead. Efficient graph update operations and graph analysis operations can be achieved simultaneously.

[0129] by Figure 4The example shown details the insertion process of a redundant index array. The index array has a size of 2, and the block size is 4. This redundant index array stores the edges of the vertex with vertex ID 2. The initial index array is [6,16], and the gap array is updated to [6,8,\,\,16,17,\,\], where \ represents the gap. There are three main cases during insertion. When inserting edges (2,5) and (2,9), there is enough space in the first block, so the data is moved within the block and inserted into the gap array [5,6,8,9,16,17,\,\], and finally the index array is updated to [5,16]. Then, when inserting edge (2,7), there is not enough space in the first block, but there is enough space in the block as a whole, so the data can be moved between blocks and inserted. The gap array is updated to [5,6,7,8,9,16,17,\], and finally the index array is updated to [5,9]. Finally, when inserting edges (2,11) and (2,12), there is no remaining space in the block, so the space is expanded, a new block is added, and the elements are evenly distributed in each block. The gap array is updated to [5,6,7,\,8,9,11,\,12,16,17,\], and the index array is updated to [5,8,12].

[0130] by Figure 5 The example shown details the insertion process of the learning index array. The learning index array is denoted as `array`, with a block size of 4, and the example uses the first 4 spaces (1 block). There are three main cases during insertion. When edge (3,6) is inserted, the predicted position of 6 in the learning index array should be 3, denoted as np.model(v). This represents the position of v predicted by the model in the learning index array. Since the position type of array[3] is unused (U) at this time, 6 is directly inserted at this position, and the position type is changed to edge (E). When edge (3,4) is inserted, the predicted position of 4 is 2. At this time, the position of array[2] has been used by 5, and its type is edge (E), which is a conflict. Therefore, the elements are moved horizontally within the block, and a gap position is found to insert 4. Then, the type of all entries in the entire block is changed to block. When edge (3,3) is inserted, there is not enough space to accommodate 3. Therefore, the data is merged, a redundant index array is created to store the merged data, and the type of all entries in the block is changed to a pointer to the redundant index array.

[0131] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A data access mode-aware, hardware-software collaborative dynamic graph processing device, characterized in that, include: Memory controller, priority scheduler, low-priority on-chip cache, high-priority on-chip cache, graph structure cache, update edge allocator, and N Each graph update processing unit; N ≥2; The memory controller is used to read the graph structure data and the update edge data of the current update batch stored in the off-chip memory into the on-chip memory, and cache the graph structure data in the graph structure cache; The updated edge data includes the edges of the graph structure to be inserted. Each edge is represented by its source vertex and destination vertex, and each vertex has a unique ID. The priority scheduler is used to update edge data with a degree higher than a threshold. Vertices and edges connected to these vertices are identified as high-priority data and permanently resided in the high-priority on-chip cache, while the remaining vertices and edges connected to them are identified as low-priority data and cached in the low-priority on-chip cache according to a preset cache replacement strategy. The update edge allocator is used to read update edge data from the high-priority on-chip cache and the low-priority on-chip cache, and divide the update edge data into categories according to the ID of the source vertex. N Groups, respectively assigned to the N Each graph update processing unit; The graph update processing unit is used to perform graph update operations to insert the received update edge data into the graph structure data; The N Each graph update processing unit has hardware parallelism; The threshold The calculation methods include: Vertices with a degree lower than a preset threshold λ in the updated edge data are identified as low-degree vertices, and the remaining vertices are identified as height vertices. according to Calculate the threshold ; in, b Indicates the size of the current update batch. y This represents the total number of edges connected to the lower-degree vertices. x This represents the total number of edges connected to the vertices whose height is a vertex.

2. The data access mode-aware, hardware-software collaborative dynamic graph processing device as described in claim 1, characterized in that, The graph update processing unit is further configured to perform a preprocessing operation before performing the graph update operation; the preprocessing operation includes: Sort the received updated edge data according to the destination vertex ID.

3. The data access mode-aware, hardware-software collaborative dynamic graph processing device as described in claim 2, characterized in that, The preprocessing operation also includes: Remove redundant edges from the received updated edge data.

4. The data access mode-aware, hardware-software collaborative dynamic graph processing device as described in claim 1, characterized in that, The update edge data is divided according to the ID of the source vertex. N Groups, including: For each source vertex, perform the ID mod N operation, and group the edges connected to source vertices with the same operation result into the same group; Here, mod represents the modulo operation.

5. The data access mode-aware, hardware-software collaborative dynamic graph processing device as described in claim 1, characterized in that, The graph structure data is stored in the graph structure cache in the form of a hierarchical index; the hierarchical index includes: a vertex block array, a normal array, a redundant index array, and a hierarchical index tree; The vertex block array includes V vertex blocks that correspond one-to-one with the V vertices in the graph structure data. Each vertex block is indexed by a vertex ID and includes L+1 slots; V is the number of vertices in the graph structure data. For the first vertex block array i The first slot of the vertex block is used to store the first vertex block. i Degree of each vertex ;like Then the first i The destination vertex corresponding to each vertex is stored in the first vertex. i In the vertex block; otherwise, in the . i The L-1 destination vertices corresponding to the vertex are stored in the first vertex. i In the second to Lth slots of a vertex block, the remaining destination vertices are stored in the next level structure, and the... i The (L+1)th slot of each vertex block stores a pointer to the next level structure; if +A, then the next level structure is a regular array; if Then the next level structure is a redundant index array; if Then the next level structure is a hierarchical index tree; The ordinary array is used to store up to A vertices; The redundant index array includes an index array and a gap array; the gap array is used to store up to M vertices, and the gap array includes one or more storage blocks of equal size, with vertices stored in the gap array in order of their IDs; the ID of the first vertex in each storage block is stored in order in the index array; The hierarchical index tree is a tree structure, with internal nodes being learning nodes and leaf nodes being redundant index arrays or ordinary arrays; the learning node includes a machine learning model and a learning index array; the machine learning model is used to predict the position of a vertex in the corresponding learning index array based on the vertex's ID; the learning index array includes one or more entries of equal size, and vertices are stored in the learning index array in an ordered manner according to their IDs; The entries in the entry block include four types: unused type, edge type, block type, and pointer type; among them, unused type entries are free entries, edge type entries are entries that store the destination vertex, block type entries are entries in the entry block where data movement has occurred and there are no child nodes, and pointer type entries are entries in the entry block where there are child nodes. Where L, A, and M are all positive integers, and A <M。 6. The data access mode-aware, hardware-software collaborative dynamic graph processing device as described in claim 5, characterized in that, The graph update operation includes: For the edge to be inserted Obtain its source vertex v degree and source vertex v If the vertex block is located, Then execute the vertex block insertion step; if If so, then perform the normal array insertion step; if Then the redundant array insertion step is performed; if If so, then the hierarchical index tree insertion step will be executed; The vertex block insertion step includes: Determine if there is remaining space in the current vertex block; if so, move the target vertex. u Insert into the current vertex block; otherwise, create a regular array for the current vertex block and set the destination vertex. u The data in the current vertex block is merged and stored in the current vertex block and the created ordinary array; The ordinary array insertion step includes: Check if there is any remaining space in the current ordinary array. If so, move the target vertex. u Insert into the current ordinary array; otherwise, promote the current ordinary array to a redundant index array and clear the current ordinary array. The redundant index array insertion step includes: (S1) Determine the destination vertex based on the index array in the current redundant index array. u The storage block to be inserted in the gap array; if there is remaining space in the storage block, then the destination vertex... u Insert the redundant index array into the storage block in sequence and update the index array. The redundant index array insertion step ends. If there is no remaining space in the storage block, proceed to (S2). (S2) If there is remaining space in the gap array, then calculate the sequential insertion of the target vertex. u The total distance the data moves is then calculated and transferred to (S3); if there is no remaining space in the gap array, then transfer to (S4). (S3) If the total data movement distance Distance ≤ Distance_Max, then the destination vertex will be... u Insert the elements sequentially into the gap array, ending the redundant index array insertion step; if Distance > Distance_Max, and the total space of the gap array has not been reached. M If Distance > Distance_Max, and the total space of the gap array reaches... M Then proceed to (S6); (S4) If the total space of the gap array has not reached M Then proceed to (S5); if the total space of the gap array reaches M Then proceed to (S6); (S5) After expanding the gap array by one storage block, the data in the gap array along with the destination vertex are... u After merging, the data are evenly distributed across the storage blocks, and the index array is updated. The redundant index array insertion step is then complete. (S6) Upgrade the current redundant index array to a hierarchical index tree, clear the current redundant index array, and the redundant index array insertion step ends; Where Distance_Max is a preset distance threshold; The hierarchical index tree insertion step includes: (T1) Set the root node of the current level index tree as the current node; (T2) If the current node is a learning node, then use the machine learning model of the current node to predict the target vertex. u Learn the position p in the index array and proceed to step (T3); if the current node is a redundant index array, execute the redundant index array insertion step and the hierarchical index tree insertion step ends; if the current node is a normal array, execute the normal array insertion step and the hierarchical index tree insertion step ends. (T3) Determine the type of the entry corresponding to position p. If it is an unused type, then set the destination vertex. u Insert the entry at position p and update the entry type to edge type, the hierarchical index tree insertion step technique; if it is edge type, then go to (T4); if it is block type, then go to (T4); if it is pointer type, then go to the next level node and go to (T2). (T4) If there is remaining space in the current entry block, then move the destination vertex. u Insert the current entry block sequentially, and set the type of each entry in the current entry block to block type; otherwise, create a regular array for the current entry block, and set the destination vertex... u The data in the current entry block is merged and stored in the created ordinary array. A pointer to the created ordinary array is set in the current entry block, and the type of each entry in the current entry block is set to pointer type.

7. The data access mode-aware, hardware-software collaborative dynamic graph processing device as described in claim 5, characterized in that, The vertex block size is an integer multiple of the cache line size.

8. The data access mode-aware, hardware-software collaborative dynamic graph processing device as described in claim 1, characterized in that, The preset cache replacement strategy is any one of FIFO, LRU, and LFU.

9. The data access mode-aware, hardware-software collaborative dynamic graph processing device as described in claim 1, characterized in that, The memory controller is also used to transfer the graph structure data to the off-chip memory after each graph update processing unit has completed the graph update operation.

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