Binary matrix comparative symmetry elimination unit combination acceleration method and system

Abstract

The invention discloses a binary matrix comparative symmetry elimination unit commitment acceleration method and system, and relates to the technical field of unit commitment symmetry elimination. Constructing a symmetric unit start-stop matrix and comparing the symmetric unit start-stop matrix with a binary matrix; and optimizing a decision process and accelerating output. According to the binary matrix comparative symmetry elimination unit commitment acceleration method provided by the invention, the binary matrix is called as a symmetric unit start-stop matrix, the sum of start-stop instruction variables is obtained, and rapid generation of a unit logic state variable sequence is completed. Through comparison of binary matrixes, elimination of unit symmetry is achieved, comparison constraints are introduced, symmetric solutions existing in symmetric units are cut off, the search space of a branch and bound algorithm is reduced, the solving efficiency is improved, and better effects are achieved in the aspects of solving efficiency, resource consumption and problem solving complexity.

Description

Technical Field

[0001] The present invention relates to the technical field of symmetry elimination of unit combinations, and in particular to a binary matrix comparison symmetry elimination unit combination acceleration method and system. Background Art

[0002] Unit commitment is a typical mixed integer programming problem, the purpose of which is to achieve the lowest unit operation cost and start-up and shutdown cost by reasonable unit selection and operation strategy under the conditions of load balance, unit operation constraints and network constraints. At present, the most commonly used unit commitment model is the 3-integer variable unit commitment model, and the most common main algorithm is the branch and bound algorithm.

[0003] Since there are a lot of symmetries in the units in the real power system, there may be multiple units with the same parameters at a node, and the network constraints can be ignored in the non-blocking area, the impact of unit symmetry is further amplified.

[0004] The influence of unit symmetry on the solution of unit combination branch and bound algorithm is as follows:

[0005] Search space expansion: Symmetry causes the branch-and-bound algorithm to generate a large number of equivalent solutions during the search process, making the search space huge and increasing the complexity of solving the problem.

[0006] Difficult pruning: Symmetry makes the pruning process difficult. Traditional branch-and-bound algorithms use pruning to reduce the search space and improve solution efficiency. However, in unit commitment problems with symmetric solutions, due to the existence of symmetry, the pruning conditions are often not met, resulting in the inability to effectively prune equivalent solutions, thereby reducing the effect of pruning.

[0007] Repeated calculation: Symmetry can lead to repeated calculation. Due to symmetry, there are equivalences between units with the same parameters, but branch-and-bound algorithms often fail to recognize these equivalences. Therefore, during the search process, the algorithm may repeatedly calculate the same subproblems, increasing the calculation time and resource consumption.

[0008] At present, the common methods for eliminating symmetry of unit combination are:

[0009] Aggregate unit: The main idea is to add the output of units with the same parameters, turning them into one equivalent unit, eliminating the symmetry of the units.

[0010] Symmetry breaking inequality: The main idea is to enforce the startup priority of the same units. Summary of the invention

[0011] In view of the above-mentioned problems, the present invention is proposed.

[0012] Therefore, the technical problem solved by the present invention is that the existing technical method for eliminating symmetry of unit combination has the problems of expansion of search space, difficulty in pruning, repeated calculation and low solution efficiency.

[0013] To solve the above technical problems, the present invention provides the following technical solutions: a binary matrix comparison symmetry elimination unit combination acceleration method, including identifying and classifying unit symmetry; constructing a symmetric unit start-stop matrix and applying binary matrix comparison; optimizing the decision process and accelerating the output

[0014] As a preferred solution of the binary matrix comparison symmetry elimination unit commitment acceleration method of the present invention, wherein: the identifying and classifying unit symmetry includes classifying the transmission lines into blocked lines and non-blocked lines according to the operation history data of the power grid;

[0015] If only non-blocking lines connect the power plants, the internal parts are considered as non-blocking system areas, and such areas are denoted by Indicates that in each unblocked area, the symmetry between the internal units is determined according to the parameters of the unit

[0016] The parameters include the unit's ramp rate, output limit, minimum start and stop time, and unit quotation.

[0017] As a preferred solution of the binary matrix comparison symmetry elimination unit combination acceleration method of the present invention, wherein: the construction of the symmetric unit start-stop matrix and the application of the binary matrix comparison are included in the unit combination model, and the logical state of the unit is represented by three 0 / 1 variables, which are the state logic variables of the unit The startup command variable of the unit and shutdown command variables Satisfying the constraints is expressed as:

[0018]

[0019] in, The logical variable representing the state of the unit, Indicates the startup command variable of the unit. represents the shutdown command variable, g represents the unit number, and t represents the current scheduling period;

[0020] The first equality constraint indicates that the logical state of the unit is affected by the start-stop command variable, and according to the second constraint, at the same time t, the sum of the start-stop variables For a 0 / 1 variable use It is expressed as:

[0021]

[0022] in, Represents the sum of start and stop variables

[0023] As a preferred solution of the binary matrix comparison symmetry elimination unit combination acceleration method described in the present invention, wherein: the construction of the symmetric unit start-stop matrix and the application of the binary matrix comparison include defining variables, eliminating the symmetry between units with the same parameters, and summing the start-stop instruction variables of the symmetric units Constructed in matrix form, assuming that there are G units with symmetry, the units have the same parameters, and a total of T scheduling periods are output, the symmetric unit start-stop matrix is ​​expressed as:

[0024]

[0025] Among them, u represents the sum of start-stop variables;

[0026] The size of the symmetric unit start-stop matrix is ​​T×G, which is a binary matrix. The sum of the start-stop variables of the unit satisfies the constraints, and the elements of the symmetric unit start-stop matrix are 1 at some times. The start-stop of the unit will lead to an increase in the start-stop cost of the unit. The direction of minimizing the objective function prompts the start-stop action to be 0. The element value of the symmetric unit start-stop matrix is ​​0, which makes the symmetric unit start-stop matrix sparse.

[0027] As a preferred solution of the binary matrix comparison symmetry elimination unit combination acceleration method of the present invention, wherein: the construction of the symmetric unit start-stop matrix and the application of the binary matrix comparison include the start-stop instruction variable and unit logic state variables After the start and stop variables of the unit are known, the state logic variables of the unit during the initial scheduling period are calculated. Perform 0 / 1 branch output of the unit's logical state variables, assuming that a column of the symmetrical unit start-stop matrix in the branch is (0101) T , then the unit logic state sequence is expressed as:

[0028]

[0029] in, Represents the state logic variable of the unit at the initial moment;

[0030] After all 0 / 1 variables of the unit are determined, there are no binary variables in the model. All the logical sequence combinations of the unit states are input into the unit combination problem model, and the output plan of the unit is output. The output of the unit is a continuous decision variable. At this time, the unit combination model is transformed into a linear programming problem, and the solution to the linear programming problem is completed in polynomial time.

[0031] If after generating the symmetric unit start-stop matrix, the unit symmetry is manifested in each column of the matrix, the values ​​of the i-th column and the j-th column of the matrix are mutually replaced, representing the variable sequence u of the corresponding two units i and u j Exchange, according to the equality constraint, the generated unit logic state variable sequence and output plan are also permuted. Since each unit contained in the matrix has the same parameters, the optimal objective function value output after permutation is the same.

[0032] As a preferred solution of the binary matrix comparison symmetry elimination unit commitment acceleration method of the present invention, wherein: the optimization decision process and accelerated output include introducing constraints to artificially destroy the property of each column permutation of the symmetric unit start-stop matrix to eliminate the symmetry between the units;

[0033] Treat each column of the matrix as a comparison object. For the jth column of the matrix, record the first row number i where the value is 1. For all If the row number i is negatively correlated with the binary value represented by the column, assuming that the number of rows with the value 1 first is the same, then the number of rows with the value 1 second is compared, which is the same as the method of converting a binary sequence into a decimal system, expressed as:

[0034]

[0035] Wherein, M represents the start-stop conversion value.

[0036] As a preferred solution of the binary matrix comparison symmetry elimination unit commitment acceleration method of the present invention, wherein: the optimization decision process and accelerated output include defining the optimal variable matrix that satisfies the column increasing order, screening out the matrix that satisfies the column increasing order, breaking the symmetry of the unit, and the constraint realization is expressed as:

[0037]

[0038] Among them, represents the start-stop conversion value;

[0039] Branch the start and stop command variables and record the variables The value and index of (t,g);

[0040] If the branch result is 1, the value in the binary matrix is ​​1, otherwise it is 0. In this case, the comparison order is listed;

[0041] By comparing constraints and continuously selecting branched binary matrices with increasing columns, the symmetric solutions are removed, the search space and the corresponding solution time are shortened, the symmetry of the unit combination is eliminated, and the accelerated solution of the unit combination is achieved.

[0042] Another object of the present invention is to provide a binary matrix comparison symmetry elimination unit combination acceleration system, which can eliminate the unit symmetry by comparing the binary matrix, thereby solving the problem of low solution efficiency in the current unit combination symmetry elimination technology.

[0043] As a preferred solution of the binary matrix comparison symmetry elimination unit combination acceleration system described in the present invention, it includes: a unit symmetry identification and classification module, a symmetric unit start-stop matrix construction module, and a decision process optimization module; the unit symmetry identification and classification module is used to provide premise information for the symmetry elimination strategy by clarifying the symmetry of the units in the power grid; the symmetric unit start-stop matrix construction module is used to destroy the symmetry between units by comparing and sorting the columns of the binary matrix; the decision process optimization module is used to determine the logical state variables of the unit through an improved branching strategy.

[0044] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of a binary matrix comparison symmetry elimination unit combination acceleration method.

[0045] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of a binary matrix comparison symmetry elimination unit combination acceleration method.

[0046] Beneficial effects of the present invention: The binary matrix comparison symmetry elimination unit combination acceleration method provided by the present invention refers to the binary matrix as a symmetric unit start-stop matrix, and uses the property that the unit start-stop instruction variables cannot be 1 at the same time to obtain the sum of the start-stop instruction variables, thereby completing the rapid generation of the unit logic state variable sequence. By comparing the binary matrix, the elimination of the unit symmetry is achieved, and comparison constraints are introduced to cut off the symmetric solutions existing in the symmetric unit, thereby reducing the search space of the branch and bound algorithm and accelerating the solution efficiency. Not too many symmetry-destroying constraints are introduced in the model, and more operations are performed in the branching process, and the model considers all unit combination constraints. The present invention achieves better results in terms of solution efficiency, resource consumption, and the complexity of solving problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0048] Figure 1An overall flow chart of a binary matrix comparison symmetry elimination unit combination acceleration method provided for the first embodiment of the present invention.

[0049] Figure 2 A diagram of the optimal objective function value solved after permutation of a binary matrix comparison symmetry elimination unit combination acceleration method provided in the first embodiment of the present invention.

[0050] Figure 3 A symmetric unit start-stop matrix diagram of a binary matrix comparison symmetry elimination unit combination acceleration method provided in the first embodiment of the present invention.

[0051] Figure 4 A flowchart of a binary matrix comparison symmetry elimination unit combination acceleration method provided for the first embodiment of the present invention.

[0052] Figure 5 A diagram for verifying the effectiveness of an algorithm for a binary matrix comparison symmetry elimination unit combination acceleration method provided in the second embodiment of the present invention.

[0053] Figure 6 An overall flow chart of a binary matrix comparison symmetry elimination unit combination acceleration system provided for the third embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0055] Example 1

[0056] Reference Figure 1-Figure 4 , is an embodiment of the present invention, and provides a binary matrix comparison symmetry elimination unit combination acceleration method, comprising:

[0057] S1: Identify and classify unit symmetries.

[0058] Furthermore, the transmission lines are divided into blocked lines and non-blocked lines according to the operation history data of the power grid;

[0059] If only non-blocking lines connect the power plants, the internal parts are considered as non-blocking system areas, and such areas are denoted by Indicates that in each unblocked area, the symmetry between the internal units is determined according to the parameters of the unit

[0060] The parameters include the unit's ramp rate, output limit, minimum start and stop time, and unit quotation.

[0061] S2: Construct a symmetric unit start-stop matrix and apply binary matrix comparison.

[0062] Furthermore, in the general unit combination model, the logical state of the unit can be represented by three 0 / 1 variables, which are the state logic variables of the unit The startup command variable of the unit and shutdown command variables Where g represents the unit number and t represents the current scheduling period. They must satisfy the following constraints:

[0063]

[0064] in, The logical variable representing the state of the unit, Indicates the startup command variable of the unit, represents the shutdown command variable, g represents the unit number, and t represents the current scheduling period.

[0065] It should be noted that the first equation constraint indicates that the logical state of the unit is affected by the start-stop command variable, and according to the second constraint, at the same time t, the sum of the start-stop variables Still a 0 / 1 variable Indicates that:

[0066]

[0067] in, Represents the sum of start and stop variables

[0068] It should also be noted that after defining the above variables, in order to eliminate the symmetry between the units with the same parameters, the sum of the start and stop command variables of the symmetrical units needs to be It is organized into a matrix form. Therefore, assuming that there are G units with symmetry, they must have the same basic parameters, and a total of T scheduling periods are solved. The specific form of the matrix is ​​as follows:

[0069]

[0070] Wherein, u represents the sum of the start-stop variables.

[0071] Furthermore, this article calls this matrix the symmetric unit start-stop matrix. By analyzing its characteristics, it can be found that the size of the matrix is ​​T×G. In addition, the matrix is ​​a binary matrix. The specific reason is that the constraints satisfied by the sum of the start-stop variables of the unit, and the elements of the symmetric unit start-stop matrix are 1 only at some times. Because frequent unit start-stop will increase the start-stop cost of the unit, the direction of minimizing the objective function will prompt the start-stop action to be as 0 as possible. Therefore, most of the elements of the symmetric unit start-stop matrix are 0, which is sparse.

[0072] It should be noted that due to the start-stop command variable and unit logic state variables After the start and stop variables of the unit are known, the state logic variables of the unit during the initial scheduling period are calculated. The 0 / 1 branch can quickly generate the logical state variables of the unit. Specifically, assuming that a column of the symmetrical unit start-stop matrix in the branch is (0101) T , then the unit logic state sequence can be generated as:

[0073]

[0074] It should also be noted that after all 0 / 1 variables of the unit are determined, there are no binary variables in the model. Only all logical sequence combinations of unit states are brought into the unit combination problem model. The unit output plan needs to be solved, and the unit output is a continuous decision variable. Therefore, the unit combination model at this time becomes a linear programming problem. The solution to the linear programming problem can be completed in polynomial time. Therefore, the characteristics of the symmetric unit start-stop matrix have a great positive effect on eliminating the symmetry between units.

[0075] After generating a symmetric unit start-stop matrix, it can be found that the unit symmetry is mainly reflected in each column of the matrix. Specifically, the values ​​of the i-th column and the j-th column of the matrix can be replaced with each other, which represents the variable sequence u of the corresponding two units. i and u j Therefore, according to the equality constraint, the generated unit logic state variable sequence and the corresponding output plan are also permuted. Since each unit contained in the matrix has the same parameters, the optimal objective function value solved after permutation is the same, which can be expressed as Figure 2 express.

[0076] Therefore, the problem of eliminating unit symmetry is transformed into eliminating column symmetry of the start-stop matrix of the symmetrical unit.

[0077] S3: Optimize the decision-making process and accelerate output.

[0078] Furthermore, according to the above description, if the permutable nature of each column of the symmetric unit start-stop matrix can be artificially destroyed by introducing constraints, the symmetry between units can be eliminated. To this end, each column of the matrix is ​​regarded as a separate comparison object. Assume that for the jth column of the above matrix, record the number of rows i where the value first appears as 1, that is, And for all If the row number i is smaller, the binary value represented by the corresponding column is larger. Assuming that the number of rows with the value 1 first is the same, the number of rows with the value 1 second is compared. This is similar to the method of converting a binary sequence into a decimal system. Specifically, there is the following relationship:

[0079]

[0080] Wherein, M represents the start-stop conversion value.

[0081] It should be noted that after stipulating the above rules, this paper defines the variable matrix that satisfies the column increasing order as the best, and selects the matrix that satisfies the column increasing order. In this process, the symmetry of the unit has been broken, which can be achieved by the following constraints:

[0082]

[0083] Among them, represents the start-stop conversion value.

[0084] This paper calls this constraint a comparison constraint. The symmetric unit start-stop matrix given in the previous article is Figure 4 .

[0085] However, in the specific implementation process, the present invention gives priority to branching the start-stop instruction variables in the variable selection of branch-bound, and records the variables The value and index (t, g) of the binary matrix. If the branch result is 1, the value in the binary matrix is ​​1, otherwise it is 0. At this time, the column has a corresponding comparison order. By comparing the constraints and continuously selecting the branched binary matrix with increasing columns, the corresponding symmetric solution can be cut off, which reduces the search space and the corresponding solution time, realizes the elimination of the symmetry of the unit combination, and then realizes the accelerated solution of the unit combination.

[0086] Example 2

[0087] Reference Figure 5 , which is an embodiment of the present invention, provides a binary matrix comparison symmetry elimination unit combination acceleration method. In order to verify the beneficial effects of the present invention, scientific demonstration is carried out through economic benefit calculation and simulation experiments.

[0088] First, in order to reflect the improvement of the efficiency of solving the unit combination problem by the method proposed in this patent, the effectiveness of the algorithm is verified by using the example of the IEEE118 standard node system. There are 54 thermal power units in the IEEE118 standard node system, of which 39 units can use the binary matrix comparison method to eliminate symmetry, and at most 15 thermal power units have consistent parameters and their scheduling plans can be exchanged with each other without changing the objective function value. We generated 20 load curves based on the normal operation data of the power grid, and compared the solution efficiency of the original algorithm and after symmetry elimination under each load curve. The final results are as follows: Figure 6 As shown, it can be seen that after the unit symmetry is eliminated, the solution efficiency of each example is improved to a certain extent. The average time taken to solve the unit combination problem using the original algorithm is 10.58 seconds, and the average time taken to solve the unit combination problem after eliminating the unit symmetry using the method proposed in this patent is 7.83 seconds, with an average improvement of 28.36% for the 20 examples.

[0089] Example 3

[0090] An embodiment of the present invention provides a binary matrix comparison symmetry elimination unit combination acceleration method. In order to verify the beneficial effects of the present invention, scientific demonstration is carried out through economic benefit calculation and simulation experiments.

[0091] First, a simulated power system is selected, which includes 100 units distributed in 10 different geographical regions. The units in each region have different technical parameters, such as output range, start-stop time and ramp speed. In addition, there are blocked and non-blocked transmission lines that affect the scheduling between units.

[0092] The purpose of the experiment is to verify the efficiency and effect of the binary matrix comparison method in the invention in eliminating symmetry and optimizing the solution process, and to compare it with the prior art.

[0093] Identify and classify unit symmetry: The experiment first analyzes the historical operating data of the units and uses a clustering algorithm to identify groups of units with similar technical parameters. This step will determine which units can be interchanged in the optimization model without affecting the final results, and thus be marked as symmetrical units in subsequent models.

[0094] Construct symmetric unit start-stop matrices and apply binary matrix comparison: For each set of identified symmetric units, construct a binary matrix to represent the start-stop status of these units at different time periods. Use a custom comparison algorithm to sort and compare the columns of these matrices to ensure that symmetries are eliminated during the solution process. This algorithm specifically considers the order in which the units are first started within a specific time period as the basis for sorting.

[0095] Optimize the decision-making process and speed up the output: After processing the binary matrix, an improved branch-and-bound algorithm is used to prioritize the processing of units with high symmetry. In this way, the number of branches in the solution process can be significantly reduced, speeding up the solution.

[0096] At the same time, a control experimental group was set up, which used the traditional symmetry processing method, namely the aggregation unit method and the method of introducing symmetry breaking constraints.

[0097] Table 1 Experimental results

[0098]

[0099] From the above table, we can observe that the test objects using the invented method are superior to the existing technology in terms of solution time and computing resource consumption. For example, in the area 1 unit group, the solution time of the invented method is 12 seconds, while the existing technology takes 20 seconds; the computing resource consumption is also reduced from 200MB to 150MB. This trend is reflected in all test objects.

[0100] Analyzing these data, it can be found that the invented method significantly improves the solution efficiency through the effective comparison and sorting of binary matrices and the optimized decision-making process. Binary matrix comparison allows accurate identification and processing of symmetries, avoiding repeated calculations of the same unit state during the solution process, which directly affects the utilization efficiency of computing resources and solution time.

[0101] In addition, the inventive method reduces redundant operations in the solution process, such as unnecessary branch generation, without sacrificing the solution quality. This shows that compared with the prior art, the invention not only has an advantage in solution time, but also shows significant improvement in resource utilization efficiency.

[0102] In summary, the present invention achieves better results in terms of solving efficiency, resource consumption and complexity of solving problems.

[0103] Example 4

[0104] Reference Figure 6 , which is an embodiment of the present invention, provides a binary matrix comparison symmetry elimination unit combination acceleration system, including a unit symmetry identification and classification module, a symmetric unit start-stop matrix construction module, and a decision process optimization module.

[0105] The unit symmetry identification and classification module is used to provide premise information for the symmetry elimination strategy by clarifying the symmetry of the units in the power grid. The symmetric unit start-stop matrix construction module is used to destroy the symmetry between units by comparing and sorting the columns of the binary matrix. The decision process optimization module is used to determine the logical state variables of the unit through an improved branching strategy.

[0106] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0107] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0108] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering, or processing in another suitable manner as necessary, and then stored in a computer memory.

[0109] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc. It should be noted that the above embodiments are only used to illustrate the technical solution of the present invention and are not limited. Although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

[0110] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A binary matrix comparison symmetry elimination unit combination acceleration method, characterized in that: include: Identify and classify unit symmetries; Construct a symmetric unit start-stop matrix and apply binary matrix comparison; Optimize decision-making processes and accelerate output.

2. The binary matrix comparison symmetry elimination unit combination acceleration method according to claim 1, characterized in that: The identifying and classifying the unit symmetry includes classifying the transmission lines into blocked lines and non-blocked lines according to the operation history data of the power grid; If only non-blocking lines connect the power plants, the internal parts are considered as non-blocking system areas, and such areas are denoted by Indicates that in each unblocked area, the symmetry between the internal units is determined according to the parameters of the unit The parameters include the unit's ramp rate, output limit, minimum start and stop time, and unit quotation.

3. The binary matrix comparison symmetry elimination unit combination acceleration method as claimed in claim 2, characterized in that: The symmetrical unit start-stop matrix is ​​constructed and the binary matrix is ​​used to compare the unit combination model. The logical states of the units are represented by three 0 / 1 variables, which are the state logic variables of the units. The startup command variable of the unit and shutdown command variables Satisfying the constraints is expressed as: in, The logical variable representing the state of the unit, Indicates the startup command variable of the unit, represents the shutdown command variable, g represents the unit number, and t represents the current scheduling period; The first equality constraint indicates that the logical state of the unit is affected by the start-stop command variable, and according to the second constraint, at the same time t, the sum of the start-stop variables For a 0 / 1 variable use It is expressed as: in, Represents the sum of start and stop variables 4. The binary matrix comparison symmetry elimination unit combination acceleration method as claimed in claim 3, characterized in that: The construction of the symmetric unit start-stop matrix and the application of binary matrix comparison include defining variables, eliminating the symmetry between units with the same parameters, and summing the start-stop instruction variables of the symmetric units. Constructed in matrix form, assuming that there are G units with symmetry, the units have the same parameters, and a total of T scheduling periods are output, the symmetric unit start-stop matrix is ​​expressed as: Among them, u represents the sum of start-stop variables; The size of the symmetric unit start-stop matrix is ​​T×G, which is a binary matrix. The sum of the start-stop variables of the unit satisfies the constraints, and the elements of the symmetric unit start-stop matrix are 1 at some times. The start-stop of the unit will lead to an increase in the start-stop cost of the unit. The direction of minimizing the objective function prompts the start-stop action to be 0. The element value of the symmetric unit start-stop matrix is ​​0, which makes the symmetric unit start-stop matrix sparse.

5. The binary matrix comparison symmetry elimination unit combination acceleration method as claimed in claim 4, characterized in that: The construction of a symmetric unit start-stop matrix and the application of binary matrix comparison include the start-stop instruction variable and unit logic state variables After the start and stop variables of the unit are known, the state logic variables of the unit during the initial scheduling period are calculated. Perform 0 / 1 branch output of the unit's logical state variables, assuming that a column of the symmetrical unit start-stop matrix in the branch is (0101) T , then the unit logic state sequence is expressed as: in, Represents the state logic variable of the unit at the initial moment; After all 0 / 1 variables of the unit are determined, there are no binary variables in the model. All the logical sequence combinations of the unit states are input into the unit combination problem model, and the output plan of the unit is output. The output of the unit is a continuous decision variable. At this time, the unit combination model is transformed into a linear programming problem, and the solution to the linear programming problem is completed in polynomial time. If after generating the symmetric unit start-stop matrix, the unit symmetry is manifested in each column of the matrix, the values ​​of the i-th column and the j-th column of the matrix are mutually replaced, representing the variable sequence u of the corresponding two units i and u j Exchange, according to the equality constraint, the generated unit logic state variable sequence and output plan are also permuted. Since each unit contained in the matrix has the same parameters, the optimal objective function value output after permutation is the same.

6. The binary matrix comparison symmetry elimination unit combination acceleration method according to claim 5, characterized in that: The optimizing decision-making process and accelerating the output include artificially destroying the property of the permutation of each column of the start-stop matrix of the symmetrical unit by introducing constraints, thereby eliminating the symmetry between the units; Treat each column of the matrix as a comparison object. For the jth column of the matrix, record the first row number i where the value is 1. For all If the row number i is negatively correlated with the binary value represented by the column, assuming that the number of rows with the value 1 first is the same, then the number of rows with the value 1 second is compared, which is the same as the method of converting a binary sequence into a decimal system, expressed as: Wherein, M represents the start-stop conversion value.

7. The binary matrix comparison symmetry elimination unit combination acceleration method according to claim 6, characterized in that: The optimization decision process and accelerated output include defining the optimal variable matrix that satisfies the column increasing order, screening out the matrix that satisfies the column increasing order, breaking the symmetry of the unit, and the constraint realization is expressed as: Among them, represents the start-stop conversion value; Branch the start and stop command variables and record the variables The value and index of (t,g); If the branch result is 1, the value in the binary matrix is ​​1, otherwise it is 0. In this case, the comparison order is listed; By comparing constraints and continuously selecting branched binary matrices with increasing columns, the symmetric solutions are removed, the search space and the corresponding solution time are shortened, the symmetry of the unit combination is eliminated, and the accelerated solution of the unit combination is achieved.

8. A system using the binary matrix comparison symmetry elimination unit combination acceleration method as claimed in any one of claims 1 to 7, characterized in that: It includes unit symmetry identification and classification module, symmetric unit start-stop matrix construction module, and decision-making process optimization module; The unit symmetry identification and classification module is used to provide premise information for the symmetry elimination strategy by clarifying the symmetry of the units in the power grid; The symmetric unit start-stop matrix building module is used to destroy the symmetry between units by comparing and sorting the columns of the binary matrix; The decision process optimization module is used to determine the logical state variables of the unit through an improved branching strategy.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the binary matrix comparison symmetry elimination unit combination acceleration method described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the binary matrix comparison symmetry elimination unit combination acceleration method according to any one of claims 1 to 7 are implemented.

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