Display panel and display device

Abstract

The invention discloses a display panel and a display device.The display panel comprises a display area and a non-display area surrounding the display area; the display area comprises a plurality of first reference voltage lines, a plurality of second reference voltage lines and data lines; the data lines extend along a first direction; the non-display area comprises a first reference voltage bus and a second reference voltage bus; the first reference voltage line is electrically connected with the first reference voltage bus; the second reference voltage line is electrically connected with the second reference voltage bus; the first reference voltage bus comprises a first bus section and a second bus section; the non-display area comprises a fan-out area and a first non-display area which are located on the two sides of the display area in the first direction. The non-display area comprises a first bus section and a second bus section; at least part of the first bus section is located in the fan-out area; at least part of the second bus segment is located in the first non-display area. According to the technical scheme, the width of the side edge frame of the display panel is reduced, and the narrow frame design is further achieved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display panel refers to a display panel in which the luminescent material emits light through carrier injection and recombination under the drive of an electric field. Compared with liquid crystal display panels, OLED display panels are thinner and lighter, and have better viewing angles and contrast, etc., so they have attracted widespread attention.

[0003] In the prior art, the fanout in AA (FIAA) technology is used to achieve the narrow frame setting of OLED. Specifically, metal in the row and column directions is added in the display area as FIAA wiring, and connected to each other through the wiring holes, so that the fanout wiring of the original lower R corner of the display panel is changed to be led out from the display area, reducing the space of the lower R corner and the lower frame, and realizing the narrow frame design. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device to reduce the width of a side frame of the display panel and further achieve a narrow frame design.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, comprising: a display area and a non-display area surrounding the display area;

[0006] The display area includes a plurality of first reference voltage lines, a plurality of second reference voltage lines and data lines; the data lines extend along a first direction;

[0007] The non-display area includes a first reference voltage bus and a second reference voltage bus; the first reference voltage line is electrically connected to the first reference voltage bus; the second reference voltage line is electrically connected to the second reference voltage bus;

[0008] The first reference voltage bus includes a first bus segment and a second bus segment;

[0009] The non-display area includes a fan-out area and a first non-display area located at both sides of the display area along the first direction; at least part of the first bus segment is located in the fan-out area; at least part of the second bus segment is located in the first non-display area.

[0010] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display panel provided by any embodiment of the present invention.

[0011] In the present invention, the display area of ​​the display panel is provided with a first reference voltage line, a second reference voltage line and a data line extending along a first direction, and the non-display area of ​​the display panel includes a first reference voltage bus and a second reference voltage bus. The first reference voltage bus is used to transmit the first reference voltage to the first reference voltage line, and the second reference voltage bus is used to transmit the second reference voltage to the second reference voltage line. Among them, the first reference voltage bus includes a first bus segment and a second bus segment, and the fan-out area and the first non-display area are respectively provided on opposite sides of the display area along the first direction, at least part of the first bus segment is provided in the fan-out area, and at least part of the second bus segment is provided in the first non-display area. Because the buses of the first reference voltage, the second reference voltage and other signals are all provided in the same layer, in this embodiment, the first reference voltage bus is provided in the lower frame where the fan-out area is located and the upper frame where the first non-display area is located, and does not occupy the plane area of ​​the side frame connecting the upper frame and the lower frame, leaving layout space for the bus of other signals, reducing the resistance value of the bus of other signals, and further realizing the narrow frame design of the side frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a structural schematic diagram of a display panel in the prior art;

[0013] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0014] Figure 3 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0015] Figure 4 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0016] Figure 5 for Figure 4 The middle part shows a schematic diagram of the enlarged structure of a local area B1 in the display panel;

[0017] Figure 6 for Figure 4 Another partial structural schematic diagram of the local area B1;

[0018] Figure 7 for Figure 4 Another partial structural schematic diagram of the local area B1;

[0019] Figure 8 for Figure 4 Another partial structural schematic diagram of the local area B1;

[0020] Fig. 9 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0021] Fig.10 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0022] Fig.11 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0023] Fig.12 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0024] Fig.13 for Figure 4 Another partial structural schematic diagram of the local area B1;

[0025] Fig.14 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0026] Fig.15 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0027] Fig.16 A schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0028] Fig.17 A schematic structural diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0029] Fig.18 A schematic structural diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0030] Fig.19 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0031] Fig. 20 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0033] In order to realize the narrow frame design of the display panel in the prior art, the fanout line is located in the display area (fanout inAA, FIAA) technology is adopted to lead the fanout line of the original lower frame of the display panel out of the display area, thereby reducing the width of the lower frame. In the process of realizing the present invention, the inventor found that the side frame width of the display panel is relatively large, which is not conducive to the design of a narrow frame. Figure 1 As shown, Figure 1 It is a schematic diagram of the structure of the display panel in the prior art. The non-display area NA' of the display panel includes a plurality of buses arranged around the display area AA'. Each bus outputs a corresponding signal to the display area AA'. For example, buses BUS1' and BUS2' for outputting reference voltages, and BUS3' for outputting power signals. Along the Y' direction, side frames are arranged on opposite sides of the display area AA', wherein the side on which the binding area 12' is arranged is the lower frame. Along the X' direction, left and right frames are arranged on opposite sides of the display area AA'. The inventor further discovered that the lower frame of the prior art solution needs to be designed with FIAA and fan-out routing, so the buses BUS1', BUS2' and BUS3' are all arranged on the side frames, and many driving circuits are usually arranged in the side frames of the display panel. The above-mentioned buses occupy more space of the side frames, which is not conducive to the narrow frame design of the side frames.

[0034] In order to reduce the width of the side frame of the display panel and further realize the narrow frame design of the side frame, an embodiment of the present invention provides a display panel, Figure 2 A schematic structural diagram of a display panel provided in an embodiment of the present invention includes: a display area AA and a non-display area NA surrounding the display area AA;

[0035] The display area AA includes a plurality of first reference voltage lines 11, a plurality of second reference voltage lines 12 and a data line 23; the data line 23 extends along a first direction Y;

[0036] The non-display area NA includes a first reference voltage bus 13 and a second reference voltage bus 14; the first reference voltage line 11 is electrically connected to the first reference voltage bus 13; the second reference voltage line 12 is electrically connected to the second reference voltage bus 14;

[0037] The first reference voltage bus 13 includes a first bus segment 131 and a second bus segment 132;

[0038] The non-display area NA includes a fan-out area 15 and a first non-display area NA1 located at both sides of the display area AA along the first direction Y; at least part of the first bus segment 131 is located in the fan-out area 15; at least part of the second bus segment 132 is located in the first non-display area NA1.

[0039] In an embodiment of the present invention, a display area of ​​a display panel is provided with a first reference voltage line, a second reference voltage line and a data line extending along a first direction, and a non-display area of ​​the display panel includes a first reference voltage bus and a second reference voltage bus. The first reference voltage bus is used to transmit a first reference voltage to the first reference voltage line, and the second reference voltage bus is used to transmit a second reference voltage to the second reference voltage line. Among them, the first reference voltage bus includes a first bus segment and a second bus segment, and a fan-out area and a first non-display area are respectively provided on opposite sides of the display area along the first direction, at least part of the first bus segment is located in the fan-out area, and at least part of the second bus segment is located in the first non-display area. In this embodiment, the first reference voltage bus is provided at the lower frame where the fan-out area is located and the upper frame where the first non-display area is located, and does not occupy the plane area of ​​the side frame connecting the upper frame and the lower frame, leaving layout space for the bus of other signals, reducing the resistance value of the bus of other signals, and further realizing the narrow frame design of the side frame.

[0040] The above is the core idea of ​​the present invention. The technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] The display panel includes a substrate and a driving circuit layer disposed on one side of the substrate. The display panel includes a display area AA and a non-display area NA, and the non-display area NA is disposed around the display area AA. The display area AA is provided with data lines 23 extending along a first direction Y, wherein the first direction Y is a direction parallel to the plane where the substrate of the display panel is located. The display area AA of the driving circuit layer also includes a pixel driving circuit ( Figure 2 The driving circuit layer further includes a light-emitting element on the side away from the substrate, and the pixel driving circuit is used to output a driving current to the light-emitting element so that the light-emitting element emits light. The data line 23 is used to provide a data signal to the pixel driving circuit.

[0042] The display area AA further includes a first reference voltage line 11 and a second reference voltage line 12. The first reference voltage line 11 is electrically connected to a first reference voltage bus 13, and receives a first reference voltage signal vref1. The first reference voltage line 11 is also used to transmit the first reference voltage signal vref1 to the pixel driving circuit. The second reference voltage line 12 is electrically connected to a second reference voltage bus 14, and receives a second reference voltage signal vref2. The second reference voltage line 12 is also used to transmit the second reference voltage signal vref2 to the pixel driving circuit.

[0043] Continue to refer Figure 2, along the first direction Y, the fan-out area 15 and the first non-display area NA1 are respectively arranged on opposite sides of the display area AA. The fan-out area 15 is arranged in the lower step area of ​​the display panel. In the lower step area, a binding area 151 is also arranged on the side of the fan-out area 15 away from the display area AA. The binding area 151 is used to bind the driver chip. The pad terminal of the driver chip is electrically connected to the data line 23 through the fan-out trace in the fan-out area 15, and is used to output a signal to the corresponding data line 23. The first reference voltage bus 13 at least includes a first bus segment 131 and a second bus segment 132, then at least a portion of the first bus segment 131 is arranged in the fan-out area 15, and at least a portion of the second bus segment 132 is arranged in the first non-display area NA1. The fan-out area 15 and the first non-display area NA1 are connected through the side non-display area. Compared with the case where the first reference voltage bus 13 and the second reference voltage bus 14 are both set in the side non-display area, the first reference voltage bus 13 is set in the first non-display area NA1 and the fan-out area 15 in this embodiment. That is, the first reference voltage bus 13 is set in the upper frame and the lower frame in this embodiment, which can effectively save the width of the side non-display area and realize the narrow frame design of the side frame of the display panel. In addition, because the present embodiment can also combine the FIAA technology to reduce the width of the lower frame occupied by the fan-out wiring, reduce the width of the fan-out area 15 along the first direction Y, and realize the narrow frame design of the lower frame of the display panel, the present embodiment can simultaneously realize the narrowing design of the side frame and the lower frame, improve the screen ratio of the display area of ​​the entire display panel, and improve the picture display effect.

[0044] Optionally, the first reference voltage vref1 is a reset signal provided to the pixel circuit, for example, a reset signal of a control terminal of a driving transistor in a pixel driving circuit, or a reset signal of a light emitting element, which is not particularly limited in this embodiment.

[0045] Figure 3 A structural schematic diagram of another display panel provided in an embodiment of the present invention, optionally, the non-display area NA may also include a second non-display area NA2 and a third non-display area NA3 located on both sides of the display area AA along the second direction X; the second direction X intersects with the first direction Y; the first non-display area NA1 is respectively arranged adjacent to the second non-display area NA2 and the third non-display area NA3; the second reference voltage bus 14 includes at least a third bus segment 141 and a fourth bus segment 142; at least a portion of the third bus segment 141 is located in the second non-display area NA2; at least a portion of the fourth bus segment 142 is located in the third non-display area NA3.

[0046] like Figure 3As shown, in this embodiment, along the first direction Y, the first non-display area NA1 and the fan-out area 15 are arranged on opposite sides of the display area AA; along the second direction X, the second non-display area NA2 and the third non-display area NA3 are arranged on opposite sides of the display area AA. Among them, the first non-display area NA1 is arranged adjacent to the second non-display area NA2 and the third non-display area NA3 respectively; the fan-out area 15 is arranged adjacent to the second non-display area NA2 and the third non-display area NA3 respectively. In this embodiment, the second direction X and the first direction Y are in an intersecting relationship, and optionally, the second direction X and the first direction Y can be perpendicular to each other.

[0047] The second reference voltage bus 14 may include a third bus segment 141 and a fourth bus segment 142. At least a portion of the third bus segment 141 is disposed in the second non-display area NA2, and at least a portion of the fourth bus segment 142 is disposed in the third non-display area NA3. In this embodiment, the first bus segment 131 of the first reference voltage bus 13 is located in the fan-out area 15, and the second bus segment 132 is located in the first non-display area NA1; the third bus segment 141 of the second reference voltage bus 14 is located in the second non-display area NA2, and the fourth bus segment 142 is located in the third non-display area NA3. That is, the first reference voltage bus 13 is arranged in the non-display areas on both sides of the display panel along the first direction Y, and the second reference voltage bus 14 is arranged in the non-display areas on both sides of the display panel along the second direction X. The first reference voltage bus 13 and the second reference voltage bus 14 are not arranged side by side in the same non-display area, so that the fan-out area 15, the first non-display area NA1, the second non-display area NA2 and the third non-display area NA3 are not occupied by multiple parallel buses, and the setting width of the non-display area is reduced, so as to further realize the narrow frame design of the display panel. Figure 1 As shown in the scheme, this embodiment sets the first reference voltage bus 13 on the upper frame and the lower frame, effectively reducing the space occupied by the side frame, facilitating the wiring and setting of the second reference voltage bus 14 on the side frame, reducing the transmission resistance of the second reference voltage bus 14, and effectively reducing the overlap of signal lines on the side frame, thereby optimizing the transmission performance of each signal line.

[0048] Continue to refer Figure 3 Optionally, adjacent non-display areas NA may be connected via R corner areas 16. To enhance the use and viewing experience of the display panel, the display panel of this embodiment may be a rounded corner screen, specifically, Figure 3 As shown, two adjacent non-display areas NA can be connected by an R angle area 16. For example, the first non-display area NA1 and the second non-display area NA2 are connected by the R angle area 16. The R angle area 16 is set so that the display panel forms a rounded rectangular plane. The display panel with a curved portion at the edge of the screen is not only beautiful but also not easily damaged, while the display panel with a right angle is easily damaged by force during use.

[0049] like Figure 3 As shown, optionally, the first non-display area NA1 and the second non-display area NA2 may be connected via the first R-angle region 161; the first non-display area NA1 and the third non-display area NA3 may be connected via the second R-angle region 162; the second bus segment 132 includes a first portion 1311 located in the first R-angle region 161 and / or a second portion 1312 located in the second R-angle region 162. Optionally, the second bus segment 132 may be partially disposed in the first non-display area NA1, or entirely disposed in the first non-display area NA1. Figure 3 Taking the second bus segment 132 partially disposed in the first non-display area NA1 as an example for illustration. Since two adjacent non-display areas NA are connected via the R corner area 16, in order to further extend the length of the second bus segment 132 and optimize the resistance of the first reference voltage bus 13, the second bus segment 132 may be extended to the R corner areas 16 on both sides of the first non-display area NA1. Specifically, Figure 3 As shown, the first R angle area 161 and the second R angle area 162 are arranged on both sides of the first non-display area NA1, the part of the second bus segment 132 extending to the first R angle area 161 may be the first part 1311, and the part of the second bus segment 132 extending to the second R angle area 162 may be the second part 1312. In this embodiment, the second bus segment 132 may include at least one of the first part 1311 and the second part 1312. On the one hand, in this embodiment, the first reference voltage bus 13 and the second reference voltage bus 14 are respectively arranged in different non-display areas, thereby reducing the frame width, especially the width of the side frame; on the other hand, in this embodiment, the second bus segment 132 in the first non-display area NA1 is extended to the R angle area 16, which can effectively increase the length of the first reference voltage bus 13, so as to directly provide the first reference voltage signal vref1 to more first reference voltage lines 11, instead of transmitting the first reference voltage signal vref1 to each other through other first reference voltage lines 11, which is conducive to reducing the voltage drop of the first reference voltage signal vref1 on the first reference voltage line 11 and improving the power supply effect of the first reference voltage bus 13 on the pixel driving circuit. It can be understood that the display area of ​​the display panel including the R corner area will usually be set corresponding to the shape of the R corner area, that is, the R corner area will also correspond to a part of the pixel driving circuit, and extending the second bus segment 132 of the first non-display area NA1 to the R corner area 16 can make the pixel driving circuits in the display area all connected to the second bus segment 132, thereby improving the power supply effect of the first reference voltage line 11.

[0050] Continue to refer Figure 3Optionally, the fan-out area 15 and the second non-display area NA2 may be connected via the third R-angle area 163; the fan-out area 15 and the third non-display area NA3 may be connected via the fourth R-angle area 164; the first bus segment 131 includes a third portion 1313 located in the third R-angle area 163 and / or a fourth portion 1314 located in the fourth R-angle area 164. Similarly, the first bus segment 131 may be partially disposed in the fan-out area 15, or entirely disposed in the fan-out area 15. Figure 3 Taking the first bus segment 131 partially disposed in the fan-out area 15 as an example for illustration. In order to further extend the length of the first bus segment 131 and optimize the resistance of the first reference voltage bus 13, the first bus segment 131 may be extended to the R corner area 16 on both sides of the first non-display area NA1. Specifically, Figure 3 As shown, the third R angle region 163 and the fourth R angle region 164 are provided on both sides of the fan-out region 15, the first bus segment 131 can be extended to the third R angle region 163 to form a third part 1313, and the first bus segment 131 can also be extended to the fourth R angle region 164 to form a fourth part 1314, or the first bus segment 131 can also be extended to the third R angle region 163 and the fourth R angle region 164 respectively to form the third part 1313 and the fourth part 1314. In this embodiment, the first bus segment 131 in the fan-out region 15 is extended to the R angle region 16, which can effectively increase the length of the first reference voltage bus 13, facilitate the provision of the first reference voltage signal vref1 to more first reference voltage lines 11, and improve the power supply effect of the first reference voltage bus 13 on the pixel driving circuit. It can be understood that the display area of ​​the display panel including the R corner area will usually be set corresponding to the shape of the R corner area, that is, the R corner area will also correspond to a part of the pixel driving circuit. Extending the first bus segment 131 of the fan-out area 15 to the R corner area 16 can make the pixel driving circuits in the display area all connected to the first bus segment 131 and its extended segment (the third part 1313 and / or the fourth part 1314), thereby improving the power supply effect of the first reference voltage line 11.

[0051] Figure 4 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Figure 5 for Figure 4 A partial structural diagram of the local area B1 in FIG. Optionally, the display area AA may include pixel driving circuits 18 arranged in an array; the display area AA includes a first shaped area 17; the first shaped area 17 is adjacent to the R-angle area 16, and the plurality of pixel driving circuits 18 in the first shaped area 17 are distributed in a stepped manner; the first bus segment 131 and the second bus segment 132 extend along the edge of the first shaped area 17.

[0052] like Figure 4As shown, the display area AA includes a pixel driving circuit 18 arranged in an array. The display area AA also includes a first reference voltage line 11 extending along the first direction Y and / or along the second direction X, and a second reference voltage line 12 extending along the first direction Y and / or along the second direction X. The first reference voltage line 11 and the second reference voltage line 12 intersect to define an area where the pixel driving circuit 18 can be set. Exemplarily, Figure 4 The display panel includes a first reference voltage line 11 extending along the first direction Y and along the second direction X, and a second reference voltage line 12 extending along the first direction Y and along the second direction X. To facilitate distinguishing the first reference voltage line 11 from the second reference voltage line 12, the present embodiment uses a solid line to represent the first reference voltage line 11 and a dotted line to represent the second reference voltage line 12.

[0053] According to the above embodiment, adjacent non-display areas are adjacent to each other through the R angle area 16, and the portion of the display panel adjacent to the display area AA and the R angle area 16 is also a special-shaped structure, such as Figure 4 As shown, the display area AA includes a first profiled area 17, and the first profiled area 17 is adjacent to the R corner area 16. Figure 5 As shown, Figure 5 for Figure 4 Schematic diagram of the enlarged structure of the local area B1 in the display panel. It should be noted that the local area B1 intercepts part of the structure of the first profiled area 17 and part of the R corner area 16, so as to clearly obtain the structure of the display panel at the junction of the first profiled area 17 and the R corner area 16. Figure 5 As shown, in the first profiled area 17, the pixel driving circuits 18 are distributed in a stepped manner along the extension direction of the first reference voltage line 11. Because the portion of the first reference voltage line 11 extending to the R angle area 16 is a curve, the pixel driving circuits 18 are arranged in a stepped manner. If the pixel driving circuits 18 are arranged in rows along the second direction Y, the number of pixel driving circuits 18 in each row gradually decreases along the first direction Y, so that the edge of the first profiled area 17 is arranged in a stepped manner. Figure 5 As shown, Figure 5 Only part of the metal film layer of the driving circuit layer is shown, and it specifically shows two metal layers, wherein one metal layer is a film layer for setting the first reference voltage line 11. In this embodiment, the portion of the second bus segment 132 extending to the R corner area 16 can be set along the edge of the first special-shaped area 17, that is, the second bus segment 132 in the R corner area 16 is also stepped. The stepped second bus segment 132 can be set close to the edge of the first special-shaped area 17, effectively saving the space in the R corner area 16 occupied by the second bus segment 132, making it easier for the R corner area 16 to leave layout space for other circuits and wirings, and reducing the width of the R corner area 16, further realizing the narrow frame design of the R corner area 16. As shown Figure 4 and Figure 5 As shown in FIG. 1 , the portion of the second bus segment 132 extending to the first R corner region 161 is the first portion 1311, and the first portion 1311 is arranged along the pixel driving circuit 18 arranged in a stepped manner. Figure 4 As shown, the portion of the first bus segment 131 extending to the R-angle region 16 may also extend along the edge of the first special-shaped region 17, and the first bus segment 131 is also arranged in a stepped manner in the R-angle region 16, so that the first bus segment 131 and the pixel circuits corresponding to the R-angle region 16 can be electrically connected, and at the same time, the space utilization rate is higher, the space occupied by the R-angle region 16 is reduced, and the narrow frame design of the display panel is further realized.

[0054] Continue to refer Figure 3 and Figure 4 Optionally, the third bus segment 141 and the fourth bus segment 142 may extend along the edge of the first profiled area 17. In this embodiment, the third bus segment 141 may be provided only in the second non-display area NA2, or may extend from the second non-display area NA2 to the R corner area 16. Figure 3 As shown, the second non-display area NA2 is adjacent to the first R angle area 161 and the third R angle area 163 respectively, and the third bus segment 141 can extend to the first R angle area 161 and / or the third R angle area 163, increasing the length of the third bus segment 141, so that the third bus segment 141 can connect more second reference voltage lines 12, thereby directly providing the second reference voltage signal vref2 for more second reference voltage lines 12, rather than transmitting the second reference voltage signal vref2 to each other through other second reference voltage lines 12. This is beneficial to reducing the voltage drop of the second reference voltage signal vref2 on the second reference voltage line 12, and improving the power supply effect of the second reference voltage bus 14 on the pixel driving circuit. Similarly, the fourth bus segment 142 can extend to the second R corner area 162 and / or the fourth R corner area 164, increasing the length of the fourth bus segment 142 so that the fourth bus segment 142 can connect more second reference voltage lines 12, reduce the voltage drop of the second reference voltage signal vref2 on the second reference voltage line 12, and enhance the power supply effect of the second reference voltage bus 14 on the pixel driving circuit.

[0055] Figure 6 for Figure 4 When the display area adjacent to the R-angle area 16 includes the first profiled area 17, and the edge of the first profiled area 17 includes the pixel driving circuit 18 arranged in a staircase shape, the portion of the third bus segment 141 and the fourth bus segment 142 extending to the R-angle area 16 can extend along the edge of the first profiled area 17, that is, the pixel driving circuit 18 arranged in a staircase shape. For example, Figure 6As shown, the portion of the third bus segment 141 extending to the first R corner region 161 is formed in a step shape, and the portion of the second bus segment 132 extending to the first R corner region 161 is also in a step shape. In this embodiment, the first reference voltage bus 13 and the second reference voltage line 12 are arranged in a step shape in the R corner region 16, further reducing the area occupied by the above-mentioned bus in the R corner region 16, reducing the border width of the R corner region 16, and further realizing the narrow border design of the R corner region 16.

[0056] Figure 7 for Figure 4 Another partial structural schematic diagram of the local area B1 in FIG. Figure 8 for Figure 4 Another partial structural diagram of the local area B1 in the middle. Optionally, the display panel may further include: a shielding bus 19; the shielding bus 19 extends along the edge of the first shaped area 17; in the first shaped area 17, the shielding bus 19 includes a linear first bus 191 and a stepped second bus 192; the first reference voltage bus 13 in the first shaped area 17 includes a plurality of first stage stages 133 extending along the first direction Y and a second stage stage 134 extending along the second direction X; the stepped second bus 192 in the first shaped area 17 includes a plurality of third stage stages 193 extending along the first direction Y and a fourth stage stage 194 extending along the second direction X; there is an overlapping area between the second stage stage 134 and the fourth stage stage 194.

[0057] In this embodiment, a shielding layer M0 may be provided between the substrate and the driving circuit layer. In a plane parallel to the substrate, the shielding layer M0 and the active layer 18a of the driving transistor in the pixel driving circuit overlap in an area, thereby preventing the driving transistor from generating leakage current. In addition, a fixed potential needs to be applied to the shielding layer to prevent the shielding layer from floating, thereby preventing the shielding layer from affecting other metal layers. Figure 7 As shown, Figure 7 Only two film layers, the shielding layer and the active layer 18a, are shown. In this embodiment, a shielding bus 19 can also be formed on the shielding layer. The shielding bus 19 can be arranged around the display area. In the first shaped area 17, the shielding bus 19 includes a linear first bus 191 and a stepped second bus 192. Among them, the linear first bus 191 is arranged linearly along the edge of the first shaped area 17, and the stepped second bus 192 includes a third stage 193 extending along the first direction Y and a fourth stage 194 extending along the second direction X. The third stage 193 and the fourth stage 194 are alternately connected to form a step shape. The first bus 191 and the stepped second bus 192 are electrically connected to form a bus as a whole. In this embodiment, the shielding bus 19 can be set to the shielding layer M0 corresponding to the pixel driving circuit of multiple rows at multiple connection ends at the same time, reduce the resistance value of the shielding layer M0, and reduce the voltage drop (IR drop) of the shielding layer M0.

[0058] Continue to refer Figure 8 , Figure 8 It only includes the shielding layer M0 and the metal layer M3 provided with the first reference voltage bus 13. In the first profiled area 17, the first reference voltage bus 13 includes multiple first stage stages 133 extending along the first direction Y and second stage stages 134 extending along the second direction X. The first stage stages 133 and the second stage stages 134 are alternately connected to form a step shape (step shape). Because the first reference voltage bus 13 and the shielding bus 19 are located in different film layers, in a plane parallel to the substrate, the fourth stage stage 194 of the stepped second bus 192 extending along the second direction X has an overlapping area B2 with the second stage stage 134 of the first reference voltage bus 13 extending along the second direction X. The design of the overlapping area B2 can improve the utilization rate of the planar space and save the space of the R corner area in the plane parallel to the substrate. The first reference voltage bus 13 overlaps with the shielding bus 19, which can improve the transmission effect and stability of the first reference voltage signal on the first reference voltage bus 13, so that the pixel driving circuit is completely reset in the reset stage without affecting the conduction of the pixel driving circuit in the next frame time, thereby enhancing the reliability of the pixel driving circuit and improving the picture display effect of the display panel.

[0059] Fig. 9 A schematic diagram of another display panel structure provided by an embodiment of the present invention, optionally, the first reference voltage bus 13 may further include: a fifth bus segment 135; the fifth bus segment 135 is located in the second non-display area NA2. In this embodiment, the first reference voltage bus 13 may also be provided on a side frame, such as Fig. 9 As shown, a fifth bus segment 135 may be provided in the second non-display area NA2. Optionally, the second bus segment 132, the fifth bus segment 135 and the first bus segment 131 are electrically connected in sequence to extend the total length of the first reference voltage bus 13. In this embodiment, the side frame where the third non-display area NA3 is located is not provided with the first reference voltage bus 13. In this embodiment, while ensuring that the width of the side frame is reduced, the first reference voltage bus 13 is extended to the second non-display area NA2 to connect the first reference voltage lines corresponding to more rows of pixel driving circuits, reduce the loss of the first reference voltage lines during the transmission process, improve the reliability of the pixel driving circuit, and thus improve the reliability of the entire display panel.

[0060] Fig.10A schematic diagram of another display panel structure provided by an embodiment of the present invention, optionally, the first reference voltage bus 13 may further include: a sixth bus segment 136; the sixth bus segment 136 is located in the third non-display area NA3. In this embodiment, the sixth bus segment 136 is also formed in the third non-display area NA3, and optionally, the second bus segment 132, the fifth bus segment 135, the first bus segment 131 and the sixth bus segment 136 can be electrically connected in sequence, effectively extending the first reference voltage bus 13, and the first reference voltage lines corresponding to more rows of pixel driving circuits can be connected through multiple connection terminals, reducing the loss of the first reference voltage lines during transmission, improving the reliability of the pixel driving circuit, and thus improving the reliability of the entire display panel. Optionally, along the second direction X, the width d1 of the fifth bus segment 135 can be smaller than the width d2 of the third bus segment 141; the width d3 of the sixth bus segment 136 can be smaller than the width d4 of the fourth bus segment 142. In order to further reduce the space of the side frame occupied by the first reference voltage bus 13, in this embodiment, the width d1 of the fifth bus segment 135 can be set to be smaller than the width d2 of the third bus segment 141, and the width d3 of the sixth bus segment 136 can be smaller than the width d4 of the fourth bus segment 142. Then, the width of the first reference voltage bus 13 in the second non-display area NA2 and the third non-display area NA3 is smaller than the width of the second reference voltage bus 14 in the second non-display area NA2 and the third non-display area NA3. In this embodiment, although the first reference voltage bus 13 and the second reference voltage bus 14 are set at the side frame at the same time, the first reference voltage bus 13 is smaller in width and occupies a smaller width of the side frame, which is conducive to the narrow frame design of the side frame of the display panel.

[0061] Optionally, the first bus segment 131, the fifth bus segment 135, the second bus segment 132 and the sixth bus segment 136 can be connected in sequence to form a ring. In this embodiment, the first bus segment 131, the fifth bus segment 135, the second bus segment 132 and the sixth bus segment 136 can be set separately, and each of the first bus segment 131, the fifth bus segment 135, the second bus segment 132 and the sixth bus segment 136 outputs the first reference voltage signal to the first reference voltage line separately, which can also increase the length of the first reference voltage bus and reduce the loss of the first reference voltage signal during transmission. In this embodiment, the first bus segment 131, the fifth bus segment 135, the second bus segment 132 and the sixth bus segment 136 can be connected to form a ring. When the first reference voltage signal is input to the first reference voltage bus 13, only one input terminal can be set, and there is no need to set input terminals for the first bus segment 131, the fifth bus segment 135, the second bus segment 132 and the sixth bus segment 136 respectively, which simplifies the wiring design and further reduces the width of each frame.

[0062] Fig.11A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention, optionally, the first reference voltage bus 13 and the second reference voltage bus 14 can be located in different film layers; the fifth bus segment 135 and the third bus segment 141 at least partially overlap; and / or the sixth bus segment 136 and the fourth bus segment 142 at least partially overlap. Fig.11 As shown, the display panel includes a substrate 100 and a driving circuit layer 101 arranged on one side of the substrate 100. In the display area AA, the driving circuit layer 101 includes pixel driving circuits arranged in an array, and each pixel driving circuit includes a plurality of thin film transistors T. In the non-display area NA, the first reference voltage bus 13 and the second reference voltage bus 14 can be located in different metal layers. Then, when the first reference voltage bus 13 is provided with a fifth bus segment 135 and a sixth bus segment 136, the first reference voltage bus 13 and the second reference voltage bus 14 can be at least partially overlapped, thereby reducing the occupation of the planar space of the side frame, improving the planar space utilization of the display panel, and facilitating the narrow frame design of the side frame of the display panel. For example, as Fig.11 As shown, the driving circuit layer 101 may include a shielding layer M0, an active layer 18a, a gate layer 102, an intermediate metal layer 103, a source-drain layer 104, and a third metal layer M3 and a fourth metal layer M4, which are sequentially away from the substrate 100. Among them, the first reference voltage bus 13 may be set in the fourth metal layer M4, and the second reference voltage bus 14 may be set in the third metal layer M3. Then, in a plane parallel to the substrate 100, the fifth bus segment 135 and the third bus segment 141 may have an overlapping area, and the sixth bus segment 136 and the fourth bus segment 142 may also have an overlapping area. In addition, as Fig.11 As shown, the display area AA also includes a data line 11 arranged at the same layer as the second reference voltage bus 14, and the data line 11 is electrically connected to the source or drain of the thin film transistor T. The display area AA also includes an auxiliary wiring 61 arranged at the same layer as the first reference voltage bus 13. The auxiliary wiring 61 is the FIAA wiring, which is used to transfer the fan-out line of the data line near the R corner area to the display area AA.

[0063] Optionally, the first reference voltage bus 13 and the second reference voltage bus 14 may be arranged in the same layer. It is understandable that the first reference voltage bus 13 and the second reference voltage bus 14 may be arranged in the same layer, for example, the first reference voltage bus 13 and the second reference voltage bus 14 may both be arranged in the third metal layer M3. In order to reduce the plane space occupied by the first reference voltage bus 13 and the second reference voltage bus 14, the width of a part of the bus segment of the first reference voltage bus 13 may be controlled to be smaller than the width of the second reference voltage bus 14, so as to realize the narrow frame design of the display panel and enhance the user viewing experience.

[0064] Continue to refer Figure 3Optionally, the first reference voltage line 11 may include a first connection line 111 extending along the first direction Y and a second connection line 112 extending along the second direction X; the first connection line 111 is electrically connected to the second connection line 112; the second reference voltage line 12 includes a third connection line 121 extending along the first direction Y and a fourth connection line 122 extending along the second direction X; the third connection line 121 is electrically connected to the fourth connection line 122; the first connection line 111 is respectively connected to the first bus segment 131 and the second bus segment 132; the fourth connection line 122 is respectively connected to the third bus segment 141 and the fourth bus segment 142.

[0065] In this embodiment, the first reference voltage line 11 may form a grid structure in the display area. Specifically, the first reference voltage line 11 includes a first connection line 111 extending in a first direction Y and a second connection line 112 extending in a second direction X. Figure 3 As shown, at the intersection of the first connection line 111 and the second connection line 112, the first connection line 111 and the second connection line 112 can be electrically connected through a via hole. Similarly, the second reference voltage line 12 can also form a grid structure in the display area, specifically including a third connection line 121 extending in the first direction Y and a fourth connection line 122 extending in the second direction X, and the third connection line 121 and the fourth connection line 122 are electrically connected through a via hole.

[0066] In this embodiment, because the first reference voltage bus 13 is provided in the fan-out area 15 and the first non-display area NA1, the first connection line 111 extending along the first direction Y is respectively connected to the first bus segment 131 and the second bus segment 132, obtains the first reference voltage signal vref1 and transmits it to the second connection line 112. Similarly, the second reference voltage line 12 is provided in the second non-display area NA2 and the third non-display area NA3, and the fourth connection line 122 extending along the second direction X is respectively connected to the third bus segment 141 and the fourth bus segment 142, obtains the second reference voltage signal vref2 and transmits it to the third connection line 121. It should be noted that, because the length of the upper and lower frames is smaller than the width of the side frames, that is, the length of the fan-out area 15 and the first non-display area NA1 is smaller, the bus branch 137 can be set in the non-display area NA in this embodiment. In this embodiment, the first reference voltage signal vref1 is transmitted to the bus branch 137 through multiple input terminals, and the bus branch 137 is connected to each first connection line 111 nearby, thereby improving the power supply capacity of the first reference voltage bus 13 for driving the pixel circuit. In addition, if Figure 2 As shown, the first reference voltage line 11 may only include a first connection line 111 extending along the first direction Y, and the second reference voltage line 12 may only include a fourth connection line 122 extending along the second direction X, so as to reduce the wiring density of the display area.

[0067] Fig.12A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Fig.12 The structures of the first reference voltage line 11 and the second reference voltage line 12 are omitted, and only the power line is shown separately. Optionally, the display area AA may also include: a first power line 21 and a second power line 22 extending along the second direction X; the non-display area NA also includes a first power bus 25 and a second power bus 24; the first power bus 25 is connected to the first power line 21; the second power bus 24 is connected to the second power line 22; the first power bus 25 includes a portion located in the second non-display area NA2 and the third non-display area NA3 and a portion extending to the R corner area 16; and / or, the second power bus 24 includes a portion located in the second non-display area NA2 and the third non-display area NA3 and a portion extending to the R corner area 16.

[0068] The buses in the non-display area NA include, in addition to the first reference voltage bus 13 and the second reference voltage bus 14, a first power bus 25 and a second power bus 24. For example, Fig.12 As shown, in the direction away from the display area AA, the buses in the non-display area NA are sequentially provided with a reference voltage bus 13, a second reference voltage bus 14, a first power bus 25 and a second power bus 24. Among them, the first power bus 25 may include a portion located in the second non-display area NA2 and the third non-display area NA3 and a portion extending to the R corner area 16. Similarly, the second power bus 24 may also include a portion located in the second non-display area NA2 and the third non-display area NA3 and a portion extending to the R corner area 16. The display area AA is provided with a first power line 21 and a second power line 22, both of which extend along the second direction X. The first power line 21 is used to obtain a first power signal PVDD from the first power bus 25 and transmit it to each pixel driving circuit, and the second power line 22 obtains a second power signal PVEE from the second power bus 24 and transmits it to each pixel driving circuit. This embodiment shows a situation where there are many types of buses, and the various types of buses are often set in the third metal layer M3. When there are many buses, the first reference voltage bus 13 is only set in the fan-out area 15 and the first non-display area NA1, occupying the area of ​​the upper and lower frames, and the remaining buses are set in the second non-display area NA2 and the third non-display area NA3, occupying the space of the side frames. This embodiment effectively balances the bus settings of each frame, so that on the whole, the frame width of the display panel is smaller, realizing the user's narrow frame demand.

[0069] In addition, the display panel may further include a first power line 21 and a second power line 22 extending along the second direction Y. Then, the first power line 21 and the second power line 22 may both form a grid shape. Fig.13 for Figure 4 Another partial structural diagram of the local area B1 in FIG. Fig.13As shown, the second power bus 24 can form a linear second power bus 241 and a stepped second power bus 242 in the first irregular region 17 to reduce the resistance of the second power bus 24, thereby reducing the loss of the second power signal PVEE during the transmission process. Similarly, the first power bus 25 can also be a combination of the above-mentioned linear and stepped shapes to improve the signal transmission effect of the first power signal PVDD.

[0070] Fig.14 A schematic diagram of the structure of another display panel provided in an embodiment of the present invention, optionally, the display panel may include: a touch line 106 connected to a touch electrode 105; a fan-out area 15 including a plurality of leads; the leads at least including: a first reference voltage lead 31, a first power lead 32, a second power lead 33, a second reference voltage lead 34 and a touch lead 35; the first reference voltage lead 31 is electrically connected to the first reference voltage bus; the second reference voltage lead 34 is electrically connected to the second reference voltage bus; the touch lead 35 is electrically connected to the touch line; the first power lead 32 is connected to the first power bus 25; the second power lead 33 is connected to the second power bus 24; along the second direction X, the second reference voltage lead 34 is located between the first reference voltage lead 31 and the touch lead 35. Fig.14As shown, the fan-out area 15 is provided with a fan-out line for transmitting the signal from the binding area 151 to the corresponding fan-out line. The fan-out area 15 specifically includes a first reference voltage lead 31, a first power lead 32, a second power lead 33 and a second reference voltage lead 34. The first reference voltage lead 31 is used to transmit the first reference voltage signal vref1 to the first reference voltage bus, the second reference voltage lead 34 is used to transmit the second reference voltage signal vref2 to the second reference voltage bus, the first power lead 32 is used to transmit the first power signal PVDD to the first power bus 25, and the second power lead 33 is used to transmit the second power signal PVEE to the second power bus 24. For a display panel with a touch function, a plurality of touch electrodes 105 and touch lines 106 connected to the touch electrodes 105 are provided, and the corresponding fan-out area 15 is provided with touch leads 35. Along the second direction X, multiple touch leads 35 are arranged at the center position, and other leads are arranged on both sides of the touch lead 35. There is a gap between the touch lead 35 and the other leads. In this embodiment, the second reference voltage lead 34 is located between the first reference voltage lead 31 and the touch lead 35, so that the second reference voltage lead 34 can be arranged at the above-mentioned gap and has a larger setting space. In this embodiment, the width of the second reference voltage lead 34 can also be set to be greater than that of other leads, thereby reducing the resistance of the second reference voltage lead 34 and reducing the loss of the second reference voltage signal vref2 during the transmission process. If the second reference voltage signal vref2 is used to reset the light-emitting element, this embodiment can provide a strong guarantee for the reset of the light-emitting element, thereby improving the display effect of the display panel and avoiding the occurrence of afterimages during the display process.

[0071] Continue to refer Fig.14 Optionally, the non-display area NA may also include: a binding area 151; the binding area 151 is located on the side of the fan-out area 15 away from the display area AA; the binding area 151 includes a plurality of pads 411; the pads 411 are respectively connected to the corresponding leads; along the second direction X, the pad 411 connected to the second reference voltage lead 34 is located between the pad 411 connected to the first power lead 32 and the pad 411 connected to the second power lead 33; the second reference voltage lead 34 connects to the corresponding pad 411 across the first reference voltage lead 31 through a jumper. In this embodiment, the binding area 151 is provided with pads 411 corresponding to the fan-out leads one by one. Although the second reference voltage lead 34 is positioned on the side of the first reference voltage lead 31 close to the touch lead 35 in this embodiment, the path sequence of the existing driver chip is that the pad 411 of the second reference voltage lead 34 is located on the side of the first reference voltage lead 31 away from the touch lead 35. Specifically, as Fig.14As shown, the second reference voltage lead 34 jumps over the first reference voltage lead 31 and the first power lead 32 through a jumper to connect the corresponding pad 411. This embodiment does not need to change the existing design of the driver chip and, while ensuring that the second reference voltage lead 34 is relatively wide, the corresponding pad is connected by a jumper, effectively reducing the manufacturing cost of the display panel.

[0072] Fig.15 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, optionally, the display area AA may further include an adjustment signal line 51; the non-display area NA may further include an adjustment signal bus 52; the adjustment signal bus 52 is electrically connected to the adjustment signal line 51; the adjustment signal bus 52 includes a seventh bus segment 53 and an eighth bus segment 54; the seventh bus segment 53 is located in the second non-display area NA2; the eighth bus segment 54 is located in the third non-display area NA3. The adjustment signal bus 52 may output an adjustment signal to the adjustment signal line 51 of the display area AA, so that the adjustment signal line 51 transmits the adjustment signal to the pixel driving circuit, and is used to adjust the bias state of the driving transistor in the pixel driving circuit. The adjustment signal bus 52 includes a seventh bus segment 53 and an eighth bus segment 54, wherein the seventh bus segment 53 is located in the second non-display area NA2, and the eighth bus segment 54 is located in the third non-display area NA3. Optionally, the seventh bus segment 53 also extends to the R angle area 16 on both sides of the second non-display area NA2, and the eighth bus segment 54 extends to the R angle area 16 on both sides of the third non-display area NA3, thereby enhancing the power supply effect of the adjustment signal bus 52 for the pixel driving circuit, effectively preventing the bias problem of the driving transistor, and improving the accuracy of the display panel image. It should be noted that the specific film layer of the adjustment signal bus 52 is as follows: Figure 5 As shown, the adjustment signal bus 52 is arranged on a side of the second reference voltage bus 14 away from the display area.

[0073] Continue to refer Fig.15Optionally, the adjustment signal line 51 may include a fifth connection line 511 extending along the first direction Y and a sixth connection line 512 extending along the second direction X; the fifth connection line 511 is electrically connected to the sixth connection line 512; the sixth connection line 512 is electrically connected to the seventh bus segment 53 and the eighth bus segment 54 respectively. In this embodiment, the fifth connection line 511 extending along the first direction Y and the sixth connection line 512 extending along the second direction X form a grid-shaped adjustment signal line 51, which reduces the loss of the adjustment signal during transmission and improves the control performance of the adjustment signal on the pixel driving circuit. In addition, the display area AA may also be provided with a first reference voltage line 11, which may include a first connection line 111 extending along the first direction Y and a second connection line 112 extending along the second direction X, so as to reduce the loss of the first reference voltage signal vref1 during transmission. The second reference voltage line 12 includes a fourth connection line 122 extending along the second direction X. Of course, in this embodiment, a third connection line ( Fig.15 In this embodiment, a grid structure of the adjustment signal line 51, the first reference voltage line 11 and the second reference voltage line 12 can be formed in the display area at the same time, so as to improve the driving capability of the adjustment signal bus 52, the first reference voltage bus 13 and the second reference voltage bus 14 to the pixel driving circuit.

[0074] Continue to refer Fig.15 Optionally, the first reference voltage bus 13, the second reference voltage bus 14 and the adjustment signal bus 52 can be arranged at the same layer. Fig.15 As shown, the first reference voltage bus 13, the second reference voltage bus 14 and the adjustment signal bus 52 are arranged side by side, and the first reference voltage bus 13 is arranged in the fan-out area 15 and the first non-display area NA1 of the display panel, occupying the area of ​​the upper and lower frames, and the second reference voltage bus 14 and the adjustment signal bus 52 are arranged in the second non-display area NA2 and the third non-display area NA3, occupying the space of the side frames. This embodiment effectively balances the bus settings of each frame, so that on the whole, the frame width of the display panel is smaller, realizing the user's narrow frame demand.

[0075] Continue to refer Fig.15 Optionally, the display area AA may also include an adjustment signal line 51; the non-display area NA also includes an adjustment signal bus 52; the adjustment signal bus 52 is electrically connected to the adjustment signal line 51; the lead also includes an adjustment signal lead 55; the adjusted signal lead 55 is electrically connected to the adjustment signal bus 52; along the second direction X, the second reference voltage lead 34 is located between the adjustment signal lead 55 and the touch lead 35; the adjustment signal lead 55 is located between the first reference voltage lead 31 and the second reference voltage lead 34.

[0076] Fig.15The touch trace 106 of the touch electrode 105 is omitted, and only the touch lead 35 is shown. In this embodiment, the fan-out area 15 includes an adjustment signal lead 55, which can transmit the adjustment signal to the adjustment signal bus 52, so that the adjustment signal bus 52 transmits the signal to the fifth connection line 511 and the sixth connection line 512. In the second direction X, a plurality of touch leads 35 are arranged at a central position, and other leads are arranged on both sides of the touch lead 35. There is a gap between the touch lead 35 and other leads. In this embodiment, the second reference voltage lead 34 is located between the first reference voltage lead 31 and the touch lead 35, so that the second reference voltage lead 34 can be arranged at the above-mentioned gap, and has a larger setting space. In this embodiment, the width of the second reference voltage lead 34 can also be arranged to be greater than that of other leads, thereby reducing the resistance of the second reference voltage lead 34 and reducing the loss of the second reference voltage signal vref2 during the transmission process. If the second reference voltage signal vref2 is used to reset the light-emitting element, this embodiment can provide a strong guarantee for the reset of the light-emitting element, thereby improving the display effect of the display panel and avoiding the occurrence of afterimages during the display process. It should be noted that the adjustment signal lead 55 is located between the first reference voltage lead 31 and the second reference voltage lead 34, so the adjustment signal lead 55 is closer to the touch lead 35 and also has a wider setting space. The width of the adjustment signal lead 55 can be set larger than other leads to reduce the loss of the adjustment signal during the transmission process.

[0077] Optionally, the non-display area NA may also include: a binding area 151; the binding area 151 is located on the side of the fan-out area 15 away from the display area AA; the binding area 151 includes a plurality of pads 411; the pads 411 are respectively connected to corresponding leads; along the second direction X, the pad 411 connected to the second reference voltage lead 34 is located between the pad 411 connected to the first power lead 32 and the pad 411 connected to the second power lead 33; the second reference voltage lead 34 connects to the corresponding pad 411 across the first reference voltage lead 31 and the adjustment signal lead 55 via a jumper. The path sequence of the existing driver chip is that the pad 411 of the second reference voltage lead 34 is located on the side of the pad 411 of the first reference voltage lead 31 away from the pad 411 of the touch lead 35. Specifically, as Fig.15 As shown, the second reference voltage lead 34 jumps over the first reference voltage lead 31, the adjustment signal lead 55 and the first power lead 32 through a jumper to connect the corresponding pads 411. This embodiment does not need to change the existing design of the driver chip and, while ensuring that the width of the second reference voltage lead 34 and the adjustment signal lead 55 is large, the corresponding pads are connected by a jumper, effectively reducing the manufacturing cost of the display panel.

[0078] Optionally, the display area AA may include pixel driving circuits arranged in an array; Fig.16 As shown, Fig.16A schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present invention. The pixel driving circuit 18 includes a driving transistor 181, a first reset module 182 and a second reset module 183; the first end of the first reset module 182 is electrically connected to the control end of the driving transistor 181, and the second end of the first reset module 182 is electrically connected to the first reference voltage line 11; the first end of the driving transistor 181 is electrically connected to the first power line; the second end of the driving transistor 181 is electrically connected to the first end of the light-emitting element D1; the first end of the second reset module 183 is electrically connected to the first end of the light-emitting element D1, and the second end of the second reset module 183 is electrically connected to the second reference voltage line 12; the second end of the light-emitting element D1 is electrically connected to the second power line.

[0079] In this embodiment, the pixel driving circuit 18 includes a first reset module 182 and a second reset module 183. The first reset module 182 is used to transmit the first reference voltage signal vref1 output by the first reference voltage line 11 to the control end of the driving transistor 181, and is used to reset the control end of the driving transistor 181 to prevent the current frame from having a residual voltage of the previous frame. The second reset module 183 is used to transmit the second reference voltage signal vref2 output by the second reference voltage line 12 to the first end of the light-emitting element D1, and is used to reset the first end of the light-emitting element D1 to avoid leakage current in the light-emitting element D1. When the pixel driving circuit 18 needs to output a driving current, the driving transistor 181 is turned on, and the first power line, the driving transistor 181, the light-emitting element D1 and the second power line are connected in sequence to form a path.

[0080] Fig.17 A schematic structural diagram of another pixel driving circuit provided by an embodiment of the present invention. Optionally, the pixel driving circuit 18 may also include: a storage capacitor C1, a light-emitting control module 184, a data writing module 185 and a threshold capture module 186; the first plate of the storage capacitor C1 is electrically connected to the first power line 21, and the second plate of the storage capacitor C1 is electrically connected to the control end of the driving transistor 181; the first end of the data writing module 185 is electrically connected to the first end of the driving transistor 181, and the second end of the data writing module 185 is electrically connected to the corresponding data line 23; the first end of the threshold capture module 186 is electrically connected to the control end of the driving transistor 181, and the second end of the threshold capture module 186 is electrically connected to the second end of the driving transistor 181; the first end of the first light-emitting control unit 187 of the light-emitting control module 184 is electrically connected to the first power line 21, and the second end of the first light-emitting control unit 187 is electrically connected to the first end of the driving transistor 181; the first end of the second light-emitting control unit 188 of the light-emitting control module 184 is electrically connected to the second end of the driving transistor 181, and the second end of the second light-emitting control unit 188 is electrically connected to the first end of the light-emitting element D1.

[0081] Fig.17 The pixel driving circuit of 7T1C is shown. Specifically, the first reset module 182 includes a sixth transistor T6, the second reset module 183 includes a seventh transistor T7, the threshold capture module 186 includes a fifth transistor T5, the first light-emitting control unit 187 includes a second transistor T2, the second light-emitting control unit 188 includes a third transistor T3, and the data writing module 185 includes a fourth transistor T4. The driving transistor 181 can be called the first transistor T1. This embodiment is illustrated by taking a low-temperature polycrystalline oxide (LTPO) display panel as an example. In the pixel driving circuit of 7T1C, the fifth transistor T5 and the sixth transistor T6 are P-type transistors, and their active layers are formed of indium gallium zinc oxide. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 are all N-type transistors, and their active layers are made of polysilicon material. Specifically, the first reset module 182 operates in response to the first scan signal SCAN1 to connect the control end of the driving transistor T1 to the first reference voltage signal vref1; the storage capacitor C1 is used to connect the first power signal PVDD to the control end of the driving transistor T1; the data writing module 185 is used to operate in response to the third scan signal SCAN3 to connect the first end of the driving transistor T1 to the corresponding data signal Vdata; the threshold capture module 186 is used to operate in response to the second scan signal SCAN2 to connect the control end of the driving transistor to the second end; the light control module 184 is used to operate in response to the light control signal EM to connect the first end of the driving transistor T1 to the first power signal PVDD, and at the same time connect the second end of the driving transistor T1 to the first end of the light emitting element D1; the second end of the light emitting element D1 is connected to the second power signal PVEE; the second reset module 183 operates in response to the third scan signal SCAN3 to connect the first end of the light emitting element D1 to the second reference voltage signal vref1. It should be noted that, in this embodiment, the first scanning signal SCAN1, the second scanning signal SCAN2, the third scanning signal SCAN3 and the fourth scanning signal SCAN4 can be set, the effective levels of the first scanning signal SCAN1 and the second scanning signal SCAN2 are high levels, and the effective levels of the third scanning signal SCAN3 and the fourth scanning signal SCAN4 are low levels. Among them, the effective level duration of the second scanning signal SCAN2 and the third scanning signal SCAN3 is exactly the same; the effective level duration of the first scanning signal SCAN1 and the fourth scanning signal SCAN4 is exactly the same.

[0082] The working process of the pixel driving circuit includes: a reset phase, a data writing phase and a light emitting phase. In the reset phase, the sixth transistor T6 is turned on, the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are turned off, and the first reference voltage signal vref1 is written into the N1 node (the control end of the driving transistor) to initialize the control end of the driving transistor T1; in the data writing phase, the driving transistor T1, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are turned on, the second transistor T2, the third transistor T3 and the sixth transistor T6 are turned off, and the second reference voltage signal vref2 is written into the N4 node (the emission end). The data signal Vdata flows to the N2 node (the first end of the light emitting element D1) through the fourth transistor T4, and then flows to the N3 node (the first end of the driving transistor) through the driving transistor T1, and then flows to N1 through the fifth transistor; in the light emitting stage, the driving transistor T1, the second transistor T2 and the third transistor T3 are turned on, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and a current path is formed from the first power supply signal PVDD to the second power supply signal PVEE, and the light emitting element D1 is lit.

[0083] Fig.18 A schematic diagram of another pixel driving circuit provided by an embodiment of the present invention. Optionally, the pixel driving circuit 18 may further include a signal adjustment module 189; a first end of the signal adjustment module 189 is connected to the signal adjustment line 51; a second end of the signal adjustment module 189 is connected to a first end of the driving transistor 181; and the signal adjustment module 189 is used to transmit the adjustment signal DVH to the driving transistor 181.

[0084] Fig.18 The pixel driving circuit of 8T1C is Fig.17 The pixel driving circuit shown in the figure, the pixel driving circuit of 8T1C adds an adjustment signal module 189, the adjustment signal module 189 includes an eighth transistor T8, the control end of the eighth transistor T8 is connected to the fourth scan signal SCAN4, the second end of the eighth transistor T8 is respectively connected to the first end of the driving transistor T1 and the second end of the fourth transistor T4, the first end of the eighth transistor T8 is connected to the adjustment signal DVH, in the reset stage, the eighth transistor T8 is turned on, the adjustment signal DVH is written into N2 to improve the bias state of the driving transistor T1, in the data writing stage and the light emitting stage, the eighth transistor T8 is in the cut-off state, and the rest of the working process is the same as the above Fig.17 The working process of the pixel driving transistor T1 is the same, and will not be described in detail again.

[0085] In this embodiment, the pixel driving circuit needs the first reference voltage bus 13, the second reference voltage bus 14, the first power bus 25, the second power bus 24 and the adjustment signal bus 52 to provide working power for it. This embodiment shows the situation where there are many types of buses, and the various types of buses are often set in the third metal layer M3. When there are many buses, the first reference voltage bus 13 is only set in the fan-out area 15 and the first non-display area NA1, occupying the area of ​​the upper and lower frames, and the remaining buses are set in the second non-display area NA2 and the third non-display area NA3, occupying the space of the side frames. Then, this embodiment effectively balances the bus settings of each frame, so that the frame width of the display panel is relatively small as a whole, realizing the user's narrow frame requirement.

[0086] Fig.19 Schematic diagram of another display panel provided by an embodiment of the present invention. Optionally, the display area AA may further include an auxiliary wiring 61; the data line 23 includes a first data line 23a and a second data line 23b; the fan-out area 15 includes a first data lead 15a and a second data lead 15b; the first data line 23a is electrically connected to the first data lead 15a; the second data line 23b is electrically connected to the second data lead 15b via the auxiliary wiring 61. Fig.19 As shown, the display area AA can be divided into a first display area AA1 and a second display area AA2; the data line 23 includes a first data line 23a and a second data line 23b. The first display area AA1 is provided with the first data line 23a, and the second display area AA2 is provided with the second data line 23b.

[0087] Optionally, a virtual routing line 12a can be provided on the same layer as the auxiliary routing line 61, and the virtual routing line 12a and the auxiliary routing line 61 form a grid shape to maintain the display uniformity of the display panel. The virtual routing line 12a can reduce the current attenuation of different signals due to the presence of routing resistance, thereby effectively improving the display effect of the display panel. The virtual routing line 12a can be connected to any of the following signals: the first power signal PVDD, the second power signal PVEE, the first reference voltage signal vref1, and the second reference voltage signal vref2. Similarly, in order to reduce the current attenuation of different signals due to the presence of routing resistance, the shielding bus can be connected to the first power signal PVDD, the second power signal PVEE, the first reference voltage signal vref1 or the second reference voltage signal vref2 to further improve the display effect of the display panel.

[0088] An embodiment of the present invention further provides a display device. Fig. 20 A schematic diagram of a display device according to an embodiment of the present invention is shown in FIG. Fig. 20 As shown, the display device provided by the embodiment of the present invention includes the display panel 200 described in any embodiment of the present invention. The display device can be as follows Fig. 20The display device of the mobile phone shown in the figure may also be a display device of an electronic device such as a computer, a television, a smart wearable device, etc., and this embodiment does not specifically limit this.

[0089] The display device in this embodiment includes the technical features of the display panel provided in any embodiment of the present invention, and has the beneficial effects of the corresponding features, which will not be described in detail here.

[0090] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: a display area and a non-display area surrounding the display area; The display area includes a plurality of first reference voltage lines, a plurality of second reference voltage lines and data lines; the data lines extend along a first direction; The non-display area includes a first reference voltage bus and a second reference voltage bus; The first reference voltage line is electrically connected to the first reference voltage bus; The second reference voltage line is electrically connected to the second reference voltage bus; The first reference voltage bus includes a first bus segment and a second bus segment; The non-display area includes a fan-out area and a first non-display area located at both sides of the display area along the first direction; at least part of the first bus segment is located in the fan-out area; at least part of the second bus segment is located in the first non-display area.

2. The display panel according to claim 1, characterized in that: The non-display area further includes a second non-display area and a third non-display area located on both sides of the display area along a second direction; the second direction intersects the first direction; the first non-display area is respectively arranged adjacent to the second non-display area and the third non-display area; The second reference voltage bus includes at least a third bus segment and a fourth bus segment; At least a portion of the third bus segment is located in the second non-display area; at least a portion of the fourth bus segment is located in the third non-display area.

3. The display panel according to claim 2, characterized in that: Adjacent non-display areas are connected via R corner areas.

4. The display panel according to claim 2, characterized in that: The first non-display area and the second non-display area are connected via a first R angle area; the first non-display area and the third non-display area are connected via a second R angle area; The second bus segment includes a first portion located in the first R angle region and / or a second portion located in the second R angle region.

5. The display panel according to claim 2, characterized in that: The fan-out area and the second non-display area are connected via a third R angle area; the fan-out area and the third non-display area are connected via a fourth R angle area; The first bus segment includes a third portion located in the third R angle region and / or a fourth portion located in the fourth R angle region.

6. The display panel according to claim 3, characterized in that: The display area includes a pixel driving circuit arranged in an array; the display area includes a first special-shaped area; The first irregularly shaped area is adjacent to the R-corner area, and the plurality of pixel driving circuits in the first irregularly shaped area are distributed in a stepped manner; The first bus segment and the second bus segment extend along edges of the first profiled area.

7. The display panel according to claim 6, characterized in that: The third bus segment and the fourth bus segment extend along edges of the first profiled area.

8. The display panel according to claim 6, characterized in that: It also includes: a shielding bus; the shielding bus extends along the edge of the first special-shaped area; in the first special-shaped area, the shielding bus includes a linear first bus and a stepped second bus; The first reference voltage bus includes a plurality of first stages extending along a first direction and a plurality of second stages extending along a second direction in the first special-shaped area; The second bus includes a plurality of third stages extending along the first direction and a fourth stage extending along the second direction in the first special-shaped area; There is an overlapping area between the second stage and the fourth stage.

9. The display panel according to claim 2, characterized in that: The first reference voltage bus further includes: a fifth bus segment; The fifth bus segment is located in the second non-display area.

10. The display panel according to claim 9, characterized in that: The first reference voltage bus further includes: a sixth bus segment; The sixth bus segment is located in the third non-display area.

11. The display panel according to claim 10, characterized in that: Along the second direction, the width of the fifth bus segment is smaller than that of the third bus segment; and the width of the sixth bus segment is smaller than that of the fourth bus segment.

12. The display panel according to claim 10, characterized in that: The first bus segment, the fifth bus segment, the second bus segment and the sixth bus segment are connected in sequence to form a ring.

13. The display panel according to claim 10, characterized in that: The first reference voltage bus and the second reference voltage bus are located in different film layers; The fifth bus segment at least partially overlaps with the third bus segment; and / or, The sixth bus segment at least partially overlaps the fourth bus segment.

14. The display panel according to claim 1, characterized in that: The first reference voltage bus and the second reference voltage bus are arranged at the same layer.

15. The display panel according to claim 2, characterized in that: The first reference voltage line includes a first connection line extending along a first direction and a second connection line extending along the second direction; the first connection line is electrically connected to the second connection line; The second reference voltage line includes a third connection line extending along the first direction and a fourth connection line extending along the second direction; the third connection line is electrically connected to the fourth connection line; The first connecting lines are respectively connected to the first bus segment and the second bus segment; The fourth connecting line is connected to the third bus segment and the fourth bus segment respectively.

16. The display panel according to claim 3, characterized in that: The display area further includes: a first power line and a second power line extending along the second direction; The non-display area further includes a first power bus and a second power bus; the first power bus is connected to the first power line; the second power bus is connected to the second power line; The first power bus includes a portion located in the second non-display area and the third non-display area and a portion extending to the R corner area; and / or, The second power bus includes portions located in the second non-display area and the third non-display area and a portion extending to the R corner area.

17. The display panel according to claim 16, characterized in that: The display panel comprises: A touch line connected to the touch electrode; the fan-out area includes a plurality of leads; the leads include at least: a first reference voltage lead, a first power lead, a second power lead, a second reference voltage lead and a touch lead; The first reference voltage lead is electrically connected to the first reference voltage bus; the second reference voltage lead is electrically connected to the second reference voltage bus; the touch lead is electrically connected to the touch trace; the first power lead is connected to the first power bus; the second power lead is connected to the second power bus; Along the second direction, the second reference voltage lead is located between the first reference voltage lead and the touch control lead.

18. The display panel according to claim 16, characterized in that: The non-display area further includes: a binding area; the binding area is located at a side of the fan-out area away from the display area; The binding area includes a plurality of pads; the pads are respectively connected to corresponding leads; Along the second direction, the pad connected to the second reference voltage lead is located between the pad connected to the first power lead and the pad connected to the second power lead; The second reference voltage lead wire is connected to a corresponding pad by crossing over the first reference voltage lead wire through a jumper wire.

19. The display panel according to claim 2, characterized in that: The display area also includes an adjustment signal line; The non-display area further comprises an adjustment signal bus; the adjustment signal bus is electrically connected to the adjustment signal line; The regulation signal bus includes a seventh bus segment and an eighth bus segment; The seventh bus segment is located in the second non-display area; The eighth bus segment is located in the third non-display area.

20. The display panel according to claim 19, characterized in that: The adjustment signal line includes a fifth connection line extending along the first direction and a sixth connection line extending along the second direction; the fifth connection line is electrically connected to the sixth connection line; The sixth connecting line is electrically connected to the seventh bus segment and the eighth bus segment respectively.

21. The display panel according to claim 19, characterized in that: The first reference voltage bus, the second reference voltage bus and the adjustment signal bus are arranged in the same layer.

22. The display panel according to claim 17, characterized in that: The display area also includes an adjustment signal line; The non-display area further comprises an adjustment signal bus; the adjustment signal bus is electrically connected to the adjustment signal line; The leads also include an adjustment signal lead; the adjustment signal lead is electrically connected to the adjustment signal bus; Along the second direction, the second reference voltage lead is located between the adjustment signal lead and the touch control lead; the adjustment signal lead is located between the first reference voltage lead and the second reference voltage lead.

23. The display panel according to claim 22, characterized in that: The non-display area further includes: a binding area; the binding area is located on a side of the fan-out area away from the display area; The binding area includes a plurality of pads; the pads are respectively connected to corresponding leads; Along the second direction, the pad connected to the second reference voltage lead is located between the pad connected to the first power lead and the pad connected to the second power lead; The second reference voltage lead is connected to corresponding pads by crossing over the first reference voltage lead and the adjustment signal lead through a jumper.

24. The display panel according to claim 1, characterized in that: The display area includes pixel driving circuits arranged in an array; The pixel driving circuit includes a driving transistor, a first reset module and a second reset module; The first end of the first reset module is electrically connected to the control end of the driving transistor, and the second end of the first reset module is electrically connected to the first reference voltage line; the first end of the driving transistor is electrically connected to the first power line; the second end of the driving transistor is electrically connected to the first end of the light-emitting element; the first end of the second reset module is electrically connected to the first end of the light-emitting element, and the second end of the second reset module is electrically connected to the second reference voltage line; the second end of the light-emitting element is electrically connected to the second power line.

25. The display panel according to claim 24, characterized in that: The pixel driving circuit also includes: a storage capacitor, a light emitting control module, a data writing module and a threshold grabbing module; The first plate of the storage capacitor is electrically connected to the first power line, and the second plate of the storage capacitor is electrically connected to the control end of the driving transistor; the first end of the data writing module is electrically connected to the first end of the driving transistor, and the second end of the data writing module is electrically connected to the corresponding data line; the first end of the threshold capture module is electrically connected to the control end of the driving transistor, and the second end of the threshold capture module is electrically connected to the second end of the driving transistor; the first end of the first light-emitting control unit of the light-emitting control module is electrically connected to the first power line, and the second end of the first light-emitting control unit is electrically connected to the first end of the driving transistor; the first end of the second light-emitting control unit of the light-emitting control module is electrically connected to the second end of the driving transistor, and the second end of the second light-emitting control unit is electrically connected to the first end of the light-emitting element.

26. The display panel according to claim 24, characterized in that: The pixel driving circuit also includes a signal adjustment module; The first end of the regulating signal module is connected to the regulating signal line; the second end of the regulating signal module is connected to the first end of the driving transistor; and the regulating signal module is used to transmit the regulating signal to the driving transistor.

27. The display panel according to claim 1, characterized in that: The display area further includes auxiliary wiring; the data line includes a first data line and a second data line; the fan-out area includes a first data lead and a second data lead; The first data line is electrically connected to the first data lead; the second data line is electrically connected to the second data lead through the auxiliary wiring.

28. A display device, characterized in that: A display panel comprising any one of claims 1 to 27.

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