Display panel, driving chip and display device

Abstract

The application discloses a display panel, a driving chip and a display device. The display panel comprises a gate driving circuit, the gate driving circuit comprises a plurality of shift registers connected in cascade, and the shift register comprises a first transistor which is connected to a power supply voltage through a resistance structure. According to the embodiment of the application, the problem that the transistor is easily damaged can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel, a driver chip, and a display device. Background Technology

[0002] Display panels typically include pixels and gate driving circuits. The gate driving circuits are used to provide gate control signals to the pixels to control the pixels to write data signals, etc.

[0003] With the development of display technology, the requirements for the reliability of display panels are increasing. If the transistors in the gate drive circuit are easily damaged, it will affect the normal operation of the gate drive circuit, and thus affect the reliability of the display panel. Summary of the Invention

[0004] This application provides a display panel, a driver chip, and a display device that can improve the problem of transistors being easily damaged.

[0005] In a first aspect, embodiments of this application provide a display panel, including: a gate driving circuit, the gate driving circuit including a plurality of cascaded shift registers, each shift register including a first transistor, the first transistor being connected to a power supply voltage through a resistor structure.

[0006] Based on the same inventive concept, in a second aspect, embodiments of this application provide a driver chip for providing a power supply voltage to a gate driving circuit in a display panel. The power supply voltage provided by the driver chip is a first level in a first stage, a second level in a second stage, and a third level in a third stage. The third stage is located between the first stage and the second stage, and the third level is between the first level and the second level. Under the first level, the first transistor in the gate driving circuit is turned on.

[0007] Based on the same inventive concept, in a third aspect, embodiments of this application provide a driver chip, including: a signal generation circuit and a signal delay structure. The signal generation circuit is used to generate a power supply voltage, one end of the signal delay structure is electrically connected to the output terminal of the signal generation circuit, and the other end of the signal delay structure is used to electrically connect to the gate driving circuit in the display panel.

[0008] Based on the same inventive concept, in a fourth aspect, embodiments of this application provide a display device, including: a display panel as described in the first aspect embodiment, and / or a driver chip as described in the second or third aspect embodiment.

[0009] When the power supply voltage changes, a transient current I is generated on the power supply voltage transmission path. For example, when the power supply voltage changes from a low potential vgl to a high potential vgh, a transient current I is generated on the power supply voltage transmission path. If the first transistor is directly connected to the power supply voltage without a resistor structure, the first transistor receives the high potential vgh, the source-drain voltage difference Vds of the first transistor is large, and the current through the first transistor is large, which can easily damage the first transistor. In this embodiment, the first transistor is connected to the power supply voltage through the resistor structure 30. When the power supply voltage changes from a low potential vgl to a high potential vgh, the instantaneous current generated on the power supply voltage transmission path will produce a voltage drop ΔV on the resistor structure. The resistance of the resistor structure 30 is denoted as R, and ΔV = I*R. The potential received by the first transistor decreases to vgh-ΔV, and the current passing through the first transistor decreases accordingly. In this way, the large current impact on the first transistor due to the instantaneous change of the connected power supply voltage can be reduced. That is, the voltage change of the power supply voltage is avoided from directly impacting the first transistor, so that the instantaneous current passing through the first transistor decreases, thereby improving the problem of easy damage to the first transistor and improving the reliability of the gate driving circuit and the display panel.

[0010] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0011] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0012] Figure 1 This illustration shows a top view of a display panel provided in an embodiment of this application.

[0013] Figure 2 This diagram illustrates another top view of the display panel provided in an embodiment of this application.

[0014] Figure 3 This illustration shows a circuit structure diagram of a shift register in a display panel provided in an embodiment of this application;

[0015] Figure 4 Show Figure 3 A corresponding timing diagram;

[0016] Figure 5 This illustration shows a circuit structure diagram of a shift register in a display panel provided in an embodiment of this application;

[0017] Figure 6 This illustration shows another circuit structure diagram of the shift register in the display panel provided in an embodiment of this application;

[0018] Figure 7 This illustration shows another circuit structure diagram of the shift register in the display panel provided in the embodiments of this application;

[0019] Figure 8 This application provides some schematic diagrams illustrating the structure of the resistor structure in a display panel.

[0020] Figure 9 This illustration shows a schematic diagram of a wiring structure in a display panel provided in an embodiment of this application;

[0021] Figure 10 This illustration shows another structural diagram of the wiring in the display panel provided in this application embodiment;

[0022] Figure 11 This illustration shows a cross-sectional structural diagram of a display panel provided in an embodiment of this application;

[0023] Figure 12 This diagram illustrates another cross-sectional structure of the display panel provided in an embodiment of this application.

[0024] Figure 13 This diagram illustrates yet another cross-sectional structure of the display panel provided in an embodiment of this application.

[0025] Figure 14 This diagram illustrates yet another cross-sectional structure of the display panel provided in an embodiment of this application.

[0026] Figure 15 This diagram illustrates yet another cross-sectional structure of the display panel provided in an embodiment of this application.

[0027] Figure 16 This illustration shows another structural diagram of the wiring in a display panel provided in an embodiment of this application;

[0028] Figure 17 This illustration shows another structural diagram of the wiring in a display panel provided in an embodiment of this application;

[0029] Figure 18 This illustration shows a connection diagram of the wiring and circuitry in a display panel provided in an embodiment of this application;

[0030] Figure 19 This illustration shows another connection diagram of the wiring and circuitry in the display panel provided in the embodiments of this application;

[0031] Figure 20This illustration shows yet another connection diagram of the wiring and circuitry in the display panel provided in the embodiments of this application;

[0032] Figure 21 This illustration shows a connection diagram of a resistor structure and a first transistor in a display panel provided in an embodiment of this application;

[0033] Figure 22 This illustration shows another connection diagram of the resistor structure and the first transistor in the display panel provided in an embodiment of this application;

[0034] Figure 23 This invention provides a timing diagram of a power supply voltage according to an embodiment of the present application.

[0035] Figure 24 This diagram illustrates a timing schematic of the power supply voltage output by the driver chip provided in an embodiment of this application.

[0036] Figure 25 This diagram illustrates another timing schematic of the power supply voltage output by the driver chip provided in an embodiment of this application.

[0037] Figure 26 This diagram illustrates yet another timing sequence of the power supply voltage output by the driver chip provided in an embodiment of this application.

[0038] Figure 27 This diagram illustrates yet another timing sequence of the power supply voltage output by the driver chip provided in an embodiment of this application.

[0039] Figure 28 This illustration shows a schematic diagram of a driver chip provided in an embodiment of this application;

[0040] Figure 29 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0041] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0042] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0043] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0044] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0045] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0046] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0047] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first provides a detailed explanation of the relevant technical issues:

[0048] The inventors of this application have discovered that, especially when the display panel is operating in a high-temperature environment, transistor devices with high bias voltage and long-term operation in the gate drive circuit are prone to damage.

[0049] For transistors that require a power supply voltage (VDD signal), when the VDD signal changes from a cutoff level to a conduction level (here, cutoff level refers to the level that controls the transistor to turn off, and conduction level refers to the level that controls the transistor to turn on), the transistor controlled by the VDD signal will be directly subjected to a high-level and high-current surge. If the transistor remains on for an extended period, it is prone to damage. Once the transistor is damaged, it cannot control the corresponding node in the gate drive circuit, causing the gate drive circuit to lose its function and malfunction, which in turn leads to display abnormalities on the display panel (such as horizontal lines appearing on the display).

[0050] In view of the inventors’ above-mentioned research findings, the embodiments of this application consider changing the actual power supply voltage received by the transistor. When the power supply voltage undergoes a potential transition, the transistor is prevented from receiving an instantaneously high potential and being impacted by a sudden large current. This reduces the instantaneous current passing through the transistor, thereby improving the problem of easy damage to the transistor and enhancing the reliability of the gate drive circuit and the display panel.

[0051] The display panel, driver chip, and display device provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0052] like Figure 1 or Figure 2 As shown in the figure, the display panel 100 provided in this embodiment includes a gate driving circuit 10, which includes a plurality of cascaded shift registers 11. The figure uses the output signal of the previous-level shift register 11 as the trigger signal of the next-level shift register 11 as an example. The cascading relationship between shift registers 11 is not limited to this; the output signal of the current-level shift register can be used as the trigger signal of several subsequent shift registers.

[0053] For example, the display panel 100 includes a display area AA and a non-display area NA surrounding the display area AA. A gate driving circuit 10 is located in the non-display area NA. The display area AA includes a plurality of pixels 20. The output of a shift register 11 is electrically connected to the pixels 20, and the signal output by the shift register 11 is used to drive the pixels 20.

[0054] The signals output by shift register 11 may include scanning signals, light control signals, etc.

[0055] When the display panel is a liquid crystal display panel, the pixel 20 may include a switching transistor. The signal output by the shift register 11 controls the switching transistor to be turned on, so that the data line provides data voltage to the pixel electrode through the switching transistor.

[0056] The shift register 11 includes a first transistor 111, which is connected to the power supply voltage VDD through a resistor structure 30. The power supply voltage VDD is provided by a driving circuit, such as a driving chip 200. It can be understood that the path from the output terminal of the driving chip 200 to the first transistor 111 passes through the resistor structure 30.

[0057] For example, the gate of the first transistor 111 is connected to the power supply voltage VDD through a resistor structure 30. The power supply voltage VDD is used to control the state of the first transistor 111. For example, when the power supply voltage VDD is at a first level, the first transistor 111 is turned on; when the power supply voltage VDD is at a second level, the first transistor 111 is turned off. When the first transistor 111 is an N-type transistor, the second level is lower than the first level, the first level is a high level vgh, and the second level is a low level vgl. Correspondingly, when the first transistor is a P-type transistor, the first level is a low level vgl, and the second level is a high level vgh.

[0058] For example, the display panel 100 also includes a power trace 41 for transmitting a power supply voltage VDD. The driver chip 200 provides the power supply voltage VDD, and the power supply voltage VDD output by the driver chip 200 is transmitted to the first transistor 111 through the power trace 41 and the resistor structure 30.

[0059] As an example, such as Figure 1 As shown, resistor structure 30 is connected between shift register 11 and power supply trace 41. In this case, the power supply voltage VDD output by driver chip 200 is first transmitted to power supply trace 41, then to resistor structure 30, and then to first transistor 111.

[0060] As another example, such as Figure 2 As shown, resistor structure 30 is connected between driver chip 200 and power supply trace 41. In this case, the power supply voltage VDD output by driver chip 200 is first transmitted to resistor structure 30, then to power supply trace 41, and then to first transistor 111.

[0061] The following provides an exemplary description of some structures of shift registers.

[0062] For example, the circuit architecture of shift register 11 includes, but is not limited to, Figure 3 The circuit architecture is shown. (As shown in the image.) Figure 3As shown, the circuit architecture of shift register 11 may include a pull-up control module 1, a pull-up module 2, a main pull-down module 3, a pull-down sustaining module 4, and a bootstrap capacitor 5. Specifically, pull-up control module 1 is used to pre-charge and enable the shift register; pull-up module 2 is used to drive the pixels in the display area; main pull-down module 3 is used to pull down nodes Gn and netA; pull-down sustaining module 4 is used to maintain the PD point potential stability; and bootstrap capacitor 5 is used to raise the potential of node netA. Here, nodes netA and PU can be understood as nodes with the same potential.

[0063] For example, the shift register 11 may also be designed to include other functional modules 6, depending on other requirements.

[0064] like Figure 4 As shown, the operation of shift register 11 can generally be divided into four stages.

[0065] In stage ①, the pull-up control module 1 controls the trigger signal STV to enter, the PU point is lifted for the first time, and the PD point is pulled down;

[0066] In stage ②, bootstrap capacitor 5 takes effect, and PU point is lifted for the second time;

[0067] In stage ③, the main pull-down module 3 takes effect, the RESET signal is entered, pulling down the PU point and the PD point begins to rise;

[0068] In stage ④, the pull-down sustaining module 4 takes effect, the PD point is kept at a high potential, and the circuit charge is continuously cleared until the PU point rises again, pulling it down.

[0069] The power supply voltage VDD is used to provide the potential of the PD point. The frequency of change of the power supply voltage VDD does not need to be high. For example, if the transistor controlled by the power supply voltage VDD is an N-type transistor, the power supply voltage VDD can be maintained at a high potential for a long time.

[0070] In some optional examples, the specific circuit structure of shift register 11 can be as follows: Figure 5 As shown, transistors M16 and M17 require a power supply voltage VDD. For ease of distinction, the voltage connected to transistor M16 is denoted as the first power supply voltage VDD1, and the voltage connected to transistor M17 is denoted as the second power supply voltage VDD2. Here, the first transistor 111 includes transistors M16 and M17, which can be connected to the first power supply voltage VDD1 and the second power supply voltage VDD2 respectively through different resistor structures 30.

[0071] In some alternative examples, the specific circuit structure of shift register 11 can be as follows: Figure 6As shown, transistor T4 needs to be connected to the power supply voltage VDD. Here, the first transistor 111 includes transistor T4, which is connected to the power supply voltage VDD through resistor structure 30.

[0072] In some alternative examples, the specific circuit structure of shift register 11 can be as follows: Figure 7 As shown, transistor M05 needs to be connected to the power supply voltage VDD. Here, the first transistor 111 includes transistor M05, which is connected to the power supply voltage VDD through resistor structure 30.

[0073] It should be noted that the technical concept of this application has universal applicability, and no specific requirements are placed on the structure of the shift register. Figures 3 to 7 The structures and timings shown are merely examples and are not intended to limit this application. For example, Figures 5 to 7 The circuit structures of the shift registers shown are 19T1C, 11T1C, and 9T1C. The structures of shift registers include, but are not limited to, 19T1C, 11T1C, 9T1C, 9T2C, 12T1C, 17T1C, and 21T1C. Here, "19T1C" means that the shift register has 19 transistors and 1 capacitor. The others are similar and will not be explained one by one.

[0074] When the power supply voltage changes, a transient current I is generated on the power supply voltage transmission path. For example, when the power supply voltage changes from a low potential vgl to a high potential vgh, a transient current I is generated on the power supply voltage transmission path. If the first transistor is directly connected to the power supply voltage without a resistor structure, the first transistor receives the high potential vgh, the source-drain voltage difference Vds of the first transistor is large, and the current through the first transistor is large, which can easily damage the first transistor. In this embodiment, the first transistor is connected to the power supply voltage VDD through a resistor structure 30. When the power supply voltage VDD changes from a low potential vgl to a high potential vgh, the instantaneous current generated on the transmission path of the power supply voltage VDD will produce a voltage drop ΔV on the resistor structure. The resistance of the resistor structure 30 is denoted as R, and ΔV = I*R. The potential received by the first transistor decreases to vgh-ΔV, and the current passing through the first transistor decreases accordingly. In this way, the large current impact on the first transistor due to the instantaneous change of the connected power supply voltage VDD can be reduced. That is, the voltage change of the power supply voltage VDD is avoided from directly impacting the first transistor, so that the instantaneous current passing through the first transistor decreases, thereby improving the problem of easy damage to the first transistor and improving the reliability of the gate driving circuit and the display panel.

[0075] Understandably, a transient current is only generated in the transmission path of the power supply voltage VDD when it changes. Therefore, the resistor structure 30 only reduces the voltage when the power supply voltage VDD changes. When the power supply voltage VDD no longer changes, almost no current flows through the transmission path, and the resistor structure no longer reduces the voltage. Therefore, this resistor structure is equivalent to adding a delay when the signal changes drastically, acting as a buffer, and will not affect the normal operating potential of the device, thus not affecting the normal operation of the shift register.

[0076] For example, the first transistor is an N-type transistor. When the voltage difference between its gate and source, Vgs, is greater than its threshold voltage, Vth, the first transistor turns on, and current flows. The resistive structure acts as a delay when the power supply voltage VDD changes from a low potential, vgl, to a high potential, vgh. When the power supply voltage VDD changes from a high potential, vgh, to a low potential, vgl, the N-type first transistor turns off, and no current flows.

[0077] For example, if the first transistor is a P-type transistor, when the voltage difference between its gate and source, Vgs, is less than its threshold voltage, Vth, the first transistor conducts and current flows. The resistive structure acts as a delay when the power supply voltage VDD changes from a high potential, vgh, to a low potential, vgl. When the power supply voltage VDD changes from a low potential, vgl, to a high potential, vgh, the P-type first transistor turns off, and no current flows.

[0078] The following are some examples of resistor structures.

[0079] In some embodiments, such as Figure 1 or Figure 2 As shown, the display panel includes a power supply trace 41 for transmitting the power supply voltage VDD, and the resistor structure 30 includes a first trace 301. The first trace 301 can be connected between the power supply trace 41 and the first transistor 111, or the first trace 301 can be connected to the first transistor 111 through the power supply trace 41.

[0080] As an example, at least a portion of the first trace 301 has an impedance per unit length greater than that of the power trace 41 per unit length. This can be designed such that the impedance of the first trace 301 is uniform, meaning that the impedance per unit length is the same for segments at different locations on the first trace 301. Alternatively, it can be designed such that the impedance per unit length of a portion of the first trace 301 is greater than that of the power trace 41, while the impedance per unit length of another portion of the first trace 301 is not required.

[0081] Understandably, both the first trace 301 and the power trace 41 are used to transmit the power supply voltage VDD. Over the same length, the impedance of the first trace 301 is greater than the impedance of the power trace 41. For example, the total impedance of the first trace 301 is greater than the total impedance of the power trace 41.

[0082] To reduce the impact of signal voltage drop on display performance, the total impedance of the power supply trace 41 is usually set to be relatively small, or even negligible. In this embodiment, the resistor structure includes a first trace, meaning the resistor structure is designed as a trace structure. This allows for the direct fabrication of the first trace using existing trace fabrication processes, making it relatively easy to implement. Furthermore, the first trace has a relatively large impedance per unit length, which is more beneficial in reducing the impact of power supply voltage VDD changes on the first transistor, thereby protecting the first transistor from damage.

[0083] In some embodiments, such as Figure 1 or Figure 2 As shown, the display panel includes a power trace 41 for transmitting the power supply voltage VDD, and the resistor structure 30 includes a first trace 301. The line width of the first trace 301 is smaller than the line width of the power supply trace 41. With the same material, a smaller line width results in a larger impedance. In this embodiment, by designing the first trace to have a smaller line width, the impedance along the transmission path from the power supply voltage VDD to the first transistor can be increased, reducing the impact on the first transistor when the power supply voltage VDD changes, thereby protecting the first transistor from damage.

[0084] In other embodiments, the transmission path of the power supply voltage VDD from the driver chip 200 to the first transistor can also be increased. For example, the trace length can be increased at certain locations on the transmission path (e.g., the location of the first trace 301).

[0085] As an example, such as Figure 8 As shown, the resistor structure includes a first trace 301, which includes a bent line. Designing the first trace to extend in a bent form increases its total length within a limited space, thereby increasing the impedance along the transmission path of the power supply voltage VDD to the first transistor. This reduces the impact on the first transistor when the power supply voltage VDD changes, thus protecting the first transistor from damage.

[0086] In some examples, such as Figure 8 As shown, the bending form of the first trace 301 may include, but is not limited to, any one of square wave, sawtooth, or serpentine shapes.

[0087] As an example, while keeping the total length of the transmission path from the power supply voltage VDD output by the driver chip 200 to the first transistor unchanged, the line width of only some locations on the transmission path (e.g., the location of the first trace 301) can be reduced.

[0088] As another example, the total length of the transmission path from the power supply voltage VDD to the first transistor can be increased (e.g., the length of the first trace can be increased) while keeping the linewidth of the transmission path of the power supply voltage VDD unchanged.

[0089] As another example, the trace width can be reduced not only at certain locations on the transmission path (e.g., where the first trace 301 is located), but also the total length of the transmission path from the power supply voltage VDD to the first transistor can be increased (e.g., the length of the first trace can be increased).

[0090] Understandably, when the width of the first trace 301 is smaller than the width of the power trace 41, the impedance of the first trace 301 per unit length is greater than that of the power trace 41 per unit length. In other examples, different materials can be used to fabricate the first trace 301 and the power trace 41, and the material used for the first trace 301 has a higher impedance to ensure that the impedance of the first trace 301 per unit length is greater than that of the power trace 41 per unit length.

[0091] In some embodiments, such as Figure 1 or Figure 2 As shown, the display panel includes a power supply trace 41, which is used to transmit the power supply voltage VDD. Please refer to [reference needed]. Figure 9 The resistor structure 30 includes at least a first segment 30a, which is located in a different film layer from the power supply trace 41.

[0092] Figure 9 Different fillers are used to represent traces located in different film layers. When the first line segment 30a and the power trace 41 are located in different film layers, they can be connected through a via h1. One end of the via h1 overlaps the power trace 41, and the other end overlaps the first line segment 30a.

[0093] Since the first segment 30a and the power line 41 are located in different film layers, the first segment 30a is not constrained by the power line 41. The design freedom of the structural and / or material characteristics of the first segment 30a is greater, which facilitates more flexible design of the first segment 30a.

[0094] For example, the material of the first segment 30a includes a transparent conductive material or a semiconductor material.

[0095] As an example, transparent conductive materials include indium tin oxide (ITO). The materials for power traces 41 typically include elemental metals or alloys such as copper, aluminum, molybdenum, and titanium, which have relatively low impedance. ITO, on the other hand, has a much higher impedance, generally 500 times or more than that of metals like copper and aluminum.

[0096] When the power supply trace 41 is a conductor, and the first segment 30a is made of semiconductor material, the first segment 30a is a semiconductor. Compared to a conductor, a semiconductor has a higher resistance and a lower conductivity than a conductor.

[0097] As an example, the semiconductor material included in the first segment 30a can be the same as the semiconductor material included in the transistor in the gate drive circuit. For example, the first segment 30a includes doped A-Si. Here, the first segment 30a can refer to a doped conductive semiconductor trace. It is understood that the doped semiconductor trace does not directly conduct current; it can carry current, but its resistance is relatively high, and the current it carries will be relatively small.

[0098] In some embodiments, such as Figure 10 As shown, the resistor structure 30 also includes a second segment 30b, which is electrically connected to the first segment 30a, and the second segment 30b and the first segment 30a are located in different layers.

[0099] For example, the resistor structure 30 may include multiple first segments 30a and second segments 30b. The first segments 30a and second segments 30b are alternately arranged and connected to each other through a via h2.

[0100] As an example, the second segment 30b and the power trace 41 are located in the same film layer. When they are located in the same film layer, they can be made of the same material, so that the second segment 30b and the power trace 41 can be fabricated simultaneously.

[0101] As another example, the second segment 30b and the power trace 41 are located in different film layers. In this case, the second segment 30b, the first segment 30a, and the power trace 41 are located in different film layers.

[0102] In this embodiment, the resistor structure 30 is configured to include a first segment 30a and a second segment 30b located in different film layers. This allows for the extension of the traces of the resistor structure within the same area, thereby increasing the total impedance of the resistor structure. This increases the impedance on the transmission path from the power supply voltage VDD to the first transistor, reduces the impact on the first transistor when the power supply voltage VDD changes, and thus protects the first transistor from damage.

[0103] In some embodiments, such as Figures 11 to 14 As shown in any of the accompanying drawings, the display panel also includes pixel electrodes 51 and common electrodes 52.

[0104] The display panel can be used as a display panel for a liquid crystal display (LCD), and the display panel includes liquid crystal molecules 53. Pixel electrodes 51 and common electrodes 52 provide an electric field for controlling the rotation of the liquid crystal molecules.

[0105] A pixel in a display panel includes a pixel circuit. Pixel electrodes are connected to transistors in the pixel circuit and are used to receive data voltages transmitted by the transistors in the pixel circuit. A common electrode is used to receive a common voltage. For example, a pixel includes sub-pixels, and the common electrodes of multiple sub-pixels can be electrically connected to each other.

[0106] Please refer to the reference. Figure 1 and Figures 11 to 14 In any of the attached figures, the resistor structure 30 includes at least a first segment 30a, which is located on a different film layer from the power supply trace 41, and is located on the same layer as the pixel electrode 51, and / or the first segment 30a is located on the same layer as the common electrode 52.

[0107] For example, the display panel also includes a substrate 54, with pixel electrodes 51 and common electrodes 52 located on one side of the substrate 54.

[0108] As an example, such as Figure 11 As shown, the pixel electrode 51 and the common electrode 52 are located on the same layer. Here, the first line segment, the pixel electrode 51, and the common electrode 52 can all be located on the same layer.

[0109] As another example, such as Figure 12 or Figure 13 As shown, the film layer where the pixel electrode 51 is located is situated between the film layer where the common electrode 52 is located and the substrate 54.

[0110] For example, the display panel also includes an opposing plate 55, liquid crystal molecules 53 located between the substrate 54 and the opposing plate 55, pixel electrodes 51 located on the side of the substrate 54 facing the liquid crystal molecules 53, and a common electrode 52 located on the side of the opposing plate 55 facing the liquid crystal molecules 53. For another example, such as... Figure 13 As shown, both the pixel electrode 51 and the common electrode 52 are located on the side of the substrate 54 facing the liquid crystal molecules 53. In the thickness direction of the display panel, the film layer containing the pixel electrode 51 is located between the film layer containing the common electrode 52 and the substrate 54, and the pixel electrode 51 and the common electrode 52 are separated by an insulating layer 01. Here, the film layer containing the pixel electrode 51 may be provided with a first line segment, and / or, the film layer containing the common electrode 52 may be provided with a first line segment.

[0111] As yet another example, such as Figure 14 As shown, the film layer containing the common electrode 52 is located between the film layer containing the pixel electrode 51 and the substrate 54. For example, both the pixel electrode 51 and the common electrode 52 are located on the side of the substrate 54 facing the liquid crystal molecules 53, and in the thickness direction of the display panel, the film layer containing the common electrode 52 is located between the film layer containing the pixel electrode 51 and the substrate 54. Here, the film layer containing the pixel electrode 51 may be provided with a first line segment, and / or, the film layer containing the common electrode 52 may be provided with a first line segment.

[0112] In this embodiment, the first segment of the resistor structure is designed to be located in the same film layer as the pixel electrode and / or common electrode. The first segment can be prepared at the same time as the pixel electrode and / or common electrode, so that no additional preparation process is required when the first segment is added.

[0113] Understandably, when the pixel electrode and / or common electrode are metal electrodes, and the first line segment is on the same layer as the pixel electrode and / or common electrode, the first line segment is a metal trace. In another embodiment, when the pixel electrode and / or common electrode are made of ITO, and the first line segment is on the same layer as the pixel electrode and / or common electrode, the first line segment is made of ITO.

[0114] In other embodiments, the first segment is a semiconductor trace. For example, the first transistor includes an active layer, and the first segment and the active layer of the first transistor are located on the same film layer. In this case, the first segment and the active layer of the first transistor are made of the same material, and the first segment can be fabricated simultaneously with the active layer of the first transistor, so that adding an additional first segment does not require additional fabrication processes.

[0115] As an example, such as Figure 15 As shown, the display panel includes a substrate 56. A gate metal layer (Gate), a semiconductor layer B, a source / drain metal layer (S / D), and a transparent conductive layer 57 are stacked on one side of the substrate 56. Additionally, 02 and 03 represent insulating layers. For example, the semiconductor layer B is made of A-Si, the transparent conductive layer 57 is made of ITO, and the gate metal layer and the source / drain metal layer (S / D) are made of metals such as copper, aluminum, and molybdenum. The impedance of the materials of the source / drain metal layer (S / D), the gate metal layer (Gate), the transparent conductive layer 57, and the semiconductor layer B increases sequentially. Any one or more of these layers can be provided with a first segment of a resistive structure, and the traces to be connected can be connected through vias.

[0116] For example, the active layer of the first transistor is located on the semiconductor layer B, and the power supply trace is located on the gate metal layer. For instance, the semiconductor layer B and / or the transparent conductive layer 57, which have relatively high material impedance, may be provided with a first segment of a resistive structure.

[0117] In some embodiments, such as Figure 16 As shown, the display panel includes multiple transmission signal traces 40, which are electrically connected to the gate drive circuit. The transmission signal traces 40 include power supply traces 41, which are used to transmit the power supply voltage VDD. Other transmission signal traces 40 can be used to transmit clock signals (CK), trigger signals (STV), reset signals (TRSET), low level (LVGL), etc.

[0118] Along a direction perpendicular to the plane of the display panel, the first line segment 30a overlaps with the transmission signal trace 40 adjacent to the power trace 41. Here, "along a direction perpendicular to the plane of the display panel" can be understood as the thickness direction of the display panel.

[0119] For example, multiple transmission signal traces 40 extend along a first direction X and are arranged in a second direction Y. At least one transmission signal trace 40 is provided on each side of the power supply trace 41 in the second direction Y. The first segment 30a overlaps with the transmission signal traces 40 on both sides of the power supply trace 41, or the first segment 30a overlaps with at least one transmission signal trace 40 on one side of the power supply trace 41. In this solution, no additional area is needed for setting the first segment, preventing an increase in the circuit layout area.

[0120] The first segment 30a overlaps with the transmission signal trace 40 other than the power supply trace 41. At least the overlapping part can form an overlapping capacitor. The overlapping capacitor can also increase the delay effect, thereby avoiding the voltage change of the power supply voltage from directly impacting the first transistor and improving the problem of the first transistor being easily damaged.

[0121] It should be noted that, Figure 16 The number of transmission signal traces 40 and the shape of the first segment 30a shown are not intended to limit this application.

[0122] In other examples, such as Figure 17 As shown, the first line segment 30a and the power supply trace 41 can also be arranged on the same layer. When they are arranged on the same layer, the first line segment 30a can also be designed as a square wave, sawtooth, serpentine, or other shaped bend to increase the length of the first line segment 30a. In this case, the first line segment 30a and the transmission signal trace 40 do not overlap in the direction perpendicular to the plane of the display panel.

[0123] In some other embodiments, such as Figure 18As shown, the display panel includes multiple signal transmission lines 40, which are electrically connected to the gate drive circuit 10. The signal transmission lines 40 include power supply lines 41. Multiple shift registers 11 of the gate drive circuit 10 are arranged along a first direction X. The display panel includes a wiring area Q1, a circuit area Q3, and a resistor area Q2. The signal transmission lines 40 are located in the wiring area Q1, the gate drive circuit 10 is located in the circuit area Q3, and the resistor structure 30 is located in the resistor area Q2. Along a second direction Y, the resistor area Q2 is located between the wiring area Q1 and the circuit area Q3, and the second direction Y intersects the first direction X.

[0124] In the routing area Q1, multiple transmission signal traces 40 extend along the first direction X and are distributed in the second direction Y.

[0125] For example, when different shift registers 11 are connected to different resistor structures 30, multiple resistor structures 30 can be arranged along the first direction X in resistor region Q2.

[0126] For example, in the second direction Y, when the resistor region Q2 is located in the middle, the connection line between the other transmission signal lines 40 (other than the power supply line 41) and the gate drive circuit 10 can pass through the resistor region Q2.

[0127] In this embodiment, the wiring area Q1 is used to set up the transmission signal wiring 40, the circuit area Q3 is used to set up the gate drive circuit, and the resistor area Q2 is used to set up the resistor structure 30. By setting up the partitions, it is convenient to flexibly design the structure in each area.

[0128] Of course, in other examples, it can also be set such that, in the second direction Y, the trace area Q1 is located in the middle, and the resistor area Q2 and the circuit area Q3 are located on both sides of the trace area Q1. Alternatively, the relative positional relationship of the trace area Q1, the circuit area Q3, and the resistor area Q2 can be designed according to other positional relationships.

[0129] In some embodiments, such as Figure 1 As shown, the resistor structure 30 is connected between the shift register 11 and the power supply trace 41. As an example, the display panel includes a power supply trace 41 and a connection line 42. The power supply trace 41 is used to transmit the power supply voltage VDD. Multiple shift registers 11 of the gate drive circuit 10 are arranged along a first direction X. The power supply trace 41 extends along the first direction X. The connection line 42 connects the power supply trace 41 and the first transistor 111; the connection line 42 includes the resistor structure 30.

[0130] For example, the impedance of the connection line 42 is greater than the impedance of the power supply line 41.

[0131] For example, at least a portion of the connecting line 42 may be configured as a zigzag, serrated, serpentine, or other shaped bend.

[0132] like Figure 1 As shown, each shift register 11 is electrically connected to the power supply trace 41 via a connecting line 42, and each connecting line 42 includes a resistor structure 30. In this example, it is ensured that the first transistor of each shift register is connected to the power supply voltage VDD through the resistor structure, thereby protecting the first transistor in each shift register from being easily damaged.

[0133] As another example, such as Figure 19 As shown, when the resistor structure 30 is connected between the shift register 11 and the power supply trace 41, one resistor structure 30 can be connected to the first transistor 111 of multiple shift registers 11. For example, one resistor structure 30 can be connected to the first transistor 111 of two shift registers 11. In this embodiment, one resistor structure 30 is shared by multiple shift registers 11.

[0134] In other embodiments, such as Figure 2 As shown, the resistor structure 30 is connected between the driver chip 200 and the power supply trace 41. Specifically, the display panel includes the power supply trace 41, which is used to transmit the power supply voltage VDD. The power supply trace 41 is electrically connected to at least two shift registers 11 and is connected between the resistor structure 30 and the first transistor 111. The driver chip 200 provides the power supply voltage VDD. The power supply voltage VDD output by the driver chip 200 is first transmitted to the resistor structure 30, then to the power supply trace 41, and then to each of the first transistors 111. It is understood that in this embodiment, the resistor structure 30 is shared by multiple shift registers, which reduces the total number of resistor structures while still protecting the first transistors in the multiple shift registers.

[0135] For example, when the resistor structure is connected between the power supply trace and the first transistor, or when the power supply trace is connected between the resistor structure and the first transistor, the trace shape of the resistor structure includes, but is not limited to, square wave, sawtooth, serpentine, etc., and the film layer position of the resistor structure includes, but is not limited to: at least a portion of the line segment of the resistor structure is located on a different film layer from the power supply trace; at least a portion of the line segment of the resistor structure is located on the same film layer as the active layer of the first transistor; at least a portion of the line segment of the resistor structure is located on a transparent conductive layer; at least a portion of the line segment of the resistor structure is located on the same film layer as the pixel electrode and / or common electrode of the display panel, etc.

[0136] In some embodiments, considering the influence of the impedance of the power supply trace 41 itself on each stage of the shift register, the resistors of the resistor structures connected to at least two different shift registers can be designed to be different.

[0137] For example, such as Figure 20As shown, the multiple shift registers 11 include a first shift register 11-1 and a second shift register 11-2. The resistor structure includes a first sub-resistor structure 30-1 and a second sub-resistor structure 30-2. The first sub-resistor structure 30-1 is connected between the power supply trace 41 and the first shift register 11-1, and the second sub-resistor structure 30-2 is connected between the power supply trace 41 and the second shift register 11-2. The transmission path length of the power supply voltage VDD connected to the first shift register 11-1 in the power supply trace 41 is shorter than the transmission path length of the power supply voltage VDD connected to the second shift register 11-2 in the power supply trace 41. The resistance of the first sub-resistor structure 30-1 is greater than the resistance of the second sub-resistor structure 30-2.

[0138] For example, in the first direction X and in the direction away from the driver chip 200, there are first shift registers 11(1) to nth shift registers 11(n), and the first shift registers 11(1) to nth shift registers 11(n) are connected to power supply traces 41 through first resistor structures 30(1) to nth resistor structures 30(n). The first shift register can be the i-th shift register, the second shift register can be the j-th shift register, and 1≤i<j≤n, where i and j are integers.

[0139] For example, the transmission path length of the power supply voltage VDD connected to the first shift register 11(1) to the nth shift register 11(n) in the power supply trace 41 increases sequentially, and the resistance of the first resistor structure 30(1) to the nth resistor structure 30(n) can decrease sequentially.

[0140] It is understood that the embodiments of this application can balance the impedance of the transmission path of the power supply voltage received by different shift registers, thereby helping to protect the first transistor in the shift register while improving display uniformity.

[0141] In some embodiments, the impedance of the resistive structure can be constant.

[0142] In other embodiments, the impedance of the resistor structure is variable. For example, the impedance of the resistor structure varies under different operating conditions of the display panel. This facilitates meeting the different protection requirements of the first transistor in the shift register under different operating conditions.

[0143] The inventors discovered that higher temperatures increase the conductivity of the active layer in a transistor, leading to increased current flow and greater damage to the first transistor caused by changes in power supply voltage. As an example, the impedance of the resistive structure increases with temperature. This mitigates the problem of the first transistor being easily damaged at high temperatures.

[0144] In some embodiments, such as Figures 5 to 7As shown, the gate and first terminal of the first transistor 111 both need to be connected to the power supply voltage VDD. At least the gate of the first transistor 111 is connected to the power supply voltage VDD through the resistor structure 30. Whether the first transistor conducts or not is mainly affected by its gate potential. Therefore, connecting its gate to the power input signal through the resistor structure can reduce the large current surge that the gate of the first transistor will suffer due to the instantaneous change of the connected power supply voltage. In other words, it avoids the voltage change of the power supply voltage from directly impacting the gate of the first transistor, thereby improving the problem of the first transistor being easily damaged.

[0145] In other examples, such as Figure 21 and Figure 22 As shown, the gate and first terminal of the first transistor 111 are both connected to the power supply voltage VDD through the resistor structure 30. For example, as Figure 21 As shown, the gate and first terminal of the first transistor 111 are connected to the power supply voltage VDD through the same resistor structure 30. Alternatively, as... Figure 22 As shown, the gate and first terminal of the first transistor 111 are connected to the power supply voltage VDD through a different resistor structure 30.

[0146] In some embodiments, the operation of the display panel includes a first stage, in which the power supply voltage VDD is at a first level, and the first level controls the first transistor 111 to turn on. For example, the first transistor 111 is an N-type transistor, and the first level is a high potential Vgh. Alternatively, the first transistor 111 is a P-type transistor, and the first level is a low potential Vgl. Here, the high potential Vgh can be approximately 30V, and the low potential Vgl can be approximately -10V.

[0147] For example, in cases where the operation of the display panel includes a first stage, such as... Figure 6 or Figure 7 As shown, the shift register may consist of only one first transistor.

[0148] In some embodiments, such as Figure 5 As shown, the shift register includes two first transistors, namely transistor M16 and transistor M17. The resistor structure 30 includes a first resistor structure 31 and a second resistor structure 32. The power supply voltage VDD includes a first power supply voltage VDD1 and a second power supply voltage VDD2. One of the first transistors (e.g., transistor M16) is connected to the first power supply voltage VDD1 through the first resistor structure 31, and the other first transistor (e.g., transistor M17) is connected to the second power supply voltage VDD2 through the second resistor structure 32.

[0149] Figure 5The shift register shown includes two pull-down sustaining modules, with the first power supply voltage VDD1 and the second power supply voltage VDD2 each controlling one pull-down sustaining module.

[0150] For example, such as Figure 23 As shown, the first power supply voltage VDD1 and the second power supply voltage VDD2 are signals with alternating high and low levels. Specifically, the operation of the display panel includes an alternately set first stage p1 and second stage p2. In the first stage p1, the first power supply voltage VDD1 is at a first level, and the second power supply voltage VDD2 is at a second level. In the second stage p2, the first power supply voltage VDD1 is at a second level, and the second power supply voltage VDD2 is at a first level. The second level is lower than the first level, and the first level controls the first transistor to be turned on, while the second level controls the first transistor to be turned off. In this embodiment, an N-type transistor is used as an example for illustration. It can be understood that the same applies to P-type first transistors; when the first transistor is a P-type transistor, the first level is lower than the second level.

[0151] The first power supply voltage VDD1 and the second power supply voltage VDD2 are high-low level interleaved signals, so that when one pull-down sustaining module is working, the other pull-down sustaining module is resting, thus allowing each of the two pull-down sustaining modules to rest for half the time, thereby increasing the reliability of the shift register.

[0152] The first power supply voltage VDD1 and the second power supply voltage VDD2 are signals with different timing sequences and can be transmitted using different traces. For example, ... Figure 5 As shown, the display panel also includes a power supply trace 41, which includes a first power supply trace 411 and a second power supply trace 412. The first power supply trace 411 is used to transmit a first power supply voltage VDD1, and the second power supply trace 412 is used to transmit a second power supply voltage VDD2.

[0153] For example, the first resistor structure 31 may be connected between the first power supply line 411 and one of the first transistors, or the first power supply line 411 may be connected between the first resistor structure 31 and one of the first transistors.

[0154] The second resistor structure 32 can be connected between the second power supply line 412 and another first transistor, or the second power supply line 412 can be connected between the second resistor structure 32 and another first transistor.

[0155] The shape, material, and film layer of the first resistor structure 31 and / or the second resistor structure 32 can be described as described in the above embodiment for resistor structure 30, and will not be repeated here.

[0156] In some embodiments, please refer to Figure 23The operation of the display panel also includes a third stage, p3. In the third stage, p3, the first power supply voltage VDD1 undergoes a level transition, and the second power supply voltage VDD2 undergoes a level transition. The third stage, p3, is located between the first stage, p1, and the second stage, p2. Both the first stage, p1, and the second stage, p2, include a frame phase, while the third stage, p3, includes a blanking phase, which is located between two adjacent frame phases. The blanking phase can also be called the blank phase.

[0157] During the framing phase, each shift register of the gate drive circuit outputs a valid pulse signal sequentially, thereby scanning pixels line by line and writing data voltages into the corresponding pixels, allowing the display panel to display normally. During the blanking phase, the gate drive circuit does not output valid pulse signals and no longer writes data voltages. Therefore, the first power supply voltage VDD1 and the second power supply voltage VDD2 are set to undergo level switching during the blanking phase, which will not affect the normal display of the display panel.

[0158] For example, the duration of the first phase p1 is longer than the duration of the third phase p3, and the duration of the second phase p2 is longer than the duration of the third phase p3.

[0159] For example, the duration of the first phase p1 and the second phase p2 are equal.

[0160] The above embodiments describe how adding a resistor structure to the display panel lengthens the voltage change process of the power supply voltage actually received by the first transistor, thereby reducing the large current surge that the first transistor suffers due to excessive instantaneous changes in the power supply voltage.

[0161] Based on the same inventive concept, the power supply voltage output by the driver chip can also be directly changed. For example, by increasing the delay of the change in the power supply voltage output by the driver chip, that is, by increasing the time for the power supply voltage level to switch, the impact on the first transistor when the power supply voltage jumps directly in a short time can be directly avoided, thereby protecting the first transistor from damage.

[0162] Specifically, embodiments of this application also provide a driver chip, such as... Figures 24 to 27 As shown, the driver chip is used to provide a power supply voltage VDD to the gate driving circuit in the display panel. The power supply voltage VDD provided by the driver chip is at a first level in the first stage p1, a second level in the second stage p2, and a third level in the third stage p3. The third stage p3 is located between the first stage p1 and the second stage p2, and the third level is between the first level and the second level. Under the first level, the first transistor in the gate driving circuit is turned on.

[0163] It should be noted that in the timing diagram of this application, the first level is represented as a high potential, the second level as a low potential, and the first transistor as an N-type transistor for illustration, but this is not intended to limit this application. The same applies to P-type first transistors; when the first transistor is a P-type transistor, the first level is a low potential and the second level is a high potential.

[0164] The third stage p3 is the switching stage between the first and second power supply voltage VDD. That is, in this embodiment of the application, the power supply voltage output by the driver chip is directly changed, which increases the time used for switching the power supply voltage level output by the driver chip. This can directly avoid the impact on the first transistor when the power supply voltage jumps directly in a short time, thereby protecting the first transistor from damage.

[0165] In some embodiments, the gate drive circuit is also connected to a clock signal. The time required for the clock signal to switch from the first level to the second level is t2, and the time required for the third stage p3 is t1, where t1 > t2. That is, the time required for the power supply voltage VDD output by the driver chip to switch levels is longer than the time required for the clock signal to switch levels.

[0166] In other examples, the specific duration of the third phase can be set according to requirements.

[0167] In some embodiments, adjacent frames of the display panel include a blanking phase, the third phase is subordinate to the blanking phase, the duration of the third phase p3 is t1, and the duration of the blanking phase is t. blank , t1≤t blank .

[0168] During the framing phase, each stage of the shift registers in the gate drive circuit outputs a valid pulse signal sequentially, thereby scanning pixels line by line, controlling pixel illumination, and enabling normal display on the display panel. During the blanking phase, the gate drive circuit does not output valid pulse signals; therefore, the power supply voltage VDD is set to undergo level switching during the blanking phase, which will not affect the normal display on the display panel.

[0169] In some embodiments, the third level is a gradually changing level. That is, the power supply voltage VDD gradually transitions from the first level to the second level. The smaller the change in power supply voltage VDD, the smaller the current in its transmission path, which is more beneficial for protecting the first transistor.

[0170] As an example, such as Figure 24 As shown, the power supply voltage VDD changes in a step-like manner at the third level of p3 in the third stage.

[0171] Specifically, when the power supply voltage VDD changes in a stepped manner at the third level of p3 in the third stage, the amount of change in the third level can be the same each time. For example, ΔV1 = ΔV2 = ΔV3.

[0172] This embodiment ensures that the Vgs of the first transistor remains the same each time the power supply voltage VDD changes, meaning that the impact on the first transistor is the same, thereby avoiding a large impact on the first transistor.

[0173] As another example, such as Figure 25 As shown, the power supply voltage VDD changes in a slanted line at the third level of p3 in the third stage.

[0174] As yet another example, such as Figure 26 or Figure 27 As shown, the power supply voltage VDD changes in a curve at the third level of p3 in the third stage.

[0175] Optional, such as Figure 26 As shown, the slope of the curve of the power supply voltage VDD changing at the third level of p3 in the third stage gradually decreases.

[0176] It should be noted that the changes in the power supply voltage VDD at the third level of p3 in the third stage include, but are not limited to, the following: Figures 24 to 26 The variations shown are as follows.

[0177] Based on the same inventive concept, a signal delay structure can also be added to the driver chip. For example, the signal delay structure includes a resistor structure to lengthen the voltage change process of the power supply voltage actually received by the first transistor, so as to reduce the large current impact on the first transistor due to the large instantaneous change of the power supply voltage.

[0178] Specifically, such as Figure 28 As shown, the driver chip 200 includes a signal generation circuit 201 and a signal delay structure 202. The signal generation circuit 201 is used to generate a power supply voltage VDD. One end of the signal delay structure 202 is electrically connected to the output terminal of the signal generation circuit 201, and the other end of the signal delay structure 202 is used to electrically connect to the gate driving circuit in the display panel.

[0179] The signal delay structure 202 can lengthen the voltage change process of the power supply voltage actually received by the first transistor, so as to reduce the large current impact on the first transistor caused by the large instantaneous change of the power supply voltage.

[0180] For example, signal delay structure 202 includes a resistor structure.

[0181] This application also provides a display device, including the display panel provided in this application, and / or, including the driver chip provided in the embodiments of this application. Please refer to... Figure 29 , Figure 29 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 29The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application, and / or the driver chip 200 provided in any of the above embodiments of this application. Figure 29 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0182] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-level is high and the off-level is low. That is, when the gate potential of an N-type transistor is high, its first and second terminals are connected; when the gate potential is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the gate potential of a P-type transistor is low, its first and second terminals are connected; when the gate potential is high, its first and second terminals are off.

[0183] In specific implementation, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first electrode can be used as the source and its second electrode as the drain, or its first electrode can be used as the drain and its second electrode as the source. No distinction is made here. In addition, the on-level and off-level in the embodiments of this application are general terms. The on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / turn off the transistor.

[0184] It should be noted that in the embodiments shown in the figures above, the resistor is presented as a single resistor, and the capacitor as a single capacitor. In other embodiments, the resistor may be an integrated combination of series, parallel, or mixed resistors, and the capacitor may be an integrated combination of series, parallel, or mixed capacitors. The specific parameters of each device can be set according to actual needs, and this application does not limit this.

[0185] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, include: A gate driving circuit includes a plurality of cascaded shift registers, each shift register including a first transistor, the first transistor being connected to a power supply voltage through a resistor structure; the gate and first terminal of the first transistor are connected to the power supply voltage, at least the gate of the first transistor is connected to the power supply voltage through the resistor structure; A power trace is provided for transmitting the power supply voltage. The resistor structure is connected between the power trace and the gate of the first transistor, or the resistor structure is connected to the gate of the first transistor through the power trace.

2. The display panel according to claim 1, characterized in that, The resistor structure includes a first trace, wherein at least a portion of the first trace has an impedance per unit length greater than that of the power trace per unit length.

3. The display panel according to claim 1, characterized in that, The resistor structure includes a first trace, the width of which is smaller than the width of the power supply trace.

4. The display panel according to claim 1, characterized in that, The resistor structure includes a first trace, which includes a bend.

5. The display panel according to claim 4, characterized in that, The bends can be any one of the following: square wave, sawtooth, or serpentine.

6. The display panel according to claim 1, characterized in that, The resistor structure includes at least a first line segment, which is located on a different layer from the power supply trace.

7. The display panel according to claim 6, characterized in that, The first line segment comprises a transparent conductive material or a semiconductor material.

8. The display panel according to claim 6, characterized in that, The display panel further includes pixel electrodes and a common electrode, wherein the first line segment is located on the same layer as the pixel electrode, and / or the first line segment is located on the same layer as the common electrode.

9. The display panel according to claim 8, characterized in that, The display panel also includes a substrate; The pixel electrode and the common electrode are located on one side of the substrate; The pixel electrode and the common electrode are located on the same layer, or the film layer containing the pixel electrode is located between the film layer containing the common electrode and the substrate, or the film layer containing the common electrode is located between the film layer containing the pixel electrode and the substrate.

10. The display panel according to claim 6, characterized in that, The first transistor includes an active layer, and the first line segment is located on the same layer as the active layer of the first transistor.

11. The display panel according to claim 6, characterized in that, The display panel includes multiple transmission signal traces, which are electrically connected to the gate driving circuit. The transmission signal traces include the power supply traces. Along a direction perpendicular to the plane of the display panel, the first line segment overlaps with the power supply trace adjacent to the transmission signal trace.

12. The display panel according to claim 6, characterized in that, The resistor structure further includes a second line segment, which is electrically connected to the first line segment and is located on a different layer from the first line segment.

13. The display panel according to claim 1, characterized in that, The display panel connection line, the plurality of shift registers of the gate driving circuit are arranged along the first direction, the power supply trace extends along the first direction, and the connection line is connected between the power supply trace and the first transistor; The connecting line includes the resistor structure.

14. The display panel according to claim 1, characterized in that, The display panel includes multiple transmission signal traces, which are electrically connected to the gate driving circuit. The transmission signal traces include the power supply traces. The multiple shift registers of the gate drive circuit are arranged along a first direction; The display panel includes a trace area, a circuit area, and a resistor area. The transmission signal trace is located in the trace area, the gate driving circuit is located in the circuit area, and the resistor structure is located in the resistor area. Along a second direction, the resistor area is located between the trace area and the circuit area, and the second direction intersects with the first direction.

15. The display panel according to claim 1, characterized in that, The impedance of the resistor structure is variable.

16. The display panel according to claim 15, characterized in that, As the temperature increases, the impedance of the resistive structure increases.

17. The display panel according to claim 1, characterized in that, The plurality of shift registers includes a first shift register and a second shift register. The resistor structure includes a first sub-resistor structure and a second sub-resistor structure. The first sub-resistor structure is connected between the power supply trace and the first shift register. The second sub-resistor structure is connected between the power supply trace and the second shift register. The transmission path length of the power supply voltage connected to the first shift register in the power supply trace is shorter than the transmission path length of the power supply voltage connected to the second shift register in the power supply trace. The resistance of the first sub-resistor structure is greater than the resistance of the second sub-resistor structure.

18. The display panel according to claim 1, characterized in that, The power supply trace is electrically connected to at least two shift registers, and the power supply trace is connected between the resistor structure and the first transistor.

19. The display panel according to claim 1, characterized in that, The operation of the display panel includes a first stage, in which the power supply voltage is a first level, and the first level controls the first transistor to be turned on.

20. The display panel according to claim 1, characterized in that, The resistor structure includes a first resistor structure and a second resistor structure, the shift register includes two first transistors, the power supply voltage includes a first power supply voltage and a second power supply voltage, one of the first transistors is connected to the first power supply voltage through the first resistor structure, and the other first transistor is connected to the second power supply voltage through the second resistor structure. The power trace includes a first power trace and a second power trace. The first power trace is used to transmit the first power voltage, and the second power trace is used to transmit the second power voltage.

21. The display panel according to claim 20, characterized in that, The operation phase of the display panel includes an alternately set first phase and second phase. In the first phase, the first power supply voltage is at a first level and the second power supply voltage is at a second level. In the second phase, the first power supply voltage is at a second level and the second power supply voltage is at a first level. The second level is lower than the first level, and the first level controls the first transistor to be turned on, while the second level controls the first transistor to be turned off.

22. The display panel according to claim 21, characterized in that, The operation phase of the display panel also includes a third phase, in which the first power supply voltage undergoes a level shift and the second power supply voltage undergoes a level shift. The third phase is located between the first phase and the second phase. Both the first phase and the second phase include a frame phase. The third phase includes a blanking phase, which is located between two adjacent frame phases.

23. A driver chip, characterized in that, The power supply voltage provided by the driving chip to the gate driving circuit in the display panel is a first level in a first stage, a second level in a second stage, and a third level in a third stage. The third stage is located between the first stage and the second stage, and the third level is between the first level and the second level. Under the first level, the first transistor in the gate driving circuit is turned on, and under the second level, the first transistor is turned off.

24. The driver chip according to claim 23, characterized in that, The third level is a gradually changing level.

25. The driver chip according to claim 24, characterized in that, The third level changes in a stepped manner.

26. The driver chip according to claim 25, characterized in that, The amount of change in the third level is the same each time.

27. The driver chip according to claim 24, characterized in that, The third level changes in a diagonal line.

28. The driver chip according to claim 24, characterized in that, The third level changes in a curve.

29. The driver chip according to claim 28, characterized in that, The slope of the curve representing the change in the third level gradually decreases.

30. The driver chip according to claim 23, characterized in that, The display panel includes a blanking phase between adjacent frames, the blanking phase including the third phase, the duration of the third phase being t1, and the duration of the blanking phase being t. blank , t1≤t blank .

31. The driver chip according to claim 24, characterized in that, The gate drive circuit is also connected to a clock signal. The time required for the clock signal to change from the first level to the second level is t2, and the time of the third stage is t1, where t1 > t2.

32. A display device, characterized in that, include: The display panel according to any one of claims 1 to 22, and / or the driver chip according to any one of claims 23 to 31.

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