Micro semiconductor device and electronic device thereof

Abstract

The invention relates to a micro-semiconductor device and an electronic device thereof. The invention provides a micro-semiconductor stacked structure which comprises at least two stacked structure array units, and one stacked structure array unit is stacked on the other stacked structure array unit. Wherein one of the stacked structure array units is stacked along the vertical direction of the other stacked structure array unit; each stacked structure array unit comprises a base material, a conductive pattern layer arranged on the base material, and a plurality of micro semiconductor devices arranged on the base material and electrically connected with the conductive pattern layer.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202010273033.9 (application date: April 9, 2020, invention name: micro-semiconductor stacked structure and its electronic device). Technical Field

[0002] The invention relates to an electronic device, in particular to an electronic device composed of a micro-semiconductor stacking structure array. Background Art

[0003] Generally, semiconductor arrays are arranged along a plane. With the demand for smaller components, the continuous improvement of process capabilities has enabled the process to achieve smaller line widths, which has always been the goal of semiconductor-related manufacturers. However, as the industry considers the balance between cost and equipment investment, the advancement of minimum line width has slowed down.

[0004] Take micro-LED display technology as an example. Figure 1 , the three micro-LEDs of red, green and blue light are three sub-pixels 110a, 120a and 130a respectively, which are arranged adjacent to each other in a plane to form a pixel 100a, and a plurality of pixel 100a arrays form a display 200a. Taking three micro-LEDs of the same size as an example, the micro-LEDs have a length L and a width W. The unit area of ​​the pixel 100a is limited by the total width 3W after the sub-pixels are combined. The pixel width P after the combination is slightly larger than 3W, and the pixel area P*P is slightly larger than 3W*3W. With the pursuit of high resolution (more pixels in a limited area), the length and width of pixels have been reduced to micron level. Even so, they still suffer from cost and technical bottlenecks, and the industry is in urgent need of proposing a new solution. Summary of the invention

[0005] In view of this, the present invention proposes a micro-semiconductor stacking structure and an electronic device thereof, which can reduce the minimum area of ​​the micro-semiconductor stacking structure as a unit and increase the density of the micro-semiconductor stacking structure array within the limited area of ​​the electronic device.

[0006] In view of this, the present invention proposes a micro-semiconductor stacking structure and an electronic device thereof, which can achieve low cost and high resolution within a limited area of ​​the electronic device.

[0007] A micro semiconductor stacking structure includes at least two stacking structures, one of which is stacked on the other stacking structure. One of the stacking structures is stacked in a vertical direction of the other stacking structure; each stacking structure includes a substrate, a conductive layer disposed on the substrate, and at least one micro semiconductor device disposed on the substrate and electrically connected to the conductive layer. Each stacking structure defines a target area, and the micro semiconductor device of each stacking structure is disposed in the target area. The target areas between the two stacking structures are aligned with each other in a vertical direction; in at least one of the at least two stacking structures, the conductive layer is an active circuit.

[0008] A micro semiconductor stacking structure includes three stacking structures, wherein two stacking structures are stacked on the bottom stacking structure; wherein: the two stacking structures are stacked in a vertical direction of the bottom stacking structure; each stacking structure includes a substrate, a conductive layer disposed on the substrate, and at least one micro light emitting diode chip disposed on the substrate and electrically connected to the conductive layer. Each stacking structure defines a pixel, and at least one micro light emitting diode chip in each stacking structure is disposed in the pixel; the target areas between the stacking structures are aligned with each other in a vertical direction; in at least one stacking structure of the three stacking structures, the conductive layer is an active circuit.

[0009] In some embodiments, a micro-semiconductor stack structure further has at least one step; along a direction toward an upper stack structure or away from a lower stack structure, the at least one step is formed by the sizes of the substrates gradually decreasing.

[0010] In some embodiments, in a micro-semiconductor stack structure, each conductive layer of the stacked structure is connected by an electrical connection component.

[0011] In some embodiments, a micro semiconductor stack structure has at least one step with an electrical connection component; and each conductive layer of the stacked structure is connected by the electrical connection component.

[0012] In some embodiments, a micro semiconductor stack structure, the size of the micro semiconductor device ranges from 1 to 50 um. In some embodiments, a micro semiconductor stack structure, the size of the micro light emitting diode chip ranges from 1 to 50 um.

[0013] In some embodiments, in a micro-semiconductor stacked structure, the substrate of the stacked structures is transparent; or, the substrate of the bottommost stacked structure is non-transparent.

[0014] In some embodiments, a micro-semiconductor stack structure, the substrate is a hard substrate, a flexible substrate, or a dielectric layer formed by a semiconductor coating process.

[0015] In some embodiments, in a micro-semiconductor stacked structure, the bottommost conductive layer of the stacked structure is an active circuit having a TFT or MOS switch.

[0016] In some embodiments, a micro-semiconductor stacked structure, each micro-semiconductor device in the stacked structure is a micro-light emitting diode chip, a micron-scale light sensing chip, or a combination thereof.

[0017] In some embodiments, a micro-semiconductor stacking structure, along the direction toward the upper stacking structure or away from the lower stacking structure, the micro-semiconductor devices of the three stacking structures are red, green, and blue micro-light-emitting diode chips in layers, and the light-emitting sides of these micro-light-emitting diode chips are close to the upper stacking structure or away from the lower stacking structure.

[0018] In some embodiments, in a micro-semiconductor stack structure, two stacked structures are bonded together by adhesive.

[0019] In some embodiments, a micro-semiconductor stack structure, the glue material planarizes the lower layer stack structure.

[0020] A micro-semiconductor stacking structure includes at least two stacked structure array units, wherein one stacked structure array unit is stacked on another stacked structure array unit; one stacked structure array unit is stacked along the vertical direction of the other stacked structure array unit, each stacked structure array unit includes a substrate, a conductive layer, and a plurality of micro-semiconductor devices arranged in an array on the substrate; each stacked unit includes a matrix circuit, and these micro-semiconductor devices are electrically connected to the matrix circuit. Each stacked structure array unit defines a plurality of target areas arranged in an array; in each stacked structure array unit, at least one of these micro-semiconductor devices corresponds to and is located in one of these target areas; between two stacked structure array units, the target areas of the upper stacked structure array unit individually correspond to and are aligned with the target areas of the lower stacked structure array unit along the vertical direction; in at least one of the three stacked structure array units, the matrix circuit of the conductive layer is an active matrix circuit.

[0021] A micro semiconductor stacking structure includes three stacked structure array units, wherein two stacked structure array units are stacked on the bottom stacked structure array unit; wherein: the two stacked structure array units are stacked along the vertical direction of the bottom stacked structure array unit, each stacked structure array unit includes a substrate, a conductive layer, and a plurality of micro light emitting diode chips arranged in an array on the substrate; the conductive layers include a matrix circuit, and the micro light emitting diode chips are electrically connected to the matrix circuit. Each stacked structure array unit is defined with a plurality of pixels arranged in an array, and in each stacked structure array unit, at least one of the micro light emitting diode chips corresponds to and is located in one of the pixels; between two stacked structure array units, the pixels of the upper stacked structure array unit correspond to and are aligned with the pixels of the lower stacked structure array unit in the vertical direction; in at least one of the three stacked structure array units, the matrix circuit of the conductive layer is an active matrix circuit.

[0022] In some embodiments, a micro semiconductor stack structure further has at least one step; wherein: along a direction toward an upper stack structure array unit or away from a lower stack structure array unit, the at least one step is formed by the sizes of the substrates gradually shrinking.

[0023] In some embodiments, in a micro semiconductor stacked structure, between two stacked structure array units, the conductive layer of the upper stacked structure array unit is connected to the conductive layer of the lower stacked structure array unit by at least one electrical connection component.

[0024] In some embodiments, a micro-semiconductor stacking structure has at least one step with an electrical connection component; between two stacked structure array units, the conductive layer of the upper stacked structure array unit is connected to the conductive layer of the lower stacked structure array unit by the electrical connection component.

[0025] A micro-semiconductor stacking structure, wherein the size of the micro-semiconductor device ranges from 1 to 50 um.

[0026] In some embodiments, in a micro semiconductor stack structure, the size of each micro light emitting diode chip is in the range of 1-50 um.

[0027] In some embodiments, in a micro-semiconductor stacked structure, the substrate of the stacked structure array units is transparent; or, the substrate of the bottom stacked structure array unit is non-transparent.

[0028] In some embodiments, in a micro-semiconductor stacking structure, the substrate of these stacked structure array units is a hard substrate or a flexible substrate.

[0029] In some embodiments, in a micro semiconductor stack structure, two stacked structure array units are bonded together by adhesive.

[0030] In some embodiments, a micro-semiconductor stack structure, the glue material planarizes the lower layer stack structure.

[0031] In some embodiments, in a micro semiconductor stacked structure, the substrate of these stacked structure array units is a dielectric layer formed by a semiconductor coating process.

[0032] In some embodiments, in a micro-semiconductor stacked structure, the conductive layer of the bottommost stacked structure array unit is an active matrix circuit with TFT or MOS switches.

[0033] In some embodiments, a micro-semiconductor stacked structure, the micro-semiconductor device of each stacked structure array unit is a micro-light emitting diode chip, a micron-scale light sensing chip, or a combination thereof.

[0034] In some embodiments, a micro-semiconductor stacking structure, along the direction toward the upper stacking structure array unit or away from the lower stacking structure array unit, three-layer stacking structure array units are arranged with red, green, and blue micro-light-emitting diode chips according to the unit, and the light-emitting sides of these micro-light-emitting diode chips are close to the upper stacking structure array unit or away from the lower stacking structure array unit.

[0035] In some embodiments, an electronic device includes a plurality of micro-semiconductor stacked structures arranged in an array, and an external electrical control structure electrically connected to the conductive layer of at least one stacked structure.

[0036] In some embodiments, an electronic device includes a micro-semiconductor stack structure, and an external electrical control structure electrically connected to at least one conductive layer of the stack structure.

[0037] In some embodiments, an electronic device includes a micro-semiconductor stacked structure, and at least one external electrical control structure electrically connected to the conductive layer of at least one stacked structure array unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a schematic top view of a conventional electronic device;

[0039] Figure 2 is a schematic top view of a first embodiment of an electronic device composed of a plurality of micro-semiconductor stacked structure arrays according to the present invention;

[0040] Figure 3A , Figure 3B They are respectively a manufacturing schematic diagram and a structural schematic diagram of a micro-semiconductor stack structure according to a first embodiment of the present invention;

[0041] Figure 4A , Figure 4B They are respectively a manufacturing schematic diagram and a structural schematic diagram of a micro-semiconductor stack structure according to a second embodiment of the present invention;

[0042] Figure 5 A schematic diagram of manufacturing and a schematic diagram of the structure of a micro-semiconductor stack structure according to a third embodiment of the present invention;

[0043] Figure 6 A schematic diagram of manufacturing and a schematic diagram of the structure of a micro-semiconductor stack structure according to a fourth embodiment of the present invention;

[0044] Figure 7 A schematic structural diagram of a micro-semiconductor stack structure according to a fifth embodiment of the present invention;

[0045] Figure 8 A schematic structural diagram of a micro-semiconductor stack structure according to a sixth embodiment of the present invention;

[0046] Fig. 9 is a schematic structural diagram of an electronic device according to a sixth embodiment of the present invention;

[0047] Fig. 10A A schematic diagram of manufacturing a micro-semiconductor stack structure according to a seventh embodiment of the present invention;

[0048] Fig. 10B is a schematic structural diagram of an electronic device composed of a micro-semiconductor stacking structure according to a seventh embodiment of the present invention;

[0049] Fig.11 is a schematic structural diagram of an electronic device composed of a micro-semiconductor stacking structure according to an eighth embodiment of the present invention;

[0050] Fig.12 is a schematic structural diagram of an electronic device composed of a micro-semiconductor stacking structure according to a ninth embodiment of the present invention;

[0051] Fig.13 is a schematic structural diagram of an electronic device composed of a micro-semiconductor stacking structure according to a tenth embodiment of the present invention; and

[0052] Fig.14 FIG. 1 is a schematic structural diagram of an electronic device composed of a micro-semiconductor stacking structure according to an eleventh embodiment of the present invention. DETAILED DESCRIPTION

[0053] A micro-semiconductor stack structure and an electronic device thereof according to a preferred embodiment of the present invention will be described below with reference to the related drawings, wherein the same elements will be described with the same reference numerals.

[0054] The present invention discloses a micro-semiconductor stacking structure, comprising at least two stacking structures: one of the stacking structures is superimposed on the other stacking structure; one of the stacking structures is superimposed along the vertical direction of the other stacking structure. Each stacking structure comprises a substrate, a conductive layer disposed on the substrate, and at least one micro-semiconductor device disposed on the substrate and electrically connected to the conductive layer. Each stacking structure defines a target area, and at least one micro-semiconductor device of each stacking structure is disposed within the target area; the target areas between the two stacking structures are aligned with each other along the aforementioned vertical direction; and in at least one of the at least two stacking structures, the conductive layer is an active circuit. The above-mentioned micro-semiconductor stacking structure can be illustrated by the following embodiments:

[0055] [First embodiment]

[0056] The present invention discloses a micro semiconductor stacking structure including three stacking structures, wherein two stacking structures are stacked on the bottom stacking structure; wherein the two stacking structures are stacked along the vertical direction of the bottom stacking structure; each stacking structure includes a substrate, a conductive layer disposed on the substrate, and a micro light emitting diode chip disposed on the substrate and electrically connected to the conductive layer. Each stacking structure defines a pixel, and the micro light emitting diode chip in each stacking structure is disposed within the pixel; the target areas between the stacking structures are aligned with each other along the aforementioned vertical direction; in at least one of the three stacking structures, the conductive layer is an active circuit. For detailed description, please also refer to Figure 2 and Figure 3A , 3B , discloses a micro-semiconductor stacked structure 10 and an electronic device 20 thereof according to a first embodiment of the present invention. In this embodiment, the electronic device 20 is a color display unit.

[0057] like Figure 3B The micro-semiconductor stacking structure 10 has a first stacking structure 12, a second stacking structure 14, and a third stacking structure 16; wherein, taking one of the three stacking structures as a reference, a vertical direction Z is defined, and the other two stacking structures are sequentially stacked on the aforementioned stacking structure along the aforementioned vertical direction Z. In the micro-semiconductor stacking structure 10 of this embodiment, the first stacking structure 12 is defined with a first direction X and a second direction Y constituting a plane, and a vertical direction Z orthogonal to the aforementioned plane; the second and third stacking structures 14 and 16 are sequentially stacked on the first stacking structure 12 along the vertical direction Z taking the first stacking structure 12 as a reference, and the third stacking structure 16 is stacked on the second stacking structure 14.

[0058] The first stacked structure 12 comprises a first substrate 122, a first conductive layer 124 disposed on the first substrate 122, and a first micro-semiconductor device 126 disposed on the first substrate 122 and electrically connected to the first conductive layer 124; the second stacked structure 14 comprises a second substrate 142, a second conductive layer 144 disposed on the second substrate 142, and a second micro-semiconductor device 146 disposed on the second substrate 142 and electrically connected to the second conductive layer 144; the third stacked structure 16 comprises a third substrate 162, a third conductive layer 164 disposed on the third substrate 162, and a third micro-semiconductor device 166 disposed on the third substrate 162 and electrically connected to the third conductive layer 164. In the micro-semiconductor stacked structure 10 of the present embodiment, the first substrate 122, the second substrate 142, and the third substrate 162 are hard transparent substrates, such as glass, quartz, sapphire or equivalents thereof, and the thickness of the hard transparent substrates ranges from 10 to 500 micrometers. In the first conductive layer 124, the second conductive layer 144 and the third conductive layer 164, at least one conductive layer is an active circuit including a TFT or a MOS switch; in the micro-semiconductor stacked structure 10 of the present embodiment, the first conductive layer 124 is an active circuit provided with a TFT or a MOS switch. The first micro-semiconductor device 126, the second micro-semiconductor device 146 and the third micro-semiconductor device 166 are respectively micro-LED chips with different light emission wavelengths, i.e., red, green and blue monochromatic micro-LED chips, with a size range of 1-50um, and are not limited to vertical or flip-chip micro-LED chips; the light-emitting side of the micro-LED chip is close to the upper stacked structure or away from the lower stacked structure.

[0059] Each stacked structure 12, 14, 16 defines a pixel, and the micro-semiconductor devices 126, 146, 166 in each stacked structure 12, 14, 16 are arranged in the pixel (that is, the micro-light-emitting diode chip is arranged in the target area); these pixels between the stacked structures 12, 14, 16 are aligned with each other along the vertical direction Z (that is, the target areas need to be aligned with each other).

[0060] In this embodiment, the sizes of the first, second, and third substrates 122, 142, and 162 are gradually reduced in sequence, so that the first substrate 122 defines a first step region 1222, and the second substrate 142 defines a second step region 1422. After the first, second, and third stacked structures 12, 14, and 16 are stacked, the first step region 1222 and the second step region 1422 may not be hidden, and may be formed as shown in FIG. Figure 3BThe first and second step portions 102 and 104 of the micro semiconductor stack structure 10 are shown. In this embodiment, the first conductive layer 124 extends to the first step region 1222 of the first substrate 122; the second conductive layer 144 extends to the second step region 1422 of the second substrate 142; the first and second step portions 102 and 104 formed above can be used to set electrical connection components between the two stacked structures by wires or metal bumps or holes filled with conductive materials. In this embodiment, wires are used as electrical connection components 18. Whether the first and second conductive layers 144 and 164 extend to the first and second step regions 1222 and 1422 respectively is not a question of the present invention, but the question is whether the electrical connection component 18 is sufficient to electrically connect the conductive layers in any two layers of the stacked structure; wherein, whether the electrical connection component 18 is a wire, a metal bump or a hole is not a question, but the question is whether the electrical connection component 18 electrically connects the first, second, and third conductive layers 124, 144, 164.

[0061] Among them, Figure 3B In the first, second, and third stacked structures 12, 14, and 16 of the micro-semiconductor stacking structure 10, the stacked structures stacked in pairs can be connected to each other; in this embodiment, the stacked structures stacked in pairs are bonded together by an adhesive 19, and the present invention does not limit the adhesive 19 to be solid or liquid, but it is sufficient to be bonded between the stacked structures stacked in pairs; in this embodiment, the adhesive 19 can flatten the lower stacked structure, but the present invention is not limited to this.

[0062] In detail, the manufacturing method of the micro semiconductor stacking structure 10 of the present invention is as follows: Figure 3A First, the first, second, and third micro-semiconductor devices 126, 146, 166 are placed on three hard and transparent first, second, and third substrates 122, 142, 162 with first, second, and third conductive layers 124, 144, 164, respectively, to form the first, second, and third stacked structures 12, 14, 16. The size of each substrate 122, 142, 162 is based on the actual application size. In other words, under the unrestricted array transfer method, the same color micro-LED array (such as an array composed of red micro-LED chips) is transferred to a target carrier (large substrate) (not shown), and then the target carrier (large substrate) is cut along the micro-LED chips of that color (such as along each red micro-LED chip), and each micro-LED chip is first formed and placed on the corresponding substrate 122, 142, 162 (such as the red micro-LED chip 126 is placed on the first substrate 122); it is worth noting that a single substrate 122, 142, 162 only carries a single-color micro-LED chip, and the relationship between the material of the substrate 122, 142, 162 and the light-emitting wavelength of the carried micro-LED chip is not limited.

[0063] Afterwards, each micro-LED chip can be tested through the conductive layers 124, 144, 164 on the corresponding substrates 122, 142, 162, and the micro-LED chips of each color can be further screened according to the needs, such as by color, wavelength, and brightness; it is worth noting that the micro-semiconductor stacked structure 10 of the present invention can first screen out defective products in this step, rather than as Figure 1 The commonly used micro-LED display technology requires that the three sub-pixels 110a, 120a, and 130a be combined into one pixel 100a before they can be screened. Then, one of the first, second, and third stacked structures 12, 14, and 16 after classification is selected and stacked to form the micro-semiconductor stacked structure 10 of this embodiment. The stacked structures 12, 14, and 16 stacked in pairs can be bonded to each other according to the selection of materials, or as in this embodiment, the stacked structures 12, 14, and 16 stacked in pairs can be bonded with an adhesive 19 that can flatten the lower stacked structure.

[0064] When the target carrier (large substrate) is cut into substrates 122, 142, and 162, the cutting size can be determined according to the requirements of each color and gradually reduced in sequence; taking this embodiment as an example, the size of the first substrate 122 for setting the red micro-LED chip is larger than the size of the second substrate 142 for setting the green micro-LED chip, and the size of the second substrate 142 for setting the green micro-LED chip is larger than the size of the third substrate 162 for setting the blue micro-LED chip, so as to facilitate the formation of the first and second step portions 102 and 104. After the first and second step portions 102 and 104 are formed, the first and second step portions 102 and 104 are provided with an electrical connection component 18 formed by a lead, a metal bump, or a hole filling method, so as to provide a signal link between other stacked structures and the stacked structure with a TFT or MOS switch (such as between the first and second stacked structures 12 and 14, between the second and third stacked structures 14 and 16, or between the first and third stacked structures 12 and 16).

[0065] Before the target carrier (large substrate) is cut into substrates 122, 142, 162, a plurality of conductive layers 124, 144, 164 are preset on the target carrier (large substrate). After the target carrier (large substrate) is cut, each substrate is provided with a conductive layer (e.g., each first substrate 122 is provided with a first conductive layer 124). The conductive layer is not limited to an active circuit or a passive circuit; but at least one of the conductive layers is an active circuit; it is worth noting that in the present embodiment, the first conductive layer 124 is an active circuit, provided with a TFT or MOS switch.

[0066] Further connecting the electrical connection component 18 to an external electrical control structure (not shown) can achieve the electronic device 20 illustrated in this embodiment with a color display unit as an example. Figure 1Compared with the commonly used micro-LED display technology, the pixel area P*P of the commonly used micro-LED display technology is slightly larger than 3W*3W; Figure 1 There are 4 pixels in a limited area. The micro-semiconductor stacking structure 10 of this embodiment is composed of the first, second, and third stacking structures 12, 14, and 16 with three-color (R, G, B) micro-LEDs. Taking three micro-LED devices of the same size as an example, the pixel width P' of this embodiment is slightly larger than L, and the pixel area P'*P' is slightly larger than L*L, which is obviously smaller than the pixel area P*P of slightly larger than 3W*3W in the commonly used micro-LED display technology. Therefore, the present invention can effectively reduce the pixel area; the electronic device 20 of this embodiment is composed of a plurality of micro-semiconductor stacking structures 10 arranged in an array, which is a color display unit, such as Figure 2 As shown, close to Figure 1 Under the condition of limited area, the unit area of ​​each micro-semiconductor stack structure 10 of the present invention is reduced, thereby increasing the pixel density distributed in the electronic device 20. Figure 1 In the commonly used micro-LED display technology, there are 4 pixels in a predetermined limited area, and Figure 2 The electronic device 20 shown may provide up to 9 pixels, which obviously improves the resolution.

[0067] It is worth noting that this embodiment can also provide a redundancy mechanism in accordance with application requirements, so that a single pixel has two micro-LED chips of the same color; wherein, in each stacked structure, the two micro-LED chips of the same color correspond to the same pixel and are driven by the aforementioned conductive layer. Here, the probability of two micro-LED chips failing at the same time is extremely low, thereby improving the process yield of the present invention. In addition, this redundancy mechanism should be applicable to each embodiment of the present invention.

[0068] It is worth noting that along the direction toward the upper stacking structure or away from the lower stacking structure, these micro semiconductor devices 126, 146, 166 of the first, second, and third stacking structures 12, 14, 16 should be red (R), green (G), and blue (B) micro light-emitting diode chips respectively, and the light-emitting sides of these micro light-emitting diode chips are close to the upper stacking structure or away from the lower stacking structure.

[0069] from Figure 2 It can be seen that the electronic device 20 of this embodiment is a color display unit, which can maintain Figure 1The commonly used micro-light-emitting diode display technology has a higher resolution in the same limited area; wherein, the electronic device 20 itself can be a color display module that is waiting to be spliced ​​and can display together, or a color display that can display separately, or its equivalent device, which is not the subject of the present invention. The only requirement is that the electronic device 2 is composed of an array arrangement of micro-semiconductor stacked structures 10.

[0070] [Second embodiment]

[0071] See also Figure 2 and Figure 4A , Figure 4B , discloses a micro-semiconductor stacking structure 10a of a second embodiment of the present invention, and an electronic device 20a composed of a plurality of micro-semiconductor stacking structures 10a arrays. In this embodiment, the micro-semiconductor stacking structure 10a and the electronic device 20a are similar to the micro-semiconductor stacking structure 10 and the color display unit of the first embodiment; only the differences from the first embodiment are disclosed below: Figure 4A The micro-semiconductor stacking structure 10a has a first stacking structure 12a, a second stacking structure 14a, and a third stacking structure 16a; the first substrate 122a of the first stacking structure 12a, the second substrate 142a of the second stacking structure 14a, and the third substrate 162a of the third stacking structure 16a are all soft transparent substrates, such as Polyimide, PEN, PET or their equivalents, and the thickness of the soft transparent substrate ranges from 5 to 100 microns.

[0072] Will Figure 4A According to the requirements, one of the first, second, and third stacked structures 12a, 14a, and 16a is selected and stacked to form Figure 4B In this embodiment, the sizes of the first, second and third substrates 122a, 142a and 162a are also gradually reduced in sequence, so that the first substrate 122a defines a first step region 1222a, and the second substrate 142a defines a second step region 1422a; since the substrates 122a, 142a and 162a of this embodiment are all soft transparent substrates, after the first, second and third stacked structures 12a, 14a and 16a are stacked, not only the first and second step regions 1222a and 1422a are not hidden, but also the first and second step regions 1222a and 1422a are formed as shown in FIG. Figure 4B As shown in the first and second step portions 102a, 104a of the micro semiconductor stacked structure 10a, the third stacked structure 16a further forms at least one third step portion 106a along the surface morphology of the second stacked structure 14a.

[0073] The stacked structures are bonded with adhesive 19a. The adhesive 19a can further have a flattening capability. After flattening the lower stacked structure, it can be bonded with the upper stacked structure. The flattening effect can be seen in Figure 3B as shown; or Figure 4B The adhesive material 19a of the present embodiment shown does not have a planarization capability, so each layer will be completely adhered to the surface morphology of the underlying stacked structure.

[0074] In this embodiment, the filled holes are used as the electrical connection components 18a to electrically connect the conductive layers between two stacked structures.

[0075] [Third embodiment]

[0076] See also Figure 2 and Figure 5 , discloses a micro semiconductor stacking structure 10b and an electronic device 20b of a third embodiment of the present invention. In this embodiment, the micro semiconductor stacking structure 10b is a mixture of the materials, processes and structures of the micro semiconductor stacking structure 10 of the first embodiment and the micro semiconductor stacking structure 10a of the third embodiment; only the differences from the first and third embodiments are disclosed below: Figure 5 The micro-semiconductor stacking structure 10b has a first stacking structure 12b, a second stacking structure 14b and a third stacking structure 16b; the first stacking structure 12b uses the first substrate 122 in the micro-semiconductor stacking structure 10 of the first embodiment, and the second stacking structure 14b and the third stacking structure 16b both use the second substrate 142a and the third substrate 162a in the micro-semiconductor stacking structure 10a of the third embodiment. The first substrate 122b of the hard transparent substrate is, for example, glass, quartz, sapphire or its equivalent, and the thickness of the hard transparent substrate ranges from 10 to 500 microns; the second substrate 142b and the third substrate 162b of the soft transparent substrate are, for example, Polyimide, PEN, PET or its equivalent, and the thickness of the soft transparent substrate ranges from 5 to 100 microns. In this embodiment, the lead wire is used as an electrical connection component to electrically connect the conductive layers between the two stacking structures.

[0077] In addition, the first substrate 122b may also be a non-transparent substrate, such as a silicon wafer or other substrate that is not transparent to visible light. The second and third substrates 142 and 162b other than the first substrate 122b are all transparent materials that allow visible light to pass. Here, the use of each stacking structure of soft and hard transparent substrates is not limited to this embodiment. For example, the substrates of two stacking structures are both hard transparent substrates, and the substrate of the other stacking structure is a soft transparent substrate; or the first substrate 122b is a hard opaque substrate, and the substrates of the other two stacking structures are both hard transparent substrates; or the substrate of at least one stacking structure includes both hard and soft transparent substrates. This embodiment is intended to illustrate that the substrates of each stacking structure can each be implemented in different forms, but on the premise that the light emission of the micro-LED is not blocked.

[0078] [Fourth embodiment]

[0079] See also Figure 2 and Figure 6 , discloses a micro semiconductor stacking structure 10c and an electronic device 20c thereof according to a fourth embodiment of the present invention. Figure 6 The micro-semiconductor stacking structure 10c has a first stacking structure 12c, a second stacking structure 14c, and a third stacking structure 16c; wherein, in a vertical direction Z based on the first stacking structure 12c, the second and third stacking structures 14c and 16c are sequentially stacked on the first stacking structure 12c.

[0080] The first stacked structure 12c has a first substrate 122c, a first conductive layer 124c disposed on the first substrate 122c, and a first micro semiconductor device 126c disposed on the first substrate 122c and electrically connected to the first conductive layer 124c. The first substrate 122c is a hard transparent or opaque substrate, such as transparent glass, quartz, sapphire, or a non-transparent substrate such as a silicon wafer; the first conductive layer 124c is an active circuit with a TFT or MOS switch; the first, second, and third micro semiconductor devices 126c, 146c, 166c can be red, green, and blue micro light emitting diode chips. The second stacked structure 14c has a second substrate 142c, a second conductive layer 144c disposed on the second substrate 142c, and a second micro semiconductor device 146c disposed on the second substrate 142c and electrically connected to the second conductive layer 144c. The third stacked structure 16c includes a third substrate 162c, a third conductive layer 164c disposed on the third substrate 162c, and a third micro semiconductor device 166c disposed on the third substrate 162c and electrically connected to the third conductive layer 164c.

[0081] The process and sequence of the stacking structure in this embodiment are slightly different from the previous embodiment: the previous embodiment completes the micro-semiconductor device and the conductive layer on the substrate to form a stacking structure, and each stacking structure is used as an implementation unit to stack in sequence to form a micro-semiconductor stacking structure; while this embodiment separates the steps of each stacking structure, takes each step as an implementation unit, and forms a micro-semiconductor stacking structure after performing individual steps one by one. The implementation steps of this embodiment are as follows: after the first micro-semiconductor device 126c is transferred to the first substrate 122c, a second substrate 142c as a dielectric layer and a second conductive layer 144c as a metal circuit are prepared by performing a semiconductor coating process (such as spin-on-glass), and then the second micro-semiconductor device 146c is transferred to the second substrate 142c, and the second micro-semiconductor device 146c is electrically connected to the second conductive layer 144c. The previous procedure is repeatedly performed. After the second micro-semiconductor device 146c is transferred to the second substrate 142c, a semiconductor coating process is performed to produce a third substrate 162c as a dielectric layer and a third conductive layer 164c as a metal circuit. The third micro-semiconductor device 166c is then transferred to the third substrate 162c and electrically connected to the third conductive layer 164c.

[0082] In this embodiment, during the semiconductor coating process, the vias are also filled using a semiconductor process to serve as the electrical connection component 18c. Therefore, the vias filled using a semiconductor process in this embodiment can provide signal links between other stacked structures and stacked structures with TFTs or MOS switches (such as between the first and second stacked structures 12c and 14c, between the second and third stacked structures 14c and 16c, or between the first and third stacked structures 12c and 16c). However, the electrical connection component is not only applicable to this embodiment, and the electrical connection component in this embodiment is not limited to the vias.

[0083] In the present embodiment, the second and third substrates 142c and 162c implemented as dielectric layers using liquid polyimide can have the ability to planarize the lower stacked structure and can also bond the lower stacked structure at the same time.

[0084] In detail, after the first micro-semiconductor device 126c is transferred to the first substrate 122c, the first conductive layer 124c is now an active circuit with a TFT or MOS switch, and the subsequent process sequence is as follows: (1) a dielectric layer is made as the second substrate 142c to isolate the first micro-semiconductor device 126c, and the layers are connected by filling holes. The dielectric layer material can be liquid polyimide, SiO2, SiN, SiON and other materials; (2) the distribution circuit of the second micro-semiconductor device 146c is made on the dielectric layer. (3) transferring the second micro-semiconductor device 146c so that the assembly of the second substrate 142c, the second conductive layer 144c and the second micro-semiconductor device 146c is equivalent to the second stacking structure 14c; and, (4) and so on, repeating steps (1)-(3) so that the assembly of the third substrate 162c, the third conductive layer 164c and the third micro-semiconductor device 166c is equivalent to the third stacking structure 16c, thereby, these stacking structures form a micro-semiconductor stacking structure 10c.

[0085] [Fifth embodiment]

[0086] See also Figure 7 , discloses a fifth embodiment of the present invention. A micro semiconductor stacked structure 10d has a first stacked structure 12d, and a second stacked structure 14d stacked in a vertical direction Z based on the first stacked structure 12d. The first stacked structure 12d has a first substrate 122d, a first conductive layer 124d disposed on the first substrate 122d, and a first micro semiconductor device 126d disposed on the first substrate 122d and electrically connected to the first conductive layer 124d. The second stacked structure 14d has a second substrate 142d, a second conductive layer 144d disposed on the second substrate 142d, and a second micro semiconductor device 146d disposed on the second substrate 142d and electrically connected to the second conductive layer 144d. Among them, the first substrate 122d is a soft transparent substrate, or a hard transparent or non-transparent substrate; the first conductive layer 124d is an active circuit with a TFT or MOS switch; the second substrate 142d is a soft or hard transparent substrate; the first micro-semiconductor device 126d and the second micro-semiconductor device 146d can respectively select micron-level optical sensors that can detect different wavelengths, such as infrared micro-sensor chips and ultraviolet micro-sensor chips. Therefore, the electronic device composed of the micro-semiconductor stacked structure 10d array in this embodiment is simply a sensing device.

[0087] Other structures can refer to the third embodiment, for example, an electrical connection component formed by a lead, a metal bump, or a via filling method (the via filling is selected as the electrical connection component 18d in this embodiment) is implemented to provide a signal connection between the first and second stacked structures 12d and 14d. In addition, the electronic device formed in this embodiment is a sensing device, so the infrared micro-sensing chip and the ultraviolet micro-sensing chip in each stacked structure 12d and 14d in the micro-semiconductor stacked structure 10d are still located in the target area in each stacked structure 12d and 14d, and the target areas also need to be aligned with each other.

[0088] Each stacked structure can be a substrate of various forms, but the premise is that it does not block the light sensing of the infrared micro-sensing chip and the ultraviolet micro-sensing chip.

[0089] This embodiment is intended to illustrate that the micro-semiconductor stacking structure of the present invention is not limited to the light-emitting structure composed of micro-LED chips (disclosed in the first to fifth embodiments), but can also be a sensing structure composed of a light-sensing chip (disclosed in this embodiment), or its equivalent; wherein the so-called equivalent also includes a micro-semiconductor stacking structure composed of a micro-LED chip and a light-sensing chip (or a pressure sensing chip or other sensing chip) stacked together, so the selection of micro-semiconductor devices is not required by the present invention. However, the micro-semiconductor devices can be placed on the corresponding substrates to form a stacked structure, and the structure formed by stacking multiple stacked structures should fall within the equivalent scope of the micro-semiconductor stacking structure of the present invention.

[0090] [Sixth embodiment]

[0091] The present invention further discloses a micro-semiconductor stacking structure, comprising at least two stacked structure array units, wherein one stacked structure array unit is stacked on another stacked structure array unit; one stacked structure array unit is stacked along the vertical direction of the other stacked structure array unit, each stacked structure array unit comprises a substrate, a conductive layer disposed on the substrate, and a plurality of micro-semiconductor devices disposed on the substrate and arranged in an array and electrically connected to the conductive layer; each conductive layer comprises a matrix circuit, and these micro-semiconductor devices are electrically connected to the matrix circuit. Each stacked structure array unit defines a plurality of target areas arranged in an array; in each stacked structure array unit, at least one of these micro-semiconductor devices corresponds to and is located in one of these target areas; between two stacked structure array units, the target areas of the upper stacked structure array unit correspond to and are aligned with the target areas of the lower stacked structure array unit along the vertical direction; in at least one of the three stacked structure array units, the matrix circuit of the conductive layer is an active matrix circuit.

[0092] The definitions of the components of the micro-semiconductor stacking structure in this embodiment are roughly the same as those in the aforementioned embodiment. The difference from the aforementioned embodiment is that this embodiment places an array of micro-semiconductor devices on a single substrate with a matrix circuit, and stacks them as a unit to form a micro-semiconductor stacking structure. Therefore, the aforementioned first to fifth embodiments are a single micro-semiconductor stacking structure with a single target area (for example, a single micro-semiconductor stacking structure has a single pixel), while this embodiment is a single semiconductor stacking structure with multiple target areas (for example, a single micro-semiconductor stacking structure has multiple pixels). The aforementioned first to fifth embodiments are a conductive layer arranged on a substrate, and a single micro-semiconductor device is placed on the substrate and electrically connected to the conductive layer as a stacking structure, and multiple stacking structures are stacked to form the micro-semiconductor stacking structure; while the stacking structure array unit of this embodiment is a conductive layer arranged on a substrate as a matrix circuit, and multiple micro-semiconductor devices are arranged in an array to electrically connect the conductive layer as a matrix circuit, as a stacking structure array unit, and multiple stacking structure array units are stacked to form the micro-semiconductor stacking structure.

[0093] The micro-semiconductor stacking structure of this embodiment can be further illustrated by a color display unit: a micro-semiconductor stacking structure includes three stacking structure array units, wherein two stacking structure array units are stacked on the bottom stacking structure array unit; wherein the two stacking structure array units are stacked along the vertical direction of the bottom stacking structure array unit, each stacking structure array unit includes a substrate, a conductive layer disposed on the substrate, and a plurality of micro-light emitting diode chips disposed on the substrate and arranged in an array; each conductive layer includes a matrix circuit, and these micro-semiconductor chips are electrically connected to the matrix circuit. Each stacking structure array unit is defined with a plurality of pixels arranged in an array; in each stacking structure array unit, at least one of these micro-light emitting diode chips corresponds to and is located in one of these pixels; between two stacking structure array units, the pixels of the upper stacking structure array unit correspond to and are aligned with the pixels of the lower stacking structure array unit in the vertical direction; in at least one of the three stacking structure array units, the matrix circuit of the conductive layer is an active matrix circuit.

[0094] See also Figure 8, discloses a micro semiconductor stacking structure 10e of the sixth embodiment of the present invention. The micro semiconductor stacking structure 10e is formed by stacking three stacking structure array units 120e, 140e, and 160e, namely, the first, second, and third stacking structure array units 120e, 140e, and 160e. Each of the first, second, and third stacking structure array units 120e, 140e, and 160e has a substrate 122e, 142e, and 162e, a conductive layer 1240e, 1440e, and 1640e disposed on the substrate 122e, 142e, and 162e, and a plurality of micro semiconductor devices 126e, 146, and 166e arranged in an array on the substrate 122e, 142e, and 162e and electrically connected to the conductive layer 1240e, 1440e, and 1640e, and the plurality of micro semiconductor devices 126e, 146, and 166e are preferably wafer-level devices. In addition, in this embodiment, the sizes of the substrates 122e, 142e, and 162e may not be gradually reduced as in the above-mentioned embodiments. Fig. 9 After these stacked structure array units 120e, 140e, and 160e are stacked, an electrical connection component 19e is formed by coating the side of these stacked structure array units 120e, 140e, and 160e with conductive glue to achieve electrical connection between any two stacked structure array units; the electrical connection component 19e can also be connected to an external electrical control structure (not shown) to further constitute the electronic device of this embodiment.

[0095] In detail, the first stacked structure array 120e has a first substrate 122e, a conductive layer 1440e disposed on the first substrate 122e, and a plurality of red micro-LED chips (i.e., micro-semiconductor devices 126e) arranged in an array on the first substrate 122e and electrically connected to the conductive layer 1240e; the reference numeral 1260e represents a red micro-LED chip array 1260e, and the conductive layer 1240e is an active matrix circuit with TFTs or MOS switches, and these red micro-LED chips are electrically connected to the matrix circuit. By analogy, the second stacked structure array unit 140e has a second substrate 142e, a conductive layer 1440e disposed on the second substrate 142e, and a plurality of green micro-LED chips (i.e., micro-semiconductor devices 146e) disposed on the second substrate 142e and arranged in an array and electrically connected to the conductive layer 1440e; the reference numeral 1460e represents a green micro-LED chip array 1460e, the conductive layer 1440e is a passive matrix circuit, and these green micro-LED chips are electrically connected to the matrix circuit. The third stacked structure array unit 160e has a third substrate 162e, a conductive layer 1440e arranged on the third substrate 162e, and a plurality of blue micro-LED device chips (i.e., micro-semiconductor devices 166e) arranged in an array on the third substrate 162e and electrically connected to the conductive layer 1640e; the label 1660e represents the blue micro-LED chip array 1660e, the conductive layer 1640e is a passive matrix circuit, and these blue micro-LED chips are electrically connected to the matrix circuit.

[0096] Each stacked structure array unit 120e, 140e, 160e is defined as a plurality of pixels arranged in an array; in each stacked structure array unit 120e, 140e, 160e, at least one of these micro light emitting diode chips (i.e., micro semiconductor devices 126e, 146e, 166e) corresponds to and is located within one of these pixels; between pairs of stacked structure array units, the pixels of the upper stacked structure array unit individually correspond to and are aligned along the vertical direction with the pixels of the lower stacked structure array unit.

[0097] In the present embodiment, the micro semiconductor devices can be screened according to electrical properties only after being arranged in an array on a substrate; compared to the first embodiment, the cost of screening out defective products in the present embodiment is higher than the cost of screening out defective products in the first embodiment; however, the present embodiment is a one-time implementation of an array arrangement of micro semiconductor devices, and its overall process cost is still lower than that of the first embodiment. In addition, it is worth noting that a redundancy mechanism as described in the first embodiment can also be used to allow a single pixel to have two micro light emitting diode chips of the same color; wherein, in each stacked structure, the two micro light emitting diode chips of the same color correspond to the same pixel and are driven by a matrix circuit of a conductive layer. Here, the probability of two micro light emitting diode chips failing at the same time is extremely low, thereby reducing the aforementioned cost of screening out defective products and improving the process yield of the present invention.

[0098] This embodiment is intended to illustrate that the micro-semiconductor stacking structure of the present invention can form an array of micro-semiconductor devices on a substrate with a matrix circuit in advance, and then stack array units of an array-type stacked structure on each other, which can further improve process efficiency; this embodiment can also maintain the beneficial effects of the present invention of reducing the limited area of ​​the micro-semiconductor stacking structure and increasing the limited area density of the electronic device.

[0099] In addition, although the present embodiment exemplifies red, green, and blue micro LED chips as micro semiconductor devices, the number of layers of micro semiconductor devices and stacked structure array units is not limited to the present embodiment.

[0100] [Seventh to Eleventh Embodiments]

[0101] The sixth embodiment, which adopts the stacked structure array unit as a unit layer, can also be applied to the first to fifth embodiments.

[0102] As in the seventh embodiment Fig. 10A , Fig. 10B , that is, the first embodiment adopts an implementation method of a stacked structure array unit: a micro semiconductor stacked structure 10f.

[0103] Based on the first embodiment, an implementation similar to the seventh embodiment using a stacked structure array unit as a unit layer is performed, wherein the first stacked structure array unit 120f comprises a first substrate 122f, a conductive layer 1440f disposed on the first substrate 122f, and a plurality of red micro-LED chips (i.e., micro-semiconductor devices 126f) disposed on the first substrate 122f and arranged in an array and electrically connected to the conductive layer 1240f; reference numeral 1260f represents a red micro-LED chip array 1260f, the conductive layer 1240f is an active matrix circuit having TFTs or MOS switches, and these red micro-LED chips (i.e., micro-semiconductor devices 126f) are electrically connected to the matrix circuit. By analogy, the second stacked structure array unit 140f has a second substrate 142f, a conductive layer 1440f disposed on the second substrate 142f, and a plurality of green micro-LED chips (i.e., micro-semiconductor devices 146f) disposed on the second substrate 142f and arranged in an array and electrically connected to the conductive layer 1440f; the reference numeral 1460f represents a green micro-LED chip array 1460f, the conductive layer 1440f is a passive matrix circuit, and these green micro-LED chips (i.e., micro-semiconductor devices 146f) are electrically connected to the matrix circuit. The third stacked structure array unit 160f has a third substrate 162f, a conductive layer 1440f arranged on the third substrate 162f, and a plurality of blue micro-LED chips (i.e., micro-semiconductor devices 166f) arranged in an array on the third substrate 162f and electrically connected to the conductive layer 1640f; the label 1660f represents the blue micro-LED chip array 1660f, the conductive layer 1640f is a passive matrix circuit, and these blue micro-LED chips (i.e., micro-semiconductor devices 166f) are electrically connected to the matrix circuit.

[0104] Slightly different from the sixth embodiment, in this embodiment, Fig. 10A The sizes of the first, second, and third substrates 122f, 142f, and 162f are gradually reduced in sequence, so that the first substrate 122f defines a first step region 1222f, and the second substrate 142f defines a second step region 1422f. After the first, second, and third stacked structure array units 120f, 140f, and 160f are stacked, the first step region 1222f and the second step region 1422f may not be hidden, and thus form a structure as shown in FIG. Fig. 10BThe first and second step portions 102f and 104f of the micro-semiconductor stacked structure 10f are shown. The first and second step portions 102f and 104f can be provided in the electrical connection component 18f implemented by the lead wire in this embodiment to electrically connect the conductive layers of any two layers of the stacked structure array unit. The external electric control structure 300f is further connected to the conductive layer 1440f of the first stacked structure array unit 120f to achieve the electronic device 200f illustrated in this embodiment with the color display unit as an example. The external electric control structure 300f of this embodiment can be implemented at one time after the aforementioned stacked structure array units 120f, 140f, and 160f are stacked. The external electric control structure 300f has a connecting board and a circuit board including a control IC; the external electric control structure 300f drawn in this embodiment is only a simple example. The external electric control structure 300f can also be electrically connected only to the electrical connection component 18f of a specific layer to achieve driving all the conductive layers of the micro-semiconductor stacked structure 10f.

[0105] As in the eighth embodiment Fig.11 , which is slightly different from the seventh embodiment in that the electrical connection component 18g of the micro semiconductor stacking structure 10g is connected to the external electrical control structure 300g. In this embodiment, the electrical connection component 18g is implemented by filling holes, and the external electrical control structure 300g includes first electrical control components 312g, 314g, 316g connected to the substrates of each stacking structure array unit 120g, 140g, 160g, and second electrical control components 322g with control IC 324g connected to the aforementioned first electrical control components 312g, 314g, 316g. This embodiment is intended to provide other embodiments of the external electrical control structure, but how the external electrical control structure is implemented is not a question, such as setting layer by layer or taking one of them, or each first electrical control component 312g, 314g, 316g is connected to the second electrical control component 322g with control IC 324g, as long as the external electrical control structure can be electrically connected to at least one electrical connection component, it can achieve driving all the conductive layers of the micro semiconductor stacking structure.

[0106] As in the ninth embodiment Fig.12 Based on the third embodiment, a similar implementation method as the seventh embodiment using a stacked structure array unit as a unit layer is performed: a micro-semiconductor stacked structure 10h. The substrate of each stacked structure array unit 120h, 140h, 160h uses a soft transparent substrate, and because the substrate is soft, the first, second, and third steps 102h, 104h, 106h are formed according to the surface morphology of each stacked structure array unit; in this embodiment, the electrical connection between two stacked structure array units is achieved by providing a hole filled in the aforementioned step as an electrical connection component 18h.

[0107] As in the tenth embodiment Fig.13Based on the fourth embodiment, a similar implementation method as the seventh embodiment using a stacked structure array unit as a unit layer is performed: a micro semiconductor stacked structure 10i. The first stacked structure array unit 120i uses a hard transparent substrate, and the substrates of the second and third stacked structure array units 140i and 160i use a soft transparent substrate, and because the substrate is soft, each step is formed according to the surface morphology of each stacked structure array unit; in this embodiment, the electrical connection between two stacked structure array units is achieved by providing a hole in the aforementioned step as an electrical connection component 18i.

[0108] As in the eleventh embodiment Fig.14 , based on the fifth embodiment: micro semiconductor stacking structure 10j. Similar to the fifth embodiment, after the substrate of the first stacking structure array unit 120j is prepared, the present embodiment uses a semiconductor process to sequentially complete the stacking structure array units 120j, 140j, and 160j; in the present embodiment, the electrical connection between the stacking structure array units is achieved by using the filled holes formed in the semiconductor process as the electrical connection component 18j.

[0109] The materials, process steps and their corresponding beneficial effects considered or applied in the first to fifth embodiments may also be equivalently viewed and embodied in the sixth to eleventh embodiments.

[0110] [Beneficial Effects]

[0111] The micro-semiconductor stacking structure and the electronic device thereof of the present invention have at least the following beneficial effects:

[0112] 1. For the micro-semiconductor stacking structure of the present invention, multiple micro-semiconductor devices are stacked in a vertical direction while maintaining the electrical functions of the micro-semiconductor devices, which can effectively and significantly reduce the pixel area.

[0113] 2. For the electronic device of the present invention, the number of micro semiconductor devices existing in a limited area is the limited area divided by the unit area. The number of micro semiconductor devices (such as the number of micro LED chips) that can exist in a limited area is: (limited area / unit area) * number of layers, that is, the pixel density that can be produced in a limited area will be Figure 1 The commonly used micro-LED display technology is several times faster.

[0114] 3. For micro-semiconductor stacked structures and electronic devices, maintaining Figure 1 Under the same limited area conditions as the conventional micro-LED display technology, the pixel density can be improved. For example, a 3.5" virtual reality or augmented reality display with a resolution of 2000 pixels per inch (ppi) can be formed by using a micro-LED chip. Therefore, the present invention can achieve low cost and high resolution at the same time within the limited area of ​​the electronic device.

[0115] 4. For the micro-semiconductor stacking structure, the stacking sequence of each stacking structure of the present invention can be determined based on the properties of the micro-semiconductor device, and only the target areas (such as pixels) of each layer need to be aligned.

[0116] 5. All embodiments in this embodiment are applicable to the redundancy mechanism, that is, in each stacked structure / stacked structure unit, a single target area has at least one micro semiconductor device (such as two micro light-emitting diode chips of the same color in a single pixel), which reduces the probability of failure of a single target area, thereby improving the process yield of the present invention.

[0117] 6. The present invention can be flexibly applied to existing processes; for the micro-semiconductor stacking structure of the first to fifth embodiments, each stacking structure of the present invention can be implemented as in the first to third embodiments, and then the desired stacking structure can be selected to form a micro-semiconductor stacking structure; or the present invention can be as in the fourth embodiment, using semiconductor technology to lay out the substrate and the conductive layer, and then set the micro-semiconductor device, and repeatedly implement the semiconductor process to sequentially form each stacking structure to form a micro-semiconductor stacking structure. Similarly, in the embodiment with the stacking structure array unit as the unit layer, the substrate and the conductive layer can also be laid out by semiconductor technology, and then the micro-semiconductor device can be set, and the micro-semiconductor stacking structure can be formed after layer by layer stacking.

[0118] The above description is for illustrative purposes only and is not intended to be limiting. Any equivalent modifications or changes made thereto without departing from the spirit and scope of the present invention shall be included in the scope of the appended claims.

Claims

1. A micro-semiconductor device, comprising: A plurality of micro semiconductor array units adjacent to each other, Wherein, each micro semiconductor array unit comprises: Base material; A conductive pattern layer disposed on the substrate; one or more micro semiconductor devices disposed on the conductive pattern layer; one or more additional micro semiconductor devices, the one or more additional micro semiconductor devices being disposed on the conductive pattern layer and respectively corresponding to the one or more micro semiconductor devices; and An electrical connection member is formed on edges of the substrate and the conductive pattern layer and is electrically connected to the conductive pattern layer.

2. The micro-semiconductor device according to claim 1, wherein: The electrical connection member includes a conductive glue formed on the edge of the micro semiconductor array unit.

3. The micro-semiconductor device according to claim 1, wherein: The electrical connection features on the edge are covered by a dielectric layer.

4. The micro-semiconductor device according to claim 1, wherein: The conductive pattern layer of at least one of the plurality of micro semiconductor array units includes an active circuit.

5. The micro-semiconductor device according to claim 4, wherein: The active circuit includes a TFT switch or a MOS switch.

6. The micro-semiconductor device according to claim 1, wherein: The substrate is a rigid transparent substrate and has a thickness ranging from 10 microns to 500 microns.

7. The micro-semiconductor device according to claim 1, wherein: The one or more micro semiconductor devices and the one or more additional micro semiconductor devices are micro LED wafers.

8. The micro-semiconductor device according to claim 7, wherein: The micro LED chip is a vertical or flip chip micro LED chip.

9. The micro-semiconductor device according to claim 1, wherein: The micro semiconductor device and an additional micro semiconductor device corresponding to the micro semiconductor device are within a single pixel and have the same color.

10. The micro-semiconductor device according to claim 9, wherein: Both the micro semiconductor device and the additional micro semiconductor device of the same color are driven by the conductive pattern layer.

11. The micro-semiconductor device according to claim 1, wherein: The plurality of micro semiconductor array units are stacked on each other.

12. The micro-semiconductor device according to claim 11, wherein: The sizes of the plurality of micro semiconductor array units are gradually reduced.

13. The micro-semiconductor device according to claim 12, wherein: At least one of the plurality of micro semiconductor array units has a step portion, and the electrical connection member is disposed in the step portion.

14. The micro-semiconductor device according to claim 1, wherein: The plurality of micro semiconductor array units are bonded by adhesive.

15. The micro-semiconductor device according to claim 1, wherein: The electrical connection component is also connected to an external electrical control structure.

16. The micro-semiconductor device according to claim 1, wherein: The one or more micro semiconductor devices and the one or more additional micro semiconductor devices are light sensing wafers or pressure sensing wafers.

17. The micro-semiconductor device according to claim 1, wherein: The micro-semiconductor device is a VR or AR display device.

18. The micro-semiconductor device according to claim 1, wherein: The substrate is a flexible transparent substrate and has a thickness ranging from 10 micrometers to 500 micrometers.

19. The micro-semiconductor device according to claim 1, wherein: The plurality of micro semiconductor array units have the same size.

20. The micro-semiconductor device according to claim 1, wherein: The conductive pattern layer of the micro semiconductor array unit is electrically connected to another conductive pattern layer of another micro semiconductor array unit adjacent to the micro semiconductor array unit through at least one electrical connection member.

21. An electronic device comprising the micro-semiconductor device according to any one of claims 1 to 20.

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