Pixel reading circuit and control method thereof
By designing a pixel readout circuit that integrates photoelectric conversion, gain adjustment, correlation dual sampling, and gain control, the problems of insufficient noise suppression, integral capacitor switching, and dynamic range improvement in traditional pixel readout circuits are solved, achieving efficient signal processing and low-power pixel readout.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-30
- Publication Date
- 2026-04-07
AI Technical Summary
Traditional pixel readout circuits suffer from poor noise suppression, slow switching of integrating capacitors, insufficient dynamic range improvement, large circuit area, and high power consumption, especially limiting their performance in high-speed, high dynamic range scenarios.
Design a pixel readout circuit that includes a photoelectric conversion module, a gain adjustment module, a correlation dual sampling module, a gain control feedback module, and an output module. The photoelectric conversion module converts the optical signal into a photocurrent signal, the gain adjustment module performs integration processing, the correlation dual sampling module performs sample-and-hold, the gain control feedback module generates a gain control signal to adjust the integral gain, and the output module buffers and outputs the valid signal.
It improves the signal-to-noise ratio, reduces pixel area, simplifies timing control, increases system frame rate and dynamic range, and reduces power consumption.
Smart Images
Figure CN121815109A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of photoelectric imaging detector technology, and in particular to a pixel readout circuit and its control method. Background Technology
[0002] Photoelectric imaging detector technology is a core component of modern optical sensors and imaging systems, widely used in military reconnaissance, medical diagnostics, industrial inspection, and consumer electronics. Among these, short-wave infrared focal plane arrays are a key technology, and their performance directly depends on the design of the pixel readout circuit. The pixel readout circuit is responsible for converting the photocurrent generated by the photosensitive device into a readable voltage signal and processing noise to improve the signal-to-noise ratio. Although traditional pixel readout circuit architectures have been developed for many years, they still have many limitations and urgently require innovation and improvement.
[0003] In existing technologies, the main problems faced by traditional photoelectric imaging detector readout circuits include: noise superposition and frame rate limitation due to column-related double sampling (CDS); slow switching response of integrating capacitors in the circuit and insufficient dynamic range improvement; large in-pixel circuit area, high power consumption, and limited noise suppression capability. These problems severely restrict the performance of photoelectric imaging systems in high-speed, high-dynamic-range scenarios. Summary of the Invention
[0004] This invention provides a pixel readout circuit and its control method to solve the technical problems of poor noise suppression capability, slow switching of integrating capacitor, insufficient dynamic range improvement, large circuit area and high power consumption in the above-mentioned photoelectric imaging detectors.
[0005] In a first aspect, the present invention provides a pixel readout circuit, comprising:
[0006] The photoelectric conversion module converts the incident light signal into a photocurrent signal; A gain adjustment module, electrically connected to the photoelectric conversion module, performs integration processing on the photocurrent signal to obtain an integrated voltage; A related dual sampling module, electrically connected to the gain adjustment module, samples and holds the integrated voltage to obtain an effective signal voltage related to the optical signal; The gain control feedback module is electrically connected to the correlated dual sampling module and the gain adjustment module respectively. In response to the effective signal voltage, it generates a gain control signal and outputs it to the gain adjustment module to adjust the integral gain of the gain adjustment module. The output module is electrically connected to the related dual sampling module and is used to buffer the output of the effective signal voltage.
[0007] In one embodiment of the present invention, the gain adjustment module includes a first capacitor, a second capacitor, a first PMOS transistor, a second PMOS transistor, and an amplification unit. The amplification unit is used to amplify the photocurrent signal. The first terminal of the first capacitor is connected to the input terminal of the amplification unit, and the second terminal of the first capacitor is connected to the output terminal of the amplification unit. The drain of the first PMOS transistor is connected to the first terminal of the first capacitor, and the drain of the first PMOS transistor is also connected to the first terminal of the second capacitor. The gate of the first PMOS transistor is connected to a first reset signal. The second terminal of the second capacitor is connected to the drain of the second PMOS transistor, and the source of the first PMOS transistor is connected to the second terminal of the first capacitor, and the source of the first PMOS transistor is also connected to the source of the second PMOS transistor. The input terminal of the amplification unit is the input terminal of the gain adjustment module, the output terminal of the amplification unit is the output terminal of the gain adjustment module, and the gate of the second PMOS transistor is the gain adjustment terminal of the gain adjustment module.
[0008] In one embodiment of the present invention, the amplification unit includes a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the third PMOS transistor is connected to a power supply voltage, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the fourth PMOS transistor is connected to a first bias voltage, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the first NMOS transistor is connected to a second bias voltage, the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to a third bias voltage. The gate of the third PMOS transistor is the input terminal of the amplification unit, and the drain of the fourth PMOS transistor is the output terminal of the amplification unit.
[0009] In one embodiment of the present invention, the capacitance value of the second capacitor is a preset multiple of the capacitance value of the first capacitor.
[0010] In one embodiment of the present invention, the correlated dual sampling module includes a third NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third capacitor, and a fourth capacitor. The source of the third NMOS transistor is connected to the drain of the fifth PMOS transistor, and the drain of the third NMOS transistor is connected to the source of the fifth PMOS transistor. The gate of the third NMOS transistor is connected to a first sampling signal, and the gate of the fifth PMOS transistor is connected to a second sampling signal. The drain of the third NMOS transistor is connected to the first terminal of the fourth capacitor, and the first terminal of the fourth capacitor is grounded after passing through the third capacitor. The second terminal of the fourth capacitor is connected to the drain of the sixth PMOS transistor, the source of the sixth PMOS transistor is connected to a reference voltage, and the gate of the sixth PMOS transistor is connected to a second reset signal. The source of the third NMOS transistor is the input terminal of the correlated dual sampling module, and the second terminal of the fourth capacitor is the output terminal of the correlated dual sampling module. The level of the first sampling signal is opposite to the level of the second sampling signal.
[0011] In one embodiment of the present invention, the gain control feedback module includes a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, and an inverter. The output terminal of the inverter is connected to the source of the fourth NMOS transistor, the drain of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fourth NMOS transistor is connected to a first control signal, the source of the fifth NMOS transistor is grounded, the gate of the fifth NMOS transistor is connected to a second control signal, the drain of the fourth NMOS transistor is also connected to the source of the sixth NMOS transistor, the drain of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor, the source of the seventh NMOS transistor is grounded, the gate of the seventh PMOS transistor is connected to a third reset signal, and the gate of the sixth NMOS transistor... The inverter's input terminal is connected to the gate of the ninth PMOS transistor, the source of the ninth PMOS transistor is connected to the power supply voltage, the drain of the ninth PMOS transistor is connected to the drain of the seventh NMOS transistor, the source of the ninth PMOS transistor is also connected to the source of the tenth PMOS transistor, the gate of the tenth PMOS transistor is connected to the gate of the eighth NMOS transistor, the gate of the tenth PMOS transistor is also connected to the drain of the sixth NMOS transistor, the drain of the tenth PMOS transistor is connected to the drain of the eighth NMOS transistor, the drain of the tenth PMOS transistor is also connected to the gate of the sixth NMOS transistor, and the source of the eighth NMOS transistor is grounded. The inverter's input terminal is the input terminal of the gain control feedback module, and the drain of the tenth PMOS transistor is the output terminal of the gain control feedback module. The first control signal and the second control signal have opposite levels.
[0012] In one embodiment of the present invention, the photoelectric conversion module includes a photodiode and a parasitic capacitor. The first end of the parasitic capacitor is connected to the cathode of the photodiode, the second end of the parasitic capacitor is connected to the anode of the photodiode, the cathode of the photodiode is connected to the power supply voltage, and the anode of the photodiode is the output terminal of the photoelectric conversion module.
[0013] Secondly, the present invention also provides a control method applied to the pixel readout circuit as described above, comprising: Acquire the photocurrent signal and perform a reset operation based on the reset signal; The photocurrent signal is integrated to obtain the integrated voltage; Under the control of the sampling signal, the integrated voltage is sampled and held to obtain the effective signal voltage; A gain control signal is generated based on the effective signal voltage to adjust the integral gain of the integral processing.
[0014] In one embodiment of the present invention, a gain control signal is generated based on the effective signal voltage to adjust the integral gain of the integral processing process, including: when the effective signal voltage is greater than or equal to a first voltage threshold, the gain control feedback module outputs a high-level gain control signal and maintains it, and the integral gain is a first gain; when the effective signal voltage is less than the first voltage threshold, the gain control feedback module outputs a low-level gain control signal and maintains it, and the integral gain is a second gain; wherein the second gain is greater than the first gain.
[0015] The beneficial effects of this invention are as follows: This invention provides a pixel readout circuit and its control method. The pixel readout circuit includes a photoelectric conversion module, a gain adjustment module, a correlation dual sampling module, a gain control feedback module, and an output module. The photoelectric conversion module converts the optical signal into a photocurrent signal. The gain adjustment module integrates the photocurrent signal to obtain an integrated voltage. The correlation dual sampling module samples the integrated voltage to obtain an effective signal voltage. The gain control feedback module generates a gain control signal based on the effective signal voltage, thereby adjusting the integral gain. The output module buffers and outputs the effective signal voltage. The circuit provided by this invention uses fewer switches, has simpler timing control, reduces pixel area, and has high chip integration. Integrating the correlation dual sampling function within the pixel avoids multiple signal transmissions between the pixel and the column-level circuit, reducing the processing pressure on the column-level circuit and improving the system frame rate. The automatic switching function of the integrating capacitor is integrated within the pixel, effectively improving the dynamic range of the pixel through automatic switching of the integrating capacitor. Attached Figure Description
[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0017] In the attached diagram: Figure 1 This is a block diagram of the pixel readout circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the specific structure of the pixel readout circuit provided in the embodiment of the present invention; Figure 3 This is a schematic diagram of the specific structure of the amplification unit provided in the embodiment of the present invention; Figure 4 This is a schematic diagram of the specific structure of the gain control feedback module provided in this embodiment of the invention; Figure 5 This is a schematic diagram of the signal path at high gain provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the output characteristic curve of the high-gain operating mode provided in the embodiments of the present invention; Figure 7 This is a schematic diagram of the signal path under low gain provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the output characteristic curve of the low-gain operating mode provided in an embodiment of the present invention.
[0018] Figure reference numerals: 110 - Photoelectric conversion module; 120 - Gain adjustment module; 121 - Amplification unit; 130 - Correlation double sampling module; 140 - Gain control feedback module; 150 - Output module; I pd - Photocurrent signal; V g -Integral voltage; V A - Effective signal voltage; P1 - Gain control signal; Vout - Target voltage signal; V REF - Reference voltage; VCC - Power supply voltage; φRST1 - First reset signal; φRST2 - Second reset signal; φRST3 - Third reset signal; φSH - First sampling signal; φNSH - Second sampling signal; φOP1 - First control signal; φNOP1 - Second control signal. Detailed Implementation
[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0020] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0021] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.
[0022] Photoelectric imaging detector technology is a core component of modern optical sensors and imaging systems, widely used in military reconnaissance, medical diagnostics, industrial inspection, and consumer electronics. Among these, short-wave infrared focal plane arrays are a key technology, and their performance directly depends on the design of the pixel readout circuit. The pixel readout circuit is responsible for converting the photocurrent generated by the photosensitive device into a readable voltage signal and processing noise to improve the signal-to-noise ratio. Although traditional pixel readout circuit architectures have been developed for many years, they still have many limitations and urgently require innovation and improvement.
[0023] In existing technologies, pixel readout circuits typically employ a capacitive feedback transimpedance amplifier (CTIA) structure combined with correlated double sampling (CDS) technology to suppress noise. The CTIA amplifies the signal by integrating the photocurrent through an integrating capacitor, but it is prone to introducing switching noise and low-frequency amplifier noise. To address this issue, correlated double sampling (CDS) technology is widely used, eliminating fixed-pattern noise and some random noise by sampling the difference between the reset signal and the integrated signal. However, traditional CDS schemes often employ a column-level implementation, where the CDS circuit is located in a column processing unit outside the pixel array. While this design simplifies the pixel structure, it has the following drawbacks: First, the signal must be transmitted from the pixel to the column-level circuit, and during transmission, it is susceptible to crosstalk and parasitic capacitance, leading to noise superposition and reduced signal-to-noise ratio. Second, column-level CDS requires complex timing control and multiplexing, increasing system power consumption and limiting frame rate increases, especially in high-speed imaging scenarios where the frame rate bottleneck is more pronounced.
[0024] Furthermore, existing pixel readout circuits often employ integral capacitor switching technology for dynamic range optimization. This involves switching between different sized integral capacitors: using a small capacitor to avoid saturation under bright light conditions and a large capacitor to improve sensitivity under low light conditions. However, traditional implementations place the capacitor switching control circuitry outside the pixel or at the column level, increasing circuit layout complexity and response delay. For example, using external logic circuitry or software to control capacitor switching introduces additional latency, making it impossible to adapt to changes in lighting conditions in real time, resulting in limited improvement in dynamic range. Simultaneously, low integration density within the pixel increases the circuit area, hindering high-density integration and contradicting the current trend of focal plane arrays towards smaller pixel sizes and higher resolutions.
[0025] Regarding noise suppression, existing in-pixel amplifier structures (such as common-source amplifiers), while simple in structure, have limited gain and are difficult to effectively suppress low-frequency noise and offset voltage. Some designs employ more complex op-amp designs (such as folded cascode op-amps), but these designs often require more transistors, increasing pixel area and power consumption, making them unsuitable for large-scale arrays. Furthermore, traditional in-pixel CDS solutions attempt to integrate some CDS functions into the pixel, but typically involve a large number of switches and complex timing, such as using multiple sampling capacitors and switching transistors. This not only increases the pixel area but also introduces additional thermal noise and charge injection errors.
[0026] To solve the above problems, such as Figure 1 As shown, the present invention provides a pixel readout circuit, comprising: The photoelectric conversion module 110 converts the incident light signal into a photocurrent signal I.pd ; Gain adjustment module 120 is electrically connected to photoelectric conversion module 110 and adjusts photocurrent signal I. pd The integral voltage Vg is obtained by performing integration. The related dual sampling module 130, electrically connected to the gain adjustment module 120, samples and holds the integrated voltage Vg to obtain the effective signal voltage V related to the optical signal. A ; The gain control feedback module 140 is electrically connected to the correlated dual sampling module 130 and the gain adjustment module 120 respectively, and responds to the effective signal voltage V. A The gain control signal P1 is generated and output to the gain adjustment module 120 to adjust the integral gain of the gain adjustment module 120. Output module 150, electrically connected to the associated dual sampling module 130, is used to buffer the output valid signal voltage V. A .
[0027] In detail, such as Figure 2 As shown, the photoelectric conversion module 110 includes a photodiode LR and a parasitic capacitance CPD, wherein the parasitic capacitance C... PD The first terminal is connected to the cathode of photodiode LR, with parasitic capacitance C. PD The second terminal is connected to the anode of photodiode LR, the cathode of photodiode LR is connected to the power supply voltage VCC, and the anode of photodiode LR is the output terminal of photoelectric conversion module 110. After receiving the optical signal, photodiode LR generates a photocurrent signal I. pd .
[0028] In detail, such as Figure 2 As shown, the gain adjustment module 120 includes a first capacitor C1, a second capacitor C2, a first PMOS transistor PM1, a second PMOS transistor PM2, and an amplification unit 121. The amplification unit 121 is used to adjust the photocurrent signal I. pdFor amplification processing, the first terminal of the first capacitor C1 is connected to the input terminal of the amplification unit 121, and the second terminal of the first capacitor C1 is connected to the output terminal of the amplification unit 121. The drain of the first PMOS transistor PM1 is connected to the first terminal of the first capacitor C1, and the drain of the first PMOS transistor PM1 is also connected to the first terminal of the second capacitor C2. The gate of the first PMOS transistor PM1 is connected to the first reset signal φRST1. The second terminal of the second capacitor C2 is connected to the drain of the second PMOS transistor PM2. The source of the first PMOS transistor PM1 is connected to the second terminal of the first capacitor C1, and the source of the first PMOS transistor PM1 is also connected to the source of the second PMOS transistor PM2. The input terminal of the amplification unit 121 is the input terminal of the gain adjustment module 120, and the input terminal of the gain adjustment module 120 is connected to the anode of the photodiode LR. The output terminal of the amplification unit 121 is the output terminal of the gain adjustment module 120. The gate of the second PMOS transistor PM2 is the gain adjustment terminal of the gain adjustment module 120, and the gain adjustment terminal of the gain adjustment module 120 is connected to the gain control signal P1.
[0029] In detail, such as Figure 3 As shown, the amplification unit 121 includes a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first NMOS transistor NM1, and a second NMOS transistor NM2. The source of the third PMOS transistor PM3 is connected to the power supply voltage VCC, the drain of the third PMOS transistor PM3 is connected to the source of the fourth PMOS transistor PM4, the drain of the fourth PMOS transistor PM4 is connected to the drain of the first NMOS transistor NM1, the gate of the fourth PMOS transistor PM4 is connected to the first bias voltage Vcasp, the source of the first NMOS transistor NM1 is connected to the drain of the second NMOS transistor NM2, the gate of the first NMOS transistor NM1 is connected to the second bias voltage Vcasn, the source of the second NMOS transistor NM2 is grounded, and the gate of the second NMOS transistor NM2 is connected to the third bias voltage Vbias. The gate of the third PMOS transistor PM3 is the input terminal of the amplification unit 121, the gate of the third PMOS transistor PM3 is connected to the anode of the photodiode LR, and the drain of the fourth PMOS transistor PM4 is the output terminal of the amplification unit 121.
[0030] More specifically, the capacitance value of the second capacitor C2 is a preset multiple of the capacitance value of the first capacitor C1, for example: the capacitance value of the second capacitor C2 is 50 times, 100 times, etc. of the capacitance value of the first capacitor C1.
[0031] In detail, such as Figure 2As shown, the related dual sampling module 130 includes a third NMOS transistor NM3, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a third capacitor C3, and a fourth capacitor C4. The source of the third NMOS transistor NM3 is connected to the drain of the fifth PMOS transistor PM5, and the drain of the third NMOS transistor NM3 is connected to the source of the fifth PMOS transistor PM5. The gate of the third NMOS transistor NM3 is connected to the first sampling signal φSH, and the gate of the fifth PMOS transistor PM5 is connected to the second sampling signal φNSH. The drain of the third NMOS transistor NM3 is connected to the first terminal of the fourth capacitor C4, and the first terminal of the fourth capacitor C4 is also grounded after passing through the third capacitor C3. The second terminal of the fourth capacitor C4 is connected to the drain of the sixth PMOS transistor PM6, and the source of the sixth PMOS transistor PM6 is connected to the reference voltage V. REF The gate of the sixth PMOS transistor PM6 is connected to the second reset signal φRST2. The source of the third NMOS transistor NM3 is the input terminal of the correlated dual sampling module 130. The input terminal of the correlated dual sampling module 130 is connected to the drain of the fourth PMOS transistor PM4. The second terminal of the fourth capacitor C4 is the output terminal of the correlated dual sampling module 130. The level of the first sampling signal φSH is opposite to the level of the second sampling signal φNSH.
[0032] In detail, such as Figure 4As shown, the gain control feedback module 140 includes a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, and an inverter INV. The output terminal of the inverter INV is connected to the source of the fourth NMOS transistor NM4, the drain of the fourth NMOS transistor NM4 is connected to the drain of the fifth NMOS transistor NM5, and the gate of the fourth NMOS transistor NM4 is connected to the first control signal φOP. 1. The source of the fifth NMOS transistor NM5 is grounded, and its gate is connected to the second control signal φNOP1. The drain of the fourth NMOS transistor NM4 is also connected to the source of the sixth NMOS transistor NM6. The drain of the sixth NMOS transistor NM6 is connected to the drain of the seventh NMOS transistor NM7. The source of the seventh NMOS transistor NM7 is grounded, and its gate is connected to the third reset signal φRST3. The gate of the sixth NMOS transistor NM6 is connected to the gate of the ninth PMOS transistor PM9. The source of PMOS transistor PM9 is connected to the power supply voltage VCC. The drain of PMOS transistor PM9 is connected to the drain of NMOS transistor NM7. The source of PMOS transistor PM9 is also connected to the source of PMOS transistor PM10. The gate of PMOS transistor PM10 is connected to the gate of NMOS transistor NM8. The gate of PMOS transistor PM10 is also connected to the drain of NMOS transistor NM6. The drain of PMOS transistor PM10 is also connected to the drain of NMOS transistor NM8. The gate of the sixth NMOS transistor NM6 is connected to the ground, and the source of the eighth NMOS transistor NM8 is grounded. The input of the inverter INV is the input of the gain control feedback module 140, which is connected to the second terminal of the fourth capacitor C4. The drain of the tenth PMOS transistor PM10 is the output of the gain control feedback module 140, which is connected to the gate of the second PMOS transistor PM2. The levels of the first control signal φOP1 and the second control signal φNOP1 are opposite.
[0033] In detail, such as Figure 2 As shown, the output module 150 includes a buffer BUF. The input terminal of the buffer BUF is connected to the second terminal of the fourth capacitor C4, and the output terminal of the buffer BUF outputs the target voltage signal Vout.
[0034] Please refer to Figures 1 to 8 As shown, the working principle of the pixel readout circuit provided by this invention is as follows: like Figure 1As shown, the pixel readout circuit includes a photoelectric conversion module 110, a gain adjustment module 120, a correlation dual sampling module 130, a gain control feedback module 140, and an output module 150. In the photoelectric conversion module 110, the photodiode LR receives the optical signal and converts the optical signal into a photocurrent signal I. pd Gain adjustment module 120 adjusts the photocurrent signal I pd The integral voltage Vg is obtained by performing integration; the coherent double sampling module 130 samples the integral voltage Vg twice to maintain the voltage and obtain the effective signal voltage Vg related to the incident light signal. A The gain control feedback module 140 responds to the effective signal voltage V output by the correlated dual sampling module 130. A Therefore, based on the effective signal voltage V A A gain control signal P1 is generated and input to the gain adjustment terminal of the gain adjustment module 120. This controls the integration path with a larger capacitance value in the gain adjustment module 120 to be turned on or off, thereby adjusting the integral gain in the gain adjustment module 120. The effective signal voltage V is then output through the output module 150. A The output is buffered to provide the target voltage signal Vout for subsequent circuits.
[0035] The pixel readout circuit provided by the present invention includes two working cycles with the same integration sampling time. The first working cycle determines the intensity of the light signal, and the second working cycle reads out the voltage signal normally.
[0036] When the pixel readout circuit operates in the first working cycle: the first PMOS transistor PM1 is turned on by the first reset signal φRST1, resetting the gain adjustment module 120; the sixth PMOS transistor PM6 is turned on by the second reset signal φRST2, resetting the related dual sampling module 130; and the seventh NMOS transistor NM7 is turned on by the third reset signal φRST3, resetting the gain control feedback module 140, making the reset gain adjustment voltage P1 high. Subsequently, the first PMOS transistor PM1 and the seventh NMOS transistor NM7 are controlled to be in the off state. After a preset time period, the sixth PMOS transistor PM6 is controlled to be in the off state.
[0037] At this time, the photoelectric conversion module 110 converts the optical signal into a photocurrent signal I. pd Photocurrent signal I pd The integral voltage Vg is generated at the output of the amplifier unit 121 by integrating the first capacitor C1 in the gain adjustment module 120. At the same time, the first sampling signal φSH controls the third NMOS transistor NM3 to turn on, and the second sampling signal φNSH controls the fifth PMOS transistor PM5 to turn on, so that the integral voltage Vg is sampled to the first terminal of the fourth capacitor C4.
[0038] like Figure 5 As shown, when the photocurrent signal I pd When the current is a small signal, such as 0.1mA, the voltage across the fourth capacitor C4 during reset is the reference voltage V. REF The voltage across the first terminal of the fourth capacitor C4 is the effective signal voltage V. A The voltage drop at the output of the dual sampling module 130 is small, and the voltage output of the inverter INT in the gain control feedback module 140 is low. The fifth NMOS transistor NM5 is turned on, the sixth NMOS transistor NM6 is turned on, and the tenth PMOS transistor PM10 is turned on. At this time, the gain control signal P1 output by the gain control feedback module 140 remains high, and the level does not change abruptly. The integration path of the second capacitor C2 in the gain adjustment module 120 is disconnected. In the second working cycle, the first capacitor C1 is still used for integration. The operating characteristic curve is as follows: Figure 6 As shown, Figure 6 This is the output characteristic curve of the pixel readout circuit in high-gain operating mode. High-gain operating mode represents the gain of charge, where V=It / C, and a small capacitor results in a high gain.
[0039] like Figure 7 As shown, when the photocurrent signal I pd When the signal current is large, such as 1000mA, the voltage of the fourth capacitor C4 during reset is the reference voltage V. REF The voltage across the first terminal of the fourth capacitor C4 is the effective signal voltage V. A The voltage drop at the output of the dual sampling module 130 is large, the voltage output of the inverter INT in the gain control feedback module 140 is high, the fifth NMOS transistor NM5 is cut off, the sixth NMOS transistor NM6 is turned on, causing the eighth NMOS transistor NM8 to turn on, changing the gain control signal P1 from high to low. Furthermore, the ninth PMOS transistor PM9 is turned on, thus keeping the gain control signal P1 output by the gain control feedback module 140 low. At this time, the integration path of the second capacitor C2 in the gain adjustment module 120 is turned on. In the second working cycle, the first capacitor C1 and the second capacitor C2 are used for integration processing. The operating characteristic curve is shown below. Figure 8 As shown, Figure 8 The output characteristic curve of the pixel readout circuit in low-gain operating mode.
[0040] At the start of the second working cycle, the integrating capacitor initially maintains the state it reached at the end of the first working cycle. A first reset signal φRST1 turns on the first PMOS transistor PM1, resetting the gain adjustment module 120. A second reset signal φRST2 turns on the sixth PMOS transistor PM6, resetting the related dual sampling module 130. A third reset signal φRST3 turns off the seventh NMOS transistor NM7, keeping the gain control feedback module 140 in its original state. Subsequently, a first sampling signal φSH turns on the third NMOS transistor NM3, and a second sampling signal φNSH turns on the fifth PMOS transistor PM5, transmitting the integrated voltage Vg to the capacitor in the related dual sampling module 130. The output module 150 then outputs the effective signal voltage Vg. A It is then transmitted to subsequent circuits.
[0041] The present invention also provides a control method for a pixel readout circuit as described above, comprising: Acquire the photocurrent signal and perform a reset operation based on the reset signal; The photocurrent signal is integrated to obtain the integrated voltage; Under the control of the sampling signal, the integrated voltage is sampled and held to obtain the effective signal voltage; A gain control signal is generated based on the effective signal voltage to adjust the integral gain of the integral processing.
[0042] Specifically, the photocurrent signal I output by the photoelectric conversion module 110 is acquired. pd The pixel readout circuit is reset based on three reset signals, and the photocurrent signal I is adjusted by the gain adjustment module 120. pd The integral voltage Vg is obtained by performing integration processing. Under the control of two sampling signals, the correlation dual sampling module 130 samples the integral voltage Vg twice to obtain the effective signal voltage V. A The gain control feedback module 140 is based on the effective signal voltage V. A A gain control signal P1 is generated, thereby controlling the on / off state of the integral path including the second capacitor C2 in the gain adjustment module 120, and changing the integral gain.
[0043] In detail, a gain control signal is generated based on the effective signal voltage to adjust the integration gain of the integration process, including: when the effective signal voltage is greater than or equal to a first voltage threshold, the gain control feedback module 140 outputs a high-level gain control signal and maintains it, and the integration gain is the first gain; when the effective signal voltage is less than the first voltage threshold, the gain control feedback module 140 outputs a low-level gain control signal and maintains it, and the integration gain is the second gain, wherein the second gain is greater than the first gain. Specifically, in the photocurrent signal I... pdWhen the current is relatively small (1mA), the effective signal voltage V obtained by the correlation dual sampling module 130 is... A When the voltage is greater than or equal to the first voltage threshold, the gain control feedback module 140 outputs a high-level gain control signal P1, and the first capacitor C1 in the gain adjustment module 120 is in an integral state, with the integral gain being the first gain; in the photocurrent signal I... pd When the current is relatively large (1000mA), the effective signal voltage V obtained by the correlation dual sampling module 130 is... A When the voltage is less than the first voltage threshold, the gain control feedback module 140 outputs a low-level gain control signal P1. The first capacitor C1 and the second capacitor C2 in the gain adjustment module 120 are both in the integral state, and the integral gain is the second gain.
[0044] This invention provides a pixel readout circuit and its control method. The pixel readout circuit includes a photoelectric conversion module, a gain adjustment module, a correlation dual sampling module, a gain control feedback module, and an output module. The photoelectric conversion module converts an optical signal into a photocurrent signal. The gain adjustment module integrates the photocurrent signal to obtain an integrated voltage. The correlation dual sampling module samples the integrated voltage to obtain an effective signal voltage. The gain control feedback module generates a gain control signal based on the effective signal voltage, thereby adjusting the integral gain. The output module buffers and outputs the effective signal voltage. The circuit provided by this invention uses fewer switches, simplifies timing control, reduces pixel area, and has high chip integration. Integrating the correlation dual sampling function within the pixel avoids multiple signal transmissions between the pixel and column-level circuits, reducing the processing pressure on the column-level circuits and improving the system frame rate. The automatic switching function of the integrating capacitor is integrated within the pixel, effectively improving the pixel's dynamic range through automatic capacitor switching. A single-ended amplifier structure is used, which has high gain and effectively reduces pixel noise.
[0045] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A pixel readout circuit, characterized in that, include: The photoelectric conversion module converts the incident light signal into a photocurrent signal; A gain adjustment module, electrically connected to the photoelectric conversion module, performs integration processing on the photocurrent signal to obtain an integrated voltage; A related dual sampling module, electrically connected to the gain adjustment module, samples and holds the integrated voltage to obtain an effective signal voltage related to the optical signal; The gain control feedback module is electrically connected to the correlated dual sampling module and the gain adjustment module respectively. In response to the effective signal voltage, it generates a gain control signal and outputs it to the gain adjustment module to adjust the integral gain of the gain adjustment module. The output module is electrically connected to the related dual sampling module and is used to buffer the output of the effective signal voltage.
2. The pixel readout circuit according to claim 1, characterized in that, The gain adjustment module includes a first capacitor, a second capacitor, a first PMOS transistor, a second PMOS transistor, and an amplification unit. The amplification unit is used to amplify the photocurrent signal. The first terminal of the first capacitor is connected to the input terminal of the amplification unit, and the second terminal of the first capacitor is connected to the output terminal of the amplification unit. The drain of the first PMOS transistor is connected to the first terminal of the first capacitor, and the drain of the first PMOS transistor is also connected to the first terminal of the second capacitor. The gate of the first PMOS transistor is connected to a first reset signal. The second terminal of the second capacitor is connected to the drain of the second PMOS transistor, and the source of the first PMOS transistor is connected to the second terminal of the first capacitor, and the source of the first PMOS transistor is also connected to the source of the second PMOS transistor. The input terminal of the amplification unit is the input terminal of the gain adjustment module, the output terminal of the amplification unit is the output terminal of the gain adjustment module, and the gate of the second PMOS transistor is the gain adjustment terminal of the gain adjustment module.
3. The pixel readout circuit according to claim 2, characterized in that, The amplification unit includes a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the fourth PMOS transistor is connected to a first bias voltage, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the first NMOS transistor is connected to a second bias voltage, the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to a third bias voltage. The gate of the third PMOS transistor is the input terminal of the amplification unit, and the drain of the fourth PMOS transistor is the output terminal of the amplification unit.
4. The pixel readout circuit according to claim 2, characterized in that, The capacitance value of the second capacitor is a preset multiple of the capacitance value of the first capacitor.
5. The pixel readout circuit according to claim 1, characterized in that, The correlated dual sampling module includes a third NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third capacitor, and a fourth capacitor. The source of the third NMOS transistor is connected to the drain of the fifth PMOS transistor, and the drain of the third NMOS transistor is connected to the source of the fifth PMOS transistor. The gate of the third NMOS transistor is connected to a first sampling signal, and the gate of the fifth PMOS transistor is connected to a second sampling signal. The drain of the third NMOS transistor is connected to the first terminal of the fourth capacitor, and the first terminal of the fourth capacitor is grounded after passing through the third capacitor. The second terminal of the fourth capacitor is connected to the drain of the sixth PMOS transistor, the source of the sixth PMOS transistor is connected to a reference voltage, and the gate of the sixth PMOS transistor is connected to a second reset signal. The source of the third NMOS transistor is the input terminal of the correlated dual sampling module, and the second terminal of the fourth capacitor is the output terminal of the correlated dual sampling module. The level of the first sampling signal is opposite to the level of the second sampling signal.
6. The pixel readout circuit according to claim 1, characterized in that, The gain control feedback module includes a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, and an inverter. The output of the inverter is connected to the source of the fourth NMOS transistor, the drain of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fourth NMOS transistor is connected to a first control signal, the source of the fifth NMOS transistor is grounded, the gate of the fifth NMOS transistor is connected to a second control signal, the drain of the fourth NMOS transistor is also connected to the source of the sixth NMOS transistor, the drain of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor, the source of the seventh NMOS transistor is grounded, the gate of the seventh PMOS transistor is connected to a third reset signal, and the gate of the sixth NMOS transistor is connected to the first NMOS transistor. The gate of the ninth PMOS transistor is connected to the power supply voltage. The drain of the ninth PMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the ninth PMOS transistor is also connected to the source of the tenth PMOS transistor. The gate of the tenth PMOS transistor is connected to the gate of the eighth NMOS transistor. The gate of the tenth PMOS transistor is also connected to the drain of the sixth NMOS transistor. The drain of the tenth PMOS transistor is connected to the drain of the eighth NMOS transistor. The drain of the tenth PMOS transistor is also connected to the gate of the sixth NMOS transistor. The source of the eighth NMOS transistor is grounded. The input terminal of the inverter is the input terminal of the gain control feedback module. The drain of the tenth PMOS transistor is the output terminal of the gain control feedback module. The first control signal and the second control signal have opposite levels.
7. The pixel readout circuit according to claim 1, characterized in that, The photoelectric conversion module includes a photodiode and a parasitic capacitor. The first end of the parasitic capacitor is connected to the cathode of the photodiode, and the second end of the parasitic capacitor is connected to the anode of the photodiode. The cathode of the photodiode is connected to the power supply voltage, and the anode of the photodiode is the output terminal of the photoelectric conversion module.
8. A control method applied to the pixel readout circuit as described in any one of claims 1-7, characterized in that, include: Acquire the photocurrent signal and perform a reset operation based on the reset signal; The photocurrent signal is integrated to obtain the integrated voltage; Under the control of the sampling signal, the integrated voltage is sampled and held to obtain the effective signal voltage; A gain control signal is generated based on the effective signal voltage to adjust the integral gain of the integral processing.
9. The control method for the pixel readout circuit according to claim 8, characterized in that, A gain control signal is generated based on the effective signal voltage to adjust the integral gain of the integral processing process, including: When the effective signal voltage is greater than or equal to the first voltage threshold, the gain control feedback module outputs a high-level gain control signal and maintains it, and the integral gain is the first gain; When the effective signal voltage is less than the first voltage threshold, the gain control feedback module outputs a low-level gain control signal and maintains it, and the integral gain is the second gain; Wherein, the second gain is greater than the first gain.