Low-power-consumption high-dynamic-range integrator suitable for Delta-Sigma modulator

Abstract

The invention relates to a low-power-consumption and high-dynamic-range integrator suitable for a Delta-Sigma modulator, and belongs to the field of integrated circuit design. The integrator specially sets an equivalent thermal noise compression mode B for a small-amplitude input signal on the basis of a traditional integrator. Under a large-amplitude input signal, an integrator is set to be in a traditional mode A; under a small-amplitude input signal, the integrator is set to be in an equivalent thermal noise compression mode B; in the mode B, signal sampling is multiplied by performing bidirectional sampling on an input signal, but introduced noise is not multiplied compared with that in a traditional mode generally, and then the integral state of the integrator and the integral gain of the signal are not changed by doubling the integrating capacitor, so that the integral gain of the signal is not changed. The integrator does not cause system faults in the application occasion of the Delta-Sigma modulator, compared with a traditional integrator, the output or equivalent input noise power of the integrator is compressed to 1 / 4 of the original noise power, and the dynamic range of the integrator is widened by 6dB on the premise that the power consumption overhead of the integrator is not increased.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a low-power, high dynamic range integrator suitable for Delta-Sigma modulators. Background Technology

[0002] With the rapid development of the Internet of Things (IoT), smart sensors, and portable audio devices, the demand for high-precision, low-power analog-to-digital converters (ADCs) is becoming increasingly urgent. As a core module of ADC systems, the Delta-Sigma modulator, with its oversampling and noise shaping characteristics, effectively suppresses quantization noise and achieves high-resolution signal conversion, thus playing an irreplaceable role in digital audio processing, medical electronics, and industrial control. However, a significant contradiction remains between the dynamic range and power consumption of modulators in current technology: on the one hand, battery-powered devices require circuits to operate at microwatt-level power consumption to extend battery life; on the other hand, acquiring weak signals in complex electromagnetic environments requires a wide dynamic range exceeding 100dB to ensure signal integrity. This contradiction is particularly prominent in the design of the first-stage integrator of the modulator, as its performance, as the starting point for noise shaping, directly determines the upper limit of the signal-to-noise ratio of the entire modulator. However, existing technologies face constraints from underlying physical mechanisms: the thermal noise contribution of the first-stage integrator exceeds 70%, becoming a key bottleneck restricting the improvement of the dynamic range of Delta-Sigma modulators. In traditional integrator designs, to balance power consumption and chip area, the sampling capacitor is often compressed to the sub-picofarad level. This results in a significant increase in thermal noise power due to the physical law that is inversely proportional to the square root of the capacitance. However, simply increasing the capacitance leads to an exponential increase in the operational amplifier's drive current demand, causing a surge in power consumption. Therefore, how to suppress the thermal noise of the first-stage integrator in a Delta-Sigma modulator without increasing system power consumption has become an urgent problem. Summary of the Invention

[0003] The purpose of this invention is to solve the problem that the dynamic range of traditional integrators is severely limited by device thermal noise, and to provide a low-power, high dynamic range integrator suitable for Delta-Sigma modulators. The invention aims to suppress the impact of device thermal noise on the system by employing equivalent thermal noise compression technology on the integrator under small-amplitude input signals, thereby improving the dynamic range of the Delta-Sigma modulator. This invention successfully expands the dynamic range of the integrator without sacrificing system power consumption, and has broad market application prospects.

[0004] To achieve the above objectives, the technical solution of the present invention is: a low-power, high dynamic range integrator suitable for Delta-Sigma modulators, which improves the dynamic range of the integrator in Delta-Sigma modulators by suppressing the influence of device thermal noise on the system through equivalent thermal noise compression technology on the integrator under small-amplitude input signals.

[0005] Furthermore, under small-amplitude input signals, the integrator is set to equivalent thermal noise compression mode B, and under large-amplitude input signals, the integrator is set to conventional mode A.

[0006] Furthermore, in the equivalent thermal noise compression mode B, the signal sampling is multiplied by bidirectional sampling of the input signal, and the integration capacitor is doubled. The integration state of the integrator and the integration gain of the signal do not change. At this time, the output or equivalent input noise power of the integrator is compressed to 1 / 4 of the original, and the dynamic range of the integrator is widened without increasing the power consumption of the integrator.

[0007] Furthermore, under the equivalent thermal noise compression mode B, the dynamic range of the integrator is widened by 6dB.

[0008] Furthermore, in the equivalent thermal noise compression mode B, the input signal is sampled bidirectionally, specifically by adding a set of switching devices to the integrator circuit.

[0009] Furthermore, in the equivalent thermal noise compression mode B, the integrating capacitor is doubled, specifically by adding a set of switching devices and a set of capacitors to the integrator circuit.

[0010] Furthermore, the integrator includes switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW11, SW12, SW13, and SW14, and capacitor C. s1a C s1b C INT1Ca C INT1Cb C INT1a C INT1b And operational amplifier OTA, first input signal V ip Through one end of SW1 and SW7, C s1a One end is connected to the first input signal V ip Also via one end of SW4 and SW6, one end of SW10, and C s1b One end is connected to the second input signal V. in Through one end of SW2 and SW8, C s1b The other end is connected to the second input signal V. in Also via one end of SW3 and SW5, one end of SW9, and C s1aThe other ends of SW5, SW6, SW7, and SW8 are all connected to GND. The other end of SW9 is connected to the inverting input of OTA, one end of SW11, and one end of SW13, respectively. The other ends of SW11 and SW13 are connected via C... INT1Ca C INT1a Connected to the first output terminal of OTA, the other end of SW10 is connected to the non-inverting input terminal of OTA, one end of SW12, and one end of SW14 respectively. The other ends of SW12 and SW14 are respectively connected via C INT1Cb、 C INT1b Connect to the second output terminal of OTA.

[0011] Furthermore, the control terminals of SW1 and SW2 are connected to the first clock signal Φ1, the control terminals of SW3 and SW4 are connected to the second clock signal Φ1b, the control terminals of SW5 and SW6 are connected to the third clock signal Φ1a, the control terminals of SW7, SW8, SW9, SW10, SW13 and SW14 are connected to the fourth clock signal Φ2, and the control terminals of SW11 and SW12 are connected to the fifth clock signal Φ2b.

[0012] Furthermore, the integrator includes the following two operating modes:

[0013] Traditional Model A:

[0014] During the sampling period, the clock signal Φ1 and Φ1a are high, SW1, SW2, SW5, and SW6 are closed, and the differential input signal V... ip With V in They were saved to C respectively S1a With C S1b Above; simultaneously, due to the thermal noise of the switching devices, there will be a power of kT / C S1a With kT / C S1b The noise is also stored in C S1a With C S1b Above, k is the Boltzmann constant, with a value of approximately T is absolute temperature, which is the temperature in Kelvin, such as room temperature (about 300K).

[0015] During the integration period, Φ2 is high, and SW7, SW8, SW9, SW10, SW13, and SW14 are closed, existing in C. S1a With C S1b The signal charge on it will flow to C INT1a With C INT1b Similar to the sampling period, due to the influence of device thermal noise, the sampling capacitor C will also be affected during the integration period. S1a With C S1b The power generated is kT / C S1a With kT / CS1b The noise, this part of the noise charge will also be transferred to C. INT1a With C INT1b ; Set C S1a =C S1b =C S1 C INT1a =C INT1b =C INT1 Furthermore, the initial value of the integrating capacitor is 0. After one cycle, due to the lack of correlation between the sampling and integration period noise, the combined noise effects of the sampling and integration periods result in the final differential output of the integrator being:

[0016] (1)

[0017] The equivalent input signal-to-noise ratio of the integrator is:

[0018] (2)

[0019] in Represents the input signal power. These are the outputs of the first and second output terminals of the OTA system, respectively.

[0020] Equivalent thermal noise compression mode B:

[0021] During the sampling period, the clock signal Φ1 and Φ1b are high, SW1, SW2, SW3, and SW4 are closed, and signal V... ip -V in With V in -V ip And saved to C S1a With C S1b Since it is a differential signal, there exists a relationship V. in =-V ip Therefore, V exists. ip -V in =2V ip V in -V ip =2V in Compared to mode A, mode B collects twice the input signal; simultaneously, due to the thermal noise of the switching devices, there will be a power of kT / C. S1a With kT / C S1b Noise also exists in C S1a With C S1b Since the sampling signal is doubled, in order to ensure that the Delta-Sigma regulator does not malfunction due to mode switching, the integral state and integral gain of the integrator should not change, so the integral capacitor should also be increased to twice its original value.

[0022] During the integration period, Φ2 and Φ2b are high, and SW7, SW8, SW9, SW10, SW11, SW12, SW13, and SW14 are closed, existing in C. S1a With C S1b The signal charge on it will flow to C INT1a +C INT1Ca With C INT1b +C INT1Cb Similar to the sampling period, due to the influence of device thermal noise, the sampling capacitor C will also be affected during the integration period. S1a With C S1b The power generated is kT / C S1a With kT / C S1a The noise, this part of the noise charge will also be transferred to C. INT1a +C INT1Ca With C INT1b +C INT1Cb ; Set C S1a =C S1b =C S1 C INT1a =C INT1b =C INT1Ca =C INT1Cb =C INT1 Furthermore, the initial value of the integrating capacitor is 0. After one cycle, since the noise of the sampling period and the integration period are uncorrelated, the combined noise effects of the sampling period and the integration period result in the final differential output of the integrator being:

[0023] (3)

[0024] The equivalent input signal-to-noise ratio of the integrator is:

[0025] (4)

[0026] By comparing formulas (2) and (4), it is found that under mode B, the equivalent input thermal noise power of mode B is suppressed to 1 / 4 of the original, that is, the equivalent input signal-to-noise ratio of the final integrator is increased by 6dB, which makes the minimum input signal amplitude of the integrator drop by 6dB and improves the dynamic range by 6dB.

[0027] Furthermore, the integrator is suitable for the design of low-power, high dynamic range Delta-Sigma modulators.

[0028] Compared to existing technologies, this invention offers the following advantages: This invention provides a low-power, high dynamic range integrator suitable for Delta-Sigma modulators. By employing equivalent thermal noise compression technology on the integrator under small-amplitude input signals, it suppresses the impact of device thermal noise on the system, thereby improving the dynamic range of the integrator in Delta-Sigma modulators. This solution successfully improves the dynamic range of the integrator without sacrificing circuit power consumption, making it suitable for the design of low-power, high dynamic range Delta-Sigma modulators and possessing broad market application prospects. Attached Figure Description

[0029] Figure 1 It is a traditional integrator.

[0030] Figure 2 This invention relates to a low-power, high dynamic range integrator with equivalent thermal noise compression. Detailed Implementation

[0031] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0032] This invention provides a low-power, high dynamic range integrator suitable for Delta-Sigma modulators. By employing equivalent thermal noise compression technology on the integrator under small-amplitude input signals, the influence of device thermal noise on the system is suppressed, thereby improving the dynamic range of the integrator in Delta-Sigma modulators.

[0033] The following is a detailed implementation process of the present invention.

[0034] Figure 1 This demonstrates a traditional integrator model in a Delta-Sigma modulator. During the sampling period, the clock signal Φ1 is high, SW1, SW2, SW3, and SW4 are closed, and the differential input signal V... ip With V in They were respectively saved to the sampling capacitor C S1a With C S1b Above. Meanwhile, due to thermal noise from the switching devices, there will be a power of kT / C. S1a With kT / C S1b The noise is also stored in C S1a With C S1b Above. During the integration period, Φ2 is high, and SW5, SW6, SW7, SW8, SW9, and SW10 are closed, existing in C. S1a With C S1b The signal charge on the capacitor will flow to the integrator capacitor C. INT1a With C INT1b Similar to the sampling period, due to the influence of device thermal noise, the sampling capacitor C will also be affected during the integration period. S1a With CS1b The power generated is kT / C S1a With kT / C S1b The noise, and this noise charge, will also be transferred to the integrating capacitor. Set C... S1a =C S1b =C S1 C INT1a =C INT1b =C INT1 Furthermore, the initial value of the integrating capacitor is 0. After one cycle, since the sampling and integration period noise are uncorrelated, the combined effects of the sampling and integration period noise result in the final differential output of the integrator being:

[0035] (1)

[0036] The equivalent input signal-to-noise ratio of the integrator system is:

[0037] (2)

[0038] in The input signal power is represented by the device thermal noise caused by the sampling and integration period. The integrator introduces a lot of noise, which limits the equivalent input signal-to-noise ratio and the minimum input signal power of the integrator, and severely limits the dynamic range of the integrator.

[0039] To improve the dynamic range performance of the integrator without increasing its power consumption in the Delta-Sigma modulator, this invention proposes an integrator with equivalent thermal noise compression, such as... Figure 2 As shown. To improve the dynamic range of the integrator in a Delta-Sigma modulator, this invention designs the integrator in two state modes: under large-amplitude input signals, to increase the maximum input amplitude of the integrator, the integrator is set to conventional mode A; under small-amplitude input signals, to achieve a lower input amplitude of the integrator, the integrator is set to equivalent thermal noise compression mode B.

[0040] In traditional mode A, consistent with traditional integrators, during the sampling period, the clock signal Φ1 and Φ1a are high, SW1, SW2, SW5, and SW6 are closed, and the differential input signal V... ip With V in They were respectively saved to the sampling capacitor C S1a With C S1b Above. Meanwhile, due to thermal noise from the switching devices, there will be a power of kT / C. S1a With kT / C S1b The noise is also stored in C S1a With C S1bAbove. During the integration period, Φ2 is high, SW7, SW8, SW9, SW10, SW13, and SW14 are closed, existing in C. S1a With C S1b The signal charge on the capacitor will flow to the integrator capacitor C. INT1a With C INT1b Similar to the sampling period, due to the influence of device thermal noise, the sampling capacitor C will also be affected during the integration period. S1a With C S1b The power generated is kT / C S1a With kT / C S1b The noise, and this noise charge, will also be transferred to the integrating capacitor. Set C... S1a =C S1b =C S1 C INT1a =C INT1b =C INT1 Furthermore, the initial value of the integrating capacitor is 0. After one cycle, since the sampling and integration cycle noise are not correlated, the combined noise effects of the sampling and integration cycle result in the final signal-to-noise ratio of the differential output and equivalent input of the integrator being consistent with formulas (1) and (2).

[0041] In equivalent thermal noise compression mode B, during the sampling period, clock signals Φ1 and Φ1b are high, SW1, SW2, SW3, and SW4 are closed, and signal V... ip -V in With V in -V ip With the sampled capacitor C S1a With C S1b Since it is a differential signal, there exists a relationship V. in =-V ip Therefore, V exists. ip -V in =2V ip V in -V ip =2V in Compared to mode A, mode B collects twice the input signal. Meanwhile, due to thermal noise from the switching devices, there will be a power of kT / C. S1a With kT / C S1b Noise also exists in C S1a With C S1b Above. Since the sampling signal is doubled, to ensure the Delta-Sigma adjuster does not malfunction due to mode switching, the integrator's integral state and integral gain should not change. Therefore, the integrating capacitor should also be increased to twice its original size. During the integration period, Φ2 and Φ2b are high, SW7, SW8, SW9, SW10, SW11, SW12, SW13, and SW14 are closed, existing in C. S1a With CS1b The signal charge on the capacitor will flow to the integrator capacitor C. INT1a +C INT1Ca With C INT1b +C INT1Cb Similar to the sampling period, due to the influence of device thermal noise, the sampling capacitor C will also be affected during the integration period. S1a With C S1b The power generated is kT / C S1a With kT / C S1a The noise, and this noise charge, will also be transferred to the integrating capacitor. If C S1a =C S1b =C S1 C INT1a =C INT1b =C INT1Ca =C INT1Cb =C INT1 Furthermore, the initial value of the integrating capacitor is 0. After one cycle, since the noise of the sampling period and the integration period are uncorrelated, the combined noise effects of the sampling period and the integration period result in the final differential output of the integrator being:

[0042] (3)

[0043] The equivalent input signal-to-noise ratio of the integrator system is:

[0044] (4)

[0045] By comparing formulas (2) and (4), it can be found that in mode B, the equivalent input thermal noise power of mode B is suppressed to 1 / 4 of the original. This means that the equivalent input signal-to-noise ratio of the final integrator is increased by 6dB, thereby reducing the minimum input signal amplitude of the integrator by 6dB and increasing the dynamic range by 6dB.

[0046] It can be seen that the proposed low-power, high dynamic range integrator scheme can successfully improve the dynamic range of the integrator without sacrificing circuit power consumption. It is suitable for the design of low-power, high dynamic range Delta-Sigma modulators and has broad market application prospects.

[0047] The above are preferred embodiments of the present invention. Any changes made to the technical solution of the present invention that do not exceed the scope of the technical solution of the present invention shall fall within the protection scope of the present invention.

Claims

1. A low-power, high dynamic range integrator suitable for Delta-Sigma modulators, characterized in that, By employing equivalent thermal noise compression technology on the integrator under small-amplitude input signals, the influence of device thermal noise on the system is suppressed, thereby improving the dynamic range of the integrator in the Delta-Sigma modulator.

2. The low-power, high dynamic range integrator suitable for Delta-Sigma modulators according to claim 1, characterized in that, For small-amplitude input signals, the integrator is set to equivalent thermal noise compression mode B, and for large-amplitude input signals, the integrator is set to conventional mode A.

3. A low-power, high dynamic range integrator suitable for Delta-Sigma modulators according to claim 2, characterized in that, In the equivalent thermal noise compression mode B, the signal sampling is multiplied by bidirectional sampling of the input signal. Then, by doubling the integrating capacitor, the integral state of the integrator and the integral gain of the signal do not change. At this time, the output or equivalent input noise power of the integrator is compressed to 1 / 4 of the original, and the dynamic range of the integrator is widened without increasing the power consumption of the integrator.

4. A low-power, high dynamic range integrator suitable for Delta-Sigma modulators according to claim 3, characterized in that, Under the equivalent thermal noise compression mode B, the dynamic range of the integrator is widened by 6dB.

5. A low-power, high dynamic range integrator suitable for Delta-Sigma modulators according to claim 3, characterized in that, In the equivalent thermal noise compression mode B, the input signal is sampled bidirectionally, specifically by adding a set of switching devices to the integrator circuit.

6. A low-power, high dynamic range integrator suitable for Delta-Sigma modulators according to claim 3, characterized in that, In the equivalent thermal noise compression mode B, the integrating capacitor is doubled, specifically by adding a set of switching devices and a set of capacitors to the integrator circuit.

7. A low-power, high dynamic range integrator suitable for Delta-Sigma modulators according to claim 1, characterized in that, Includes switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW11, SW12, SW13, and SW14, and capacitor C. s1a C s1b C INT1Ca C INT1Cb C INT1a C INT1b And operational amplifier OTA, first input signal V ip Through one end of SW1 and SW7, C s1a One end is connected to the first input signal V ip Also via one end of SW4 and SW6, one end of SW10, and C s1b One end is connected to the second input signal V. in Through one end of SW2 and SW8, C s1b The other end is connected to the second input signal V. in Also via one end of SW3 and SW5, one end of SW9, and C s1a The other ends of SW5, SW6, SW7, and SW8 are all connected to GND. The other end of SW9 is connected to the inverting input of OTA, one end of SW11, and one end of SW13, respectively. The other ends of SW11 and SW13 are connected via C... INT1Ca C INT1a Connected to the first output terminal of OTA, the other end of SW10 is connected to the non-inverting input terminal of OTA, one end of SW12, and one end of SW14 respectively. The other ends of SW12 and SW14 are respectively connected via C INT1Cb、 C INT1b Connect to the second output terminal of OTA.

8. A low-power, high dynamic range integrator suitable for Delta-Sigma modulators according to claim 7, characterized in that, The control terminals of SW1 and SW2 are connected to the first clock signal Φ1, the control terminals of SW3 and SW4 are connected to the second clock signal Φ1b, the control terminals of SW5 and SW6 are connected to the third clock signal Φ1a, the control terminals of SW7, SW8, SW9, SW10, SW13 and SW14 are connected to the fourth clock signal Φ2, and the control terminals of SW11 and SW12 are connected to the fifth clock signal Φ2b.

9. A low-power, high dynamic range integrator suitable for Delta-Sigma modulators according to claim 8, characterized in that, The integrator includes the following two operating modes: Traditional Model A: During the sampling period, the clock signal Φ1 and Φ1a are high, SW1, SW2, SW5, and SW6 are closed, and the differential input signal V... ip With V in They were saved to C respectively S1a With C S1b Above; simultaneously, due to the thermal noise of the switching devices, there will be a power of kT / C S1a With kT / C S1b The noise is also stored in C S1a With C S1b Above, k is Boltzmann's constant, and T is the absolute temperature; During the integration period, Φ2 is high, and SW7, SW8, SW9, SW10, SW13, and SW14 are closed, existing in C. S1a With C S1b The signal charge on it will flow to C INT1a With C INT1b Similar to the sampling period, due to the influence of device thermal noise, the sampling capacitor C will also be affected during the integration period. S1a With C S1b The power generated is kT / C S1a With kT / C S1b The noise, this part of the noise charge will also be transferred to C. INT1a With C INT1b ; Set C S1a =C S1b =C S1 C INT1a =C INT1b =C INT1 Furthermore, the initial value of the integrating capacitor is 0. After one cycle, due to the lack of correlation between the sampling and integration period noise, the combined noise effects of the sampling and integration periods result in the final differential output of the integrator being: (1) The equivalent input signal-to-noise ratio of the integrator is: (2) in Represents the input signal power. These are the outputs of the first and second output terminals of the OTA system, respectively. Equivalent thermal noise compression mode B: During the sampling period, the clock signal Φ1 and Φ1b are high, SW1, SW2, SW3, and SW4 are closed, and signal V... ip -V in With V in -V ip And saved to C S1a With C S1b Since it is a differential signal, there exists a relationship V. in =-V ip Therefore, V exists. ip -V in =2V ip V in -V ip =2V in Compared to mode A, mode B collects twice the input signal; simultaneously, due to the thermal noise of the switching devices, there will be a power of kT / C. S1a With kT / C S1b Noise also exists in C S1a With C S1b Since the sampling signal is doubled, in order to ensure that the Delta-Sigma regulator does not malfunction due to mode switching, the integral state and integral gain of the integrator should not change, so the integral capacitor should also be increased to twice its original value. During the integration period, Φ2 and Φ2b are high, and SW7, SW8, SW9, SW10, SW11, SW12, SW13, and SW14 are closed, existing in C. S1a With C S1b The signal charge on it will flow to C INT1a +C INT1Ca With C INT1b +C INT1Cb Similar to the sampling period, due to the influence of device thermal noise, the sampling capacitor C will also be affected during the integration period. S1a With C S1b The power generated is kT / C S1a With kT / C S1a The noise, this part of the noise charge will also be transferred to C. INT1a +C INT1Ca With C INT1b +C INT1Cb ; Set C S1a =C S1b =C S1 C INT1a =C INT1b =C INT1Ca =C INT1Cb =C INT1 Furthermore, the initial value of the integrating capacitor is 0. After one cycle, since the noise of the sampling period and the integration period are uncorrelated, the combined noise effects of the sampling period and the integration period result in the final differential output of the integrator being: (3) The equivalent input signal-to-noise ratio of the integrator is: (4) By comparing formulas (2) and (4), it is found that under mode B, the equivalent input thermal noise power of mode B is suppressed to 1 / 4 of the original, that is, the equivalent input signal-to-noise ratio of the final integrator is increased by 6dB, which makes the minimum input signal amplitude of the integrator drop by 6dB and improves the dynamic range by 6dB.

10. A low-power, high dynamic range integrator suitable for Delta-Sigma modulators according to claim 1, characterized in that, The integrator is suitable for the design of low-power, high dynamic range Delta-Sigma modulators.

Images