Device and method for simulation test of wireless communication system

Abstract

The invention provides a device and a method for a simulation test of a wireless communication system, and the device comprises an FPGA board card which comprises an FPGA chip and a cache control module, the FPGA chip is configured to realize each function unit for executing decoding in the wireless communication system to be tested through programmable logic, and the cache control module is configured to control the FPGA chip to execute decoding in the wireless communication system to be tested; the cache control module is configured to cache the baseband data and the processing result to a preset storage position; the FPGA board card is set to contain at least two working modes, in the first working mode, the FPGA board card is configured to forward a corresponding processing result to the upper computer after processing baseband data with a preset symbol number every time and monitor whether a switching request for switching to the second working mode is obtained or not, if yes, the FPGA board card is switched to the second working mode, and if not, the FPGA board card is switched to the second working mode; the switching request is sent out when the upper computer determines that the decoding performance is not expected according to the received processing result; and in the second working mode, the FPGA board card is configured to suspend the processing of the baseband data and transmit the original baseband data to the upper computer in an unvarnished manner.

Description

Technical Field

[0001] The present invention relates to the field of communications, in particular to the technical field of wireless communication simulation test platforms, and more particularly to a device and method for simulation testing of wireless communication systems. Background Art

[0002] With the demand for high-speed data transmission in the 5G and 6G eras, how to achieve high-speed and efficient data transmission has always been a hot topic of research. Traditional bus technologies such as the Industrial Standard Architecture (ISA) and the Peripheral Component Interconnect (PCI) can no longer meet the needs of high-speed I / O communication.

[0003] Therefore, the third-generation I / O bus standard, Peripheral Component Interconnect Express (PCIe), is often selected as a high-speed data transmission bus standard for terminal devices to interact with personal computers (PCs). The PCIe bus uses end-to-end, full-duplex, differential signals for signal transmission. The connected devices are allocated exclusive channel bandwidth, which avoids interference between signals and greatly improves the performance of data transmission. It is widely used in high-speed data transmission scenarios.

[0004] In the process of wireless communication system design, a simulation test platform is often needed to analyze and test the designed wireless communication system to determine whether there are problems with certain functional units of the designed wireless communication system and make improvements. When the inventor was conducting research on high-speed data processing of wireless communication systems, he found that the simulation test process involves decoding the baseband data in the wireless communication system to analyze the bit error rate; although the PC has powerful data processing capabilities and can handle complex precision calculations, the processing speed is slow. Therefore, the prior art uses FPGA (field programmable gate array) to accelerate the signal processing process. FPGA can perform signal processing in parallel and has a fast processing speed. It is often used in scenarios with high real-time requirements. During simulation testing, the hardware of FPGA can be used to implement and test the various functional units that decode the baseband data. However, the prior art has the following problems:

[0005] 1. Using FPGA to process situations where it is difficult to monitor intermediate signal processing in real time;

[0006] 2. If the decoding effect does not meet the standard during FPGA processing, it is difficult to quickly conduct a more detailed analysis due to the limited functions of FPGA. It is necessary to use PC for more detailed analysis, which makes the test process repetitive and cumbersome, resulting in high test overhead. Because after the problem is found in the test phase, it is necessary to manually adjust the equipment that receives and processes the baseband data and repeat the simulation process, resulting in insufficient flexibility and affecting the development efficiency of the wireless communication system. Summary of the invention

[0007] Therefore, the purpose of the present invention is to overcome the above-mentioned defects of the prior art and provide a device and method for simulation testing of a wireless communication system.

[0008] The objective of the present invention is achieved through the following technical solutions:

[0009] According to a first aspect of the present invention, there is provided a device for simulating a wireless communication system, comprising: an FPGA board, comprising an FPGA chip and a cache control module, wherein the FPGA chip is configured to implement various functional units for performing decoding in a wireless communication system to be tested through programmable logic, so as to process received baseband data to obtain a processing result, wherein the processing result is a CRC check decoding result, and the cache control module is configured to cache the baseband data and the processing result to a preset storage location; the FPGA board is configured to have at least two working modes, wherein: working mode one: the FPGA board is configured to forward the corresponding processing result to a host computer after processing a predetermined number of baseband data symbols, and monitor whether a switching request to switch to working mode two is obtained, and if so, the switching is switched to working mode two in response to the switching request, wherein the switching instruction is issued by the host computer when it determines that the decoding performance is not as expected according to the received processing result; working mode two: the FPGA board is configured to suspend the processing of baseband data, and transparently transmit the processed baseband data and the subsequently received baseband data to the host computer.

[0010] Optionally, the device also includes: an SDR radio frequency board, which is configured to perform a simulation test on a wireless signal receiving process of a wireless communication system to be tested, perform radio frequency front-end receiving processing on the received radio frequency signal, obtain processed baseband data, and transmit the baseband data to the FPGA board; a host computer, which is configured to control the FPGA board and the SDR radio frequency board for test verification, and control the FPGA board and the SDR radio frequency board to test the signal receiving process under a plurality of preset signal-to-noise ratio levels and obtain corresponding baseband data, wherein a corresponding bit error rate threshold is preset for each signal-to-noise ratio level, and wherein the switching request is issued when the bit error rate of the currently received processing result is higher than the bit error rate threshold preset for the signal-to-noise ratio level corresponding to the processing result.

[0011] Optionally, the host computer is also configured to: preset multiple instruction generation interfaces based on API, and generate instructions for controlling the FPGA board and the SDR radio frequency board to perform corresponding operations by calling the API, wherein the multiple instruction generation interfaces include an interface for generating instructions corresponding to the switching request.

[0012] Optionally, the FPGA board also includes a first memory configured to cache baseband data received from the SDR radio frequency board, a second memory configured to cache processing results, and an FPGA chip, wherein the FPGA chip includes: a baseband data processing module, configured to implement various functional units that perform a decoding process in the wireless communication system to be tested through hardware, so as to decode the baseband data and obtain corresponding processing results; a real-time processing result framing module, configured to frame the processing results corresponding to the predetermined number of symbols after completing the processing of the baseband data of a predetermined number of symbols, to obtain a processing result frame; a two-selection module, configured to selectively obtain data from the first memory or the second memory and send it to the host computer through the XDMA module; and a downlink instruction processing module, configured to receive and execute instructions from the host computer, wherein, when an instruction corresponding to a switching request is received, the operating state of the corresponding module is adjusted to switch the working mode.

[0013] Optionally, when the instruction processing module receives the corresponding instruction of the switching request, the operation of the baseband data processing module and the real-time processing result framing module is suspended, and the two-choice module is controlled to change from obtaining the processing result frame from the second memory to obtaining the baseband data from the first memory and transparently transmitting it to the host computer.

[0014] Optionally, the two-choice module is configured as follows: in working mode one, a frame header is added to form a data frame after obtaining the processing result frame, and the processing result frame is sent to the host computer in the form of a data frame; in working mode two, a frame header is added to form a data frame after obtaining a predetermined number of baseband data in the order of baseband data reception, and the processing result frame is sent to the host computer in the form of a data frame; wherein the frame header contains a frame count parameter, which indicates the frame sequence number of the processing result frame or baseband data currently being sent.

[0015] Optionally, the host computer is also configured to: obtain the data output by each functional unit when the baseband data is subjected to theoretical simulation decoding; call a decoding program based on MATLAB to decode the received baseband data, wherein the decoding program is deployed with each functional unit that performs the decoding process in the wireless communication system to be tested, and after decoding, the data output by each functional unit in the decoding program of MATLAB is obtained; compare the data output by each functional unit during theoretical simulation decoding with the data output by each functional unit in the decoding program of MATLAB to locate the abnormal functional unit. Optionally, the host computer is also configured to: for different test scenarios, respectively set the data output by each functional unit during theoretical simulation decoding corresponding to the test scenario; when the SDR RF board and FPGA board are deployed to the corresponding test scenario, locate the abnormal functional unit according to the data output by each functional unit during theoretical simulation decoding corresponding to the test scenario.

[0016] Optionally, the size of the first memory is at least sufficient to store all baseband data during the simulation test, and the size of the second memory is at least sufficient to store all processing results during the simulation test.

[0017] According to a second aspect of the present invention, a method for testing a wireless communication system based on the device described in the first aspect is provided, comprising: B1, deploying each functional unit that performs a decoding process in the wireless communication system onto the FPGA chip; B2, deploying the device into an environment that needs to be tested and performing a test verification process of data reception and decoding, comprising: in an initial state, the FPGA board operates according to the working mode 1, and the host computer receives the processing result and displays the bit error rate calculated according to the processing result; when the decoding effect is not as expected, the host computer issues a switching request, and the FPGA board switches to the working mode 2 to transparently transmit the original baseband data; the host computer obtains the data output by each functional unit when theoretical simulation decoding is performed on the baseband data; the host computer calls a decoding program based on MATLAB to decode the received baseband data, wherein each functional unit that performs a decoding process in the wireless communication system to be tested is deployed in the decoding program, and the data output by each functional unit in the decoding program of MATLAB is obtained after decoding; the host computer compares the data output by each functional unit during theoretical simulation decoding with the data output by each functional unit in the decoding program of MATLAB to locate the abnormal functional unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0019] Figure 1 A schematic diagram of the module structure of a device for simulation testing of a wireless communication system according to an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of the module structure of an FPGA board according to an embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of a baseband data processing module according to an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of a host computer printing a CRC check decoding result according to an embodiment of the present invention;

[0023] Figure 5 The figure is a schematic diagram of a bit error rate curve displayed by a host computer according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0025] As mentioned in the background technology section, the existing technology has the problem that it is difficult to monitor signal processing, the equipment for processing baseband data needs to be manually adjusted after the simulation test has problems, which affects the development efficiency of the wireless communication system and is not flexible enough. In this regard, the inventor has found through research that the FPGA board has stronger parallel computing capabilities and faster processing speed, but when the various functional units of the wireless communication system to be tested and the analysis units for verification are fully implemented on the FPGA, the development cost will be high; the PC can handle complex calculations with high precision, but the processing speed is slow, but the PC itself can use corresponding analysis tools to perform more efficient and detailed analysis on the various functional units of the wireless communication system. Therefore, the PC can be used as a host computer to control the FPGA board for signal processing. Moreover, in order to efficiently test and quickly find problems, in the channel state verification scenario, only the verification decoding results need to be monitored in real time. To ensure the processing speed, the data processing at this stage should be placed in the FPGA board; when the verification decoding result is wrong, the original baseband data needs to be returned to the host computer for further correction analysis to locate the problem. In order to improve the adaptability of the communication system and reduce the development cost, the present invention is designed to provide a device for simulation testing of a wireless communication system in view of the above situation. Through the flexible communication mechanism designed therein, an FPGA board is always used to obtain baseband data, but the FPGA board is set to have at least two working modes. When the decoding effect meets the expectation, working mode one is adopted. At this time, the FPGA board can be used to efficiently process the baseband data, and the final CRC check decoding result is sent to the host computer to monitor the signal processing situation in real time; if the host computer determines that the decoding effect is not as expected according to the received processing result, a switching request is issued. At this time, the FPGA board is automatically switched to a data transfer device, and the processed baseband data and the subsequently received baseband data are transparently transmitted to the host computer; this process does not require manual configuration. When the decoding effect does not meet the standard, the processed baseband data stored in the FPGA board and the subsequently received baseband data can be directly used for more detailed analysis, so as to achieve flexible switching, avoid repeated operations, and improve the development efficiency of the wireless communication system.

[0026] The following will start with a device for wireless communication system simulation testing, first introducing an illustrative embodiment of the device; then, a method for testing the wireless communication system based on the device will be described.

[0027] According to one embodiment of the present invention, there is provided a device for simulation testing of a wireless communication system, comprising an FPGA board 100, an SDR radio frequency board and a host computer, wherein the FPGA board 100 is configured with a communication interface for connecting to the host computer and the SDR radio frequency board. The FPGA board 100 is a slave device and the host computer is a master device. In order to provide sufficient storage space, the FPGA board 100 can also use an external memory, and the device can also include: a first memory M1 and a second memory M2.

[0028] According to one embodiment of the present invention, the FPGA board 100 includes an FPGA chip 140, and the FPGA chip 140 is configured to implement various functional units that perform decoding in the wireless communication system to be tested through programmable logic, so as to process baseband data to obtain a processing result, wherein the baseband data is obtained by the SDR radio frequency board 200 performing radio frequency front-end processing on the received radio frequency data, and the processing result is a CRC check decoding result, and the cache control module 130 is configured to cache the baseband data and the processing result to a preset storage location; wherein the FPGA board 100 is configured to have at least two working modes, wherein:

[0029] Working mode 1: the FPGA board 100 is configured to forward the corresponding processing result to the upper computer 300 after processing the baseband data of a predetermined number of symbols, and monitor whether a switching request is obtained. If so, it switches to working mode 2 in response to the switching request. The switching request is issued by the upper computer 300 when it determines that the decoding performance is not as expected based on the received processing result;

[0030] Working mode 2: The FPGA board 100 is configured to suspend the processing of the baseband data, and transparently transmit the processed baseband data and the subsequently received baseband data to the host computer 300.

[0031] The following is a description of the exemplary implementations of each component:

[0032] (1) First memory M1 and second memory M2

[0033] According to one embodiment of the present invention, the first memory M1 is configured to cache the baseband data received from the SDR radio frequency board 200. The second memory M2 is configured to cache the processing results. Preferably, the size of the first memory M1 at least meets the storage of all baseband data during the simulation test, and the size of the second memory M2 at least meets the storage of all processing results during the simulation test. The first memory M1 is a DDR or Flash memory. The second memory M2 is a DDR or Flash memory. Schematically, the storage space size of the first memory M1 and the second memory M2 is greater than or equal to 8GB, preferably 16G, 32GB, etc. DDR memory is preferably used to achieve continuous storage and reading of data through the internal counting pointer of DDR. Of course, it should be understood that an interface for communication connection with the first memory M1 and the second memory M2 can be reserved on the FPGA board 100. When in use, the implementer purchases the first memory M1 and the second memory M2 that meet the simulation test needs and installs them.

[0034] (2) FPGA board 100

[0035] The FPGA board 100 can use some high-speed communication interfaces to implement external communication. Figure 2 , the FPGA board 100 and the host computer 300 are configured to communicate with each other through a preset first communication interface 110 (for example, Figure 2 The PCIe interface and PCIe controller provided by the XDMA module are shown. Of course, as technology changes, other communication interfaces, such as USB data cables, may also be used for connection. Schematically, the optical port module can adopt a four-channel SFP (small form factor pluggable) interface to achieve higher-speed hot plugging. The interface design of optical port communication is implemented using Xilinx's Aurora 64B / 66BIP core. The optical port module transmits relevant parameters to the SDR radio frequency board 200 and receives baseband data from the SDR radio frequency board 200. Its operating rate can be flexibly configured according to actual needs. The FPGA board 100 and the SDR radio frequency board 200 are configured to be able to communicate through a preset second communication interface 120 (for example, Figure 1Schematically, the XDMA module can use Xilinx's DMA / Bridge Subsystem for PCI Express IP core to implement the interface design of the PCIe bus standard. The FPGA board 100 can be connected to the first memory M1 and the second memory M2 through the interface corresponding to the first memory M1 and the second memory M2, and the cache control module 130 can be used to implement the storage control of the interface corresponding to the first memory M1 and the second memory M2 connected to the first memory M1 and the second memory M2. The cache control module 130 includes a baseband data cache control unit 131 and a processing result cache control unit 132. The baseband data cache control unit 131 is used to implement the storage control of caching the baseband data to the first memory M1, and the processing result cache control unit 132 is used to implement the storage control of caching the baseband data to the second memory M2.

[0036] The FPGA board 100 includes an FPGA chip 140, which is the main device for realizing functions. FPGA is the abbreviation of Field Programmable Gate Array. The FPGA chip 140 is a product further developed on the basis of programmable devices such as programmable array logic (PAL), programmable logic array (PLA), general array logic (GAL), and complex programmable logic device (CPLD). It overcomes the shortcomings of the limited number of gate circuits of the original programmable device, has a fast real-time processing speed, can process a large amount of data in parallel, and has strong flexibility. The schematic structure of the communication and function realization of the FPGA board 100 is described below. The schematic structure of the FGPA chip is described below. According to one embodiment of the present invention, the FPGA chip 140 includes a baseband data processing module 141, a real-time processing result framing module 142, a two-choice module 143, and a command processing module 144. The programmable logic gate array in the FPGA chip 140 can implement the baseband data processing module 141, the real-time processing result framing module 142, the two-choice module 143 and the instruction processing module 144 in a hardware manner. Among them:

[0037] The baseband data processing module 141 is configured to implement various functional units that perform the decoding process in the wireless communication system to be tested through hardware, so as to decode the baseband data and obtain corresponding processing results. The various functional units of the decoding process are determined according to the decoding program of the wireless communication system designed by the implementer, but for ease of understanding, Figure 3 A schematic structure of the baseband data processing module 141 is given; wherein the baseband data processing module 141 includes Figure 3In the various functional units shown, the input baseband data is processed by the cyclic prefix removal unit, the serial-to-parallel conversion unit, the FFT unit, the channel estimation unit, the channel equalization unit, the soft demodulation unit and the CRC check decoding unit in sequence to obtain the processing result. It should be understood that if the decoding program of the wireless communication system developed by the implementer is different, the functional units contained will be different. For example, in some cases, there may be no serial-to-parallel conversion unit, and the embodiment of the present invention does not limit this. The enable state of the data processing module in the FPGA board 100 can be changed by a switching request. When the FPGA board 100 is selected as the baseband data processing position, the module enable is valid, otherwise the module is reset to pause. In communication scenarios that focus on real-time performance and have low accuracy requirements, such as channel state estimation scenarios, only the CRC check decoding result needs to be paid attention to. Considering the processing speed of the host computer 300, placing the data processing position in the FPGA board 100 can greatly improve the data processing speed.

[0038] The real-time processing result framing module 142 is configured to frame the processing results corresponding to the predetermined number of symbols each time the baseband data of the predetermined number of symbols is processed to obtain a processing result frame. Schematically, it is assumed that the baseband data processing module 141 processes a symbol data approximately every 2ms to generate a single-bit processing result (CRC check decoding result). Considering that the host computer 300 initiates a read operation by calling an API function, it is necessary to frame the CRC check decoding result of the real-time processing and then transmit it back. Specifically, the input CRC check decoding result is cached, and the framing is completed at a frequency of 0.5s per frame, that is, each frame has a 250-bit check decoding result, and in order to verify the continuity of the framed data, the frame count parameter and the decoding result count parameter are placed in the frame header of each frame of data, and then the check decoding result after framing is sent to the processing result cache control module 130. Of course, the implementer can also select the number of bits of the CRC check decoding result contained in each frame after framing as needed.

[0039] The two-choose-one module 143 is configured to selectively obtain data from the first memory M1 or the second memory M2 and send it to the host computer 300 through the XDMA module. According to one embodiment of the present invention, the two-choose-one module 143 is configured to: in working mode 1, after obtaining the processing result frame, add a frame header to form a data frame, and send the processing result frame to the host computer 300 in the form of a data frame; in working mode 2, after obtaining a predetermined number of baseband data in the order of receiving the baseband data, add a frame header to form a data frame, and send the processing result frame to the host computer 300 in the form of a data frame; wherein the frame header contains a framing count parameter, and the framing count parameter indicates the framing sequence number of the processing result frame or baseband data currently sent. Schematically, the XDMA module can use Xilinx's DMA / Bridge Subsystem for PCI Express IP core to implement the interface design of the PCIe bus standard, receive data and related signals from the two-choose-one module 143, and complete the data interaction between the FPGA board 100 and the host computer 300. For example, when the host computer 300 initiates a read-back operation, the module selects corresponding return data from two DDR memories according to the control of the host computer 300, and then outputs the return data and matching related signals to the XDMA module according to the AXI protocol.

[0040] The instruction processing module 144 is configured to receive and execute instructions from the host computer 300, wherein when receiving an instruction corresponding to a switching request, the operating state of the corresponding module is adjusted to switch the working mode.

[0041] According to one embodiment of the present invention, when the instruction processing module 144 receives the instruction corresponding to the switching request, the operation of the baseband data processing module 141 and the real-time processing result framing module 142 is suspended, and the two-selection module 143 is controlled to change from obtaining the processing result frame from the second memory M2 to obtaining the baseband data from the first memory M1 and transparently transmitting it to the host computer 300. Preferably, the instruction processing module 144 is configured to receive the instruction issued by the host computer 300, identify the frame header according to the specific connection identifier, match and extract the instruction information under the specific instruction number; the type of instruction information includes the working configuration information of the SDR radio frequency board 200 and the working configuration information of the FPGA board 100; the working configuration information of the SDR radio frequency board 200 is transmitted to the SDR radio frequency board 200 through the optical port module to complete the working configuration of the SDR radio frequency board 200, wherein the working configuration information of the SDR radio frequency board 200 includes radio frequency working configuration information and data transmission framing length. For the working configuration information of the FPGA board 100, including the working configuration information corresponding to the instruction of the switching request, the instruction of the switching request includes a data processing position selection parameter for indicating the processing position of the baseband data; for example, 1 indicates that the baseband data is processed by the host computer 300, and 0 indicates that the baseband data is processed by the FPGA board 100. Of course, the instruction of the switching request can also be implemented in other ways, and it is not necessary to set the data processing position selection parameter in this form. For example, if there are only two working modes, a unique switching number indicating the need to switch can be set in the instruction. If the received instruction contains the switching number, the switch is performed. In addition, in addition to working mode one and working mode two, the implementer can also add other working modes, thereby, different working modes that need to be switched can be indicated by different switching numbers, and the embodiment of the present invention is not limited to this.

[0042] (3) SDR RF board 200

[0043] The SDR radio frequency board 200 is configured to simulate and test the wireless signal receiving process of the wireless communication system to be tested, perform radio frequency front-end receiving processing on the received radio frequency signal, obtain the processed baseband data, and transmit the baseband data to the FPGA board 100. Considering the channel state verification scenario, the SDR (software defined radio platform) radio frequency board completes radio frequency data acquisition, down-conversion, DA conversion and other processing to obtain baseband data, and transmits the baseband data to the FPGA board 100. For example, a universal radio frequency front-end board can be used to build a portable software radio platform. Schematically, the SDR radio frequency board 200 may include Analog Device's highly integrated agile radio frequency transceiver ADRV9009, which can realize a wide-band software radio system with a spectrum range of 75MHz to 6GHz and an analog bandwidth of 100 / 250MHz.

[0044] (4) Host computer 300

[0045] According to one embodiment of the present invention, the host computer 300 is configured to control the FPGA board 100 and the SDR radio frequency board 200 for simulation testing, and control the FPGA board 100 and the SDR radio frequency board 200 to test the signal receiving process under a plurality of preset signal-to-noise ratio levels and obtain corresponding baseband data, wherein a corresponding bit error rate threshold is preset for each signal-to-noise ratio level, wherein the switching request is issued when the bit error rate of the currently received processing result is higher than the bit error rate threshold preset for the signal-to-noise ratio level corresponding to the processing result. The technical solution of this embodiment can at least achieve the following beneficial technical effects: the embodiment of the present invention sets the corresponding bit error rate threshold independently for different signal-to-noise ratio levels, and the implementer can preset the corresponding bit error rate threshold for each signal-to-noise ratio level according to the previous theoretical simulation experience, so as to perform the test more accurately and in detail.

[0046] According to one embodiment of the present invention, the host computer 300 is further configured to: obtain data output by each functional unit when theoretical simulation decoding is performed on the baseband data; call a decoding program based on MATLAB to decode the received baseband data, wherein the decoding program is deployed with each functional unit that performs the decoding process in the wireless communication system to be tested, and after decoding, the data output by each functional unit in the decoding program of MATLAB is obtained; compare the data output by each functional unit during theoretical simulation decoding with the data output by each functional unit in the decoding program of MATLAB to locate the abnormal functional unit. The technical solution of this embodiment can at least achieve the following beneficial technical effects: because the value of the data output by each functional unit in the theoretical simulation can be used as a reference value, after switching to the host computer 300 to process the baseband data, if the output of a functional unit that executes the decoding process in the wireless communication system to be tested deployed in the decoding program is inconsistent with the corresponding reference value, the abnormal functional unit can be determined; thus, when there is no problem with the decoding, the test can be efficiently completed through the FPGA board 100, but when there is a problem with the decoding, the test can be not interrupted, and all the original baseband data can be directly returned to the host computer 300, and the abnormal functional unit can be efficiently located through the decoding program in the host computer 300; the labor and time costs of the test are greatly reduced, and the efficient development of the wireless communication system is promoted.

[0047] For different test scenarios, a set of data output by each functional unit during theoretical simulation decoding can be used to locate abnormal functional units in different test scenarios; however, in order to perform more fine-grained and accurate verification in different test scenarios (such as in a moving car, in a building, on the road, in an underground garage, etc.), further improvements can be made. According to one embodiment of the present invention, the host computer is also configured to: for different test scenarios, respectively set the data output by each functional unit during the theoretical simulation decoding corresponding to the test scenario; when the SDR radio frequency board and the FPGA board are deployed to the corresponding test scenario, locate the abnormal functional unit according to the data output by each functional unit during the theoretical simulation decoding corresponding to the test scenario. For example, in different test scenarios, the test-related environmental data in the test scenario is collected in advance for theoretical simulation decoding, and the data output by each functional unit during the theoretical simulation decoding of the test scenario is obtained and stored, so that it can be called when testing in the corresponding test scenario in the later stage.

[0048] According to one embodiment of the present invention, the host computer 300 is further configured to: preset multiple instruction generation interfaces based on API, and generate instructions for controlling the FPGA board 100 and the SDR radio frequency board 200 to perform corresponding operations by calling the API, wherein the multiple instruction generation interfaces include an interface for generating instructions corresponding to the switching request. For example, a host computer 300 control platform is built on the host computer 300 based on the MATLAB software of the Windows system, and various work configuration information and other transactions required by the SDR radio frequency board 200 are encapsulated in an API function, and the underlying function realizes data interaction based on the PCIe bus standard. Encapsulation into an API function decouples the PCIe interface from a specific program so that it can be flexibly called in MATLAB or any C program. In the same set of devices, the configuration parameters of the SDR radio frequency board 200 can be changed online by setting different values, and the data processing position (FPGA board 100 or host computer 300) can also be flexibly switched according to data processing requirements, without the need to develop software and hardware again for differences in configuration parameters and data processing positions. The technical solution of this embodiment can at least achieve the following beneficial technical effects: the embodiment of the present invention presets a variety of instruction generation interfaces based on API in the host computer 300, which can avoid the implementer's need to understand the specific form and working principle of the instructions in the host computer 300 and the FPGA board 100, and can directly and efficiently generate the required instructions through the multiple instruction generation interfaces based on API to achieve the purpose of controlling the FPGA board 100 and / or the SDR radio frequency board 200.

[0049] For illustration, this embodiment also provides schematic instructions that may be issued by the host computer 300 through Table 1, wherein 1-14 are instructions for controlling the SDR radio frequency board 200 to perform corresponding operations, i.e., instructions containing the working configuration information of the SDR radio frequency board 200; 13-17 are instructions for controlling the FPGA board 100 to perform corresponding operations, i.e., instructions containing the working configuration information of the FPGA board 100. It should be understood that the instructions shown in Table 1 are only for illustration, and can be adjusted according to the specific situation of the implementer during implementation. For example, the SDR radio frequency board in Table 1 adopts a structure of 4 transmitting channels and 4 receiving channels. If a structure of 8 transmitting channels and 8 receiving channels is adopted, it can be adjusted accordingly; in addition, read 0 / write 1 can also be swapped; the instruction bit width can also be adjusted as needed, etc., so as to generate other implementation methods, which are not limited in the embodiment of the present invention.

[0050] Table 1 Instruction number table

[0051]

[0052]

[0053] The schematic structure of the instruction sent by the host computer 300 to the FPGA board 100 is shown in Table 2:

[0054] Table 2 Instruction format

[0055]

[0056] As an example, Table 3 shows a specific schematic instruction structure:

[0057] Table 3 Command examples

[0058]

[0059] The data transmission between the FPGA board 100 and the host computer 300 is also transmitted in frames with a frame header structure. The schematic data frame is shown in Table 4:

[0060] Table 4 Data frame format

[0061]

[0062] As an example, Table 5 gives a specific schematic data frame:

[0063] Table 5 Data frame example

[0064]

[0065] It should be understood that the numbering of the above instructions, the frame header structure, and the number of bits indicating various information can be adjusted as needed to produce different implementation methods. The data frame is similar and will not be described in detail here.

[0066] According to one embodiment of the present invention, a method for testing a wireless communication system based on the device of the aforementioned embodiment is also provided, comprising: B1, deploying each functional unit that performs a decoding process in the wireless communication system onto the FPGA chip; B2, deploying the device into a test scenario and performing a test verification process of data reception and decoding, comprising: in an initial state, the FPGA board operates according to the working mode 1, and the host computer receives the processing result and displays the bit error rate calculated according to the processing result; when the decoding effect is not as expected, the host computer issues a switching request, and the FPGA board switches to the working mode 2 to transparently transmit the original baseband data; the host computer obtains the data output by each functional unit when theoretical simulation decoding is performed on the baseband data; the host computer calls a decoding program based on MATLAB to decode the received baseband data, wherein the decoding program is deployed with each functional unit that performs a decoding process in the wireless communication system to be tested, and after decoding, the data output by each functional unit in the decoding program of MATLAB is obtained; the host computer compares the data output by each functional unit during theoretical simulation decoding with the data output by each functional unit in the decoding program of MATLAB to locate the abnormal functional unit.

[0067] In the initial stage, in order to ensure the processing speed, the data is placed in the FPGA board to complete the verification and decoding processing. The host computer calls the relevant API function and transmits the corresponding work configuration information (RF work configuration parameters, transmission parameters, etc.) to the FPGA board via the PCIe interface in the XDMA module. After the instruction processing module of the FPGA board completes the instruction parsing, the corresponding RF work configuration information (such as the transmission carrier frequency, the receiving carrier frequency, etc.) is transmitted to the SDR RF board via the optical port module, and the data processing position selection parameters, data transmission framing length, etc. are transmitted to the FPGA board baseband data processing module, the real-time processing result framing module, and the two-choice module.

[0068] The optical port module of the SDR RF board receives the working configuration information sent by the host computer through the FPGA board, identifies the type of instruction according to the instruction number, parses and stores the RF chip configuration parameters (such as the RF chip receive / transmit channel enable, receive carrier frequency, receive gain and other configuration information), configures the RF chip on the RF board accordingly, and enables the receive / transmit channel to start communication. For example, in the channel status verification scenario, only the receive channel 1 is enabled. At this time, the SDR RF board enters the data receiving state after completing the parameter configuration. The external RF signal is processed in the SDR RF board by down-conversion, AD conversion, filtering, gain control, etc., and the obtained baseband I / Q data is framed according to the framing parameters, and then transmitted to the FPGA board through the optical port module, one way is sent to the baseband data processing module of the FPGA board, and the other way is sent to the baseband data cache control unit.

[0069] Assuming that the data processing position selection parameter is used in the instruction to indicate the working mode, schematically, the data processing position selection parameter in the initial stage is 0x00, that is, the FPGA board is selected to process the data, corresponding to working mode 1, the baseband data processing module and the real-time processing result framing module are enabled, and the single-bit check decoding result obtained by single symbol processing is framed according to the data transmission framing length, and stored in the corresponding memory by the processing result cache control unit. When the host computer initiates the data read back instruction, the two-choice module selects the check decoding result framing data given by the processing result cache control unit to be transmitted back to the host computer via the XDMA module. For example, in the channel verification scenario, the baseband data is selected to be stored in the first memory in the initial stage and sent to the FPGA board for data processing, that is, the data processing position selection parameter is set to 0x00, at which time the baseband data processing module and the real-time processing result framing module are both enabled and effective. In the baseband data processing module, the baseband data is first processed to remove the CP (cyclic prefix), and then the serial-to-parallel conversion is sent to FFT (fast Fourier transform), channel estimation, channel equalization, soft demodulation, CRC (cyclic redundancy check code) verification and decoding to complete the baseband signal processing, and the corresponding CRC verification and decoding results are output. Then, in the real-time processing result framing module, the CRC verification and decoding results are framed according to the framing parameters, and sent to the second memory cache in the board card through the processing result cache control unit. After the receiving link has been working for a period of time, the host computer initiates a read-back instruction. After the FPGA board card parses the read-back data instruction in the instruction processing module, it enables the two-choice module to select the verification and decoding result sent by the processing result cache control unit, and transmits it back to the host computer through the XDMA module.

[0070] To put it simply, in working mode 1, the baseband data processing module generates a single-bit check decoding result for each symbol data. A decoding result of "0" indicates a correct decoding, and a decoding result of "1" indicates a decoding error. The FPGA board frames the processed check decoding result and transmits it back to the host computer. The host computer prints and monitors the CRC check decoding result in real time, calculates the bit error rate, and displays the bit error rate curve in real time in the host computer GUI interface. The schematic diagram of the host computer printing the CRC check decoding result is shown in the figure below. Figure 4 As shown; the schematic diagram of the bit error rate curve displayed by the host computer is as follows Figure 5 As shown, the horizontal axis is the number of frames and the vertical axis is the bit error rate.

[0071] In the early simulation (theoretical simulation) of the simulation test, the theoretical bit error rate curve will be derived for the channel status of different environments. In a specific channel status verification scenario, the host computer monitors and statistically verifies the decoding results in real time. If the statistical bit error rate exceeds the bit error rate threshold, it means that there is an abnormality in the receiving link at this time; this bit error rate threshold can be obtained by adding the preset theoretical bit error rate to the preset deviation. At this time, the host computer can issue a data processing position selection parameter of 0x01 through an instruction.

[0072] If the FPGA board receives an instruction indicating that the data processing position selection parameter is 0x01, that is, it receives a switching request, and chooses to process data on the host computer, then resets the baseband data processing module and the real-time processing result framing module. At this time, the baseband data returned by the SDR radio frequency board is stored in the corresponding DDR via the return data cache control module. When the host computer initiates a data read back instruction, the two-choice module selects the original baseband data given by the return data cache control module and returns it to the host computer via the XDMA module. In this way, the host computer adaptively controls the switching of data processing positions, and the FPGA board realizes data transparent transmission, and the baseband data transmitted from the SDR radio frequency board to the FPGA board is directly returned to the host computer for further data analysis to locate the cause of the abnormality.

[0073] After the host computer obtains the original baseband data, it calls the MATLAB-based decoding program to implement the corresponding functional units, such as removing the cyclic prefix, serial-to-parallel conversion, FFT (fast Fourier transform), channel estimation, channel equalization, soft demodulation, CRC (cyclic redundancy check code) check decoding, storing the data output by each module, and comparing it with the data output by each functional unit of the receiving link during theoretical simulation to locate the abnormal functional unit, and further adjust the test environment and link module according to the cause of the abnormality to speed up equipment debugging and verification.

[0074] In general, the communication mechanism of the host computer provided in the embodiment of the present invention to control the FPGA board card in real time via API instructions is compatible with the return of different instructions and different types of data, and can effectively respond to various communication needs. For high-real-time processing needs, it can quickly switch to the FPGA board card for data processing; for high-precision processing needs such as abnormal analysis, it can quickly switch to the host computer for data processing, which greatly improves the adaptability of the board-level communication interface; by flexibly switching the data processing position, it can improve the data processing speed while reducing the development, debugging and maintenance costs.

[0075] It should be noted that although the above describes the various steps in a specific order, it does not mean that the various steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0076] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0077] Computer readable storage medium can be a tangible device that holds and stores instructions used by an instruction execution device. Computer readable storage medium can include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination thereof.

[0078] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A device for simulation testing of a wireless communication system, characterized in that: include: An FPGA board, comprising an FPGA chip and a cache control module, wherein the FPGA chip is configured to implement various functional units for performing decoding in a wireless communication system to be tested through programmable logic, so as to process baseband data to obtain a processing result, wherein the processing result is a CRC check decoding result, and the cache control module is configured to cache the baseband data and the processing result to a preset storage location; The FPGA board is configured to have at least two operating modes, wherein: Working mode 1: The FPGA board is configured to forward the corresponding processing result to the upper computer after processing the baseband data of a predetermined number of symbols, and monitor whether a switching request to switch to working mode 2 is obtained. If so, it switches to working mode 2 in response to the switching request. The switching instruction is issued by the upper computer when it determines that the decoding performance is not as expected based on the received processing result; Working mode 2: The FPGA board is configured to suspend the processing of baseband data, and transparently transmit the processed baseband data and the subsequently received baseband data to the host computer.

2. The device according to claim 1, characterized in that The device also includes: The SDR radio frequency board is configured to simulate the wireless signal reception process of the wireless communication system to be tested, perform radio frequency front-end reception processing on the received radio frequency signal, obtain processed baseband data, and transmit the baseband data to the FPGA board; The host computer is configured to control the FPGA board and the SDR radio frequency board for test verification, and control the FPGA board and the SDR radio frequency board to test the signal receiving process under multiple preset signal-to-noise ratio levels and obtain corresponding baseband data, wherein a corresponding bit error rate threshold is preset for each signal-to-noise ratio level, wherein the switching request is issued when the bit error rate of the currently received processing result is higher than the bit error rate threshold preset for the signal-to-noise ratio level corresponding to the processing result.

3. The device according to claim 2, characterized in that The host computer is also configured as follows: A plurality of instruction generation interfaces based on an API are preset, and instructions for controlling the FPGA board and the SDR radio frequency board to perform corresponding operations are generated by calling the API, wherein the plurality of instruction generation interfaces include an interface for generating instructions corresponding to the switching request.

4. The device according to claim 3, characterized in that The FPGA board also includes a first memory configured to cache baseband data received from the SDR radio frequency board, a second memory configured to cache processing results, and an FPGA chip, wherein the FPGA chip includes: The baseband data processing module is configured to implement various functional units that perform the decoding process in the wireless communication system to be tested through hardware, so as to decode the baseband data and obtain corresponding processing results; The real-time processing result framing module is configured to frame the processing results corresponding to the predetermined number of symbols after processing the baseband data of the predetermined number of symbols to obtain a processing result frame; A two-selection module is configured to selectively obtain data from the first memory or the second memory and send it to the host computer through the XDMA module; The instruction processing module is configured to receive and execute instructions from the host computer, wherein when receiving the instruction corresponding to the switching request, the operating state of the corresponding module is adjusted to switch the working mode.

5. The device according to claim 4, characterized in that When the instruction processing module receives the corresponding instruction of the switching request, the operation of the baseband data processing module and the real-time processing result framing module is suspended, and the two-choice module is controlled to change from obtaining the processing result frame from the second memory to obtaining the baseband data from the first memory and transparently transmitting it to the host computer.

6. The device according to claim 5, characterized in that The two-choice module is configured as follows: In working mode 1, after obtaining the processing result frame, a frame header is added to form a data frame, so that the processing result frame is sent to the host computer in the form of a data frame; In working mode 2, after obtaining a predetermined amount of baseband data in the order of receiving the baseband data, a frame header is added to form a data frame, so as to send the processing result frame to the host computer in the form of a data frame; The frame header contains a framing count parameter, and the framing count parameter indicates the framing sequence number of the processing result frame or baseband data currently being sent.

7. The device according to claim 6, characterized in that The host computer is also configured as follows: Obtain the data output by each functional unit when performing theoretical simulation decoding on baseband data; Calling a decoding program based on MATLAB to decode the received baseband data, wherein the decoding program is deployed with various functional units that perform a decoding process in the wireless communication system to be tested, and after decoding, data output by each functional unit in the decoding program of MATLAB is obtained; Compare the data output by each functional unit during theoretical simulation decoding with the data output by each functional unit in the MATLAB decoding program to locate the abnormal functional unit.

8. The device according to claim 7, characterized in that The host computer is also configured as follows: For different test scenarios, the data output by each functional unit during theoretical simulation decoding corresponding to the test scenario is set respectively; When the SDR radio frequency board and the FPGA board are deployed to the corresponding test scenario, the abnormal functional unit is located according to the data output by each functional unit during the theoretical simulation decoding corresponding to the test scenario.

9. The device according to any one of claims 4 to 8, characterized in that: The size of the first memory is at least sufficient to store all baseband data during the simulation test, and the size of the second memory is at least sufficient to store all processing results during the simulation test.

10. A method for testing a wireless communication system based on the device according to any one of claims 1 to 9, characterized in that: include: B1. deploying each functional unit that performs the decoding process in the wireless communication system onto the FPGA chip; B2. Deploy the device to a test scenario and perform a test verification process of data reception and decoding, including: In the initial state, the FPGA board operates in the working mode 1, and the host computer receives the processing result and displays the bit error rate calculated according to the processing result; When the decoding effect is not as good as expected, the host computer sends a switching request, and the FPGA board switches to the working mode 2 to transparently transmit the original baseband data; The host computer obtains the data output by each functional unit when performing theoretical simulation decoding on the baseband data; The host computer calls a decoding program based on MATLAB to decode the received baseband data, wherein the decoding program is deployed with various functional units that perform the decoding process in the wireless communication system to be tested, and after decoding, the data output by each functional unit in the decoding program of MATLAB is obtained; The host computer compares the data output by each functional unit during theoretical simulation decoding with the data output by each functional unit in the MATLAB decoding program to locate the abnormal functional unit.

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