Hardware abstraction layer module based on software radio

Abstract

The invention discloses a hardware abstraction layer module based on software radio, and relates to the field of wireless communication. The device is used for transmitting signals between an application component and a target component, and comprises an address mapping module, a waveform instance number module, an SRIO bottom layer module, a sending module, a receiving module and a data packet statistics module. A hardware abstraction layer is realized based on a software radio technology, and a standard data transmission channel is provided, so that a user layer does not need to care about transmission of underlying data, and free data transmission among different application components is realized.

Description

Technical Field

[0001] The invention relates to the technical field of wireless communication, in particular to a hardware abstraction layer module based on software radio, which can be used for tropospheric scatter communication. Background Art

[0002] The so-called software radio is a system and technology that uses a general hardware platform as the basis and custom software as the core to realize various wireless communication system functions. Software radio technology is to establish a general software architecture to maximize the portability and configurability of different application software (including changing waveforms), as well as the interoperability between different software function modules.

[0003] Since the concept of software radio was proposed in 1992, it has been more than 30 years. From its first application in the military field to its popularization in the civilian field, software radio technology has developed rapidly. The emergence of software radio technology has changed the research of communication platforms from hardware upgrades to software upgrades, and it is necessary to continuously study new technologies to improve the processing rate of the software part. In recent years, the software radio platform based on ZYNQ has been widely used. It is integrated by ARM and FPGA, and users can flexibly use signal processing and logic resources to complete the programming and upgrade of the platform.

[0004] The hardware abstraction layer, MHAL, is mainly used to shield the underlying SRIO hardware interface, abstract the underlying data transmission into a data sending and receiving bus interface that complies with the specifications, and provide a unified data interface to upper-level application developers. Through the hardware abstraction layer, waveform designers do not need to spend time and energy to care about data transmission issues at the bottom layer, so they can focus on the development of upper-level applications.

[0005] In recent years, with the development of tropospheric scatter communications, scattering devices for different usage scenarios and multiple systems have emerged in an endless stream. The devices are incompatible with each other, and the hardware cost has increased accordingly, which urgently needs to be reduced. Software Defined Radio (SDR) refers to a software-defined radio communication system that can realize multiple functions. The Joint Tactical Network Center of the US Army has released the Software Communicatinas Architecture (SCA), which is beneficial to enhance the interoperability of communication systems and reduce the cost of hardware system development and deployment.

[0006] At present, tropospheric scatter communication has been highly valued and widely used in the construction of wireless communication systems in various countries. However, with the continuous development and evolution of digitalization and informatization, the requirements of communication systems in terms of communication bandwidth, communication distance, reliability, adaptability and business carrying capacity have been continuously improved, and a variety of modulation and demodulation waveforms supporting different scenarios and systems have emerged. These waveforms are often incompatible due to performance, interfaces, etc. Summary of the invention

[0007] In view of this, the present invention proposes a hardware abstraction layer module based on software radio. The present invention implements the hardware abstraction layer based on software radio technology, provides a standardized data transmission channel, and enables the user layer to not care about the transmission of the underlying data, thereby realizing free data transmission between different application components.

[0008] The technical solution adopted by the present invention is:

[0009] A hardware abstraction layer module based on software radio is used to transmit signals between application components and target components. The frame format of the signal includes a flow flag field IU, a logical address field LD, a frame length field Length, and a message load field Payload; the module includes:

[0010] The address mapping module is used to maintain an address mapping table from a logical address LD to a physical address PD;

[0011] The waveform instance number module provides a waveform instance number setting interface to update the waveform instance number, and then accumulates the logical address of the target component and the waveform instance number to obtain a new logical address; the default value of the waveform instance number is 0;

[0012] The SRIO bottom-level module is used to connect analog devices and digital signal processing modules, send encapsulated data packets to the outside through the physical interface, and receive data packets sent by the target component;

[0013] The sending module is used to receive the data packets sent by the application component and the logical address of the target component, and store them in the sending FIFO buffer; after the waveform instance number module generates a new logical address, it searches the address mapping table of the address mapping module for the corresponding physical address according to the new logical address, and then sends the data packet to the target component corresponding to the physical address through the SRIO bottom layer module;

[0014] The receiving module is used to provide a data channel for the application component to read the data packets of the SRIO bottom layer module; the receiving module parses the data packets and stores them in the receiving FIFO buffer, and the application component reads the data according to the reading timing of the receiving module; the receiving module also includes a receiving data packet calculation interface to process the number of received data packets;

[0015] The data packet statistics module is used to count the data packet traffic of the sending module and the receiving module respectively; the data packet statistics results are sent by the sending module to the target component of the corresponding logical address.

[0016] Optionally, the address mapping module has a reserved interface, and the external device updates the address mapping table through the reserved interface; the storage space of the address mapping table is 1024 bytes, and the length from the logical address LD to the physical address PD is 2 bytes.

[0017] The beneficial effects of the present invention are:

[0018] 1. The present invention can package the user layer data into a unified format and send it out through the Ethernet bus, or parse the received Ethernet data into data in a unified format and pass it to the user layer, thereby solving the barrier-free data transmission between different processing units.

[0019] 2. The present invention realizes the hardware abstraction layer based on software radio technology, provides a standardized data transmission channel, makes the user layer no longer care about the transmission of the underlying data, and realizes the free transmission of data between different application components. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a principle block diagram of a hardware abstraction layer module based on software radio in an embodiment of the present invention.

[0021] Figure 2 It is an interface timing diagram of an embodiment of the present invention.

[0022] Figure 3 It is a schematic diagram of an application scenario of an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the present invention more clear, the following will be described through specific embodiments in conjunction with the accompanying drawings.

[0024] A hardware abstraction layer module based on software radio is used to transmit signals between application components and target components. The frame format of the hardware abstraction layer is shown in the following table:

[0025] IU LD Length Payload

[0026] The explanation of the frame format is shown in the following table:

[0027]

[0028] The hardware abstraction layer module includes a sending module, a receiving module, a waveform instance number module, an address mapping module, a data packet statistics module, and an SRIO bottom layer module.

[0029] When needed, the user can directly write data to the sending bus. When the sending module detects that data is written, it will package the data and transmit it to the destination according to the bus protocol; when receiving data, the receiving module will give a flag signal when it detects that data has arrived, and the user can read the data on the receiving bus when needed. The user does not need to care about the underlying data transmission.

[0030] For both ends of data transmission and reception, data can be transmitted without physical direct connection. Users only need to set the address of the destination component receiving the data, and through the address mapping mechanism (conversion of physical address and logical address), the correct data transmission can be completed at the bottom layer.

[0031] The hardware abstraction layer includes a sending module and a receiving module. The sending module provides a user sending interface, which contains a variable-length storage. Users can send data packets of different lengths as needed. The receiving module also contains a variable-length storage, so that it can receive data packets of different lengths.

[0032] Specifically, the structure of the hardware abstraction layer module is as follows Figure 1 As shown, where:

[0033] 1) Sending module

[0034] The sending module is the channel for the application component to send data externally. The specific sending process is described as follows:

[0035] The application component sends the logical address LD and data of the target component to the FIFO of MHAL. MHAL processes the logical address LD, adds the instance number of the waveform (the waveform instance number is set by the FPGA's processing system PS) to obtain a new component LD, searches the LD-PD mapping table for the corresponding PD based on the newly generated LD, and then sends the data packet generated by MHAL to the target component corresponding to the PD through the driver.

[0036] The interface signal definition of the hardware abstraction layer sending module is shown in the following table:

[0037] Signal Definition Signal Description Remark WRITE_EN Indicates the write enable of WRITE_DATA data, high level is valid WRITE_EOM_MSB A high level indicates "end of message" in the high byte of the data WRITE_EOM_LSB A high level indicates "end of message" in the low byte of data WRITE_DATA Write data bus (16bit wide) user_clk Output clock provided by application component, rising edge valid FULL_FLAG* High level indicates FIFO is full, (reserved) ALMOST_FULL_FLAG* A high level indicates that the FIFO is about to be full. (Reserved)

[0038] 2) Receiver module

[0039] The receiving module provides the application component with a data channel for reading the underlying bus data packets. It parses the data packets, converts them into the specified data format and stores them in the receiving FIFO. The application component reads the data according to the reading timing of the receiving module. The receiving module contains a FIFO and corresponding timing control logic, as well as a receiving data packet calculation interface to process the number of received data packets.

[0040] The interface signal definition of the hardware abstraction layer receiving module is shown in the following table:

[0041] Signal Definition Signal Description Remark READ_EN A high level indicates that WRITE_DATA data is write enabled. USER_CLK_R User-supplied output clock, rising edge valid READ_FLAG A high level indicates that a packet has been received and the user is ready to process it. READ_EOM_MSB A high level indicates "end of message" in the high byte of the data READ_EOM_LSB A high level indicates "end of message" in the low byte of data READ_DATA Read data bus (16 bits wide)

[0042] 3) Packet statistics module

[0043] The main function of the data packet statistics module is to count the data packet traffic of the sending module and the receiving module respectively; the data packet statistics results are sent by the sending module to the target component of the corresponding logical address.

[0044] 4) Waveform instance number module

[0045] PS updates the waveform instance number through the waveform instance number setting interface. The default value of the waveform instance number is 0. When the waveform component sends data to MHAL, it also passes the LD of the target component. At this time, the LD is accumulated with the application instance number to obtain a new LD. MHAL sends the data to the device at the other end according to the newly generated LD.

[0046] 5) Address mapping module

[0047] The main function of the address mapping module is to maintain an address mapping table from logical address LD to physical address PD. The sending module converts LD to PD through address mapping, and then the underlying hardware driver sends the data to the target device corresponding to PD.

[0048] The address mapping module reserves an interface for the PS, and the PS can update the address mapping table through the reserved interface; the storage space of the address mapping table is designed as 1024Bytes, and the LD and PD lengths are both calculated as 2Bytes to meet the storage of 254 address mapping information. The Message Type and Table Items occupy a total of 8 bytes.

[0049] 6) SRIO underlying module

[0050] The function of the SRIO bottom-level module is to send the MHAL-encapsulated data packets to the outside through the physical interface. It is the link between the analog device and the digital signal processing module.

[0051] The interface timing between the hardware abstraction layer and each application component is carried out in accordance with the specified timing. When the hardware abstraction layer receives signals, the interface signals of the hardware abstraction layer include read enable, read clock, data, and reception completion flag. Because the received data is 16 bits, and the received data in the program is 8 bits, in order to avoid data confusion, two flag bits are added, the message end is the low byte flag bit and the message end is the high byte flag bit. Read enable is aligned with the read clock data. When the hardware abstraction layer sends signals, the interface signals of the hardware abstraction layer include write enable, write clock, data, transmission completion flag bit, the message end is the low byte flag bit and the message end is the high byte flag bit. Write enable is aligned with the write clock data.

[0052] Figure 2 The interface definition timing between the hardware abstraction layer and the waveform component in the embodiment of the present invention is shown, and is described in detail as follows:

[0053] The application component can be any module that interacts with the hardware abstraction layer. When the hardware abstraction layer sends information to the application component, the signal name is read and the timing is as follows Figure 2 As shown in the figure. The interface signals include write enable, write clock, data, send complete flag, message end is low byte flag and message end is high byte flag. Write enable is aligned with write clock data. When the hardware abstraction layer receives information from the application component, the signal names are read enable, read clock, data, receive complete flag, message end is low byte flag and message end is high byte flag, and the timing is the same as the timing of writing data.

[0054] The hardware abstraction layer can realize data routing between different application components. These application components include waveform components, user components, SPI components, sampling components, and GPIO components. The so-called application components refer to digital or analog modules with independent functions that can transmit information with the hardware abstraction layer. According to the needs of the application components, some components can send and receive information with the hardware abstraction layer, some components only receive messages from the hardware abstraction layer without sending them, and some components only send information from the hardware abstraction layer without receiving it. In general, waveform components and user components exchange information with the hardware abstraction layer in a two-way manner.

[0055] Figure 3 The figure shows the relationship between the hardware abstraction layer and each application component in the embodiment of the present invention. The hardware abstraction layer provides a platform that connects the upper and lower parts, so that the data of each application component can be freely transmitted. The RF component uses the SPI interface. The waveform component 1, the waveform component 2 and the user component can send and receive information with the hardware abstraction layer, and the RF component 1, the RF component 2 and the sampling component only receive information from the hardware abstraction layer and do not reply to the information.

[0056] According to the software architecture mentioned in SCA4.1, the present invention designs a hardware abstraction layer (Modem Hardware Abstract Layer, MHAL) implementation scheme based on FPGA for Windows operating system, which is particularly suitable for tropospheric scatter communication. The hardware abstraction layer of the present invention can abstract the underlying data transmission into interface data that meets the specifications, and provide a unified data interface for upper-layer application developers. Therefore, the designers of application components do not have to spend time and energy to care about the transmission problem of data at the bottom layer, which reduces the cost of hardware development.

[0057] The above-mentioned embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them. Although the present invention has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above-mentioned embodiments, or replace some of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A hardware abstraction layer module based on software radio, characterized in that: Used to transmit signals between application components and target components. The frame format of the signal includes the traffic flag field IU, the logical address field LD, the frame length field Length, and the message load field Payload. This module includes: The address mapping module is used to maintain an address mapping table from a logical address LD to a physical address PD; The waveform instance number module provides a waveform instance number setting interface to update the waveform instance number, and then accumulates the logical address of the target component and the waveform instance number to obtain a new logical address; the default value of the waveform instance number is 0; The SRIO bottom-level module is used to connect analog devices and digital signal processing modules, send encapsulated data packets to the outside through the physical interface, and receive data packets sent by the target component; The sending module is used to receive the data packets sent by the application component and the logical address of the target component, and store them in the sending FIFO buffer; after the waveform instance number module generates a new logical address, it searches the address mapping table of the address mapping module for the corresponding physical address according to the new logical address, and then sends the data packet to the target component corresponding to the physical address through the SRIO bottom layer module; The receiving module is used to provide a data channel for the application component to read the data packets of the SRIO bottom layer module; the receiving module parses the data packets and stores them in the receiving FIFO buffer, and the application component reads the data according to the reading timing of the receiving module; the receiving module also includes a receiving data packet calculation interface to process the number of received data packets; The data packet statistics module is used to count the data packet traffic of the sending module and the receiving module respectively; the data packet statistics results are sent by the sending module to the target component of the corresponding logical address.

2. A hardware abstraction layer module based on software radio according to claim 1, characterized in that: The address mapping module has a reserved interface, and the external device updates the address mapping table through the reserved interface; the storage space of the address mapping table is 1024 bytes, and the length of the logical address LD to the physical address PD is 2 bytes.

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