Memory cell structure, memory cell array and preparation method thereof

Abstract

The invention relates to a memory cell structure, a memory cell array and a preparation method of the memory cell structure. The memory cell structure comprises an active base station, a target active column, a bit line structure, a first word line structure and a second word line structure, the target active column is positioned on the top surface of the active base station and comprises a public active column, and a first active column, a middle isolation structure and a second active column which are positioned on the top surface of the public active column and are sequentially distributed along a first direction; the bit line structure is located on the top surface of the active base station and circumferentially surrounds the bottom of the target active column; the first word line structure and the second word line structure are located on the two opposite sides of the common active column in the first direction. The floating body effect can be effectively avoided, and the problems of bit line flatness and current leakage are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and manufacturing, and in particular to a memory cell structure, a memory cell array and a preparation method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, in order to form more devices in the same area, the integration of semiconductor devices continues to increase, and the process nodes of devices continue to decrease. In order to increase the integration of devices, researchers have improved the topology of semiconductor units and developed vertical channel transistors (Vertical Channel Transistor, VCT) with vertical distribution of source, gate, and drain, replacing horizontal transistors with horizontal distribution of source, gate, and drain, thereby reducing the area occupied by semiconductor units under the same feature size conditions.

[0003] However, conventional vertical channel transistors have the problem of floating body effect, and the flatness of the fabricated bit lines is poor and there is leakage current, which results in reduced performance and reliability of the vertical channel transistors. Summary of the invention

[0004] Based on this, the present disclosure provides a memory cell structure, a memory cell array and a method for preparing the same, which can at least effectively avoid the floating body effect of the vertical channel transistor and improve the bit line flatness and leakage current problems.

[0005] In order to solve the above-mentioned technical problems and other problems, according to some embodiments, one aspect of the present disclosure provides a memory cell structure, which includes an active base, a target active pillar, a bit line structure, a first word line structure and a second word line structure; the target active pillar is located on the top surface of the active base and includes a common active pillar, and a first active pillar, an intermediate isolation structure and a second active pillar located on the top surface of the common active pillar and distributed in sequence along a first direction; the bit line structure is located on the top surface of the active base and circumferentially surrounds the bottom of the target active pillar; the first word line structure and the second word line structure are located on opposite sides of the common active pillar along the first direction.

[0006] In the memory cell structure of the above embodiment, the bit line structure circumferentially surrounds the bottom of the target active column, which can reduce the resistance of the bit line structure, reduce leakage current, and effectively improve the flatness of the bit line structure, thereby improving the performance and reliability of the semiconductor device. In addition, the first active column and the second active column can be used to form two transistors, corresponding to the first word line structure and the second word line structure respectively. Since the two transistors are located in the same target active column, that is, the two transistors share the same bit line structure, the number of bit line structures can be reduced by half, saving the structure size, which is conducive to improving the integration of semiconductor devices.

[0007] In some embodiments, the common active pillar includes a first common channel layer and a second common channel layer; the first common channel layer is located between the first active pillar and the second active pillar and the bottom surface is connected to the active base; the second common channel layer is located on the top surface of the first common channel layer and between the first word line structure and the second word line structure.

[0008] In some embodiments, the target active column also includes a first source structure, a second source structure, a first drain structure and a second drain structure; the first source structure includes the first active column and a portion of the common active column below it; the second source structure includes the second active column and a portion of the common active column below it; the first drain structure is located between the second common channel layer and the active base, and is located on the first side of the first common channel layer along the first direction; the second drain structure is located between the second common channel layer and the active base, and is located on the second side of the first common channel layer opposite to the first side along the first direction; or the first drain structure includes the first active column and a portion of the common active column below it; the second drain structure includes the second active column and a portion of the common active column below it; the first source structure is located between the second common channel layer and the active base, and is located on the first side of the first common channel layer along the first direction; the second source structure is located between the second common channel layer and the active base, and is located on the second side of the first common channel layer opposite to the first side along the first direction.

[0009] In some embodiments, a first doped region directly below the first common channel layer and second doped regions located on opposite sides of the first doped region along a second direction are also formed in the active base; the second direction intersects with the first direction.

[0010] In some embodiments, the doping type of the first doping region is opposite to the doping type of the second doping region; the doping type of the first doping region is the same as the doping type of the first common channel layer and the second common channel layer; the doping type of the second doping region is the same as the doping type of the first source structure, the second source structure, the first drain structure, and the second drain structure.

[0011] In some embodiments, the first word line structure includes a first gate dielectric layer and a first gate conductive layer stacked along a first direction; the first gate dielectric layer is located between the first gate conductive layer and the second common channel layer; and / or the second word line structure includes a second gate dielectric layer and a second gate conductive layer stacked along the first direction; the second gate dielectric layer is located between the second gate conductive layer and the second common channel layer.

[0012] In some embodiments, the storage cell structure also includes a first capacitor contact plug, a second capacitor contact plug, a first capacitor structure and a second capacitor structure; the first capacitor contact plug is located on the top surface of the first active column; the second capacitor contact plug is located on the top surface of the second active column; the first capacitor structure is located on the top surface of the first capacitor contact plug; and the second capacitor structure is located on the top surface of the second capacitor contact plug.

[0013] According to some embodiments, the present disclosure provides a memory cell array on the other hand, comprising a plurality of memory cell structures of any one of the above embodiments arranged in an array along a first direction and a second direction; memory cell structures adjacent to each other along the first direction share a bit line structure, and memory cell structures adjacent to each other along the second direction are connected to different bit line structures; memory cells adjacent to each other along the second direction share a first word line structure and a second word line structure, and memory cell structures adjacent to each other along the first direction are connected to different first word line structures / second word line structures.

[0014] In the memory cell array of the above embodiment, the bit line structure circumferentially surrounds the bottom of the target active column, which can reduce the resistance of the bit line structure, reduce leakage current, and effectively improve the flatness of the bit line structure, thereby improving the performance and reliability of the semiconductor device. In addition, the first active column and the second active column can be used to form two transistors, corresponding to the first word line structure and the second word line structure respectively. Since the two transistors are located in the same target active column, that is, the two transistors share the same bit line structure, the number of bit line structures can be reduced by half, saving the structure size, which is conducive to improving the integration of semiconductor devices.

[0015] In some embodiments, the memory cell array further includes a bit line isolation structure and a word line isolation structure; the bit line isolation structure is located between bit line structures adjacent along the second direction; and / or the word line isolation structure is located between a first word line structure and a second word line structure adjacent along the first direction, and is located between target active pillars adjacent along the first direction.

[0016] According to some embodiments, the present disclosure provides a method for preparing a memory cell array on another aspect, the method comprising: providing a target substrate, the target substrate comprising reference cells and bit line structures distributed in an array along a first direction and a second direction, the reference cells comprising an active base and an initial active column stacked in sequence along a thickness direction of the target substrate, the bit line structure being located on a top surface of the active base and circumferentially surrounding a bottom of the initial active column; the first direction intersects with the second direction; forming a first word line structure and a second word line structure on opposite sides of the initial active column along the first direction; forming an intermediate isolation structure in the initial active column to obtain a target active column, the target active column comprising a common active column and a first active column, an intermediate isolation structure and a second active column located on a top surface of the common active column and distributed in sequence along the first direction.

[0017] In the memory cell array of the above embodiment, by forming a bit line structure that circumferentially surrounds the bottom of the initial active column, the resistance of the bit line structure can be reduced, the leakage current can be reduced, and the flatness of the bit line structure can be effectively improved, thereby improving the performance and reliability of the semiconductor device. In addition, the first active column and the second active column can be used to form two transistors, corresponding to the first word line structure and the second word line structure respectively. Since the two transistors are located in the same target active column, that is, the two transistors share the same bit line structure, the number of bit line structures can be reduced by half, the structure size can be saved, and it is beneficial to improve the integration of the semiconductor device.

[0018] In some embodiments, a target substrate is provided, including: providing an initial substrate, the initial substrate including initial active pillars arrayed along a first direction and a second direction; forming a bit line material layer on the initial substrate between the initial active pillars adjacent to each other along the first direction and the second direction; forming a bit line isolation structure extending along the first direction in the initial substrate between the initial active pillars adjacent to each other along the second direction to obtain active bases arranged at intervals along the second direction and extending along the first direction, the initial active pillars being located in the middle of the active bases directly below them; the bit line material layer located on the top surface of the active bases is used to form a bit line structure.

[0019] In some embodiments, forming a first word line structure and a second word line structure includes: forming a dielectric material layer, the dielectric material layer is located on the top surface of the bit line structure and between adjacent initial active pillars; removing part of the dielectric material layer to form a first word line groove and a second word line groove located on opposite sides of the initial active pillars along a first direction, and a first gate dielectric layer between the initial active pillar and the first word line groove, and a second gate dielectric layer between the initial active pillar and the second word line groove; the bottom surface of the first word line groove and the bottom surface of the second word line groove are both higher than the top surface of the bit line structure; forming a first gate conductive layer in the first word line groove and forming a second gate conductive layer in the second word line groove; the top surface of the first gate conductive layer and the top surface of the second gate conductive layer are both lower than the bottom surface of the intermediate isolation structure; wherein the first gate dielectric layer and the first gate conductive layer are used to form the first word line structure, and the second gate dielectric layer and the second gate conductive layer are used to form the second word line structure.

[0020] In some embodiments, forming the first word line structure and the second word line structure includes: forming a dielectric material layer, the dielectric material layer is located on the top surface of the bit line structure and is located between adjacent initial active pillars; removing a portion of the dielectric material layer to form a third word line groove and a fourth word line groove located on opposite sides of the initial active pillar along a first direction, the bottom surface of the third word line groove and the bottom surface of the fourth word line groove are both higher than the top surface of the bit line structure and lower than the bottom surface of the intermediate isolation structure; the third word line groove exposes a portion of the first side surface of the initial active pillar, and the fourth word line groove exposes a portion of the first side surface of the initial active pillar. A portion of the second side surface of the initial active column is exposed; the first side surface and the second side surface are surfaces of the initial active column that are opposite to each other along the first direction; a first gate dielectric layer covering the first side surface is formed in the third word line groove, and a second gate dielectric layer covering the second side surface is formed in the fourth word line groove; a first gate conductive layer is formed in the third word line groove, and a second gate conductive layer is formed in the fourth word line groove; wherein the first gate dielectric layer and the first gate conductive layer are used to form a first word line structure, and the second gate dielectric layer and the second gate conductive layer are used to form a second word line structure.

[0021] In some embodiments, after forming the intermediate isolation structure, it also includes: forming a first capacitor contact plug located on the top surface of the first active pillar, and a second capacitor contact plug located on the top surface of the second active pillar; forming a first capacitor structure located on the top surface of the first capacitor contact plug, and a second capacitor structure located on the top surface of the second capacitor contact plug.

[0022] In some embodiments, it also includes: forming a first common channel layer and a second common channel layer in a common active column after forming an intermediate isolation structure and before forming a first capacitor contact plug and a second capacitor contact plug, or after forming an initial active column and before forming a bit line material layer; the first common channel layer is located between the first active column and the second active column and the bottom surface is connected to the active base; the second common channel layer is located on the top surface of the first common channel layer and between the first word line structure and the second word line structure.

[0023] In some embodiments, it also includes: after forming the initial substrate and before forming the first common channel layer, forming a first doped region in the initial substrate directly below the first common channel layer; after forming the first common channel layer and before forming the second common channel layer, forming a second doped region in the initial substrate and on opposite sides of the first common channel layer along a second direction; the second direction intersects with the first direction.

[0024] In some embodiments, the method further includes: after forming the second common channel layer and before forming the first capacitor contact plug and the second capacitor contact plug, forming a second doped region at least in the first active pillar and the second active pillar. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic diagram of an SOI device provided in an embodiment of the present disclosure;

[0027] Figure 2 A schematic diagram of a principle diagram of a floating body effect provided in an embodiment of the present disclosure;

[0028] Figure 3 A schematic diagram of the structure of a vertical channel transistor provided in one embodiment of the present disclosure;

[0029] Figure 4 A schematic diagram of a bit line structure provided in an embodiment of the present disclosure;

[0030] Figure 5 A schematic diagram of a bit line structure provided in another embodiment of the present disclosure;

[0031] Figure 6 A schematic top view of a storage unit structure provided in one embodiment of the present disclosure;

[0032] Figure 7 A memory cell structure provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of the cross section along the aa' direction;

[0033] Figure 8 A memory cell structure provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of the cross section along the cc' direction;

[0034] Fig. 9 A schematic diagram of a process for preparing a memory cell array provided in an embodiment of the present disclosure;

[0035] Fig. 10A The structure obtained in step S20 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0036] Fig. 10B The structure obtained in step S20 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of cc' and dd' directions;

[0037] Fig.11AThe structure obtained in step S21 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0038] Fig. 11B The structure obtained in step S21 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of cc' and dd' directions;

[0039] Fig. 12A The structure obtained in step S22 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0040] Fig. 12B The structure obtained in step S23 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of cc' and dd' directions;

[0041] Fig.13A The structure obtained in step S23 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0042] Fig. 13B The structure obtained in step S23 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of cc' and dd' directions;

[0043] Fig.14A The structure obtained in step S40 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0044] Fig. 14B The structure obtained in step S40 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of cc' and dd' directions;

[0045] Fig.15A The structure obtained in step S60 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0046] Fig. 15B The structure obtained in step S60 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6Schematic diagram of cc' and dd' directions;

[0047] Fig.16A The structure obtained in step S80 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0048] Fig. 16B The structure obtained in step S80 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of cc' and dd' directions;

[0049] Fig.17A The structure obtained in step S70 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0050] Fig. 17B The structure obtained in step S70 of a method for preparing a memory cell array provided in an embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of the cc' and dd' directions.

[0051] Description of reference numerals:

[0052] 1. Active base; 11. First doping region; 12. Second doping region; 2. Target active column; 201. Initial active column; 21. Common active column; 211. First common channel layer; 212. Second common channel layer; 213. First source structure; 214. Second source structure; 215. First drain structure; 216. Second drain structure; 22. First active column; 23. Intermediate isolation structure; 24. Second active column; 3. Bit line structure; 31. Bit line material layer; 301. Bit line groove; 4. First word line structure; 41. First gate dielectric layer; 42. First gate conductive layer; 5. Second word line structure; 51. Second gate dielectric layer; 52. Second gate conductive layer; 61. First capacitor contact plug; 62. Second capacitor contact plug; 71. Bit line isolation structure; 72. Word line isolation structure; 8. Target substrate; 9. Initial substrate; 91. Mask stack; 911. First mask layer; 912. Second mask layer; 913. Third mask layer; 914. Fourth mask layer; 915. Fifth mask layer. DETAILED DESCRIPTION

[0053] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0055] The term "and / or" used herein includes any and all combinations of one or more of the related listed items. In the case of using "including", "having", and "comprising" described herein, another component may be added unless a clear limiting term such as "only", "consisting of", etc. is used. Unless mentioned to the contrary, a term in the singular form may include a plural form and is not to be understood as having one number.

[0056] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0057] In the description of the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0058] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0059] Please refer to Figure 1 and Figure 2 Silicon On Insulator (SOI) devices can be divided into thin film fully depleted SOI (FDSOI) devices and Figure 1 The thick film partially depleted SOI (PDSOI) device shown in Figure 1. In SOI devices, the body potential and bias of the device are related to the carrier recombination process. Since the top silicon film is floating relative to the substrate, the transistor forms a capacitor relative to the bottom plate, such as Figure 2 As shown by the floating body F in the figure, the charge accumulates on the capacitor to form an adverse effect, namely the floating body effect. As an inherent problem of SOI devices, the floating body effect can cause warping effect, parasitic bipolar transistor effect, abnormal subthreshold slope, device threshold voltage drift, etc. These effects will not only reduce the device gain, causing unstable device operation, reduce the drain breakdown voltage, but also cause the single-tube latch effect, resulting in a large leakage current and increased power consumption.

[0060] Please refer to Figure 3 Some VCT structure memories include a vertically stacked source structure S, a vertical channel CH, and a drain structure D, which are used to form a selection transistor T. The first word line structure 4 is located on one side of the vertical channel CH, which is used to control the on and off of the selection transistor T. The top surface of the source structure S is formed with a first capacitor contact plug 61 and a capacitor structure C, which are used to store charge. The influence of the floating body effect in the VCT structure should not be underestimated. For example, the parasitic transistor leaks electricity, resulting in higher current loss. In the memory, the floating body effect will also cause the information of the storage unit to be lost. It can be seen that the floating body effect seriously affects the performance of the VCT structure memory device and hinders the development of the VCT structure memory device.

[0061] Please refer to Figure 4 In the process of forming some bit line structures 3, a bit line groove 301 is usually formed at the bottom of the active pillar, and then the bit line structure 3 is formed in the bit line groove 301. However, the flatness of the bit line structure 3 prepared in this way is poor and there is a risk of leakage. Please refer to Figure 5 In the process of forming the bit line structure 3 of other systems, the bit line structure 3 is usually formed by an ion implantation process on both sides of the active pillar. The resistance of the bit line structure 3 prepared in this way is relatively large, and there is a leakage current problem between adjacent bit line structures 3.

[0062] The present disclosure aims to provide a memory cell structure, a memory cell array and a method for preparing the same, which can at least effectively avoid the floating body effect of a vertical channel transistor and improve the flatness of the bit line and the leakage current problem.

[0063] Please refer to Figures 6 to 8According to some embodiments, one aspect of the present disclosure provides a memory cell structure, which includes an active base 1, a target active pillar 2, a bit line structure 3, a first word line structure 4 and a second word line structure 5; the target active pillar 2 is located on the top surface of the active base 1 and includes a common active pillar 21, and a first active pillar 22, an intermediate isolation structure 23 and a second active pillar 24 located on the top surface of the common active pillar 21 and sequentially distributed along a first direction; the bit line structure 3 is located on the top surface of the active base 1 and circumferentially surrounds the bottom of the target active pillar 2; the first word line structure 4 and the second word line structure 5 are located on opposite sides of the common active pillar 21 along the first direction.

[0064] For example, the first direction may be an OY direction, and the first direction may be Figure 6 The aa' direction or the bb' direction shown in the figure, the aa' direction and the bb' direction are parallel to each other, and the first direction can be parallel to the extension direction of the bit line structure 3; the directions in subsequent embodiments can refer to the directions in this embodiment, and will not be repeated in the following text.

[0065] Please continue to refer to Figures 6 to 8 In the memory cell structure of the above embodiment, the bit line structure 3 surrounding the bottom of the target active column 2 can reduce the resistance of the bit line structure 3, reduce the leakage current, and effectively improve the flatness of the bit line structure 3, thereby improving the performance and reliability of the semiconductor device. In addition, the first active column 22 and the second active column 24 can be used to form two transistors, corresponding to the first word line structure 4 and the second word line structure 5, respectively. Since the two transistors are located in the same target active column 2, that is, the two transistors share the same bit line structure 3, the number of bit line structures 3 can be reduced by half, saving the structure size, which is conducive to improving the integration of semiconductor devices.

[0066] Please continue to refer to Figures 6 to 8 , illustratively, the material of the bit line structure 3 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride silicon and combinations thereof.

[0067] Please continue to refer to Figures 6 to 8 For example, the material of the first word line structure 4 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride and combinations thereof; the material of the second word line structure 5 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride and combinations thereof.

[0068] Please continue to refer to Figures 6 to 8In some embodiments, the common active pillar 21 includes a first common channel layer 211 and a second common channel layer 212; the first common channel layer 211 is located between the first active pillar 22 and the second active pillar 24 and the bottom surface is connected to the active base 1; the second common channel layer 212 is located on the top surface of the first common channel layer 211 and between the first word line structure 4 and the second word line structure 5. The first active pillar 22 and the second active pillar 24 share the first common channel layer 211 or the second common channel layer 212, which can effectively improve the size utilization of the memory cell structure, thereby improving the integration of the device, and facilitating the preparation of high-density memory devices.

[0069] Please continue to refer to Figures 6 to 8 By way of example, the material of the common active pillar 21 is selected from single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, germanium silicon, etc. and combinations thereof.

[0070] Please continue to refer to Figures 6 to 8In some embodiments, the target active pillar 2 further includes a first source structure 213, a second source structure 214, a first drain structure 215, and a second drain structure 216; the first source structure 213 includes the first active pillar 22 and a portion of the common active pillar 21 thereunder; the second source structure 214 includes the second active pillar 24 and a portion of the common active pillar 21 thereunder; the first drain structure 215 is located between the second common channel layer 212 and the active platform 1, and is located on a first side of the first common channel layer 211 along a first direction; the second drain structure 216 is located between the second common channel layer 212 and the active platform 1, and Located on the second side of the first common channel layer 211 along the first direction opposite to the first side; or the first drain structure 215 includes the first active pillar 22 and a portion of the common active pillar 21 thereunder; the second drain structure 216 includes the second active pillar 24 and a portion of the common active pillar 21 thereunder; the first source structure 213 is located between the second common channel layer 212 and the active base 1, and is located on the first side of the first common channel layer 211 along the first direction; the second source structure 214 is located between the second common channel layer 212 and the active base 1, and is located on the second side of the first common channel layer 211 along the first direction opposite to the first side. The first source structure 213 and the first drain structure 215 can be used to form a first transistor, and correspondingly, the second source structure 214 and the second drain structure 216 can be used to form a second transistor. The first word line structure 4 is located on a side close to the first transistor, and the second word line structure 5 is located on a side close to the second transistor. Since the first transistor and the second transistor are located on the same target active column 2, that is, the two transistors share the same bit line structure 3, the number of bit line structures 3 can be reduced by half, thereby saving the structural size, which is conducive to improving the integration of semiconductor devices. In addition, since the corresponding transistors share the channel structure, the channel range corresponding to each transistor is increased, thereby improving the floating body effect. In addition, based on the first common channel layer 211 and the second common channel layer 212, vertical channel transistors can be formed. Since the drain of the vertical channel transistor is located at the bottom of the transistor, it is not necessary to directly lead out from the surface of the transistor, so that the isolation between transistors in the array is easier to form, thereby reducing the power consumption of the semiconductor device, and can reduce the volume of the semiconductor unit under the premise of ensuring the storage capacity of the semiconductor device, and improve the response speed and storage density of the semiconductor device.

[0071] Please continue to refer to Figures 6 to 8 In some embodiments, the active base 1 further includes a first doping region 11 located directly below the first common channel layer 211 and a second doping region 12 located on opposite sides of the first doping region 11 along a second direction; the second direction intersects the first direction.

[0072] For example, the second direction may be the OX direction. For example, the second direction may be Figure 6The cc' direction or dd' direction shown in the figure is parallel to each other, and the second direction can be parallel to the directions of the first word line structure 4 and the second word line structure 5. The directions in the subsequent embodiments can refer to the directions in this embodiment, and will not be repeated in the following text.

[0073] Please continue to refer to Figures 6 to 8 In some embodiments, the doping type of the first doping region 11 may be N-type or P-type; the doping type of the second doping region 12 may be N-type or P-type.

[0074] Please continue to refer to Figures 6 to 8 In some embodiments, the doping type of the first doping region 11 is opposite to the doping type of the second doping region 12; the doping type of the first doping region 11 is the same as the doping type of the first common channel layer 211 and the second common channel layer 212; the doping type of the second doping region 12 is the same as the doping type of the first source structure 213, the second source structure 214, the first drain structure 215, and the second drain structure 216.

[0075] Please continue to refer to Figures 6 to 8 In some embodiments, the doping type of the first common channel layer 211 and the second common channel layer 212 may be N-type or P-type; the doping type of the first source structure 213, the second source structure 214, the first drain structure 215, and the second drain structure 216 may also be N-type or P-type.

[0076] Please continue to refer to Figures 6 to 8 For example, the first common channel layer 211 and the second common channel layer 212 have the same doping type, both of which are P-type, the doping type of the first doping region 11 is also P-type, the doping type of the first source structure 213, the second source structure 214, the first drain structure 215, and the second drain structure 216 are all N-type, and the doping type of the second doping region 12 is also N-type. The first source structure 213 and the first drain structure 215, the second source structure 214, and the second drain structure 216 can be used to form two selection transistors respectively. Since the two selection transistors are located in the same target active column 2 and share the P-type first common channel layer 211 and the P-type second common channel layer 212 between the two selection transistors, the device structure size can be saved, which is beneficial to improving the integration of the semiconductor device, and the floating body effect can be further improved by forming a P-type channel through doping.

[0077] Please continue to refer to Figures 6 to 8In some embodiments, the first word line structure 4 includes a first gate dielectric layer 41 and a first gate conductive layer 42 stacked along a first direction; the first gate dielectric layer 41 is located between the first gate conductive layer 42 and the second common channel layer 212; and / or the second word line structure 5 includes a second gate dielectric layer 51 and a second gate conductive layer 52 stacked along the first direction; the second gate dielectric layer 51 is located between the second gate conductive layer 52 and the second common channel layer 212.

[0078] Please continue to refer to Figures 6 to 8 For example, the material of the first gate conductive layer 42 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide and combinations thereof; the material of the second gate conductive layer 52 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide and combinations thereof; the material of the first gate dielectric layer 41 is selected from silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide and combinations thereof; the material of the second gate dielectric layer 51 is selected from silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide and combinations thereof.

[0079] Please continue to refer to Figures 6 to 8 In some embodiments, the memory cell structure further includes a first capacitor contact plug 61, a second capacitor contact plug 62, a first capacitor structure (not shown) and a second capacitor structure (not shown); the first capacitor contact plug 61 is located on the top surface of the first active pillar 22; the second capacitor contact plug 62 is located on the top surface of the second active pillar 24; the first capacitor structure is located on the top surface of the first capacitor contact plug 61; the second capacitor structure is located on the top surface of the second capacitor contact plug 62. The first capacitor structure and the second capacitor structure are used to store charge. The first capacitor contact plug 61 is used to reduce the contact resistance between the first capacitor structure and the first active pillar 22, and the second capacitor contact plug 62 is used to reduce the contact resistance between the second capacitor structure and the second active pillar 24.

[0080] Please continue to refer to Figures 6 to 8 For example, the materials of the first capacitor contact plug 61 and the second capacitor contact plug 62 may be metal silicide, thereby further reducing the contact resistance between the first capacitor structure and the first active pillar 22 , and further reducing the contact resistance between the second capacitor structure and the second active pillar 24 .

[0081] Please continue to refer to Figures 6 to 8According to some embodiments, a memory cell array is provided, comprising a plurality of memory cell structures of any one of the above embodiments arranged in an array along a first direction and a second direction; memory cell structures adjacent to each other along the first direction share a bit line structure 3, and memory cell structures adjacent to each other along the second direction are connected to different bit line structures 3; memory cells adjacent to each other along the second direction share a first word line structure 4 and a second word line structure 5, and memory cell structures adjacent to each other along the first direction are connected to different first word line structures 4 / second word line structures 5.

[0082] Please continue to refer to Figures 6 to 8 In the memory cell array of the above embodiment, the bit line structure 3 surrounding the bottom of the target active column 2 can reduce the resistance of the bit line structure 3, reduce the leakage current, and effectively improve the flatness of the bit line structure 3, thereby improving the performance and reliability of the semiconductor device. In addition, the first active column 22 and the second active column 24 can be used to form two transistors, corresponding to the first word line structure 4 and the second word line structure 5, respectively. Since the two transistors are located in the same target active column 2, that is, the two transistors share the same bit line structure 3, the number of bit line structures 3 can be reduced by half, saving the structure size, which is conducive to improving the integration of semiconductor devices.

[0083] Please continue to refer to Figures 6 to 8 In some embodiments, the memory cell array further includes a bit line isolation structure 71 and a word line isolation structure 72; the bit line isolation structure 71 is located between the bit line structures 3 adjacent to each other along the second direction; and / or the word line isolation structure 72 is located between the first word line structure 4 and the second word line structure 5 adjacent to each other along the first direction, and between the target active pillars 2 adjacent to each other along the first direction. The bit line isolation structure 71 insulates the bit line structures 3 adjacent to each other along the second direction. The word line isolation structure insulates the first word line structure 4 and the second word line structure 5 adjacent to each other along the first direction.

[0084] Please continue to refer to Figures 6 to 9 According to some embodiments, the present disclosure provides a method for preparing a memory cell array, the method comprising:

[0085] Step S20: providing a target substrate 8, the target substrate 8 comprising reference units and bit line structures 3 arrayed along a first direction and a second direction, the reference units comprising an active platform 1 and an initial active column 201 sequentially stacked along a thickness direction of the target substrate 8, the bit line structure 3 being located on a top surface of the active platform 1 and circumferentially surrounding a bottom of the initial active column 201; the first direction intersects with the second direction;

[0086] Step S40: forming a first word line structure 4 and a second word line structure 5 on two opposite sides of the initial active pillar 201 along the first direction;

[0087] Step S60: forming an intermediate isolation structure 23 in the initial active pillar 201 to obtain a target active pillar 2, wherein the target active pillar 2 includes a common active pillar 21 and a first active pillar 22, an intermediate isolation structure 23 and a second active pillar 24 located on the top surface of the common active pillar 21 and sequentially distributed along a first direction.

[0088] Please continue to refer to Figures 6 to 9 In step S20, the target substrate 8 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the target substrate 8 may be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI), or a silicon germanium on insulator. An ion implantation process may be used to implant P-type ions into the target substrate 8 to form a first type doped well region (not shown), and the P-type ions may include, but are not limited to, at least one of boron (B) ions, gallium (Ga) ions, boron fluoride ions, and indium (In) ions.

[0089] Please continue to refer to Figures 6 to 9 In step S20, illustratively, the material of the bit line structure 3 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride silicon and combinations thereof.

[0090] Please continue to refer to Figures 6 to 9 In step S40, for example, the material of the first word line structure 4 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride and combinations thereof; the material of the second word line structure 5 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride and combinations thereof.

[0091] Please continue to refer to Figures 6 to 9 In step S60 , illustratively, the material of the common active pillar 21 is selected from single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, germanium silicon, etc. and combinations thereof.

[0092] Please continue to refer to Figures 6 to 9In the memory cell array of the above embodiment, by forming a bit line structure 3 that circumferentially surrounds the bottom of the initial active pillar 201, the resistance of the bit line structure 3 can be reduced, the leakage current can be reduced, and the flatness of the bit line structure 3 can be effectively improved, thereby improving the performance and reliability of the semiconductor device. In addition, the first active pillar 22 and the second active pillar 24 can be used to form two transistors, corresponding to the first word line structure 4 and the second word line structure 5, respectively. Since the two transistors are located in the same target active pillar 2, that is, the two transistors share the same bit line structure 3, the number of bit line structures 3 can be reduced by half, saving the structure size, which is conducive to improving the integration of semiconductor devices.

[0093] Please refer to FIG. 10A to FIG. 13B In some embodiments, step S20 includes:

[0094] Step S21: providing an initial substrate 9, wherein the initial substrate 9 comprises initial active pillars 201 distributed in an array along a first direction and a second direction;

[0095] Step S22: forming a bit line material layer 31 on the initial substrate 9 between the initial active pillars 201 adjacent to each other along the first direction and the second direction;

[0096] Step S23: forming a bit line isolation structure 71 extending along the first direction in the initial substrate 9 between the initial active pillars 201 adjacent to each other along the second direction, so as to obtain an active platform 1 arranged at intervals along the second direction and extending along the first direction, wherein the initial active pillars 201 are located in the middle of the active platform 1 directly below the initial active pillars 201; and the bit line material layer 31 located on the top surface of the active platform 1 is used to form a bit line structure 3.

[0097] Please refer to FIG. 10A to FIG. 11B In step S21, for example, it also includes:

[0098] Step S211: forming a mask stack 91 on the top surface of the initial substrate 9;

[0099] Step S212: patterning the mask stack 91 to obtain a pattern layer; etching the initial substrate 9 based on the pattern layer to obtain an initial active pillar 201; and removing the pattern layer.

[0100] Please refer to FIG. 10A to FIG. 10B For example, the mask stack 91 may be a single-layer structure, or the mask stack 91 may be a multi-layer structure. For example, the mask stack 91 includes a first mask layer 911, a second mask layer 912, a third mask layer 913, a fourth mask layer 914, and a fifth mask layer 915 sequentially stacked along the thickness direction of the initial substrate 9.

[0101] Please refer to FIG. 12A to FIG. 12BIn step S21, for example, a deposition process may be adopted to form the bit line material layer 31, and the deposition process may include but is not limited to at least one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a high-density plasma deposition process, a plasma enhanced deposition process, and a spin-on dielectric layer process.

[0102] Please refer to FIG. 13A to FIG. 13B In step S23, for example, it also includes:

[0103] Step S231: etching the initial substrate 9 and the bit line material layer 31 to form a bit line isolation trench extending along the first direction in the initial substrate 9 between the initial active pillars 201 adjacent to each other along the second direction; the remaining bit line material layer 31 constitutes the bit line structure 3;

[0104] Step S232: forming a bit line isolation structure 71 in the bit line isolation trench.

[0105] Please refer to FIG. 14A to FIG. 14B In some embodiments, the first word line structure 4 and the second word line structure 5 are formed, and step S40 includes:

[0106] Step S41: forming a dielectric material layer (not shown), the dielectric material layer is located on the top surface of the bit line structure 3 and between adjacent initial active pillars 201;

[0107] Step S42: removing part of the dielectric material layer to form a first word line trench and a second word line trench located on opposite sides of the initial active pillar 201 along the first direction, and a first gate dielectric layer 41 located between the initial active pillar 201 and the first word line trench, and a second gate dielectric layer 51 located between the initial active pillar 201 and the second word line trench; the bottom surface of the first word line trench and the bottom surface of the second word line trench are both higher than the top surface of the bit line structure 3;

[0108] Step S43: forming a first gate conductive layer 42 in the first word line groove and forming a second gate conductive layer 52 in the second word line groove; the top surface of the first gate conductive layer 42 and the top surface of the second gate conductive layer 52 are both lower than the bottom surface of the intermediate isolation structure 23; wherein, the first gate dielectric layer 41 and the first gate conductive layer 42 are used to constitute the first word line structure 4, and the second gate dielectric layer 51 and the second gate conductive layer 52 are used to constitute the second word line structure 5.

[0109] In step S42, for example, a dry etching process may be used to remove part of the dielectric material layer. The dry etching process may include but is not limited to any one of a reactive ion etching process (RIE), an inductively coupled plasma etching process (ICP) or a high concentration plasma etching process (HDP).

[0110] Please refer to FIG. 14A to FIG. 14BIn some embodiments, forming the first word line structure 4 and the second word line structure 5 includes:

[0111] Step S44: forming a dielectric material layer, the dielectric material layer being located on the top surface of the bit line structure 3 and between adjacent initial active pillars 201;

[0112] Step S45: removing part of the dielectric material layer to form a third word line groove and a fourth word line groove located on opposite sides of the initial active pillar 201 along the first direction, the bottom surface of the third word line groove and the bottom surface of the fourth word line groove are both higher than the top surface of the bit line structure 3 and lower than the bottom surface of the intermediate isolation structure 23; the third word line groove exposes part of the first side surface of the initial active pillar 201, and the fourth word line groove exposes part of the second side surface of the initial active pillar 201; the first side surface and the second side surface are opposite surfaces of the initial active pillar 201 along the first direction;

[0113] Step S46: forming a first gate dielectric layer 41 covering the first side surface in the third word line groove, and forming a second gate dielectric layer 51 covering the second side surface in the fourth word line groove; forming a first gate conductive layer 42 in the third word line groove and forming a second gate conductive layer 52 in the fourth word line groove; wherein the first gate dielectric layer 41 and the first gate conductive layer 42 are used to constitute a first word line structure 4, and the second gate dielectric layer 51 and the second gate conductive layer 52 are used to constitute a second word line structure 5.

[0114] Please refer to FIG. 14A to FIG. 15B For example, in step S60, an intermediate isolation structure 23 is formed in the initial active column 201 to obtain a target active column 2, the target active column 2 including a common active column 21 and a first active column 22, an intermediate isolation structure 23 and a second active column 24 located on the top surface of the common active column 21 and distributed in sequence along the first direction.

[0115] Please refer to FIG. 16A to FIG. 17B In some embodiments, after forming the intermediate isolation structure 23, the method further includes:

[0116] Step S80: forming a first capacitor contact plug 61 located on the top surface of the first active pillar 22 and a second capacitor contact plug 62 located on the top surface of the second active pillar 24; forming a first capacitor structure located on the top surface of the first capacitor contact plug 61 and a second capacitor structure located on the top surface of the second capacitor contact plug 62.

[0117] Please refer to FIG. 17A to FIG. 17B , in some embodiments, further comprising:

[0118] Step S70: After forming the intermediate isolation structure 23 and before forming the first capacitor contact plug 61 and the second capacitor contact plug 62, or after forming the initial active pillar and before forming the bit line material layer, a first common channel layer 211 and a second common channel layer 212 are formed in the common active pillar 21; the first common channel layer 211 is located between the first active pillar 22 and the second active pillar 24 and the bottom surface is connected to the active base 1; the second common channel layer 212 is located on the top surface of the first common channel layer 211 and between the first word line structure 4 and the second word line structure 5.

[0119] Please continue to refer to FIG. 17A to FIG. 17B , in some embodiments, further comprising:

[0120] Step S50: After forming an initial substrate and before forming a first common channel layer 211, a first doped region 11 is formed in the initial substrate directly below the first common channel layer 211; after forming the first common channel layer 211 and before forming the second common channel layer 212, a second doped region 12 is formed in the initial substrate and on opposite sides of the first common channel layer 211 along a second direction; the second direction intersects with the first direction.

[0121] Please continue to refer to FIG. 17A to FIG. 17B In some embodiments, the doping type of the first doping region 11 may be N-type or P-type; the doping type of the second doping region 12 may be N-type or P-type.

[0122] Please continue to refer to FIG. 17A to FIG. 17B In some embodiments, the method further includes: after forming the second common channel layer 212 and before forming the first capacitor contact plug 61 and the second capacitor contact plug 62 , forming a second doped region 12 at least in the first active pillar 22 and the second active pillar 24 .

[0123] Please continue to refer to FIG. 17A to FIG. 17BIn some embodiments, the method further includes: after forming the target active pillar 2, doping the target active pillar 2 to form a first source structure 213, a second source structure 214, a first drain structure 215 and a second drain structure 216; the first source structure 213 includes the first active pillar 22 and a portion of the common active pillar 21 thereunder; the second source structure 214 includes the second active pillar 24 and a portion of the common active pillar 21 thereunder; the first drain structure 215 is located between the second common channel layer 212 and the active base 1, and is located on a first side of the first common channel layer 211 along a first direction; the second drain structure 216 is located on the second common channel layer 212 and the active base 1, and is located on the second side of the first common channel layer 211 opposite to the first side along the first direction; or the first drain structure 215 includes the first active pillar 22 and part of the common active pillar 21 thereunder; the second drain structure 216 includes the second active pillar 24 and part of the common active pillar 21 thereunder; the first source structure 213 is located between the second common channel layer 212 and the active base 1, and is located on the first side of the first common channel layer 211 along the first direction; the second source structure 214 is located between the second common channel layer 212 and the active base 1, and is located on the second side of the first common channel layer 211 opposite to the first side along the first direction. The first source structure 213 and the first drain structure 215 can be used to form a first transistor, and correspondingly, the second source structure 214 and the second drain structure 216 can be used to form a second transistor. The first word line structure 4 is located on a side close to the first transistor, and the second word line structure 5 is located on a side close to the second transistor. Since the first transistor and the second transistor are located on the same target active column 2, that is, the two transistors share the same bit line structure 3, the number of bit line structures 3 can be reduced by half, thereby saving the structural size, which is conducive to improving the integration of semiconductor devices. In addition, since the corresponding transistors share the channel structure, the channel range corresponding to each transistor is increased, thereby improving the floating body effect. In addition, based on the first common channel layer 211 and the second common channel layer 212, vertical channel transistors can be formed. Since the drain of the vertical channel transistor is located at the bottom of the transistor, it is not necessary to directly lead out from the surface of the transistor, so that the isolation between transistors in the array is easier to form, thereby reducing the power consumption of the semiconductor device, and can reduce the volume of the semiconductor unit under the premise of ensuring the storage capacity of the semiconductor device, and improve the response speed and storage density of the semiconductor device.

[0124] Please continue to refer to FIG. 17A to FIG. 17BIn some embodiments, the doping type of the first doping region 11 is opposite to the doping type of the second doping region 12; the doping type of the first doping region 11 is the same as the doping type of the first common channel layer 211 and the second common channel layer 212; the doping type of the second doping region 12 is the same as the doping type of the first source structure 213, the second source structure 214, the first drain structure 215, and the second drain structure 216.

[0125] Please continue to refer to FIG. 17A to FIG. 17B For example, the doping type of the first common channel layer 211 and the second common channel layer 212 can be N-type or P-type; the doping type of the first source structure 213, the second source structure 214, the first drain structure 215, and the second drain structure 216 can also be N-type or P-type.

[0126] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0127] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0128] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0129] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.

Claims

1. A storage unit structure, characterized in that: include: an active base, a target active pillar, a bit line structure, a first word line structure, and a second word line structure; The target active column is located on the top surface of the active base and includes a common active column, and a first active column, an intermediate isolation structure and a second active column which are located on the top surface of the common active column and are sequentially distributed along a first direction; The bit line structure is located on the top surface of the active platform and circumferentially surrounds the bottom of the target active pillar; The first word line structure and the second word line structure are located on two opposite sides of the common active pillar along the first direction.

2. The storage unit structure according to claim 1, characterized in that: The common active column comprises: A first common channel layer, located between the first active pillar and the second active pillar and having a bottom surface connected to the active base; The second common channel layer is located on the top surface of the first common channel layer and between the first word line structure and the second word line structure.

3. The storage unit structure according to claim 2, characterized in that: The target active column also includes: A first source structure, comprising the first active pillar and a portion of the common active pillar thereunder; A second source structure, comprising the second active pillar and a portion of the common active pillar thereunder; A first drain structure is located between the second common channel layer and the active platform and located on a first side of the first common channel layer along the first direction; a second drain structure located between the second common channel layer and the active platform and located on a second side of the first common channel layer opposite to the first side along the first direction; or A first drain structure, comprising the first active pillar and a portion of the common active pillar thereunder; A second drain structure, comprising the second active pillar and a portion of the common active pillar thereunder; A first source structure, located between the second common channel layer and the active base, and located on a first side of the first common channel layer along the first direction; The second source structure is located between the second common channel layer and the active platform, and is located on a second side of the first common channel layer opposite to the first side along the first direction.

4. The storage unit structure according to claim 2, characterized in that: The active base also has a first doped region located directly below the first common channel layer and a second doped region located on opposite sides of the first doped region along a second direction; the second direction intersects with the first direction.

5. The storage unit structure according to claim 4, characterized in that: The doping type of the first doping region is opposite to the doping type of the second doping region; The doping type of the first doping region is the same as the doping type of the first common channel layer and the second common channel layer; the doping type of the second doping region is the same as the doping type of the first source structure, the second source structure, the first drain structure, and the second drain structure.

6. The storage unit structure according to any one of claims 2 to 5, characterized in that: The first word line structure includes a first gate dielectric layer and a first gate conductive layer stacked along the first direction; the first gate dielectric layer is located between the first gate conductive layer and the second common channel layer; and / or The second word line structure includes a second gate dielectric layer and a second gate conductive layer stacked along the first direction; the second gate dielectric layer is located between the second gate conductive layer and the second common channel layer.

7. A memory cell array, characterized in that: A storage unit structure according to any one of claims 1 to 6 comprising a plurality of storage unit structures arranged in an array along a first direction and a second direction; The memory cell structures adjacent to each other along the first direction share a bit line structure, and the memory cell structures adjacent to each other along the second direction are connected to different bit line structures; The memory cells adjacent to each other along the second direction share a first word line structure and a second word line structure, and the memory cell structures adjacent to each other along the first direction are connected to different first word line structures / second word line structures.

8. A method for preparing a memory cell array, characterized in that: The method comprises: Providing a target substrate, the target substrate comprising reference units and bit line structures distributed in an array along a first direction and a second direction, the reference units comprising an active base and an initial active column stacked in sequence along a thickness direction of the target substrate, the bit line structure being located on a top surface of the active base and circumferentially surrounding a bottom of the initial active column; the first direction intersects with the second direction; forming a first word line structure and a second word line structure on opposite sides of the initial active pillar along the first direction; An intermediate isolation structure is formed in the initial active column to obtain a target active column, which includes a common active column and a first active column, the intermediate isolation structure and a second active column located on a top surface of the common active column and sequentially distributed along the first direction.

9. The method for preparing a memory cell array according to claim 8, characterized in that: The providing of a target substrate comprises: Providing an initial substrate, the initial substrate comprising initial active pillars distributed in an array along the first direction and the second direction; forming a bit line material layer on the initial substrate between the initial active pillars adjacent to each other along the first direction and the second direction; A bit line isolation structure extending along the first direction is formed in the initial substrate between the initial active pillars adjacent to each other along the second direction to obtain the active bases arranged at intervals along the second direction and extending along the first direction, wherein the initial active pillars are located in the middle of the active bases directly below them; and a bit line material layer located on the top surface of the active bases is used to form the bit line structure.

10. The method for preparing a memory cell array according to claim 9, characterized in that: The first word line structure and the second word line structure are formed, including: forming a dielectric material layer, wherein the dielectric material layer is located on the top surface of the bit line structure and between adjacent initial active pillars; Removing part of the dielectric material layer to form a first word line trench and a second word line trench located on opposite sides of the initial active pillar along the first direction, and a first gate dielectric layer between the initial active pillar and the first word line trench, and a second gate dielectric layer between the initial active pillar and the second word line trench; the bottom surface of the first word line trench and the bottom surface of the second word line trench are both higher than the top surface of the bit line structure; A first gate conductive layer is formed in the first word line groove, and a second gate conductive layer is formed in the second word line groove; the top surface of the first gate conductive layer and the top surface of the second gate conductive layer are both lower than the bottom surface of the intermediate isolation structure; wherein the first gate dielectric layer and the first gate conductive layer are used to constitute the first word line structure, and the second gate dielectric layer and the second gate conductive layer are used to constitute the second word line structure.

11. The method for preparing a memory cell array according to claim 9, characterized in that: The first word line structure and the second word line structure are formed, including: forming a dielectric material layer, wherein the dielectric material layer is located on the top surface of the bit line structure and between adjacent initial active pillars; Removing part of the dielectric material layer to form a third word line groove and a fourth word line groove located on opposite sides of the initial active pillar along the first direction, wherein the bottom surface of the third word line groove and the bottom surface of the fourth word line groove are both higher than the top surface of the bit line structure and lower than the bottom surface of the intermediate isolation structure; the third word line groove exposes part of the first side surface of the initial active pillar, and the fourth word line groove exposes part of the second side surface of the initial active pillar; the first side surface and the second side surface are opposite surfaces of the initial active pillar along the first direction; forming a first gate dielectric layer covering the first side surface in the third word line trench, and forming a second gate dielectric layer covering the second side surface in the fourth word line trench; A first gate conductive layer is formed in the third word line trench and a second gate conductive layer is formed in the fourth word line trench; wherein the first gate dielectric layer and the first gate conductive layer are used to constitute the first word line structure, and the second gate dielectric layer and the second gate conductive layer are used to constitute the second word line structure.

12. The method for preparing a memory cell array according to any one of claims 9 to 11, characterized in that: After forming the intermediate isolation structure, the method further includes: forming a first capacitor contact plug located on a top surface of the first active pillar and a second capacitor contact plug located on a top surface of the second active pillar; A first capacitor structure is formed on a top surface of the first capacitor contact plug, and a second capacitor structure is formed on a top surface of the second capacitor contact plug.

13. The method for preparing a memory cell array according to claim 12, wherein: Also includes: After forming the intermediate isolation structure and before forming the first capacitor contact plug and the second capacitor contact plug, or after forming the initial active column and before forming the bit line material layer, a first common channel layer and a second common channel layer are formed in the common active column; the first common channel layer is located between the first active column and the second active column and the bottom surface is connected to the active base; the second common channel layer is located on the top surface of the first common channel layer and between the first word line structure and the second word line structure.

14. The method for preparing a memory cell array according to claim 13, wherein: Also includes: After forming the initial substrate and before forming the first common channel layer, forming a first doped region directly below the first common channel layer in the initial substrate; After forming the first common channel layer and before forming the second common channel layer, a second doping region is formed in the initial substrate and on two opposite sides of the first common channel layer along a second direction; the second direction intersects with the first direction.

15. The method for preparing a memory cell array according to claim 14, characterized in that: Also includes: After forming the second common channel layer and before forming the first capacitor contact plug and the second capacitor contact plug, a second doping region is formed at least in the first active pillar and the second active pillar.

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