Display device

Abstract

A display device includes: first-first pixel circuit portions in first pixel rows and first pixel columns; first-second pixel circuit portions in the first pixel row and the second pixel column; a second-first pixel circuit portion in the second pixel row and the first pixel column; second-second pixel circuit portions in a second pixel row and a second pixel column; a first sub-data line overlapping the first-first pixel circuit portion and the second-first pixel circuit portion in a plan view and extending in a column direction; and a second sub-data line overlapping the first-second pixel circuit portion and the second-second pixel circuit portion in a plan view and extending in the column direction. The first-first pixel circuit portion and the second-second pixel circuit portion may be electrically connected to the first sub-data line, and the first-second pixel circuit portion and the second-first pixel circuit portion may be electrically connected to the second sub-data line.

Description

Technical Field

[0001] Embodiments generally relate to a display device. Background Art

[0002] The display device includes a display area for displaying an image, and a plurality of pixel circuit parts including at least a semiconductor pattern, a plurality of data lines for supplying data voltages to the plurality of pixel circuit parts, and a plurality of light emitting parts electrically connected to the plurality of pixel circuit parts may be disposed in the display area.

[0003] In the display area, the plurality of pixel circuit parts may be arranged in a matrix form, but the plurality of light emitting parts may not be arranged in a matrix form. Configure settings.

[0004] Under such circumstances, in order to display a high-resolution image with higher space efficiency in a limited display area, various methods are being studied to electrically connect a plurality of pixel circuit parts to a plurality of light emitting parts and simultaneously to a plurality of data lines. Summary of the invention

[0005] The embodiment provides a display device capable of displaying a high-resolution image.

[0006] The display device according to the embodiment includes: a first-first pixel circuit portion located in a first pixel row and a first pixel column; a first-second pixel circuit portion located in the first pixel row and the second pixel column; a second-first pixel circuit portion located in the second pixel row and the first pixel column; a second-second pixel circuit portion located in the second pixel row and the second pixel column; a first sub-data line overlapping the first-first pixel circuit portion and the second-first pixel circuit portion in a plan view and extending in a column direction; and a second sub-data line overlapping the first-second pixel circuit portion and the second-second pixel circuit portion in the plan view and extending in the column direction. Each of the first-first pixel circuit portion and the second-second pixel circuit portion is electrically connected to the first sub-data line, and each of the first-second pixel circuit portion and the second-first pixel circuit portion is electrically connected to the second sub-data line.

[0007] In an embodiment, the first-first pixel circuit portion and the first-second pixel circuit portion may be symmetrical to each other, and the second-first pixel circuit portion and the second-second pixel circuit portion may be asymmetrical to each other.

[0008] In an embodiment, the first-first pixel circuit portion may include a first-first semiconductor pattern, the first-second pixel circuit portion may include a first-second semiconductor pattern, the second-first pixel circuit portion may include a second-first semiconductor pattern, the second-second pixel circuit portion may include a second-second semiconductor pattern, the first-first semiconductor pattern and the first-second semiconductor pattern may be symmetrical to each other, and the second-first semiconductor pattern and the second-second semiconductor pattern may be asymmetrical to each other.

[0009] In an embodiment, each of the first-first semiconductor pattern and the second-second semiconductor pattern may be electrically connected to the first sub data line, and each of the first-second semiconductor pattern and the second-first semiconductor pattern may be electrically connected to the second sub data line.

[0010] In an embodiment, the display device may further include: a first-third pixel circuit portion located in the first pixel row and the third pixel column; a first-fourth pixel circuit portion located in the first pixel row and the fourth pixel column; a second-third pixel circuit portion located in the second pixel row and the third pixel column; a second-fourth pixel circuit portion located in the second pixel row and the fourth pixel column; a third sub-data line overlapping the first-third pixel circuit portion and the second-third pixel circuit portion in the plan view and extending in the column direction; and a fourth sub-data line overlapping the first-fourth pixel circuit portion and the second-fourth pixel circuit portion in the plan view and extending in the column direction. Each of the first-third pixel circuit portion and the second-fourth pixel circuit portion may be electrically connected to the third sub-data line, and each of the first-fourth pixel circuit portion and the second-third pixel circuit portion may be electrically connected to the fourth sub-data line.

[0011] In an embodiment, the display device may also include: a first-first light-emitting portion, electrically connected to the first-first pixel circuit portion and emitting light of a first color; a first-second light-emitting portion, electrically connected to the first-second pixel circuit portion and emitting light of a second color; a first-third light-emitting portion, electrically connected to the first-third pixel circuit portion and emitting light of a third color; and a first-fourth light-emitting portion, electrically connected to the first-fourth pixel circuit portion and emitting light of the second color.

[0012] In an embodiment, the display device may further include: a second-first light emitting portion, electrically connected to the second-first pixel circuit portion and emitting light of the second color; a second-second light emitting portion, electrically connected to the second-second pixel circuit portion and emitting light of the first color; a second-third light emitting portion, electrically connected to the second-third pixel circuit portion and emitting light of the second color; and a second-fourth light emitting portion, electrically connected to the second-fourth pixel circuit portion and emitting light of the third color.

[0013] In an embodiment, the first-first light-emitting portion and the first-third light-emitting portion may be arranged in a row direction intersecting the column direction, the first-second light-emitting portion and the first-fourth light-emitting portion may be arranged in the row direction and spaced apart from the first-first light-emitting portion and the first-third light-emitting portion in the column direction, the second-second light-emitting portion and the second-fourth light-emitting portion may be arranged in the row direction and spaced apart from the first-second light-emitting portion and the first-fourth light-emitting portion in the column direction, and the second-first light-emitting portion and the second-third light-emitting portion may be arranged in the row direction and spaced apart from the second-second light-emitting portion and the second-fourth light-emitting portion in the column direction.

[0014] In an embodiment, the display device may further include: a first-zeroth dummy pixel circuit portion, arranged in the first pixel row and a dummy pixel column adjacent to the first pixel column and spaced apart from the second pixel column; a second-zeroth dummy pixel circuit portion, arranged in the second pixel row and the dummy pixel column; a dummy data line, overlapping the first-zeroth dummy pixel circuit portion and the second-zeroth dummy pixel circuit portion in the plan view, electrically connected to the second-zeroth dummy pixel circuit portion, and extending in the column direction; and a second-zeroth light-emitting portion, electrically connected to the second-zeroth dummy pixel circuit portion.

[0015] In an embodiment, the second-zeroth light emitting parts, the second-second light emitting parts, and the second-fourth light emitting parts may be arranged in the row direction.

[0016] In an embodiment, the display device may further include: a second-zeroth light-emitting portion, electrically connected to the first-third pixel circuit portion through the first-third light-emitting portion; and a connecting electrode, electrically connecting the anode electrode of the first-third light-emitting portion and the anode electrode of the second-zeroth light-emitting portion.

[0017] In an embodiment, the second-zeroth light emitting parts, the second-second light emitting parts, and the second-fourth light emitting parts may be arranged in the row direction.

[0018] The display device according to the embodiment includes: a plurality of first pixel circuit parts arranged in a row direction along a first pixel row; a plurality of second pixel circuit parts arranged in the row direction along a second pixel row; a plurality of sub-data lines electrically connected to the plurality of first pixel circuit parts and the plurality of second pixel circuit parts and extending in a column direction intersecting the row direction; a plurality of extension lines, including a plurality of first extension lines electrically connected one-to-one to the plurality of first pixel circuit parts and a plurality of second extension lines electrically connected one-to-one to the plurality of second pixel circuit parts; a plurality of first light-emitting parts electrically connected one-to-one to the plurality of first extension lines; and a plurality of second light-emitting parts electrically connected one-to-one to the plurality of second extension lines. The number of extension lines overlapping with the sub-data line arranged in the Nth pixel column among the plurality of sub-data lines in the plan view is the same as the number of extension lines overlapping with the sub-data line arranged in the (N+2)th pixel column among the plurality of sub-data lines in the plan view (where N=4M+1, and M is an integer equal to or greater than 0).

[0019] In an embodiment, the extension line overlapping with the sub-data line arranged in the Nth pixel column among the multiple sub-data lines in the plan view may also overlap with the sub-data line arranged in the (N+1)th pixel column among the multiple sub-data lines in the plan view.

[0020] In an embodiment, the extension line overlapping with the sub-data line arranged in the (N+2)th pixel column among the multiple sub-data lines in the plan view may also overlap with the sub-data line arranged in the (N+3)th pixel column among the multiple sub-data lines in the plan view.

[0021] In an embodiment, the sub data line disposed in the N-th pixel column among the plurality of sub data lines may overlap two second extension lines among the plurality of second extension lines in the plan view.

[0022] In an embodiment, the sub data line disposed in the (N+2)th pixel column among the plurality of sub data lines may overlap two first extension lines among the plurality of first extension lines in the plan view.

[0023] In an embodiment, the sub data line disposed in the (N+2)th pixel column among the plurality of sub data lines may overlap two second extension lines among the plurality of second extension lines in the plan view.

[0024] In an embodiment, the sub data line disposed in the (N+2)th pixel column among the plurality of sub data lines may overlap with one second extension line among the plurality of second extension lines and one first extension line among the plurality of first extension lines.

[0025] In an embodiment, the sub data line disposed in the N-th pixel column among the plurality of sub data lines may overlap with two second extension lines among the plurality of second extension lines and one first extension line among the plurality of first extension lines.

[0026] In an embodiment, the sub data line disposed in the (N+2)th pixel column among the plurality of sub data lines may overlap with one first extension line among the plurality of first extension lines and two second extension lines among the plurality of second extension lines.

[0027] In an embodiment, the sub data line disposed in the (N+2)th pixel column among the plurality of sub data lines may overlap with two first extension lines among the plurality of first extension lines and one second extension line among the plurality of second extension lines.

[0028] In an embodiment, the sub data lines disposed in the N-th pixel column among the plurality of sub data lines may overlap with two first extension lines among the plurality of first extension lines and two second extension lines among the plurality of second extension lines.

[0029] In an embodiment, the sub data lines disposed in the (N+2)th pixel column among the plurality of sub data lines may overlap with two first extension lines among the plurality of first extension lines and two second extension lines among the plurality of second extension lines.

[0030] The display device according to the embodiment may include: a first-first pixel circuit portion located in a first pixel row and a first pixel column; a first-second pixel circuit portion located in the first pixel row and the second pixel column; a second-first pixel circuit portion located in the second pixel row and the first pixel column; a second-second pixel circuit portion located in the second pixel row and the second pixel column; a first sub-data line overlapping the first-first pixel circuit portion and the second-first pixel circuit portion in a plan view and extending in a column direction; and a second sub-data line overlapping the first-second pixel circuit portion and the second-second pixel circuit portion in the plan view and extending in the column direction. Each of the first-first pixel circuit portion and the second-second pixel circuit portion may be electrically connected to the first sub-data line, and each of the first-second pixel circuit portion and the second-first pixel circuit portion may be electrically connected to the second sub-data line.

[0031] Therefore, within a limited display area, the first-first pixel circuit portion, the first-second pixel circuit portion, the second-first pixel circuit portion, the second-second pixel circuit portion, the first sub-data line, and the second sub-data line can be effectively arranged.

[0032] The display device according to the embodiment may include: a plurality of first pixel circuit parts arranged in a row direction along a first pixel row; a plurality of second pixel circuit parts arranged in the row direction along a second pixel row; a plurality of sub-data lines electrically connected to the plurality of first pixel circuit parts and the plurality of second pixel circuit parts and extending in a column direction intersecting the row direction; a plurality of extension lines including a plurality of first extension lines electrically connected one-to-one to the plurality of first pixel circuit parts and a plurality of second extension lines electrically connected one-to-one to the plurality of second pixel circuit parts; a plurality of first light-emitting parts electrically connected one-to-one to the plurality of first extension lines; and a plurality of second light-emitting parts electrically connected one-to-one to the plurality of second extension lines. The number of extension lines overlapping with a sub-data line arranged in an Nth pixel column among the plurality of sub-data lines in a plan view may be the same as the number of extension lines overlapping with a sub-data line arranged in an (N+2)th pixel column among the plurality of sub-data lines in a plan view (where N=4M+1 and M is an integer equal to or greater than 0).

[0033] Therefore, in each of the plurality of sub-data lines, the coupling influence due to the plurality of extension lines may be at substantially the same level. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0035] Figure 1 is a plan view for explaining a display device according to a first embodiment of the present disclosure.

[0036] Figure 2 yes Figure 1 An enlarged plan view of Area A.

[0037] Figure 3 It is used to illustrate Figure 2 A cross-sectional view of the first-first light emitting portion shown in .

[0038] Figure 4 , Figure 5 , Figure 6 and Figure 7 It is used to illustrate Figure 2 A view of the first-first pixel circuit portion, the first-second pixel circuit portion, the first sub-data line, and the second sub-data line shown in FIG.

[0039] Figure 8 , Fig. 9 , Fig.10 and Fig.11 It is used to illustrate Figure 2 A view of the second-first pixel circuit portion, the second-second pixel circuit portion, the first sub-data line, and the second sub-data line shown in FIG.

[0040] Fig.12 is a plan view for explaining a display device according to a second embodiment of the present disclosure.

[0041] Fig.13 yes Fig.12 An enlarged plan view of Area B.

[0042] Fig.14 is a plan view for explaining a display device according to a third embodiment of the present disclosure.

[0043] Fig.15 is an equivalent circuit diagram showing one pixel.

[0044] Fig.16 It is used to describe the settings Fig.14 A plan view of the pixel circuit portion and sub-data lines in area C.

[0045] Fig.17 It is used to describe the settings Fig.14 A plan view of the extension line of Area C.

[0046] Fig.18 yes Fig.14 An enlarged plan view of Area C.

[0047] Fig.19 It is along Fig.18 A cross-sectional view taken along line V-V'.

[0048] Fig. 20 is a plan view for explaining a display device according to a fourth embodiment of the present disclosure.

[0049] Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 and Fig. 27 It is used to describe the settings Fig. 20 Plan views of various embodiments of the extension lines in area D. DETAILED DESCRIPTION

[0050] Hereinafter, a display device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0051] Figure 1 is a plan view for explaining a display device according to a first embodiment of the present disclosure.

[0052] refer to Figure 1 , the display device DDa according to the first embodiment of the present disclosure may include a display area DA and a peripheral area PA.

[0053] The display area DA may be an area where an image is displayed. To this end, a plurality of light emitting parts may be provided in the display area DA. For example, the plurality of light emitting parts may include a first color emission part EB, a second color emission part EG, and a third color emission part ER. The "... emission part" may also be referred to as a "... light emitting part".

[0054] The first color light emitting portion EB may emit light of a first color visible to a user of the display device DDa. The second color light emitting portion EG may emit light of a second color visible to a user of the display device DDa. The third color light emitting portion ER may emit light of a third color visible to a user of the display device DDa. In some embodiments, the first color may be blue, the second color may be green, and the third color may be red. However, the present disclosure is not limited to these color assignments, and the first color, the second color, and the third color may have various combinations of three different colors.

[0055] In an embodiment, a plurality of first color light emitting portions EB, a plurality of second color light emitting portions EG, and a plurality of third color light emitting portions ER may be provided. The first color light emitting portions EB and the third color light emitting portions ER may be arranged alternately along the row direction DR1, and the second color light emitting portions EG may be arranged along the row direction DR1. In this case, the first color light emitting portions EB and the third color light emitting portions ER alternately arranged along the row direction DR1 may be alternately arranged with the second color light emitting portions EG arranged along the row direction DR1 in the column direction DR2 intersecting the row direction DR1. In this way, Figure 1 The planar arrangement of the first color light emitting portion EB, the second color light emitting portion EG, and the third color light emitting portion ER shown in FIG. Configuration.

[0056] The peripheral area PA may be disposed at least one side of the display area DA. The peripheral area PA may surround the display area DA. A plurality of driving circuits generating or transmitting driving signals provided to a plurality of light emitting parts may be disposed in the peripheral area PA.

[0057] Figure 2 yes Figure 1 The area A may be a display area DA (see Figure 1 ) part.

[0058] refer to Figure 2 , a plurality of pixel circuit parts SP and a plurality of dummy pixel circuit parts DSP may be disposed in the display area DA.

[0059] In an embodiment, the plurality of pixel circuit parts SP may be arranged in a matrix form. For example, the plurality of pixel circuit parts SP may include a first-first pixel circuit part SP11, a first-second pixel circuit part SP12, a first-third pixel circuit part SP13, a first-fourth pixel circuit part SP14, a second-first pixel circuit part SP21, a second-second pixel circuit part SP22, a second-third pixel circuit part SP23, and a second-fourth pixel circuit part SP24 arranged in a matrix of two rows and four columns.

[0060] The first-first pixel circuit portion SP11, the first-second pixel circuit portion SP12, the first-third pixel circuit portion SP13, and the first-fourth pixel circuit portion SP14 may be disposed in the first pixel row R1. The first-first pixel circuit portion SP11, the first-second pixel circuit portion SP12, the first-third pixel circuit portion SP13, and the first-fourth pixel circuit portion SP14 may be arranged in the row direction DR1.

[0061] The second-first pixel circuit portion SP21, the second-second pixel circuit portion SP22, the second-third pixel circuit portion SP23, and the second-fourth pixel circuit portion SP24 may be disposed in the second pixel row R2. The second pixel row R2 may be adjacent to the first pixel row R1 in the column direction DR2. The second-first pixel circuit portion SP21, the second-second pixel circuit portion SP22, the second-third pixel circuit portion SP23, and the second-fourth pixel circuit portion SP24 may be arranged in the row direction DR1.

[0062] The first-first pixel circuit portion SP11 and the second-first pixel circuit portion SP21 may be disposed in the first pixel column C1. The first-first pixel circuit portion SP11 and the second-first pixel circuit portion SP21 may be arranged adjacent to each other in the column direction DR2.

[0063] The first-second pixel circuit portion SP12 and the second-second pixel circuit portion SP22 may be disposed in the second pixel column C2. The second pixel column C2 may be adjacent to the first pixel column C1 in the row direction DR1. The first-second pixel circuit portion SP12 and the second-second pixel circuit portion SP22 may be arranged adjacent to each other in the column direction DR2.

[0064] The first-third pixel circuit portion SP13 and the second-third pixel circuit portion SP23 may be disposed in the third pixel column C3. The third pixel column C3 may be adjacent to the second pixel column C2 in the row direction DR1. The first-third pixel circuit portion SP13 and the second-third pixel circuit portion SP23 may be arranged adjacent to each other in the column direction DR2.

[0065] The first to fourth pixel circuit portions SP14 and the second to fourth pixel circuit portions SP24 may be disposed in the fourth pixel column C4. The fourth pixel column C4 may be adjacent to the third pixel column C3 in the row direction DR1. The first to fourth pixel circuit portions SP14 and the second to fourth pixel circuit portions SP24 may be arranged adjacent to each other in the column direction DR2.

[0066] The plurality of dummy pixel circuit portions DSP may include a first-0th dummy pixel circuit portion DSP10 and a second-0th dummy pixel circuit portion DSP20 .

[0067] The first-0th dummy pixel circuit portion DSP10 may be disposed in the first pixel row R1. The second-0th dummy pixel circuit portion DSP20 may be disposed in the second pixel row R2.

[0068] The first-zeroth dummy pixel circuit portion DSP10 and the second-zeroth dummy pixel circuit portion DSP20 may be disposed in the dummy pixel column C0. The dummy pixel column C0 may be adjacent to the first pixel column C1 in the row direction DR1. In this case, the dummy pixel column C0 may be disposed closer to the peripheral area PA than the first pixel column C1 (see Figure 1 The first-0th dummy pixel circuit portion DSP10 and the second-0th dummy pixel circuit portion DSP20 may be arranged in the column direction DR2.

[0069] The first data line pair DL1 and the second data line pair DL2 may overlap the plurality of pixel circuit portions SP. The first data line pair DL1 may include a first sub-data line DL1B and a second sub-data line DL1G. The second data line pair DL2 may include a third sub-data line DL2R and a fourth sub-data line DL2G.

[0070] The first sub data line DL1B may be disposed in the first pixel column C1. That is, the first sub data line DL1B may overlap the first-first pixel circuit portion SP11 and the second-first pixel circuit portion SP21 in a plan view. The first sub data line DL1B may extend in the column direction DR2.

[0071] The second sub data line DL1G may be disposed in the second pixel column C2. That is, the second sub data line DL1G may overlap the first-second pixel circuit portion SP12 and the second-second pixel circuit portion SP22 in a plan view. The second sub data line DL1G may extend in the column direction DR2.

[0072] The third sub data line DL2R may be disposed in the third pixel column C3. That is, the third sub data line DL2R may overlap the first-third pixel circuit portion SP13 and the second-third pixel circuit portion SP23 in a plan view. The third sub data line DL2R may extend in the column direction DR2.

[0073] The fourth sub data line DL2G may be disposed in the fourth pixel column C4. That is, the fourth sub data line DL2G may overlap the first-fourth pixel circuit portion SP14 and the second-fourth pixel circuit portion SP24 in a plan view. The fourth sub data line DL2G may extend in the column direction DR2.

[0074] The first sub data line DL1B may be electrically connected to each of the first-first pixel circuit portion SP11 and the second-second pixel circuit portion SP22. In an embodiment, a first color data voltage corresponding to a first color may be provided to the first sub data line DL1B.

[0075] The second sub data line DL1G may be electrically connected to each of the first-second pixel circuit portion SP12 and the second-first pixel circuit portion SP21. In an embodiment, a second color data voltage corresponding to a second color may be provided to the second sub data line DL1G.

[0076] The third sub data line DL2R may be electrically connected to each of the first-third pixel circuit portion SP13 and the second-fourth pixel circuit portion SP24. In an embodiment, a third color data voltage corresponding to a third color may be provided to the third sub data line DL2R.

[0077] The fourth sub data line DL2G may be electrically connected to each of the first-fourth pixel circuit portion SP14 and the second-third pixel circuit portion SP23. In an embodiment, a second color data voltage corresponding to the second color may be provided to the fourth sub data line DL2G.

[0078] The dummy data line DL0 may be arranged on a plurality of dummy pixel circuit portions DSP. The dummy data line DL0 may be arranged in a dummy pixel column C0. That is, the dummy data line DL0 may overlap the first-zeroth dummy pixel circuit portion DSP10 and the second-zeroth dummy pixel circuit portion DSP20 in a plan view. The dummy data line DL0 may extend in the column direction DR2. In an embodiment, the dummy data line DL0 may be electrically connected to the second-zeroth dummy pixel circuit portion DSP20.

[0079] The first color light emitting part EB, the second color light emitting part EG, and the third color light emitting part ER may be disposed in the display area DA. The first color light emitting part EB, the second color light emitting part EG, and the third color light emitting part ER may be disposed on a plurality of pixel circuit parts SP, a plurality of dummy pixel circuit parts DSP, a dummy data line DL0, a first data line pair DL1, and a second data line pair DL2.

[0080] The first color light emitting part EB may include a first-first light emitting part EB11 electrically connected to the first-first pixel circuit part SP11 and a second-second light emitting part EB22 electrically connected to the second-second pixel circuit part SP22.

[0081] The second color light-emitting portion EG may include a first-second light-emitting portion EG12 electrically connected to the first-second pixel circuit portion SP12, a first-fourth light-emitting portion EG14 electrically connected to the first-fourth pixel circuit portion SP14, a second-first light-emitting portion EG21 electrically connected to the second-first pixel circuit portion SP21, and a second-third light-emitting portion EG23 electrically connected to the second-third pixel circuit portion SP23.

[0082] The third color light emitting part ER may include a first-third light emitting part ER13 electrically connected to the first-third pixel circuit part SP13, a second-zeroth light emitting part ER20 electrically connected to the second-zeroth dummy pixel circuit part DSP20, and a second-fourth light emitting part ER24 electrically connected to the second-fourth pixel circuit part SP24.

[0083] The first color light emitting portion EB, the second color light emitting portion EG, and the third color light emitting portion ER may include substantially similar structures. For example, if the description is based on the first-first light emitting portion EB11, the first-first light emitting portion EB11 may include a pixel electrode PXE, and the pixel electrode PXE may be electrically connected to the first-first pixel circuit portion SP11 through a contact hole (or through hole) CNT.

[0084] In this case, a portion of the pixel electrode PXE may be exposed through the pixel opening PXO, and the light emitting layer EL (see FIG. 1 ) that emits light of the first color may be exposed. Figure 3 ) may be disposed on the portion of the pixel electrode PXE. This will be referred to later Figure 3 Detailed description.

[0085] The first color light emitting part EB, the second color light emitting part EG and the third color light emitting part ER may be Configure settings.

[0086] The first-first light emitting part EB11 and the first-third light emitting part ER13 may be disposed adjacently in the row direction DR1. In this case, the first color light may be emitted from the first-first light emitting part EB11, and the third color light may be emitted from the first-third light emitting part ER13.

[0087] The first-second light emitting parts EG12 and the first-fourth light emitting parts EG14 may be arranged in the row direction DR1, and the first-second light emitting parts EG12 and the first-fourth light emitting parts EG14 may be spaced apart from the first-first light emitting parts EB11 and the first-third light emitting parts ER13 in the column direction DR2. The light of the second color may be emitted from each of the first-second light emitting parts EG12 and the first-fourth light emitting parts EG14.

[0088] The second-0th light emitting part ER20, the second-second light emitting part EB22, and the second-fourth light emitting part ER24 may be disposed adjacent to each other in the row direction DR1, and the second-0th light emitting part ER20, the second-second light emitting part EB22, and the second-fourth light emitting part ER24 may be spaced apart from the first-second light emitting part EG12 and the first-fourth light emitting part EG14 in the column direction DR2. The light of the third color may be emitted from each of the second-0th light emitting part ER20 and the second-fourth light emitting part ER24, and the light of the first color may be emitted from the second-second light emitting part EB22.

[0089] The second-first light emitting part EG21 and the second-third light emitting part EG23 may be arranged in the row direction DR1, and the second-first light emitting part EG21 and the second-third light emitting part EG23 may be spaced apart from the second-zeroth light emitting part ER20, the second-second light emitting part EB22 and the second-fourth light emitting part ER24 in the column direction DR2.

[0090] In the display device DDa according to the first embodiment of the present disclosure (see Figure 1 ), a plurality of pixel circuit parts SP and a plurality of dummy pixel circuit parts DSP may be arranged in a matrix form. However, the first color light emitting part EB, the second color light emitting part EG, and the third color light emitting part ER electrically connected to the plurality of pixel circuit parts SP and the plurality of dummy pixel circuit parts DSP may be arranged in a matrix form. Configure settings.

[0091] In order to electrically connect a plurality of pixel circuit portions SP and a plurality of dummy pixel circuit portions DSP arranged in a matrix form to the first color light emitting portion EB, the second color light emitting portion EG, and the third color light emitting portion ER, in the present disclosure, the pixel circuit portions connected to one sub data line may not be aligned in the column direction DR2. For example, in the first pixel row R1, the first sub data line DL1B may be electrically connected to the first-first pixel circuit portion SP11 located in the first pixel column C1, but in the second pixel row R2, the first sub data line DL1B may be electrically connected to the second-second pixel circuit portion SP22 located in the second pixel column C2.

[0092] although Figure 2 Only the following are shown Figure 1 The display area DA shown in FIG. 1 is area A, but is arranged in Figure 2 The components in area A shown in FIG. 1 can be applied to the entire display area DA. More specifically, Figure 2 The components shown in can be repeatedly arranged in the column direction DR2. Figure 2 Among the components shown in FIG. 1 , except for the dummy pixel circuit part DSP, the dummy data line DL0 and the second-zeroth light emitting part ER20 , the components may be repeatedly arranged in the row direction DR1 .

[0093] Figure 3 It is used to illustrate Figure 2 A cross-sectional view of the first-first light emitting portion shown in .

[0094] refer to Figure 3 And combined with Figure 1 and Figure 2 The display device DDa according to the first embodiment of the present disclosure may include a substrate SUB, a circuit layer CIR, a line layer LL, a via insulating layer VIA, a pixel electrode PXE, a pixel defining layer PDL, a light emitting layer EL and a common electrode layer CE which are respectively arranged in a thickness direction DR3 perpendicular to a row direction DR1 and a column direction DR2.

[0095] The substrate SUB may include glass or plastic, etc. In an embodiment, the substrate SUB may include a flexible material.

[0096] The circuit layer CIR may be disposed on the substrate SUB. The circuit layer CIR may include at least one transistor and may include a plurality of pixel circuit parts SP. Figure 3 As shown in FIG. 1 , the circuit layer CIR may include a first-zeroth dummy pixel circuit portion DSP10 and a first-first pixel circuit portion SP11 .

[0097] The line layer LL may be disposed on the circuit layer CIR. The line layer LL may include at least a data line. Figure 3 Although not shown in the figure, the line layer LL may include a dummy data line DL0, a first data line pair DL1, and a second data line pair DL2.

[0098] The via insulating layer VIA may be disposed on the line layer LL. The via insulating layer VIA may include an organic insulating material and / or an inorganic insulating material. An upper surface of the via insulating layer VIA may be substantially flat.

[0099] The pixel electrode PXE may be disposed on the via insulating layer VIA. The pixel electrode PXE may include a conductive material. The pixel electrode PXE may be electrically connected to the first-first pixel circuit portion SP11 of the circuit layer CIR at least through a through hole CNT penetrating the via insulating layer VIA. For example, Figure 3 As shown in FIG. 1 , the pixel electrode PXE may be electrically connected to the first-first pixel circuit portion SP11 through a through hole CNT extending through the via insulating layer VIA and the line layer LL. Figure 3 Unlike shown in , the pixel electrode PXE may be electrically connected to a bridge electrode included in the line layer LL through a via CNT, and the bridge electrode may be electrically connected to the first-first pixel circuit portion SP11. In an embodiment, the pixel electrode PXE may be an anode electrode.

[0100] The pixel defining layer PDL may be disposed on the via insulating layer VIA and the pixel electrode PXE. The pixel defining layer PDL may define a pixel opening PXO exposing at least a portion of the pixel electrode PXE. The pixel defining layer PDL may include an organic insulating material and / or an inorganic insulating material.

[0101] The light emitting layer EL may be disposed on a portion of the pixel electrode PXE exposed by the pixel opening PXO. In an embodiment, the light emitting layer EL may include an organic light emitting material.

[0102] The common electrode layer CE may be disposed on the light emitting layer EL. The common electrode layer CE may include a conductive material. In an embodiment, the common electrode layer CE may be a cathode electrode.

[0103] The pixel electrode PXE, the light emitting layer EL, and the common electrode layer CE may define a first-first light emitting portion EB11.

[0104] exist Figure 3 , only the first-first light emitting portion EB11 is shown. However, Figure 3 Other light-emitting parts not shown (for example, Figure 2Each of the first-second light emitting part EG12, the first-third light emitting part ER13, the first-fourth light emitting part EG14, the second-zeroth light emitting part ER20, the second-first light emitting part EG21, the second-second light emitting part EB22, the second-third light emitting part EG23 and the second-fourth light emitting part ER24 can be Figure 3 The first-first light emitting part EB11 shown in FIG. 1 has a substantially similar structure.

[0105] Figure 4 , Figure 5 , Figure 6 and Figure 7 It is used to illustrate Figure 2 A view of the first-first pixel circuit portion, the first-second pixel circuit portion, the first sub-data line, and the second sub-data line shown in FIG.

[0106] refer to Figure 4 , the first-first pixel circuit portion SP11 may include a first-first data write transistor TDATA11 electrically connected to the first sub data line DL1B, and the first-second pixel circuit portion SP12 may include a first-second data write transistor TDATA12 electrically connected to the second sub data line DL1G.

[0107] In an embodiment, an input terminal of the first-first data write transistor TDATA11 may be directly connected to the first sub data line DL1B without passing through another transistor.

[0108] In an embodiment, an input terminal of the first-second data write transistor TDATA12 may be directly connected to the second sub data line DL1G without passing through another transistor.

[0109] refer to Figure 5 And combined with Figure 4 , the first-first pixel circuit portion SP11 may include a first-first semiconductor pattern ATV11, and the first-second pixel circuit portion SP12 may include a first-second semiconductor pattern ATV12.

[0110] The first-first semiconductor pattern ATV11 may include a first portion ATV11 - P1 and a second portion ATV11 - P2 .

[0111] The second portion ATV11-P2 of the first-first semiconductor pattern ATV11 may include conductive regions I11 and O11 and a semiconductor region C11. The conductive region I11 may be an input terminal of the first-first data write transistor TDATA11 or may be electrically connected to the input terminal of the first-first data write transistor TDATA11. The semiconductor region C11 may define a channel of the first-first data write transistor TDATA11. The conductive region O11 may be an output terminal of the first-first data write transistor TDATA11 or may be electrically connected to the output terminal of the first-first data write transistor TDATA11.

[0112] The first portion ATV11-P1 of the first-first semiconductor pattern ATV11 may be a portion of the first-first semiconductor pattern ATV11 except the second portion ATV11-P2 of the first-first semiconductor pattern ATV11. In this case, the first portion ATV11-P1 of the first-first semiconductor pattern ATV11 may have various known shapes.

[0113] The first-second semiconductor pattern ATV12 may include a first portion ATV12 - P1 and a second portion ATV12 - P2 .

[0114] The second portion ATV12-P2 of the first-second semiconductor pattern ATV12 may include conductive regions I12 and O12 and a semiconductor region C12. The conductive region I12 may be an input terminal of the first-second data write transistor TDATA12, or may be electrically connected to the input terminal of the first-second data write transistor TDATA12. The semiconductor region C12 may define a channel of the first-second data write transistor TDATA12. The conductive region O12 may be an output terminal of the first-second data write transistor TDATA12, or may be electrically connected to the output terminal of the first-second data write transistor TDATA12.

[0115] The first portion ATV12-P1 of the first-second semiconductor pattern ATV12 may be a portion of the first-second semiconductor pattern ATV12 except the second portion ATV12-P2 of the first-second semiconductor pattern ATV12. In this case, the first portion ATV12-P1 of the first-second semiconductor pattern ATV12 may have various known shapes.

[0116] In an embodiment, the first-first semiconductor pattern ATV11 and the first-second semiconductor pattern ATV12 may be symmetrical to each other with respect to an imaginary line extending between the first-first semiconductor pattern ATV11 and the first-second semiconductor pattern ATV12. That is, the first portion ATV11-P1 of the first-first semiconductor pattern ATV11 may be symmetrical with the first portion ATV12-P1 of the first-second semiconductor pattern ATV12, and the second portion ATV11-P2 of the first-first semiconductor pattern ATV11 may be symmetrical with the second portion ATV12-P2 of the first-second semiconductor pattern ATV12.

[0117] In an embodiment, the first-first semiconductor pattern ATV11 and the first-second semiconductor pattern ATV12 may be physically connected to each other. For example, at least a portion of the first portion ATV11-P1 of the first-first semiconductor pattern ATV11 may be physically connected to at least a portion of the first portion ATV12-P1 of the first-second semiconductor pattern ATV12.

[0118] In embodiments, the first-first semiconductor pattern ATV11 and the first-second semiconductor pattern ATV12 may be symmetrical to each other, and at the same time, the first-first semiconductor pattern ATV11 and the first-second semiconductor pattern ATV12 may be physically connected to each other.

[0119] refer to Figure 6 , the first data line pair DL1 may be disposed on the first-first semiconductor pattern ATV11 and the first-second semiconductor pattern ATV12.

[0120] The first sub data line DL1B may be electrically connected to the second portion ATV11 - P2 of the first-first semiconductor pattern ATV11. More specifically, the first sub data line DL1B may be electrically connected to the conductive region I11 of the first-first semiconductor pattern ATV11.

[0121] The second sub data line DL1G may be electrically connected to the second portion ATV12 - P2 of the first-second semiconductor pattern ATV12. More specifically, the second sub data line DL1G may be electrically connected to the conductive region I12 of the first-second semiconductor pattern ATV12.

[0122] refer to Figure 7 , Figure 7 It is along Figure 6 Cross-sectional views taken along line II' and line II-II'.

[0123] The buffer layer BUF may be disposed on the substrate SUB. The buffer layer BUF may include a Figure 3The circuit layer CIR described in the embodiment of the present invention is shown in FIG. 1 . The buffer layer BUF may include an inorganic insulating material. The buffer layer BUF may be used to protect components disposed on the buffer layer BUF from foreign substances present on the substrate SUB. In an embodiment, the buffer layer BUF may be omitted.

[0124] First-first semiconductor pattern ATV11 (see, for example, Figure 6 ) and the first-second semiconductor pattern ATV12 (see, for example, Figure 6 ) can be arranged on the buffer layer BUF. Figure 7 As shown in , the conductive region I11 of the first-first semiconductor pattern ATV11 may be disposed on the buffer layer BUF, and the conductive region I12 of the first-second semiconductor pattern ATV12 may be disposed on the buffer layer BUF.

[0125] The insulating layer array ILA may be disposed on the buffer layer BUF. The insulating layer array ILA may cover the conductive region I11 of the first-first semiconductor pattern ATV11 and the conductive region I12 of the first-second semiconductor pattern ATV12. The insulating layer array ILA may include a plurality of insulating layers stacked in the thickness direction DR3. The insulating layer array ILA may include a plurality of insulating layers stacked in the reference direction DR4. Figure 3 Described in the circuit layer CIR and the line layer LL.

[0126] The first sub-data line DL1B and the second sub-data line DL1G may be disposed on the insulating layer array ILA. In this case, the first sub-data line DL1B may be disposed to overlap at least a portion of the conductive region I11 of the first-first semiconductor pattern ATV11, and the second sub-data line DL1G may be disposed to overlap at least a portion of the conductive region I12 of the first-second semiconductor pattern ATV12.

[0127] The first sub data line DL1B may be electrically connected to the conductive region I11 of the first-first semiconductor pattern ATV11.

[0128] For example, Figure 7 As shown in , the first sub data line DL1B may electrically contact the first-first bridging electrode BR11, and the first-first bridging electrode BR11 may electrically contact the conductive region I11 of the first-first semiconductor pattern ATV11. In this case, the first-first bridging electrode BR11 may be disposed between the first sub data line DL1B and the first-first semiconductor pattern ATV11 in the circuit layer CIR and the line layer LL.

[0129] In some embodiments, Figure 7, the first sub data line DL1B may electrically contact the conductive region I11 of the first-first semiconductor pattern ATV11 through two or more bridge electrodes. In some embodiments, the first-first bridge electrode BR11 may be omitted, and the first sub data line DL1B may electrically contact the conductive region I11 of the first-first semiconductor pattern ATV11.

[0130] The second sub data line DL1G may be electrically connected to the conductive region I12 of the first-second semiconductor pattern ATV12.

[0131] For example, Figure 7 As shown in , the second sub data line DL1G may electrically contact the first-second bridging electrode BR12, and the first-second bridging electrode BR12 may electrically contact the conductive region I12 of the first-second semiconductor pattern ATV12. In this case, the first-second bridging electrode BR12 may be disposed between the second sub data line DL1G and the first-second semiconductor pattern ATV12 in the circuit layer CIR and the line layer LL.

[0132] and Figure 7 Different from the above, the second sub data line DL1G may electrically contact the conductive area I12 of the first-second semiconductor pattern ATV12 through two or more bridge electrodes. For example, the first-second bridge electrode BR12 may be omitted, and the second sub data line DL1G may electrically contact the conductive area I12 of the first-second semiconductor pattern ATV12.

[0133] exist Figure 4 , Figure 5 , Figure 6 and Figure 7 In the description, only the first-first pixel circuit portion SP11, the first-second pixel circuit portion SP12, the first sub-data line DL1B and the second sub-data line DL1G are described. Figure 4 , Figure 5 , Figure 6 and Figure 7 The description can be similarly applied to Figure 2 The first-third pixel circuit portion SP13, the first-fourth pixel circuit portion SP14, the third sub-data line DL2R, and the fourth sub-data line DL2G shown in FIG. That is, the first-third pixel circuit portion SP13, the first-fourth pixel circuit portion SP14, the third sub-data line DL2R, and the fourth sub-data line DL2G may have substantially the same structure as the first-first pixel circuit portion SP11, the first-second pixel circuit portion SP12, the first sub-data line DL1B, and the second sub-data line DL1G.

[0134] Figure 8 , Fig. 9 , Fig.10 and Fig.11 It is used to illustrate Figure 2 A view of the second-first pixel circuit portion, the second-second pixel circuit portion, the first sub-data line, and the second sub-data line shown in FIG.

[0135] refer to Figure 8 , the second-first pixel circuit portion SP21 may include a second-first data write transistor TDATA21 electrically connected to the second sub data line DL1G, and the second-second pixel circuit portion SP22 may include a second-second data write transistor TDATA22 electrically connected to the first sub data line DL1B.

[0136] In an embodiment, an input terminal of the second-first data write transistor TDATA21 may be directly connected to the second sub data line DL1G without passing through another transistor.

[0137] In an embodiment, an input terminal of the second-second data write transistor TDATA22 may be directly connected to the first sub data line DL1B without passing through another transistor.

[0138] refer to Fig. 9 And combined with Figure 8 , the second-first pixel circuit portion SP21 may include a second-first semiconductor pattern ATV21, and the second-second pixel circuit portion SP22 may include a second-second semiconductor pattern ATV22.

[0139] The second-first semiconductor pattern ATV21 may include a first portion ATV21 - P1 and a second portion ATV21 - P2 .

[0140] The second portion ATV21-P2 of the second-first semiconductor pattern ATV21 may include conductive regions I21 and O21 and a semiconductor region C21. The conductive region I21 may be an input terminal of the second-first data write transistor TDATA21, or may be electrically connected to the input terminal of the second-first data write transistor TDATA21. The semiconductor region C21 may define a channel of the second-first data write transistor TDATA21. The conductive region O21 may be an output terminal of the second-first data write transistor TDATA21, or may be electrically connected to the output terminal of the second-first data write transistor TDATA21.

[0141] The first portion ATV21-P1 of the second-first semiconductor pattern ATV21 may be a portion of the second-first semiconductor pattern ATV21 except the second portion ATV21-P2 of the second-first semiconductor pattern ATV21. In this case, the first portion ATV21-P1 of the second-first semiconductor pattern ATV21 may have various known shapes.

[0142] The second-second semiconductor pattern ATV22 may include a first portion ATV22 - P1 and a second portion ATV22 - P2 .

[0143] The second portion ATV22-P2 of the second-second semiconductor pattern ATV22 may include conductive regions I22 and O22 and a semiconductor region C22. The conductive region I22 may be an input terminal of the second-second data write transistor TDATA22, or may be electrically connected to the input terminal of the second-second data write transistor TDATA22. The semiconductor region C22 may define a channel of the second-second data write transistor TDATA22. The conductive region O22 may be an output terminal of the second-second data write transistor TDATA22, or may be electrically connected to the output terminal of the second-second data write transistor TDATA22.

[0144] The first portion ATV22-P1 of the second-second semiconductor pattern ATV22 may be a portion of the second-second semiconductor pattern ATV22 except the second portion ATV22-P2 of the second-second semiconductor pattern ATV22. In this case, the first portion ATV22-P1 of the second-second semiconductor pattern ATV22 may have various known shapes.

[0145] In an embodiment, the second-first semiconductor pattern ATV21 and the second-second semiconductor pattern ATV22 may be asymmetric to each other. Fig. 9 As shown in , the second portion ATV21 - P2 of the second-first semiconductor pattern ATV21 and the second portion ATV22 - P2 of the second-second semiconductor pattern ATV22 may be asymmetric to each other.

[0146] In embodiments, the first portion ATV21 - P1 of the second-first semiconductor pattern ATV21 and the first portion ATV22 - P1 of the second-second semiconductor pattern ATV22 may be symmetrical to each other.

[0147] In an embodiment, the second-first semiconductor pattern ATV21 and the second-second semiconductor pattern ATV22 may be physically connected to each other. For example, at least a portion of the first portion ATV21-P1 of the second-first semiconductor pattern ATV21 may be physically connected to at least a portion of the first portion ATV22-P1 of the second-second semiconductor pattern ATV22.

[0148] refer to Fig.10 , the first data line pair DL1 (ie, the first sub-data line DL1B and the second sub-data line DL1G) may be disposed on the second-first semiconductor pattern ATV21 and the second-second semiconductor pattern ATV22.

[0149] The first sub data line DL1B may be electrically connected to the second portion ATV22 - P2 of the second-second semiconductor pattern ATV22. More specifically, the first sub data line DL1B may be electrically connected to the conductive region I22 of the second-second semiconductor pattern ATV22.

[0150] The second sub data line DL1G may be electrically connected to the second portion ATV21 - P2 of the second-first semiconductor pattern ATV21. More specifically, the second sub data line DL1G may be electrically connected to the conductive region I21 of the second-first semiconductor pattern ATV21.

[0151] refer to Fig.11 , the second-first semiconductor pattern ATV21 (see, for example, Fig.10 ) and a second-second semiconductor pattern ATV22 (see, for example, Fig.10 ) can be arranged on the buffer layer BUF. Fig.11 As shown in , the conductive region I21 of the second-first semiconductor pattern ATV21 may be disposed on the buffer layer BUF, and the conductive region I22 of the second-second semiconductor pattern ATV22 may be disposed on the buffer layer BUF.

[0152] The insulating layer array ILA may be disposed on the buffer layer BUF, and may cover the conductive region I21 of the second-first semiconductor pattern ATV21 and the conductive region I22 of the second-second semiconductor pattern ATV22.

[0153] The first sub-data line DL1B and the second sub-data line DL1G may be disposed on the insulating layer array ILA. In this case, the first sub-data line DL1B may be disposed to overlap at least a portion of the conductive region I22 of the second-second semiconductor pattern ATV22, and the second sub-data line DL1G may overlap at least a portion of the conductive region I21 of the second-first semiconductor pattern ATV21.

[0154] The first sub data line DL1B may be electrically connected to the conductive region I22 of the second-second semiconductor pattern ATV22.

[0155] For example, Fig.11 As shown in FIG. 1 , the first sub data line DL1B may be electrically connected to the second-second bridging electrode BR22, and the second-second bridging electrode BR22 may be electrically connected to the conductive region I22 of the second-second semiconductor pattern ATV22. In this case, the second-second bridging electrode BR22 may be electrically connected to the conductive region I22 of the second-second semiconductor pattern ATV22. Figure 3 ) and line layer LL (see Figure 3 ) is disposed between the first sub data line DL1B and the second-second semiconductor pattern ATV22.

[0156] and Fig.11 In some embodiments, the second-second bridging electrode BR22 may be omitted, and the first sub-data line DL1B may be electrically connected to the conductive region I22 of the second-second semiconductor pattern ATV22.

[0157] The second sub data line DL1G may be electrically connected to the conductive region I21 of the second-first semiconductor pattern ATV21.

[0158] For example, Fig.11 As shown in , the second sub data line DL1G may electrically contact the second-first bridging electrode BR21, and the second-first bridging electrode BR21 may electrically contact the conductive region I21 of the second-first semiconductor pattern ATV21. In this case, the second-first bridging electrode BR21 may be disposed between the second sub data line DL1G and the second-first semiconductor pattern ATV21 in the circuit layer CIR and the line layer LL.

[0159] In some embodiments, Fig.11 In some embodiments, the second-first bridge electrode BR21 may be omitted and the second sub-data line DL1G may electrically contact the conductive region I21 of the second-first semiconductor pattern ATV21 through two or more bridge electrodes.

[0160] exist Figure 8 , Fig. 9 , Fig.10 and Fig.11 In the description, only the second-first pixel circuit portion SP21, the second-second pixel circuit portion SP22, the first sub-data line DL1B and the second sub-data line DL1G are described. Figure 8 , Fig. 9 , Fig.10 and Fig.11 The description can be similarly applied to Figure 2 The second-third pixel circuit portion SP23, the second-fourth pixel circuit portion SP24, the third sub-data line DL2R, and the fourth sub-data line DL2G shown in FIG. That is, the second-third pixel circuit portion SP23, the second-fourth pixel circuit portion SP24, the third sub-data line DL2R, and the fourth sub-data line DL2G may have substantially the same structure as the second-first pixel circuit portion SP21, the second-second pixel circuit portion SP22, the first sub-data line DL1B, and the second sub-data line DL1G.

[0161] Fig.12 is a plan view for explaining a display device according to a second embodiment of the present disclosure.

[0162] refer to Fig.12 , the display device DDb according to the second embodiment of the present disclosure may include a display area DA and a peripheral area PA, and the first color light emitting part EB, the second color light emitting part EG, and the third color light emitting part ER may be disposed in the display area DA.

[0163] in this case, Fig.12 The display device DDb according to the second embodiment of the present disclosure shown in FIG. Figure 1 The display device DDa according to the first embodiment of the present disclosure is described to be substantially the same, and therefore, redundant descriptions of the elements will be omitted.

[0164] Fig.13 yes Fig.12 An enlarged plan view of Area B.

[0165] refer to Fig.13 And combined with Figure 1 , Figure 2 and Fig.12 , a plurality of pixel circuit parts SP, a first data line pair DL1, a second data line pair DL2, a first color light emitting part EB, a second color light emitting part EG, and a third color light emitting part ER may be disposed in the display area DA.

[0166] The plurality of pixel circuit portions SP may be connected to the reference Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11The described plurality of pixel circuit portions SP are substantially the same, and therefore, redundant descriptions of the elements will be omitted.

[0167] The first data line pair DL1 and the second data line pair DL2 may be connected to the reference Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 The first data line pair DL1 and the second data line pair DL2 are described as being substantially the same, and therefore, redundant descriptions of the elements will be omitted.

[0168] The first color light emitting portion EB and the second color light emitting portion EG may be aligned with the reference Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 The first color light emitting portion EB and the second color light emitting portion EG described are substantially the same, and therefore, redundant descriptions of the elements will be omitted.

[0169] The third color light emitting portion ER may include a first-third light emitting portion ER13 electrically connected to the first-third pixel circuit portion SP13, a second-fourth light emitting portion ER24 electrically connected to the second-fourth pixel circuit portion SP24, and a second-zeroth light emitting portion ER20 electrically connected to the first-third light emitting portion ER13. In this case, the first-third light emitting portion ER13 and the second-fourth light emitting portion EG24 may be substantially the same. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 The first to third light emitting part ER13, the second to fourth light emitting part EG24, and the second to zeroth light emitting part ER20 are described. Redundant description of the components will be omitted.

[0170] and Figure 2 The display device DDa according to the first embodiment of the present disclosure shown in FIG. Fig.13The second-zeroth light emitting portion ER20 in the display device DDb according to the second embodiment of the present disclosure shown in FIG. 1 is not connected to the second-zeroth dummy pixel circuit portion ( Figure 2 On the contrary, the second-zeroth light emitting part ER20 may be electrically connected to the first-third light emitting part ER13, and thus, the second-zeroth light emitting part ER20 may receive the same light emitting signal as that provided to the first-third light emitting part ER13.

[0171] More specifically, the second-zeroth light emitting portion ER20 may include a second-zeroth pixel electrode PXE20, and the first-third light emitting portion ER13 may include a first-third pixel electrode PXE13. In this case, the first-third pixel electrode PXE13 may be electrically connected to the first-third pixel circuit portion SP13. In addition, the first-third pixel electrode PXE13 may be electrically connected to the second-zeroth pixel electrode PXE20 through the connection electrode CNE. Therefore, the second-zeroth pixel electrode PXE20 may be electrically connected to the first-third pixel circuit portion SP13 through the first-third pixel electrode PXE13.

[0172] In an embodiment, the first to third pixel electrodes PXE13 , the connection electrode CNE, and the second to zeroth pixel electrodes PXE20 may be integrally formed.

[0173] In an embodiment, the connection electrode CNE may extend diagonally / obliquely to pass between the first-second light emitting part EG12 and the second-second light emitting part EB22. In this case, the connection electrode CNE may be electrically insulated from each of the first-second light emitting part EG12 and the second-second light emitting part EB22.

[0174] Therefore, in the display device DDb according to the second embodiment of the present disclosure, the dummy pixel circuit portion DSP and the dummy data line DL0 included in the display device DDa according to the first embodiment of the present disclosure may be omitted. In this case, even if the dummy pixel circuit portion DSP and the dummy data line DL0 are omitted, in the display device DDb according to the second embodiment of the present disclosure, the first color light emitting portion EB, the second color light emitting portion EG, and the third color light emitting portion ER may be displayed as Configure settings.

[0175] Fig.14 is a plan view for explaining a display device according to a third embodiment of the present disclosure.

[0176] refer to Fig.14, the display device DDc according to the third embodiment of the present disclosure may include a display area DA and a peripheral area PA, and the first color light emitting part EB, the second color light emitting part EG, and the third color light emitting part ER may be disposed in the display area DA.

[0177] Fig.14 The display device DDc according to the third embodiment of the present disclosure shown in FIG. Figure 1 The display device DDa according to the first embodiment of the present disclosure described is substantially the same. Any redundant description of the elements will be omitted.

[0178] Fig.15 is an equivalent circuit diagram showing one pixel.

[0179] refer to Fig.15 , the pixel PX may include a pixel circuit PC generating a driving current IOLED and a light emitting element LED electrically connected to the pixel circuit PC. Here, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor CST.

[0180] The light emitting element LED may emit light based on the driving current IOLED. The light emitting element LED may include a first terminal and a second terminal. For example, the second terminal of the light emitting element LED may receive a common voltage ELVSS.

[0181] The first transistor T1 may generate a driving current IOLED. In an embodiment, the first transistor T1 may be defined as a driving transistor for driving the pixel PX. The first transistor T1 may generate a driving current IOLED based on a voltage difference between a gate terminal and a source terminal of the first transistor T1.

[0182] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor T2 may receive the first scan signal GW. The first terminal of the second transistor T2 may receive the data voltage DATA. The second terminal of the second transistor T2 may be connected to the first terminal of the first transistor T1.

[0183] The third transistor T3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the third transistor T3 may receive the first scan signal GW. The first terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1. The second terminal of the third transistor T3 may be connected to the gate terminal of the first transistor T1.

[0184] The fourth transistor T4 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fourth transistor T4 may receive a data initialization signal GI. The first terminal of the fourth transistor T4 may receive an initialization voltage VINT. The second terminal of the fourth transistor may be connected to the second terminal of the third transistor T3.

[0185] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fifth transistor T5 may receive the light emission control signal EM. The first terminal of the fifth transistor T5 may receive the driving voltage ELVDD. The second terminal of the fifth transistor T5 may be connected to the first terminal of the first transistor T1.

[0186] The sixth transistor T6 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the sixth transistor T6 may receive the light emission control signal EM. The first terminal of the sixth transistor T6 may be connected to the second terminal of the first transistor T1. The second terminal of the sixth transistor T6 may be connected to the first terminal of the light emitting element LED.

[0187] The seventh transistor T7 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the seventh transistor T7 may receive the second scan signal GB. The first terminal of the seventh transistor T7 may receive the initialization voltage VINT. The second terminal of the seventh transistor T7 may be connected to the first terminal of the light emitting element LED.

[0188] The storage capacitor CST may include a first terminal and a second terminal. The first terminal of the storage capacitor CST may receive the driving voltage ELVDD. The second terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor T1.

[0189] Fig.15 The pixel circuit PC and the light emitting element LED correspond to Fig.14 as well as Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 and Fig. 27 The pixel circuit part SP' and the color light emitting parts EB, ER and EG are electrically connected to each other. That is, the extended line described later is not a component of the pixel circuit PC, but may be a line electrically connecting the pixel circuit PC and the light emitting element LED.

[0190] in addition, Fig.15 The pixel circuit PC and the light emitting element LED correspond to Figure 1 , Figure 2 , Fig.12 and Fig.13 The pixel circuit part SP and the color light emitting parts EB, ER and EG are electrically connected to each other.

[0191] However, reference Fig.15 , the pixel circuit PC has been described as including seven transistors and one storage capacitor, but the embodiments of the present disclosure are not limited thereto. For example, the pixel circuit PC may have a component including at least one transistor and at least one storage capacitor.

[0192] Fig.16 It is used to describe the settings Fig.14 A plan view of a pixel circuit portion and a sub-data line in a region C of FIG. The region C may be a display region DA (eg, see Fig.14 ) part.

[0193] refer to Fig.16 , a plurality of pixel circuit parts SP' may be disposed in the display area DA.

[0194] In an embodiment, a plurality of pixel circuit parts SP' may be arranged in a matrix form. For example, a plurality of pixel circuit parts SP' may include a first-first pixel circuit part SP11', a first-second pixel circuit part SP12', a first-third pixel circuit part SP13', a first-fourth pixel circuit part SP14', a first-fifth pixel circuit part SP15', a first-sixth pixel circuit part SP16', a first-seventh pixel circuit part SP17', a first-eighth pixel circuit part SP18', a second-first pixel circuit part SP21', a second-second pixel circuit part SP22', a second-third pixel circuit part SP23', a second-fourth pixel circuit part SP24', a second-fifth pixel circuit part SP25', a second-sixth pixel circuit part SP26', a second-seventh pixel circuit part SP27', and a second-eighth pixel circuit part SP28' in two rows and eight columns.

[0195] The first-first pixel circuit portion SP11', the first-second pixel circuit portion SP12', the first-third pixel circuit portion SP13', the first-fourth pixel circuit portion SP14', the first-fifth pixel circuit portion SP15', the first-sixth pixel circuit portion SP16', the first-seventh pixel circuit portion SP17' and the first-eighth pixel circuit portion SP18' may be arranged in a logical order along the first pixel row R1 in the row direction DR1. In this case, the first-first pixel circuit portion SP11', the first-second pixel circuit portion SP12', the first-third pixel circuit portion SP13', the first-fourth pixel circuit portion SP14', the first-fifth pixel circuit portion SP15', the first-sixth pixel circuit portion SP16', the first-seventh pixel circuit portion SP17' and the first-eighth pixel circuit portion SP18' may be referred to as the first pixel circuit portion SP1'.

[0196] The second-first pixel circuit portion SP21', the second-second pixel circuit portion SP22', the second-third pixel circuit portion SP23', the second-fourth pixel circuit portion SP24', the second-fifth pixel circuit portion SP25', the second-sixth pixel circuit portion SP26', the second-seventh pixel circuit portion SP27' and the second-eighth pixel circuit portion SP28' may be arranged in a logical order in the row direction DR1 along the second pixel row R2 adjacent to the first pixel row R1 in the column direction DR2. In this case, the second-first pixel circuit portion SP21', the second-second pixel circuit portion SP22', the second-third pixel circuit portion SP23', the second-fourth pixel circuit portion SP24', the second-fifth pixel circuit portion SP25', the second-sixth pixel circuit portion SP26', the second-seventh pixel circuit portion SP27' and the second-eighth pixel circuit portion SP28' may be referred to as the second pixel circuit portion SP2'.

[0197] The first-first pixel circuit portion SP11' and the second-first pixel circuit portion SP21' may be disposed in the first pixel column C1. The first-first pixel circuit portion SP11' and the second-first pixel circuit portion SP21' may be arranged in a logical order in the column direction DR2.

[0198] The first-second pixel circuit portion SP12' and the second-second pixel circuit portion SP22' may be disposed in the second pixel column C2. The second pixel column C2 may be adjacent to the first pixel column C1 in the row direction DR1. The first-second pixel circuit portion SP12' and the second-second pixel circuit portion SP22' may be arranged in a logical order in the column direction DR2.

[0199] The first-third pixel circuit portion SP13' and the second-third pixel circuit portion SP23' may be disposed in the third pixel column C3. The third pixel column C3 may be adjacent to the second pixel column C2 in the row direction DR1. The first-third pixel circuit portion SP13' and the second-third pixel circuit portion SP23' may be arranged in a logical order in the column direction DR2.

[0200] The first-fourth pixel circuit portion SP14' and the second-fourth pixel circuit portion SP24' may be disposed in the fourth pixel column C4. The fourth pixel column C4 may be adjacent to the third pixel column C3 in the row direction DR1. The first-fourth pixel circuit portion SP14' and the second-fourth pixel circuit portion SP24' may be arranged in a logical order in the column direction DR2.

[0201] The first-fifth pixel circuit portion SP15' and the second-fifth pixel circuit portion SP25' may be disposed in the fifth pixel column C5. The fifth pixel column C5 may be adjacent to the fourth pixel column C4 in the row direction DR1. The first-fifth pixel circuit portion SP15' and the second-fifth pixel circuit portion SP25' may be arranged in a logical order in the column direction DR2.

[0202] The first to sixth pixel circuit portions SP16' and the second to sixth pixel circuit portions SP26' may be disposed in the sixth pixel column C6. The sixth pixel column C6 may be adjacent to the fifth pixel column C5 in the row direction DR1. The first to sixth pixel circuit portions SP16' and the second to sixth pixel circuit portions SP26' may be arranged in a logical order in the column direction DR2.

[0203] The first to seventh pixel circuit portions SP17' and the second to seventh pixel circuit portions SP27' may be disposed in the seventh pixel column C7. The seventh pixel column C7 may be adjacent to the sixth pixel column C6 in the row direction DR1. The first to seventh pixel circuit portions SP17' and the second to seventh pixel circuit portions SP27' may be arranged in a logical order in the column direction DR2.

[0204] The first to eighth pixel circuit portions SP18' and the second to eighth pixel circuit portions SP28' may be disposed in the eighth pixel column C8. The eighth pixel column C8 may be adjacent to the seventh pixel column C7 in the row direction DR1. The first to eighth pixel circuit portions SP18' and the second to eighth pixel circuit portions SP28' may be arranged in a logical order in the column direction DR2.

[0205] The first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may be disposed on the plurality of pixel circuit parts SP′.

[0206] The first data line pair DL1' may include a first sub-data line DL1B' and a second sub-data line DL1G'. The second data line pair DL2' may include a third sub-data line DL2R' and a fourth sub-data line DL2G'. The third data line pair DL3' may include a fifth sub-data line DL3B' and a sixth sub-data line DL3G'. The fourth data line pair DL4' may include a seventh sub-data line DL4R' and an eighth sub-data line DL4G'.

[0207] The first sub data line DL1B' may be disposed in the first pixel column C1. Fig.16 In the embodiment of the present invention, the first sub data line DL1B' is disposed on a portion of the first pixel column C1 close to the second pixel column C2. The first sub data line DL1B' may be disposed on the first-first pixel circuit portion SP11' and the second-first pixel circuit portion SP21' in a plan view. The first sub data line DL1B' may extend in the column direction DR2.

[0208] The second sub data line DL1G' may be disposed in the second pixel column C2. Fig.16 In the embodiment of the present invention, the second sub data line DL1G' is disposed on a portion of the second pixel column C2 close to the first pixel column C1. The second sub data line DL1G' may be disposed on the first-second pixel circuit portion SP12' and the second-second pixel circuit portion SP22' in a plan view. The second sub data line DL1G' may extend in the column direction DR2.

[0209] The third sub-data line DL2R' may be disposed in the third pixel column C3. Fig.16 In the embodiment of the present invention, the third sub-data line DL2R' is disposed on a portion of the third pixel column C3 away from the second pixel column C2. That is, the third sub-data line DL2R' may be disposed on the first-third pixel circuit portion SP13' and the second-third pixel circuit portion SP23' in a plan view. The third sub-data line DL2R' may extend in the column direction DR2.

[0210] The fourth sub-data line DL2G' may be disposed in the fourth pixel column C4. Fig.16 In the embodiment of the present invention, the fourth sub-data line DL2G' is disposed on a portion of the fourth pixel column C4 close to the third pixel column C3. The fourth sub-data line DL2G' may be disposed on the first-fourth pixel circuit portion SP14' and the second-fourth pixel circuit portion SP24' in a plan view. The fourth sub-data line DL2G' may extend in the column direction DR2.

[0211] The fifth sub-data line DL3B' may be disposed in the fifth pixel column C5. Fig.16In the embodiment of the present invention, the fifth sub-data line DL3B' is disposed on a portion of the fifth pixel column C5 away from the fourth pixel column C4. The fifth sub-data line DL3B' may be disposed on the first-fifth pixel circuit portion SP15' and the second-fifth pixel circuit portion SP25' in a plan view. The fifth sub-data line DL3B' may extend in the column direction DR2.

[0212] The sixth sub-data line DL3G' may be disposed in the sixth pixel column C6. Fig.16 In the embodiment of the present invention, the sixth sub-data line DL3G' is disposed on a portion of the sixth pixel column C6 close to the fifth pixel column C5. The sixth sub-data line DL3G' may be disposed on the first-sixth pixel circuit portion SP16' and the second-sixth pixel circuit portion SP26' in a plan view. The sixth sub-data line DL3G' may extend in the column direction DR2.

[0213] The seventh sub-data line DL4R' may be disposed in the seventh pixel column C7. Fig.16 In the embodiment of the present invention, the seventh sub-data line DL4R' is disposed on a portion of the seventh pixel column C7 away from the sixth pixel column C6. The seventh sub-data line DL4R' may be disposed on the first-seventh pixel circuit portion SP17' and the second-seventh pixel circuit portion SP27' in a plan view. The seventh sub-data line DL4R' may extend in the column direction DR2.

[0214] The eighth sub-data line DL4G' may be disposed in the eighth pixel column C8. Fig.16 In the embodiment of the present invention, the eighth sub-data line DL4G' is disposed on a portion of the eighth pixel column C8 close to the seventh pixel column C7. The eighth sub-data line DL4G' may be disposed on the first-eighth pixel circuit portion SP18' and the second-eighth pixel circuit portion SP28' in a plan view. The eighth sub-data line DL4G' may extend in the column direction DR2.

[0215] The first sub data line DL1B' may be electrically connected to each of the first-first pixel circuit portion SP11' and the second-first pixel circuit portion SP21'. In an embodiment, a first color data voltage corresponding to a first color may be provided to the first sub data line DL1B'.

[0216] The second sub data line DL1G' may be electrically connected to each of the first-second pixel circuit portion SP12' and the second-second pixel circuit portion SP22'. In an embodiment, a second color data voltage corresponding to a second color may be provided to the second sub data line DL1G'.

[0217] The third sub data line DL2R' may be electrically connected to each of the first-third pixel circuit portion SP13' and the second-third pixel circuit portion SP23'. In an embodiment, a third color data voltage corresponding to a third color may be provided to the third sub data line DL2R'.

[0218] The fourth sub data line DL2G' may be electrically connected to each of the first-fourth pixel circuit portion SP14' and the second-fourth pixel circuit portion SP24'. In an embodiment, a second color data voltage corresponding to a second color may be provided to the fourth sub data line DL2G'.

[0219] The fifth sub data line DL3B' may be electrically connected to each of the first-fifth pixel circuit portion SP15' and the second-fifth pixel circuit portion SP25'. In an embodiment, a first color data voltage corresponding to a first color may be provided to the fifth sub data line DL3B'.

[0220] The sixth sub data line DL3G' may be electrically connected to each of the first-sixth pixel circuit portion SP16' and the second-sixth pixel circuit portion SP26'. In an embodiment, a second color data voltage corresponding to a second color may be provided to the sixth sub data line DL3G'.

[0221] The seventh sub data line DL4R' may be electrically connected to each of the first-seventh pixel circuit portion SP17' and the second-seventh pixel circuit portion SP27'. In an embodiment, a third color data voltage corresponding to a third color may be provided to the seventh sub data line DL4R'.

[0222] The eighth sub data line DL4G' may be electrically connected to each of the first-eighth pixel circuit portion SP18' and the second-eighth pixel circuit portion SP28'. In an embodiment, a second color data voltage corresponding to a second color may be provided to the eighth sub data line DL4G'.

[0223] Fig.16 The first-first pixel circuit portion SP11′, the first-second pixel circuit portion SP12′, the first sub-data line DL1B′ and the second sub-data line DL1G′ shown in FIG. Figure 4 , Figure 5 , Figure 6 and Figure 7 The described first-first pixel circuit portion SP11, the first-second pixel circuit portion SP12, the first sub-data line DL1B, and the second sub-data line DL1G are substantially the same.

[0224] In this case, the second-first pixel circuit portion SP21', the second-second pixel circuit portion SP22', the first sub data line DL1B' electrically connected to the second-first pixel circuit portion SP21', and the second sub data line DL1G' electrically connected to the second-second pixel circuit portion SP22' may have a structure substantially the same as that of the first-first pixel circuit portion SP11', the first-second pixel circuit portion SP12', the first sub data line DL1B' electrically connected to the first-first pixel circuit portion SP11', and the second sub data line DL1G' electrically connected to the first-second pixel circuit portion SP12'.

[0225] The structure of the first-first pixel circuit part SP11', the first-second pixel circuit part SP12', the second-first pixel circuit part SP21', the second-second pixel circuit part SP22', the first sub-data line DL1B' and the second sub-data line DL1G' can also be applied to the first-third pixel circuit part SP13', the first-fourth pixel circuit part SP14', the second-third pixel circuit part SP23', the second-fourth pixel circuit part SP24', the third sub-data line DL2R' and the fourth sub-data line DL2G'.

[0226] Similarly, the first-fifth pixel circuit portion SP15', the first-sixth pixel circuit portion SP16', the second-fifth pixel circuit portion SP25', the second-sixth pixel circuit portion SP26', the fifth sub-data line DL3B' and the sixth sub-data line DL3G' may have a structure substantially the same as the first-first pixel circuit portion SP11', the first-second pixel circuit portion SP12', the second-first pixel circuit portion SP21', the second-second pixel circuit portion SP22', the first sub-data line DL1B' and the second sub-data line DL1G'. Similarly, the first-seventh pixel circuit portion SP17', the first-eighth pixel circuit portion SP18', the second-seventh pixel circuit portion SP27', the second-eighth pixel circuit portion SP28', the seventh sub-data line DL4R' and the eighth sub-data line DL4G' can have a structure substantially the same as the first-first pixel circuit portion SP11', the first-second pixel circuit portion SP12', the second-first pixel circuit portion SP21', the second-second pixel circuit portion SP22', the first sub-data line DL1B' and the second sub-data line DL1G'.

[0227] Fig.17 It is used to describe the settings Fig.14 A plan view of the extension line of Area C.

[0228] refer to Fig.17, the plurality of extension lines ABR' may be disposed on the plurality of pixel circuit parts SP', the first data line pair DL1', the second data line pair DL2', the third data line pair DL3', and the fourth data line pair DL4'.

[0229] The plurality of extension lines ABR' may include a plurality of first extension lines ABR1' electrically connected one-to-one with the plurality of first pixel circuit parts SP1' and a plurality of second extension lines ABR2' electrically connected one-to-one with the plurality of second pixel circuit parts SP2'.

[0230] The plurality of first extension lines ABR1' may include first-first extension lines ABR11', first-second extension lines ABR12', first-third extension lines ABR13', first-fourth extension lines ABR14', first-fifth extension lines ABR15', first-sixth extension lines ABR16', first-seventh extension lines ABR17', first-eighth extension lines ABR18' and first-ninth extension lines ABR19'.

[0231] The first-first extension line ABR11' may be electrically connected to the first-first pixel circuit portion SP11'. For example, the first-first extension line ABR11' may be electrically connected to the first-first pixel circuit portion SP11' through a first contact hole (or a first through hole) CNT1.

[0232] Similarly, the first-second extension line ABR12' can be electrically connected to the first-second pixel circuit part SP12', the first-third extension line ABR13' can be electrically connected to the first-third pixel circuit part SP13', the first-fourth extension line ABR14' can be electrically connected to the first-fourth pixel circuit part SP14', the first-fifth extension line ABR15' can be electrically connected to the first-fifth pixel circuit part SP15', the first-sixth extension line ABR16' can be electrically connected to the first-sixth pixel circuit part SP16', the first-seventh extension line ABR17' can be electrically connected to the first-seventh pixel circuit part SP17', and the first-eighth extension line ABR18' can be electrically connected to the first-eighth pixel circuit part SP18'.

[0233] In this case, the first to ninth extension lines ABR19' may be electrically connected to the first to ninth pixel circuit parts not shown provided in the ninth pixel column and the first pixel row R1. In addition, the first to ninth extension lines ABR19' may have substantially the same planar shape as the first to fifth extension lines ABR15'.

[0234] The plurality of second extension lines ABR2' may include second-first extension lines ABR21', second-second extension lines ABR22', second-third extension lines ABR23', second-fourth extension lines ABR24', second-fifth extension lines ABR25', second-sixth extension lines ABR26', second-seventh extension lines ABR27', second-eighth extension lines ABR28' and second-eleventh extension lines ABR211'.

[0235] The second-first extension line ABR21' can be electrically connected to the second-first pixel circuit portion SP21', the second-second extension line ABR22' can be electrically connected to the second-second pixel circuit portion SP22', the second-third extension line ABR23' can be electrically connected to the second-third pixel circuit portion SP23', the second-fourth extension line ABR24' can be electrically connected to the second-fourth pixel circuit portion SP24', the second-fifth extension line ABR25' can be electrically connected to the second-fifth pixel circuit portion SP25', the second-sixth extension line ABR26' can be electrically connected to the second-sixth pixel circuit portion SP26', the second-seventh extension line ABR27' can be electrically connected to the second-seventh pixel circuit portion SP27', and the second-eighth extension line ABR28' can be electrically connected to the second-eighth pixel circuit portion SP28'.

[0236] In this case, the second to eleventh extension lines ABR211' may be electrically connected to the second to eleventh pixel circuit parts not shown disposed in the eleventh pixel column and the second pixel row R2. In addition, the second to eleventh extension lines ABR211' may have substantially the same planar shape as the second to seventh extension lines ABR27'.

[0237] In an embodiment, Fig.17 As shown in the figure, the second-first extension line ABR21' may overlap with each of the first sub-data line DL1B' and the second sub-data line DL1G' in a plan view, the second-third extension line ABR23' may overlap with each of the first sub-data line DL1B' and the second sub-data line DL1G' in a plan view, the second-fifth extension line ABR25' may overlap with each of the fifth sub-data line DL3B' and the sixth sub-data line DL3G' in a plan view, and the second-seventh extension line ABR27' may overlap with each of the fifth sub-data line DL3B' and the sixth sub-data line DL3G' in a plan view.

[0238] Fig.18 yes Fig.14 An enlarged plan view of Area C.

[0239] refer to Fig.17 and Fig.18 , Fig.14 The first color light emitting parts EB, the second color light emitting parts EG, and the third color light emitting parts ER shown in FIG. 1 may be disposed on the plurality of extension lines ABR′.

[0240] The first color emission part EB may include a first-first emission part EB11', a first-fifth emission part EB15', a first-ninth emission part EB19', a second-first emission part EB21', and a second-fifth light emitting part EB25'.

[0241] The first-first emission part EB11' may be electrically connected to the first-first extension line ABR11'. For example, the first-first emission part EB11' may include a pixel electrode PXE' (see Fig.19 ), and the pixel electrode PXE' can pass through the second contact hole (or second through hole) CNT2 (see Fig.19 ) is connected to the first-first extension line ABR11'.

[0242] Likewise, the first-fifth emission portion EB15' may be electrically connected to the first-fifth extension wire ABR15', the first-ninth emission portion EB19' may be electrically connected to the first-ninth extension wire ABR19', the second-first emission portion EB21' may be electrically connected to the second-first extension wire ABR21', and the second-fifth light emitting portion EB25' may be electrically connected to the second-fifth extension wire ABR25'.

[0243] The second color light emitting part EG may include a first-second light emitting part EG12', a first-fourth light emitting part EG14', a first-sixth light emitting part EG16', a first-eighth light emitting part EG18', a second-second light emitting part EG22', a second-fourth light emitting part EG24', a second-sixth light emitting part EG26' and a second-eighth light emitting part EG28'.

[0244] The first-second light-emitting part EG12' can be electrically connected to the first-second extension wire ABR12', the first-fourth light-emitting part EG14' can be electrically connected to the first-fourth extension wire ABR14', the first-sixth light-emitting part EG16' can be electrically connected to the first-sixth extension wire ABR16', the first-eighth light-emitting part EG18' can be electrically connected to the first-eighth extension wire ABR18', the second-second light-emitting part EG22' can be electrically connected to the second-second extension wire ABR22', the second-fourth light-emitting part EG24' can be electrically connected to the second-fourth extension wire ABR24', the second-sixth light-emitting part EG26' can be electrically connected to the second-sixth extension wire ABR26', and the second-eighth light-emitting part EG28' can be electrically connected to the second-eighth extension wire ABR28'.

[0245] The third color emission part ER may include a first-third emission part ER13', a first-seventh emission part ER17', a second-third emission part ER23', a second-seventh emission part ER27', and a second-eleventh light emitting part ER211'.

[0246] The first-third emitting portion ER13' may be electrically connected to the first-third extension wire ABR13', the first-seventh emitting portion ER17' may be electrically connected to the first-seventh extension wire ABR17', the second-third emitting portion ER23' may be electrically connected to the second-third extension wire ABR23', the second-seventh emitting portion ER27' may be electrically connected to the second-seventh extension wire ABR27', and the second-eleventh emitting portion ER211' may be electrically connected to the second-eleventh extension wire ABR211'.

[0247] like Fig.18 As shown in FIG. 1 , the first color light emitting part EB, the second color light emitting part EG and the third color light emitting part ER can be Configure settings.

[0248] That is, in the display device DDc according to the third embodiment of the present disclosure (see Fig.14 ), the plurality of pixel circuit parts SP' may be arranged in a matrix form, but the first color light emitting part EB, the second color light emitting part EG and the third color light emitting part ER electrically connected to the plurality of pixel circuit parts SP' may be arranged in a matrix form. Configure settings.

[0249] The display device DDc according to the third embodiment of the present disclosure may include a plurality of extension lines ABR'. In this case, at least one extension line among the plurality of extension lines ABR' may extend in the row direction DR1 and / or the column direction DR2, and one light emitting portion (e.g., the first-first emission portion EB11') may be electrically connected to a corresponding pixel circuit portion (e.g., the first-first extension line ABR11') through one extension line (e.g., the first-first extension line ABR11'). Therefore, a plurality of pixel circuit portions SP' arranged in a matrix form may be electrically connected to the plurality of pixel circuit portions arranged in a matrix form. The first color light emitting part EB, the second color light emitting part EG and the third color light emitting part ER are configured and arranged.

[0250] Fig.19 It is along Fig.18 A cross-sectional view taken along line V-V'.

[0251] refer to Fig.19 And combined with Fig.14 , Fig.17 and Fig.18, the display device DDc according to the third embodiment of the present disclosure may include a substrate SUB, a circuit layer CIR', a line layer LL', a first via insulating layer VIA1, a second-first extension line ABR21', a second via insulating layer VIA2, a pixel electrode PXE', a pixel defining layer PDL', a light emitting layer EL' and a common electrode layer CE'.

[0252] The substrate SUB may include glass or plastic, etc. In an embodiment, the substrate SUB may include a flexible material.

[0253] The circuit layer CIR' may be disposed on the substrate SUB. The circuit layer CIR' may include at least one transistor and may include a plurality of pixel circuit parts SP'. Fig.19 As shown in FIG. 1 , the circuit layer CIR′ may include a second-first pixel circuit portion SP21 ′ and a second-second pixel circuit portion SP22 ′.

[0254] The line layer LL' may be disposed on the circuit layer CIR'. The line layer LL' may include at least a data line. Fig.19 As shown in FIG, the line layer LL' may include a first sub-data line DL1B' and a second sub-data line DL1G'. Fig.19 Although not shown in the drawings, the line layer LL′ may include a second data line pair DL2′, a third data line pair DL3′, and a fourth data line pair DL4′.

[0255] The first via insulating layer VIA1 may be disposed on the line layer LL'. The first via insulating layer VIA1 may include an organic insulating material and / or an inorganic insulating material. An upper surface of the first via insulating layer VIA1 may be substantially flat.

[0256] A plurality of extension lines ABR' may be disposed on the first via insulating layer VIA1. Fig.19 As shown in FIG. 1 , the second-first extension wire ABR21′ may be disposed on the first via insulating layer VIA1. In this case, the second-first extension wire ABR21′ may be electrically connected to the second-first pixel circuit portion SP21′ through a first through hole CNT1 penetrating at least the first via insulating layer VIA1 and the line layer LL′.

[0257] The second via insulating layer VIA2 may be disposed on the first via insulating layer VIA1. The second via insulating layer VIA2 may include an organic insulating material and / or an inorganic insulating material. An upper surface of the second via insulating layer VIA2 may be substantially flat.

[0258] The pixel electrode PXE' may be disposed on the second via insulating layer VIA2. The pixel electrode PXE' may include a conductive material. The pixel electrode PXE' may be electrically connected to the second-first extension line ABR21' through a second through hole CNT2 penetrating the second via insulating layer VIA2. In an embodiment, the pixel electrode PXE' may be an anode electrode.

[0259] The pixel defining layer PDL' may be disposed on the second via insulating layer VIA2 and the pixel electrode PXE'. The pixel defining layer PDL' may define a pixel opening PXO' exposing at least a portion of the pixel electrode PXE'. The pixel defining layer PDL' may include an organic insulating material and / or an inorganic insulating material.

[0260] The light emitting layer EL' may be disposed on a portion of the pixel electrode PXE' exposed by the pixel opening PXO'. In an embodiment, the light emitting layer EL' may include an organic light emitting material.

[0261] The common electrode layer CE' may be disposed on the light emitting layer EL'. The common electrode layer CE' may include a conductive material. In an embodiment, the common electrode layer CE' may be a cathode electrode.

[0262] The pixel electrode PXE', the light emitting layer EL', and the common electrode layer CE' may define a second-first light emitting portion EB21'.

[0263] Reference again Fig.17 and Fig.19 , the second-first extension line ABR21' may overlap with each of the first sub-data line DL1B' and the second sub-data line DL1G' in a plan view. Therefore, a coupling effect CP1 may occur between the second-first extension line ABR21' and the first sub-data line DL1B', and a coupling effect CP2 may occur between the second-first extension line ABR21' and the second sub-data line DL1G'. That is, in an area where an extension line (e.g., the second-first extension line ABR21') and a sub-data line (e.g., the first sub-data line DL1B' or the second sub-data line DL1G') overlap in a plan view, the sub-data line may be affected by a coupling effect (e.g., coupling effect CP1 or coupling effect CP2).

[0264] In this case, if Fig.17 As shown in FIG. 1 , the first data line pair DL1 ′ may overlap the two extension lines ABR21 ′ and ABR23 ′ in a plan view, and the third data line pair DL3 ′ may overlap the two extension lines ABR25 ′ and ABR27 ′.

[0265] In contrast, each of the second data line pair DL2 ′ and the fourth data line pair DL4 ′ may not overlap with the plurality of extension lines ABR′ in a plan view.

[0266] Therefore, each of the first data line pair DL1' and the third data line pair DL3' may be affected by the coupling due to the overlap with the plurality of extension lines ABR', and each of the second data line pair DL2' and the fourth data line pair DL4' may not be affected by the coupling. In this way, when each data line pair has different coupling characteristics, the display device DDc (see Fig.14 ) may deteriorate in display quality.

[0267] Fig. 20 is a plan view for explaining a display device according to a fourth embodiment of the present disclosure.

[0268] refer to Fig. 20 , the display device DDd according to the fourth embodiment of the present disclosure may include a display area DA and a peripheral area PA, and the first color light emitting part EB, the second color light emitting part EG, and the third color light emitting part ER may be disposed in the display area DA.

[0269] in this case, Fig. 20 The display device DDd according to the fourth embodiment of the present disclosure shown in FIG. Figure 1 The display device DDa according to the first embodiment of the present disclosure is described to be substantially the same, and therefore, redundant descriptions of the elements will be omitted.

[0270] Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 and Fig. 27 It is used to describe the settings Fig. 20 1 and 2. Plan views of various embodiments of extension lines in area D of FIG. The area D may be a portion of the display area DA.

[0271] refer to Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 and Fig. 27 , with reference Fig.16 , Fig.17 and Fig.18 All components described above that are substantially the same as the components may be provided in region D. Therefore, reference to the above examples will be omitted. Fig.16 , Fig.17 and Fig.18 Description of the element that has been described.

[0272] In this case, with reference Fig.17 The multiple extension lines ABR' described are different, Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 and Fig. 27 The multiple extension lines ABR' shown in each of the references may include additional components to prevent each data line pair from having different coupling characteristics. Therefore, in the following, we will focus on the references Fig.17 Describe the difference in the content described Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 and Fig. 27 The multiple extension lines ABR' shown in .

[0273] refer to Fig.21 , Fig.21 is a plan view showing a plurality of extension lines ABR' according to the first embodiment.

[0274] In this case, with reference Fig.17 Unlike the described multiple extension lines ABR', the first to third extension lines ABR13' may further include dummy portions DP13', the first to fifth extension lines ABR15' may further include dummy portions DP15', the first to seventh extension lines ABR17' may further include dummy portions DP17', and the first to ninth extension lines ABR19' may further include dummy portions DP19'.

[0275] In this case, the dummy portion DP13' can be connected to the reference Fig.17 The first to third extension lines ABR13' described above are formed integrally, and the dummy portion DP15' may be formed with the reference Fig.17 The first to fifth extension lines ABR15' described above are formed integrally, and the dummy portion DP17' may be formed with the reference Fig.17 The first to seventh extension lines ABR17' described above are formed integrally, and the dummy portion DP19' may be formed with the reference Fig.17 The described first to ninth extension lines ABR19' are integrally formed.

[0276] The dummy portion DP13' of the first to third extension lines ABR13' may overlap with the second data line pair DL2' in a plan view, the dummy portion DP15' of the first to fifth extension lines ABR15' may overlap with the second data line pair DL2' in a plan view, the dummy portion DP17' of the first to seventh extension lines ABR17' may overlap with the fourth data line pair DL4' in a plan view, and the dummy portion DP19' of the first to ninth extension lines ABR19' may overlap with the fourth data line pair DL4' in a plan view.

[0277] Therefore, each of the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may overlap with the same number of extension lines ABR′ in a plan view.

[0278] That is, the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may be affected by substantially the same level of coupling, and thus display quality may be improved.

[0279] At the same time, as referenced Fig.14 , Fig.16 , Fig.17 and Fig.18 As described above, a plurality of pixel circuit parts SP' arranged in a matrix form can be electrically connected to the plurality of extension lines ABR'. The first color light emitting part EB, the second color light emitting part EG and the third color light emitting part ER are configured and arranged.

[0280] refer to Fig. 22 , Fig. 22 is a plan view showing a plurality of extension lines ABR' according to the second embodiment.

[0281] In this case, with reference Fig.17 Unlike the described multiple extension lines ABR', the first to fifth extension lines ABR15' may further include dummy portions DP15', the first to ninth extension lines ABR19' may further include dummy portions DP19', the second to third extension lines ABR23' may further include dummy portions DP23', and the second to seventh extension lines ABR27' may further include dummy portions DP27'.

[0282] In this case, the dummy portion DP15' can be connected to the reference Fig.17 The first to fifth extension lines ABR15' described above are formed integrally, and the dummy portion DP19' may be connected to the reference Fig.17 The first to ninth extension lines ABR19' described above are formed integrally, and the dummy portion DP23' may be connected to the reference Fig.17 The second-third extension line ABR23' described above is formed integrally, and the dummy portion DP27' may be formed with the reference Fig.17 The described second to seventh extension lines ABR27' are integrally formed.

[0283] The dummy portions DP15' of the first to fifth extension lines ABR15' may overlap with the second data line pair DL2' in a plan view, the dummy portions DP19' of the first to ninth extension lines ABR19' may overlap with the fourth data line pair DL4' in a plan view, the dummy portions DP23' of the second to third extension lines ABR23' may overlap with the second data line pair DL2' in a plan view, and the dummy portions DP27' of the second to seventh extension lines ABR27' may overlap with the fourth data line pair DL4' in a plan view.

[0284] Therefore, each of the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may overlap with the same number of extension lines ABR′ in a plan view.

[0285] That is, the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may be affected by substantially the same level of coupling, and thus display quality may be improved.

[0286] At the same time, as referenced Fig.14 , Fig.16 , Fig.17 and Fig.18 As described above, a plurality of pixel circuit parts SP' arranged in a matrix form can be electrically connected to the plurality of extension lines ABR'. The first color light emitting part EB, the second color light emitting part EG and the third color light emitting part ER are configured and arranged.

[0287] refer to Fig.23 , Fig.23 is a plan view showing a plurality of extension lines ABR' according to the third embodiment.

[0288] In this case, with reference Fig.17 Different from the multiple extension lines ABR' described above, the first to fifth extension lines ABR15' may further include a dummy portion DP15', the first to ninth extension lines ABR19' may further include a dummy portion DP19', and the second to fifth extension lines ABR25' may further include a dummy portion DP25'. In addition, Fig.17 The second to ninth extension lines not shown in the figure may further include a dummy portion DP29'. The second to ninth extension lines may be electrically connected to the second to ninth pixel circuit portions not shown and disposed in the ninth pixel column and the second pixel row R2. In addition, the second to ninth extension lines may have substantially the same planar shape as the second to fifth extension lines ABR25'.

[0289] In this case, the dummy portion DP15' can be connected to the reference Fig.17The first to fifth extension lines ABR15' described above are formed integrally, and the dummy portion DP19' may be connected to the reference Fig.17 The first to ninth extension lines ABR19' described above are integrally formed, and the dummy portion DP25' may be formed with the reference Fig.17 The described second to fifth extension lines ABR25' are integrally formed.

[0290] The dummy portion DP15' of the first to fifth extension lines ABR15' may overlap with the second data line pair DL2' in a plan view, the dummy portion DP19' of the first to ninth extension lines ABR19' may overlap with the fourth data line pair DL4' in a plan view, the dummy portion DP25' of the second to fifth extension lines ABR25' may overlap with the second data line pair DL2' in a plan view, and the dummy portion DP29' of the second to ninth extension lines may overlap with the fourth data line pair DL4' in a plan view.

[0291] Therefore, each of the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may overlap with the same number of extension lines ABR′ in a plan view.

[0292] That is, the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may be affected by substantially the same level of coupling, and thus display quality may be improved.

[0293] At the same time, as referenced Fig.14 , Fig.16 , Fig.17 and Fig.18 As described above, a plurality of pixel circuit parts SP' arranged in a matrix form can be electrically connected to the plurality of extension lines ABR'. The first color light emitting part EB, the second color light emitting part EG and the third color light emitting part ER are configured and arranged.

[0294] refer to Fig.24 , Fig.24 is a plan view showing a plurality of extension lines ABR' according to the fourth embodiment.

[0295] In this case, with reference Fig.17 Different from the multiple extension lines ABR' described above, the second to third extension lines ABR23' may further include a dummy portion DP23', the second to fifth extension lines ABR25' may further include a dummy portion DP25', and the second to seventh extension lines ABR27' may further include a dummy portion DP27'. In addition, Fig.17The second to ninth extension lines not shown in the figure may further include a dummy portion DP29'. The second to ninth extension lines may be electrically connected to the second to ninth pixel circuit portions not shown and disposed in the ninth pixel column and the second pixel row R2. In addition, the second to ninth extension lines may have substantially the same planar shape as the second to fifth extension lines ABR25'.

[0296] In this case, the dummy portion DP23' can be connected to the reference Fig.17 The second-third extension line ABR23' described above is formed integrally, and the dummy portion DP25' can be connected to the reference Fig.17 The second to fifth extension lines ABR25' described above are formed integrally, and the dummy portion DP27' may be formed with the reference Fig.17 The described second to seventh extension lines ABR27' are integrally formed.

[0297] The dummy portion DP23' of the second to third extension lines ABR23' may overlap with the second data line pair DL2' in a plan view, the dummy portion DP25' of the second to fifth extension lines ABR25' may overlap with the second data line pair DL2' in a plan view, the dummy portion DP27' of the second to seventh extension lines ABR27' may overlap with the fourth data line pair DL4' in a plan view, and the dummy portion DP29' of the second to ninth extension lines may overlap with the fourth data line pair DL4' in a plan view.

[0298] Therefore, each of the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may overlap with the same number of extension lines ABR′ in a plan view.

[0299] That is, the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may be affected by substantially the same level of coupling, and thus display quality may be improved.

[0300] At the same time, as referenced Fig.14 , Fig.16 , Fig.17 and Fig.18 As described above, a plurality of pixel circuit parts SP' arranged in a matrix form can be electrically connected to the plurality of extension lines ABR'. The first color light emitting part EB, the second color light emitting part EG and the third color light emitting part ER are configured and arranged.

[0301] refer to Fig.25 , Fig.25 is a plan view showing a plurality of extension lines ABR' according to the fifth embodiment.

[0302] In this case, with reference Fig.24 Compared to the multiple extension lines ABR' described according to the fourth embodiment, in the multiple extension lines ABR' according to the fifth embodiment, the first-first extension lines ABR11' may also include a dummy portion DP11', the first-third extension lines ABR13' may also include a dummy portion DP13', the first-fifth extension lines ABR15' may also include a dummy portion DP15', the first-seventh extension lines ABR17' may also include a dummy portion DP17', and the planar shape of the first-ninth extension lines ABR19' may be substantially the same as the planar shape of the first-fifth extension lines ABR15'.

[0303] In this case, the dummy part DP11' can be connected to the reference Fig.17 The first-first extension line ABR11' described above is formed integrally, and the dummy portion DP13' may be connected to the reference Fig.17 The first to third extension lines ABR13' described above are formed integrally, and the dummy portion DP15' may be formed with the reference Fig.17 The first to fifth extension lines ABR15' described above are formed integrally, and the dummy portion DP17' may be formed with the reference Fig.17 The described first to seventh extension lines ABR17' are integrally formed.

[0304] The dummy portion DP11' may overlap the first data line pair DL1' in plan view, the dummy portion DP13' may overlap the second data line pair DL2' in plan view, the dummy portion DP15' may overlap the third data line pair DL3' in plan view, and the dummy portion DP17' may overlap the fourth data line pair DL4' in plan view.

[0305] Therefore, each of the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may overlap with the same number of extension lines ABR′ in a plan view.

[0306] That is, the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may be affected by substantially the same level of coupling, and thus display quality may be improved.

[0307] At the same time, as referenced Fig.14 , Fig.16 , Fig.17 and Fig.18 As described above, a plurality of pixel circuit parts SP' arranged in a matrix form can be electrically connected to the plurality of extension lines ABR'. The first color light emitting part EB, the second color light emitting part EG and the third color light emitting part ER are configured and arranged.

[0308] refer to Fig.26 , Fig.26 is a plan view showing a plurality of extension lines ABR' according to the sixth embodiment.

[0309] In this case, with reference Fig.23 Compared to the multiple extension lines ABR' described according to the third embodiment, in the multiple extension lines ABR' according to the sixth embodiment, the first-first extension lines ABR11' may also include a dummy portion DP11', the first-third extension lines ABR13' may also include a dummy portion DP13', the first-fifth extension lines ABR15' may also include a dummy portion DP15", the first-seventh extension lines ABR17' may also include a dummy portion DP17', and the planar shape of the first-ninth extension lines ABR19' may be substantially the same as the planar shape of the first-fifth extension lines ABR15'.

[0310] In this case, the dummy part DP11' can be connected to the reference Fig.17 The first-first extension line ABR11' described above is formed integrally, and the dummy portion DP13' may be connected to the reference Fig.17 The first to third extension lines ABR13' described above are formed integrally, and the dummy portion DP15" may be connected to the reference Fig.17 The first to fifth extension lines ABR15' described above are formed integrally, and the dummy portion DP17' may be formed with the reference Fig.17 The described first to seventh extension lines ABR17' are integrally formed.

[0311] The dummy portion DP11' may overlap the first data line pair DL1' in plan view, the dummy portion DP13' may overlap the second data line pair DL2' in plan view, the dummy portion DP15" may overlap the third data line pair DL3' in plan view, and the dummy portion DP17' may overlap the fourth data line pair DL4' in plan view.

[0312] Therefore, each of the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may overlap with the same number of extension lines ABR′ in a plan view.

[0313] That is, the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may be affected by substantially the same level of coupling, and thus display quality may be improved.

[0314] At the same time, as referenced Fig.14 , Fig.16 , Fig.17 and Fig.18As described above, a plurality of pixel circuit parts SP' arranged in a matrix form can be electrically connected to the plurality of extension lines ABR'. The first color light emitting part EB, the second color light emitting part EG and the third color light emitting part ER are configured and arranged.

[0315] refer to Fig. 27 , Fig. 27 is a plan view showing a plurality of extension lines ABR' according to the seventh embodiment.

[0316] In this case, with reference Fig.26 Compared to the multiple extension lines ABR' described according to the sixth embodiment, in the multiple extension lines ABR' according to the seventh embodiment, the first to third extension lines ABR13' may also include a dummy portion DP13', the first to seventh extension lines ABR17' may also include a dummy portion DP17', the second to third extension lines ABR23' may also include a dummy portion DP23', and the second to seventh extension lines ABR27' may also include a dummy portion DP27'.

[0317] In this case, the dummy part DP13" can be connected with the reference Fig.17 The first to third extension lines ABR13' described above are formed integrally, and the dummy portion DP17" may be connected to the reference Fig.17 The first to seventh extension lines ABR17' described above are formed integrally, and the dummy portion DP23' may be connected to the reference Fig.17 The second-third extension line ABR23' described above is formed integrally, and the dummy portion DP27' may be formed with the reference Fig.17 The described second to seventh extension lines ABR27' are integrally formed.

[0318] The dummy portion DP13'' may overlap the first data line pair DL1' in plan view, the dummy portion DP17'' may overlap the third data line pair DL3' in plan view, the dummy portion DP23' may overlap the second data line pair DL2' in plan view, and the dummy portion DP27' may overlap the fourth data line pair DL4' in plan view.

[0319] Therefore, each of the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may overlap with the same number of extension lines ABR′ in a plan view.

[0320] That is, the first data line pair DL1 ′, the second data line pair DL2 ′, the third data line pair DL3 ′, and the fourth data line pair DL4 ′ may be affected by substantially the same level of coupling, and thus display quality may be improved.

[0321] At the same time, as referenced Fig.14 , Fig.16 , Fig.17 and Fig.18 As described above, a plurality of pixel circuit parts SP' arranged in a matrix form can be electrically connected to the plurality of extension lines ABR'. The first color light emitting part EB, the second color light emitting part EG and the third color light emitting part ER are configured and arranged.

[0322] Reference again Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 and Fig. 27 In each of the first, second, third, fourth, fifth, sixth and seventh embodiments, the first data line pair DL1', the second data line pair DL2', the third data line pair DL3' and the fourth data line pair DL4' may overlap with the same number of extension lines ABR' in a plan view.

[0323] For example, Fig.21 As shown in, in the extension line ABR' according to the first embodiment, each of the first data line pair DL1' and the third data line pair DL3' can overlap with two extension lines in the second pixel row R2 in a plan view, and each of the second data line pair DL2' and the fourth data line pair DL4' can overlap with two extension lines in the first pixel row R1 in a plan view.

[0324] In addition, if Fig. 22 and Fig.23 As shown in, in the extension line ABR' according to the second embodiment and the third embodiment, each of the first data line pair DL1' and the third data line pair DL3' can overlap with two extension lines in the second pixel row R2 in a plan view, and each of the second data line pair DL2' and the fourth data line pair DL4' can overlap with one extension line in the first pixel row R1 in a plan view, and overlap with one extension line in the second pixel row R2 in a plan view.

[0325] In addition, if Fig.24 As shown in, in the extension line ABR' according to the fourth embodiment, each of the first data line pair DL1' and the third data line pair DL3' can overlap with two extension lines in the second pixel row R2 in a plan view, and each of the second data line pair DL2' and the fourth data line pair DL4' can overlap with two extension lines in the second pixel row R2 in a plan view.

[0326] In addition, if Fig.25As shown in, in the extension line ABR' according to the fifth embodiment, each of the first data line pair DL1' and the third data line pair DL3' may overlap with one extension line in the first pixel row R1 in a plan view, and overlap with two extension lines in the second pixel row R2 in a plan view. Each of the second data line pair DL2' and the fourth data line pair DL4' may overlap with one extension line in the first pixel row R1 in a plan view, and overlap with two extension lines in the second pixel row R2 in a plan view.

[0327] In addition, if Fig.26 As shown in, in the extension line ABR' according to the sixth embodiment, each of the first data line pair DL1' and the third data line pair DL3' may overlap with one extension line in the first pixel row R1 in a plan view, and overlap with two extension lines in the second pixel row R2 in a plan view. Each of the second data line pair DL2' and the fourth data line pair DL4' may overlap with two extension lines in the first pixel row R1 in a plan view, and overlap with one extension line in the second pixel row R2 in a plan view.

[0328] In addition, if Fig. 27 As shown in, in the extension line ABR' according to the seventh embodiment, each of the first data line pair DL1' and the third data line pair DL3' may overlap with two extension lines in the first pixel row R1 in a plan view, and overlap with two extension lines in the second pixel row R2 in a plan view. Each of the second data line pair DL2' and the fourth data line pair DL4' may overlap with two extension lines in the first pixel row R1 in a plan view, and overlap with two extension lines in the second pixel row R2 in a plan view.

[0329] The present disclosure may be applied to display devices included in computers, smart tablets, smart phones, cars, and the like.

[0330] The foregoing is illustrative of the embodiments and is not to be construed as limiting thereof. Although several embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it will be understood that the foregoing is illustrative of various embodiments and is not to be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, in, The display device comprises: first - a first pixel circuit portion located in a first pixel row and a first pixel column; A first-second pixel circuit portion located in the first pixel row and the second pixel column; A second-first pixel circuit portion located in a second pixel row and in the first pixel column; a second-second pixel circuit portion located in the second pixel row and the second pixel column; a first sub data line overlapping the first-first pixel circuit portion and the second-first pixel circuit portion in a plan view and extending in a column direction; and a second sub data line overlapping the first-second pixel circuit portion and the second-second pixel circuit portion in the plan view and extending in the column direction, wherein each of the first-first pixel circuit portion and the second-second pixel circuit portion is electrically connected to the first sub-data line, and Each of the first-second pixel circuit portion and the second-first pixel circuit portion is electrically connected to the second sub data line.

2. The display device according to claim 1, in, The first-first pixel circuit portion and the first-second pixel circuit portion are symmetrical to each other, and The second-first pixel circuit portion and the second-second pixel circuit portion are asymmetric to each other.

3. The display device according to claim 1, in, The first-first pixel circuit portion includes a first-first semiconductor pattern, The first-second pixel circuit portion includes first-second semiconductor patterns, The second-first pixel circuit portion includes a second-first semiconductor pattern, The second-second pixel circuit portion includes a second-second semiconductor pattern, The first-first semiconductor pattern and the first-second semiconductor pattern are symmetrical to each other, and The second-first semiconductor pattern and the second-second semiconductor pattern are asymmetric to each other.

4. The display device according to claim 3, in, Each of the first-first semiconductor pattern and the second-second semiconductor pattern is electrically connected to the first sub data line, and Each of the first-second semiconductor pattern and the second-first semiconductor pattern is electrically connected to the second sub data line.

5. The display device according to claim 1, in, The display device further includes: A first to third pixel circuit portion, located in the first pixel row and the third pixel column; A first to fourth pixel circuit portion, located in the first pixel row and the fourth pixel column; a second-third pixel circuit portion located in the second pixel row and the third pixel column; A second to fourth pixel circuit portion, located in the second pixel row and the fourth pixel column; a third sub data line overlapping the first-third pixel circuit portion and the second-third pixel circuit portion in the plan view and extending in the column direction; and a fourth sub data line, overlapping the first to fourth pixel circuit portions and the second to fourth pixel circuit portions in the plan view and extending in the column direction, wherein each of the first to third pixel circuit portions and the second to fourth pixel circuit portions is electrically connected to the third sub data line, and Each of the first to fourth pixel circuit portions and the second to third pixel circuit portions is electrically connected to the fourth sub data line.

6. The display device according to claim 5, in, The display device further includes: a first-first light emitting portion electrically connected to the first-first pixel circuit portion and emitting light of a first color; a first-second light emitting portion electrically connected to the first-second pixel circuit portion and emitting light of a second color; first to third light emitting parts electrically connected to the first to third pixel circuit parts and emitting light of a third color; and First to fourth light emitting portions are electrically connected to the first to fourth pixel circuit portions and emit light of the second color.

7. The display device according to claim 6, in, The display device further includes: a second-first light emitting portion electrically connected to the second-first pixel circuit portion and emitting light of the second color; a second-second light emitting portion electrically connected to the second-second pixel circuit portion and emitting light of the first color; a second-third light emitting portion electrically connected to the second-third pixel circuit portion and emitting light of the second color; and The second to fourth light emitting parts are electrically connected to the second to fourth pixel circuit parts and emit light of the third color.

8. The display device according to claim 7, in, The first-first light emitting parts and the first-third light emitting parts are arranged in a row direction crossing the column direction, The first-second light emitting parts and the first-fourth light emitting parts are arranged in the row direction and are spaced apart from the first-first light emitting parts and the first-third light emitting parts in the column direction, The second-second light emitting parts and the second-fourth light emitting parts are arranged in the row direction and are spaced apart from the first-second light emitting parts and the first-fourth light emitting parts in the column direction, and The second-first light emitting portion and the second-third light emitting portion are arranged in the row direction and are spaced apart from the second-second light emitting portion and the second-fourth light emitting portion in the column direction.

9. The display device according to claim 8, in, The display device further includes: a first to zeroth dummy pixel circuit portion disposed in the first pixel row and a dummy pixel column adjacent to the first pixel column and spaced apart from the second pixel column; a second to zeroth dummy pixel circuit portion, arranged in the second pixel row and the dummy pixel column; a dummy data line overlapping the first-0th dummy pixel circuit portion and the second-0th dummy pixel circuit portion in the plan view, electrically connected to the second-0th dummy pixel circuit portion, and extending in the column direction; and The second to zeroth light emitting portion is electrically connected to the second to zeroth dummy pixel circuit portion.

10. The display device according to claim 9, in, The second-0th light emitting part, the second-second light emitting part and the second-fourth light emitting part are arranged in the row direction.

11. The display device according to claim 8, in, The display device further includes: second to zeroth light emitting parts electrically connected to the first to third pixel circuit parts through the first to third light emitting parts; and A connecting electrode electrically connects the anode electrodes of the first to third light emitting parts and the anode electrodes of the second to zeroth light emitting parts.

12. The display device according to claim 11, in, The second-0th light emitting part, the second-second light emitting part and the second-fourth light emitting part are arranged in the row direction.

13. A display device, in, The display device comprises: A plurality of first pixel circuit portions are arranged in a row direction along a first pixel row; A plurality of second pixel circuit parts are arranged along the second pixel row in the row direction; a plurality of sub data lines electrically connected to the plurality of first pixel circuit portions and the plurality of second pixel circuit portions and extending in a column direction crossing the row direction; a plurality of extension lines, including a plurality of first extension lines electrically connected to the plurality of first pixel circuit portions one-to-one and a plurality of second extension lines electrically connected to the plurality of second pixel circuit portions one-to-one; a plurality of first light emitting portions electrically connected to the plurality of first extension lines one by one; and a plurality of second light emitting portions, electrically connected to the plurality of second extension lines one by one, In which, the number of extended lines overlapping with the sub-data lines arranged in the Nth pixel column among the multiple sub-data lines in the plan view is the same as the number of extended lines overlapping with the sub-data lines arranged in the N+2th pixel column among the multiple sub-data lines in the plan view, wherein N=4M+1, and M is an integer equal to or greater than 0.

14. The display device according to claim 13, in, The extension line overlapping the sub-data line disposed in the N-th pixel column among the plurality of sub-data lines in the plan view also overlaps the sub-data line disposed in the N+1-th pixel column among the plurality of sub-data lines in the plan view.

15. The display device according to claim 13, in, The extension line overlapping the sub-data line disposed in the N+2 th pixel column among the plurality of sub-data lines in the plan view also overlaps the sub-data line disposed in the N+3 th pixel column among the plurality of sub-data lines in the plan view.

16. The display device according to claim 13, in, The sub data lines disposed in the N-th pixel column among the plurality of sub data lines overlap two second extension lines among the plurality of second extension lines in the plan view.

17. The display device according to claim 16, in, The sub data lines disposed in the (N+2)th pixel column among the plurality of sub data lines overlap two first extension lines among the plurality of first extension lines in the plan view.

18. The display device according to claim 16, in, The sub data lines disposed in the (N+2)th pixel column among the plurality of sub data lines overlap two second extension lines among the plurality of second extension lines in the plan view.

19. The display device according to claim 16, in, The sub data line disposed in the N+2 th pixel column among the plurality of sub data lines overlaps with one second extension line among the plurality of second extension lines and one first extension line among the plurality of first extension lines.

20. The display device according to claim 13, in, The sub data line disposed in the N-th pixel column among the plurality of sub data lines overlaps with two second extension lines among the plurality of second extension lines and one first extension line among the plurality of first extension lines.

21. The display device according to claim 20, in, The sub data line disposed in the N+2 th pixel column among the plurality of sub data lines overlaps with one first extension line among the plurality of first extension lines and two second extension lines among the plurality of second extension lines.

22. The display device according to claim 20, in, The sub data line disposed in the (N+2)th pixel column among the plurality of sub data lines overlaps with two first extension lines among the plurality of first extension lines and one second extension line among the plurality of second extension lines.

23. The display device according to claim 13, in, The sub data lines disposed in the N-th pixel column among the plurality of sub data lines overlap with two first extension lines among the plurality of first extension lines and two second extension lines among the plurality of second extension lines.

24. The display device according to claim 23, in, The sub data lines disposed in the N+2 th pixel column among the plurality of sub data lines overlap with two first extension lines among the plurality of first extension lines and two second extension lines among the plurality of second extension lines.

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