A voltage-stabilized power supply and electronic equipment

Abstract

The present application proposes a voltage-stabilized power supply and electronic equipment, wherein the voltage-stabilized power supply includes a driving tube, a first resistor, a second resistor, an error amplifying unit, a first feedback unit and a second feedback unit, wherein the error amplifying unit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube and a second PMOS tube, and a first terminal is led out between the second resistor and the second end of the driving tube as the output end of the voltage-stabilized power supply; the first end of the first feedback unit is connected between the second PMOS tube and the second NMOS tube, and the second end of the first feedback unit is connected to the gate of the third NMOS tube; the first end of the second feedback unit is connected to the first terminal, the second end of the second feedback unit is connected to the first PMOS tube and the second PMOS tube, and the third end of the second feedback unit is connected to the control end of the first feedback unit, which can improve the problem of poor load current response speed of the voltage-stabilized power supply without external capacitors.

Description

Technical Field

[0001] The present application relates to the field of power supplies, and in particular to a voltage-stabilized power supply and electronic equipment. Background Art

[0002] Low-dropout (LDO) voltage regulators (LDOs) are essential components of power management chips, offering low cost, low input voltage, high output voltage, and high drive capability. Traditional LDOs rely on large external capacitors for output regulation and loop stability, typically requiring hundreds of nanofarad to ultra-fine (µF) capacitors on the PCB. Since a complete power supply system may require the integration of more than ten voltage regulators, capacitor-free LDOs are gaining popularity and are more conducive to system integration. Capacitor-free LDOs eliminate the need for external ultra-fine capacitors when powering the chip internally or externally, effectively reducing peripheral component costs and PCB area.

[0003] Therefore, those skilled in the art continue to focus on how to implement LDO without external capacitors. Summary of the Invention

[0004] The purpose of this application is to provide a voltage-stabilized power supply and an electronic device to at least partially improve the above-mentioned problems.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0006] In a first aspect, an embodiment of the present application provides a regulated power supply, comprising a driving transistor, a first resistor, a second resistor, an error amplifying unit, a first feedback unit, and a second feedback unit, wherein the error amplifying unit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor;

[0007] A first end of the driving tube is connected to a first power supply, a second end of the driving tube is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the first resistor, the other end of the first resistor is grounded, and a first terminal is connected between the second resistor and the second end of the driving tube, the first terminal being the output end of the regulated power supply;

[0008] The source of the first PMOS transistor and the source of the second PMOS transistor are both connected to a first power supply, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the source of the first NMOS transistor and the source of the second NMOS transistor are both connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, the gate of the first NMOS transistor is used to access a reference voltage, the gate of the second NMOS transistor is connected between the first resistor and the second resistor, a second terminal is connected between the drain of the first PMOS transistor and the drain of the first NMOS transistor, and the second terminal is connected to the third end of the driving transistor;

[0009] The first end of the first feedback unit is connected between the drain of the second PMOS transistor and the drain of the second NMOS transistor, and the second end of the first feedback unit is connected to the gate of the third NMOS transistor;

[0010] The first end of the second feedback unit is connected to the first terminal, the second end of the second feedback unit is connected to the gate of the first PMOS tube and the gate of the second PMOS tube, and the third end of the second feedback unit is connected to the control end of the first feedback unit.

[0011] Optionally, the first feedback unit includes a third PMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a first capacitor;

[0012] The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, and a third terminal is connected between the source of the third PMOS transistor and one end of the first capacitor, and the third terminal serves as the first end of the first feedback unit;

[0013] The drain of the third PMOS transistor is connected to the other end of the first capacitor, the drain of the fifth NMOS transistor is connected to the drain of the third PMOS transistor, the source of the fifth NMOS transistor is grounded, and a fourth terminal is connected between the drain of the fifth NMOS transistor and the drain of the third PMOS transistor, and the fourth terminal serves as the second end of the first feedback unit;

[0014] The source of the fourth PMOS transistor is connected to the first power supply, the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor;

[0015] A fifth connection terminal is led out from the connection between the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor. The fifth connection terminal is the control end of the first feedback unit.

[0016] Optionally, the second feedback unit includes: a fifth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a third resistor and a second capacitor;

[0017] The gate of the sixth NMOS transistor is connected to the first end of the third resistor, the second end of the third resistor is connected to the gate of the seventh NMOS transistor, the first end of the second capacitor serves as the first end of the second feedback unit, the second end of the second capacitor is connected between the gate of the sixth NMOS transistor and the first end of the third resistor, a sixth terminal is extended between the gate of the sixth NMOS transistor and the first end of the third resistor, and the sixth terminal serves as the third end of the second feedback unit;

[0018] The source of the sixth NMOS transistor is grounded, the drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor, the source of the fifth PMOS transistor is connected to the first power supply, the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor, and the gate of the fifth PMOS transistor serves as the second end of the second feedback unit;

[0019] The source node of the seventh NMOS transistor and the drain of the seventh NMOS transistor are used to connect to the second current source, and the drain of the seventh NMOS transistor is connected between the gate of the seventh NMOS transistor and the third resistor.

[0020] Optionally, the second feedback unit further includes an eighth NMOS transistor, a first switch transistor and a low-power logic unit;

[0021] The gate of the eighth NMOS transistor is connected to the gate of the seventh NMOS transistor, the source of the eighth NMOS transistor is grounded, the drain of the eighth NMOS transistor is connected to the first end of the first switch transistor, the second end of the first switch transistor is connected to the drain of the seventh NMOS transistor, and the control end of the first switch transistor is connected to the low-power logic unit;

[0022] The low-power logic unit is used to send a trigger instruction to the first switch tube to switch the first switch tube to a closed state when the regulated power supply switches to a low-power mode.

[0023] Optionally, the second feedback unit further includes a power-on logic unit, a second switch tube, a third switch tube and a third capacitor;

[0024] One end of the third capacitor is connected to the second end of the second capacitor, and the other end of the third capacitor is grounded;

[0025] The first end of the second switch is connected to the second end of the second capacitor, the second end of the second switch is connected to the first end of the third resistor, the first end of the third switch is connected to one end of the third capacitor, and the second end of the third switch is connected to the other end of the third capacitor;

[0026] The control end of the second switch tube and the control end of the third switch tube are connected to the power-on logic unit.

[0027] Optionally, the power-on logic unit is used to control the second switch tube to be in an off state and the third switch tube to be in a closed state when the regulated power supply is powered on; and after the regulated power supply is powered on for a preset time length, the second switch tube is controlled to be in a closed state and the third switch tube is controlled to be in an off state.

[0028] Optionally, the error amplification unit further includes a fourth resistor and a fourth capacitor, one end of the fourth resistor is connected to the second end of the driving tube, the other end of the fourth resistor is connected to one end of the fourth capacitor, and the other end of the fourth capacitor is connected to the third end of the driving tube.

[0029] Optionally, the fourth resistor is a variable resistor and / or the fourth capacitor is a variable capacitor.

[0030] In a second aspect, an embodiment of the present application provides an electronic device comprising the above-mentioned voltage-stabilized power supply.

[0031] Optionally, the electronic device further includes a post-stage load circuit, and the post-stage load circuit is connected to the output end of the regulated power supply.

[0032] Compared to the prior art, the embodiments of the present application provide a voltage-stabilized power supply and electronic device, wherein the voltage-stabilized power supply includes a driving transistor, a first resistor, a second resistor, an error amplifying unit, a first feedback unit, and a second feedback unit, wherein the error amplifying unit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor; a first end of the driving transistor is connected to the first power supply, a second end of the driving transistor is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the first resistor, the other end of the first resistor is grounded, and a first terminal is connected between the second resistor and the second end of the driving transistor, the first terminal being the output end of the voltage-stabilized power supply; a first end of the first feedback unit is connected between the drain of the second PMOS transistor and the drain of the second NMOS transistor, a second end of the first feedback unit is connected to the gate of the third NMOS transistor; a first end of the second feedback unit is connected to the first terminal, a second end of the second feedback unit is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor, and a third end of the second feedback unit is connected to the control end of the first feedback unit. This can improve the problem of poor load current response speed of a voltage-stabilized power supply without external capacitors.

[0033] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 A schematic diagram of the structure of a voltage-stabilized power supply provided in an embodiment of the present application;

[0036] Figure 2 A schematic structural diagram of a first feedback unit provided in an embodiment of the present application;

[0037] Figure 3 A schematic structural diagram of a second feedback unit provided in an embodiment of the present application;

[0038] Figure 4 A schematic diagram of the transient characteristics of an LDO load current and output voltage provided in an embodiment of the present application.

[0039] In the figure: 101 - error amplification unit; 102 - first feedback unit; 103 - second feedback unit; 1031 - low power logic unit; 1032 - power-on logic unit. DETAILED DESCRIPTION

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0042] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0043] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0044] In the description of this application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0045] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0046] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0047] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the voltage-stabilized power supply provided by the embodiment of the present application, which has a fast response voltage-stabilized power supply circuit structure without external capacitors and bidirectional transient acceleration technology. Figure 1 As shown, the regulated power supply includes a driving transistor MP0, a first resistor R1, a second resistor R2, an error amplifying unit 101, a first feedback unit 102 and a second feedback unit 103. The error amplifying unit 101 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1 and a second PMOS transistor MP2.

[0048] A first end of the driving transistor MP0 is connected to a first power supply (VCC), a second end of the driving transistor MP0 is connected to one end of a second resistor R2, the other end of the second resistor R2 is connected to one end of a first resistor R1, the other end of the first resistor R1 is grounded, and a first terminal is extended between the second resistor R2 and the second end of the driving transistor MP0. The first terminal is the output end (Vout) of the voltage-regulated power supply.

[0049] The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are both connected to the first power supply, the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are both connected to the drain of the third NMOS transistor MN3, the source of the third NMOS transistor MN3 is grounded, the gate of the first NMOS transistor MN1 is used to connect to the reference voltage (VREF), the gate of the second NMOS transistor MN2 is connected between the first resistor R1 and the second resistor R2 (at VFB in the figure), and a second connection terminal (at Va in the figure) is extended between the drain of the first PMOS transistor MP1 and the drain of the first NMOS transistor MN1, and the second connection terminal is connected to the third end of the driving transistor MP0.

[0050] Optionally, the driving transistor MP0 is a PMOS transistor, the first end of the driving transistor MP0 is a source, the second end of the driving transistor MP0 is a drain, and the third end of the driving transistor MP0 is a gate.

[0051] A first end of the first feedback unit 102 is connected between the drain of the second PMOS transistor MP2 and the drain of the second NMOS transistor MN2 (at Vb in the figure), and a second end of the first feedback unit 102 is connected to the gate of the third NMOS transistor MN3 (at Vc in the figure).

[0052] A first end of the second feedback unit 103 is connected to the first connection terminal, a second end of the second feedback unit 103 is connected to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2, and a third end of the second feedback unit 103 is connected to the control end of the first feedback unit 102.

[0053] Optionally, the second feedback unit 103 is used to provide a driving signal to the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the control end of the first feedback unit 102. It can be understood that the second feedback unit 103 is a current source for the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the control end of the first feedback unit 102.

[0054] The second feedback unit 103 is further configured to adjust the driving signal when the output voltage Vout at the output terminal changes, so as to change the working states of the first feedback unit 102 and the error amplifying unit 101 , thereby responding to the change in the output voltage Vout.

[0055] The first feedback unit 102 is configured to transmit voltage changes at Vb to Vc when a fast output load response is required in the mid- to high-frequency band, thereby adjusting the current flowing through the third NMOS transistor MN3 and, in turn, the current (Ibias1) flowing through the first NMOS transistor MN1, thereby changing the pull-down capability of the gate voltage of the driver transistor MP0. The mid- to high-frequency band refers to 20-100 MHz.

[0056] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the first feedback unit provided in the embodiment of the present application. Figure 2 As shown, the first feedback unit 102 includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5 and a first capacitor Cf1.

[0057] The gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4. A third terminal is connected between the source of the third PMOS transistor MP3 and one end of the first capacitor Cf1. The third terminal serves as the first end of the first feedback unit 102 and is connected to Vb.

[0058] The drain of the third PMOS transistor MP3 is connected to the other end of the first capacitor Cf1. The drain of the fifth NMOS transistor MN5 is connected to the drain of the third PMOS transistor MP3. The source of the fifth NMOS transistor MN5 is grounded. A fourth terminal is extended between the drain of the fifth NMOS transistor MN5 and the drain of the third PMOS transistor MP3. The fourth terminal serves as the second end of the first feedback unit 102 and is connected to the gate of the third NMOS transistor MN3.

[0059] The source of the fourth PMOS transistor MP4 is connected to the first power supply, the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4, and the gate of the fourth PMOS transistor MP4 is connected to the drain of the fourth PMOS transistor MP4.

[0060] A fifth terminal is connected between the gate of the fourth NMOS transistor MN4 and the gate of the fifth NMOS transistor MN5 . The fifth terminal is the control terminal of the first feedback unit 102 and is used to connect to the third terminal of the second feedback unit 103 .

[0061] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of the second feedback unit provided in the embodiment of the present application. Figure 3 As shown, the second feedback unit 103 includes: a fifth PMOS transistor MP5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a third resistor R3 and a second capacitor Cf2.

[0062] The gate of the sixth NMOS transistor MN6 is connected to the first end of the third resistor R3. The second end of the third resistor R3 is connected to the gate of the seventh NMOS transistor MN7. The first end of the second capacitor Cf2 serves as the first end of the second feedback unit 103 and is connected to the first terminal (Vout). The second end of the second capacitor Cf2 is connected between the gate of the sixth NMOS transistor MN6 and the first end of the third resistor R3. A sixth terminal is extended between the gate of the sixth NMOS transistor MN6 and the first end of the third resistor R3. The sixth terminal serves as the third end of the second feedback unit 103 and is connected to the gates of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5.

[0063] The source of the sixth NMOS transistor MN6 is grounded, the drain of the sixth NMOS transistor MN6 is connected to the drain of the fifth PMOS transistor MP5, the source of the fifth PMOS transistor MP5 is connected to the first power supply, the gate of the fifth PMOS transistor MP5 is connected to the drain of the fifth PMOS transistor MP5, and the gate of the fifth PMOS transistor MP5 serves as the second end of the second feedback unit 103, and is connected to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2.

[0064] The source node and drain of the seventh NMOS transistor MN7 are connected to the second current source (eg, Ibias in the figure). The drain of the seventh NMOS transistor MN7 is connected between the gate of the seventh NMOS transistor MN7 and the third resistor R3.

[0065] Please continue to refer to Figure 3 The second feedback unit 103 further includes an eighth NMOS transistor MN8 , a first switch transistor Q1 and a low-power logic unit 1031 .

[0066] The gate of the eighth NMOS transistor MN8 is connected to the gate of the seventh NMOS transistor MN7, the source of the eighth NMOS transistor MN8 is grounded, the drain of the eighth NMOS transistor MN8 is connected to the first end of the first switch transistor Q1, the second end of the first switch transistor Q1 is connected to the drain of the seventh NMOS transistor MN7, and the control end of the first switch transistor Q1 is connected to the low-power logic unit 1031;

[0067] The low power logic unit 1031 is configured to send a trigger instruction to the first switch tube Q1 to switch the first switch tube Q1 to a closed state when the regulated power supply switches to the low power mode.

[0068] It should be understood that the low-power logic unit 1031 can receive instructions from the host computer (MCU or CPU) to determine whether the regulated power supply is switched to the low-power mode.

[0069] Please continue to refer to Figure 3 The second feedback unit 103 further includes a power-on logic unit 1032 , a second switch tube Q2 , a third switch tube Q3 and a third capacitor Cf3 .

[0070] One end of the third capacitor Cf3 is connected to the second end of the second capacitor Cf2 , and the other end of the third capacitor Cf3 is grounded.

[0071] A first end of the second switch tube Q2 is connected to the second end of the second capacitor Cf2, a second end of the second switch tube Q2 is connected to the first end of the third resistor R3, a first end of the third switch tube Q3 is connected to one end of the third capacitor Cf3, and a second end of the third switch tube Q3 is connected to the other end of the third capacitor Cf3.

[0072] The control end of the second switch tube Q2 and the control end of the third switch tube Q3 are connected to the power-on logic unit 1032 .

[0073] The power-on logic unit 1032 is used to control the second switch tube Q2 to be in the off state and the third switch tube Q3 to be in the on state when the regulated power supply is powered on. After the regulated power supply is powered on for a preset time length, the second switch tube Q2 is controlled to be in the on state and the third switch tube Q3 is controlled to be in the off state.

[0074] In a possible implementation, the error amplification unit 101 further includes a fourth resistor R4 and a fourth capacitor Cf4, one end of the fourth resistor R4 is connected to the second end of the driving tube MP0, the other end of the fourth resistor R4 is connected to one end of the fourth capacitor Cf4, and the other end of the fourth capacitor Cf4 is connected to the third end of the driving tube MP0.

[0075] Optionally, the fourth resistor R4 is a variable resistor and / or the fourth capacitor Cf4 is a variable capacitor.

[0076] The Miller compensation circuit composed of the fourth resistor R4 and the fourth capacitor Cf4 realizes the stability of the entire regulated power supply (LDO loop). The regulated power supply in this application is also referred to as LDO without external capacitors. The output pole (Va) of the error amplifier unit 101 of the LDO without external capacitors is the main pole, and the LDO output pole (Vout) is the secondary pole. When the LDO is unloaded, the distance between the LDO output pole and the main pole is the shortest, and the closed-loop stability is the worst. However, due to the introduction of Miller compensation, the output pole of the LDO without external capacitors is still the main pole. When the LDO is loaded, the distance between the LDO output pole and the output pole of the LDO without external capacitors is the farthest, and the closed-loop stability is the best at this time. Setting Miller compensation can easily make the loop stability greater than 70 degrees of phase margin.

[0077] Please refer to Figure 4 , Figure 4 Schematic diagram of transient characteristics of LDO load current and output voltage provided by an embodiment of the present application. Figure 4 As shown in the figure, the biggest challenge facing capacitor-less LDOs is the lack of output voltage-stabilizing capacitors. Limited bandwidth prevents the LDO from responding promptly to sudden changes in load current. When the load current or power supply changes instantaneously, the LDO output voltage drops and overshoots significantly, significantly impacting the performance of the entire system.

[0078] The fast output load response of the regulated power supply provided in this application to medium and high frequency bands is achieved through dynamic bias current technology. For example, when the output voltage Vout drops due to increased load current, the medium and high frequency variations in Vout are fed back through the feedback network to the gate voltage of the second NMOS transistor MN2. After amplification by the first-stage voltage amplifier (the second NMOS transistor MN2), the voltage Vb rises. Vb is then pre-transmitted to Vc via the feedforward capacitor (the first capacitor Cf1), causing the tail current I of the third NMOS transistor MN3 of the entire error amplifier unit 101 to increase. Because the reference voltage VREF remains unchanged while the gate voltage of the second NMOS transistor MN2 drops, the current flowing through the second NMOS transistor MN2 is lower than the current flowing through the first NMOS transistor MN1. Combined with the increase in the tail current of the third NMOS transistor MN3, the current flowing through the first NMOS transistor MN1 is ultimately doubled. This significantly enhances the pull-down capability Ibias1 of the gate voltage of the driver transistor MP0, rapidly reducing the voltage of the driver transistor MP0. This strengthens the output drive capability of the driver transistor MP0, thereby raising the output voltage Vout to its normal value. It should be understood that the output voltage reverse jump process is also valid and will not be described in detail here.

[0079] The dynamic bias current technology provided by the embodiments of this application does not consume the static power of the LDO. The LDO's bias current increases only when the load consumes high current, thus changing the pull-down current of the driver transistor's gate voltage and the bandwidth of the entire LDO loop. This technology significantly improves the output voltage Vout from transient drops caused by increased load current, significantly reducing the voltage amplitude of Vout transient undershoots.

[0080] The voltage-stabilized power supply provided in the present application also adopts a high-frequency bidirectional transient acceleration circuit. Specifically, when the output voltage Vout overshoots, the pull-up current Ibais2 of the gate voltage of the driving tube MP0 is enhanced, and the pull-down current Ibais1 of the gate voltage of the driving tube MP0 is reduced. Therefore, the gate voltage of the driving tube MP0 increases rapidly, so that the power supply of the driving tube MP0 to the load is reduced, and the output voltage quickly returns to a normal value. When the output voltage Vout drops, the pull-up current Ibais2 of the gate voltage of the driving tube MP0 decreases, and the pull-down current Ibais1 of the gate voltage of the driving tube MP0 increases. Therefore, the gate voltage of the PMOS driving tube decreases rapidly, so that the PMOS driving tube provides more current to the load, and the output voltage quickly rises to a normal value. Since the current signal transmission is faster than the voltage amplification, the high-frequency bidirectional transient acceleration technology has an obvious transient acceleration effect on the jitter of the output voltage. This technology does not rely on the voltage stabilizing effect of the output capacitor Cout, and does not require additional static power consumption.

[0081] The working principle of the pull-up current Ibias2 used to increase the gate voltage of the driver transistor MP0 in the bidirectional transient acceleration technology is to dynamically adjust the gate voltages of the first and second PMOS transistors MP1 and MP2 in the LDO error amplifier unit 101 by outputting the NMOS current mirror gate voltage Vbias after passing through the high-pass RC filter composed of the third resistor and the second capacitor Cf2 through the output Vout.

[0082] When the load decreases and the output voltage Vout overshoots, the positive jitter of the output voltage Vout is transmitted in advance to the gate voltage Vbias of the sixth NMOS transistor MN6 through the high-pass RC filter, causing the branch current of the sixth NMOS transistor MN6 to increase. The gate voltage of the first PMOS transistor MP1 and the second PMOS transistor MP2 is reduced through the PMOS current mirror, thereby dynamically increasing the gate voltage current of the first PMOS transistor MP1 and the second PMOS transistor MP2, thereby accelerating the pull-up current Ibias2 of the gate voltage of the driver transistor MP0.

[0083] The bidirectional transient acceleration technology, which increases the high-frequency dynamic pull-down current Ibias1 of the PMOS driver transistor's gate voltage, works as follows: When the load decreases and the output voltage Vout overshoots, the positive jitter of the output voltage Vout is simultaneously transmitted in advance through the feedback high-pass RC filter to the gate voltage Vbias of the fifth NMOS transistor MN5. This amplification causes the drain voltage of the fifth NMOS transistor MN5 to decrease, thereby reducing the tail current (I) of the third NMOS transistor MN3. Since the reference VREF voltage remains unchanged, the gate voltage of the second NMOS transistor MN2 increases with the output voltage Vout, increasing the current divided by the second NMOS transistor MN2. Combined with the reduction in the branch current of the third NMOS transistor MN3, the final result is that the current flowing through the first NMOS transistor MN1 is doubled, thereby reducing the pull-down current Ibais1 of the gate voltage of the driver transistor MP0.

[0084] The capacitor-free voltage-stabilized power supply provided by the present application utilizes high-frequency, bidirectional transient acceleration technology. When a high-speed change in load current causes an output voltage drop or overshoot, the bidirectional regulation increases the pull-up and pull-down currents on the PMOS driver gate voltage, allowing the PMOS driver gate voltage to respond more quickly, thus achieving a high-frequency, rapid response to the output voltage. This also applies to changes in the opposite direction of the output.

[0085] The fast-response, capacitor-free, voltage-regulated power supply provided by the present invention incorporates a transient acceleration loop enabling circuit designed to eliminate disturbances caused by the bidirectional transient acceleration circuit during the LDO power-up process. When the LDO enable signal arrives, the output voltage Vout is extremely low. This voltage is fed back through an RC high-pass filter to the gate voltage Vbias of the current mirrors corresponding to the sixth NMOS transistor MN6, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5. Consequently, the Vbias voltage is also very low, preventing the sixth NMOS transistor MN6, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 from turning on properly. This results in the tail current source third NMOS transistor MN3 and the load current mirror fifth PMOS transistor MP5 in the error amplifier unit 101 not operating at the correct point. The addition of the enabling circuit prevents the transient acceleration loop from turning on during the LDO power-up process. The specific principle is as follows: upon receipt of the LDO enable signal, the power-up logic unit 1032 (also known as the power-up counting circuit) charges a fixed capacitor with a small current, achieving a fixed delay of 50µs to 100µs. After ensuring that the LDO completes the power-on process, the power-on logic unit 1032 provides a bidirectional transient acceleration circuit enable signal TREN, which closes the second switch tube Q2 and opens the third switch tube Q3, enabling the feedback switch of the output RC high-pass filter, effectively eliminating the interference caused by the transient acceleration loop to the LDO main loop during the initial power-on period.

[0086] Another technology used in this application's capacitor-free, fast-response voltage-regulated power supply is to achieve both normal and low-power modes through a single loop. In low-power mode, the LDO's load current capability is reduced to one-twentieth of that in normal mode, eliminating the need for a separate low-power loop. This eliminates the jitter in the output voltage generated when switching between the two modes. Because the capacitor-free LDO output lacks large capacitors for voltage regulation, if two loops were used for both modes, the different loop gains would result in significant output voltage jitter during the transition between the two modes. The capacitor-free LDO's low-power mode reduces power consumption to one-tenth of that in normal mode. This feature is achieved by having the width-to-length ratios of the seventh and eighth NMOS transistors MN7 and MN8 of the IBIAS current mirror transistors differ by a preset multiple, for example, nine times. The seventh and sixth NMOS transistors MN7 and MN6 have the same width-to-length ratio. The low-power logic unit 1031 simply issues an ECOEN signal when low-power mode is enabled, closing the first switch Q1 and enabling the series switch of the eighth NMOS transistor MN8. This reduces the error amplifier power consumption by 90% in low-power mode.

[0087] In one possible embodiment, the capacitor-free, fast-response linear voltage regulator provided by this application achieves a full-corner load transition speed of 100ns, from no load to a full load of 20mA. The LDO output voltage has a transient overshoot of less than 200mV and an undershoot of less than 120mV. The load capacitance of the capacitor-free linear voltage regulator is equivalent to the digital circuit load capacitance, and the on-chip voltage regulator capacitor is 100pF.

[0088] An embodiment of the present application further provides an electronic device, comprising the above-mentioned voltage-stabilized power supply.

[0089] Optionally, the electronic device further includes a post-stage load circuit, which is connected to the output end of the voltage-stabilized power supply.

[0090] In summary, the embodiments of the present application provide a voltage-stabilized power supply and electronic device. The voltage-stabilized power supply includes a driver tube, a first resistor, a second resistor, an error amplification unit, a first feedback unit, and a second feedback unit. The error amplification unit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube, and a second PMOS tube. The first end of the driver tube is connected to the first power supply, the second end of the driver tube is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the first resistor, the other end of the first resistor is grounded, and a first terminal is connected between the second resistor and the second end of the driver tube. The first terminal is the output end of the voltage-stabilized power supply. The first end of the first feedback unit is connected between the drain of the second PMOS tube and the drain of the second NMOS tube, and the second end of the first feedback unit is connected to the gate of the third NMOS tube. The first end of the second feedback unit is connected to the first terminal, the second end of the second feedback unit is connected to the gate of the first PMOS tube and the gate of the second PMOS tube, and the third end of the second feedback unit is connected to the control end of the first feedback unit. The problem of poor load current response speed of a voltage-stabilized power supply without external capacitors can be improved.

[0091] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

[0092] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present application is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A voltage-stabilized power supply, characterized in that: The voltage-stabilized power supply includes a driving tube, a first resistor, a second resistor, an error amplifying unit, a first feedback unit, and a second feedback unit. The error amplifying unit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube, and a second PMOS tube. A first end of the driving tube is connected to a first power supply, a second end of the driving tube is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the first resistor, the other end of the first resistor is grounded, and a first terminal is connected between the second resistor and the second end of the driving tube, the first terminal being the output end of the regulated power supply; The source of the first PMOS transistor and the source of the second PMOS transistor are both connected to a first power supply, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the source of the first NMOS transistor and the source of the second NMOS transistor are both connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, the gate of the first NMOS transistor is used to access a reference voltage, the gate of the second NMOS transistor is connected between the first resistor and the second resistor, a second terminal is connected between the drain of the first PMOS transistor and the drain of the first NMOS transistor, and the second terminal is connected to the third end of the driving transistor; The first end of the first feedback unit is connected between the drain of the second PMOS transistor and the drain of the second NMOS transistor, and the second end of the first feedback unit is connected to the gate of the third NMOS transistor; The first end of the second feedback unit is connected to the first terminal, the second end of the second feedback unit is connected to the gate of the first PMOS tube and the gate of the second PMOS tube, and the third end of the second feedback unit is connected to the control end of the first feedback unit.

2. The voltage-stabilized power supply according to claim 1, wherein: The first feedback unit includes a third PMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a first capacitor; The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, and a third terminal is connected between the source of the third PMOS transistor and one end of the first capacitor, and the third terminal serves as the first end of the first feedback unit; The drain of the third PMOS transistor is connected to the other end of the first capacitor, the drain of the fifth NMOS transistor is connected to the drain of the third PMOS transistor, the source of the fifth NMOS transistor is grounded, and a fourth terminal is connected between the drain of the fifth NMOS transistor and the drain of the third PMOS transistor, and the fourth terminal serves as the second end of the first feedback unit; The source of the fourth PMOS transistor is connected to the first power supply, the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor; A fifth connection terminal is led out from the connection between the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor. The fifth connection terminal is the control end of the first feedback unit.

3. The voltage-stabilized power supply according to claim 1, wherein: The second feedback unit includes: a fifth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a third resistor and a second capacitor; The gate of the sixth NMOS transistor is connected to the first end of the third resistor, the second end of the third resistor is connected to the gate of the seventh NMOS transistor, the first end of the second capacitor serves as the first end of the second feedback unit, the second end of the second capacitor is connected between the gate of the sixth NMOS transistor and the first end of the third resistor, a sixth terminal is extended between the gate of the sixth NMOS transistor and the first end of the third resistor, and the sixth terminal serves as the third end of the second feedback unit; The source of the sixth NMOS transistor is grounded, the drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor, the source of the fifth PMOS transistor is connected to the first power supply, the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor, and the gate of the fifth PMOS transistor serves as the second end of the second feedback unit; The source of the seventh NMOS transistor is grounded, the drain of the seventh NMOS transistor is used to connect to the second current source, and the drain of the seventh NMOS transistor is connected between the gate of the seventh NMOS transistor and the third resistor.

4. The voltage-stabilized power supply according to claim 3, wherein: The second feedback unit further includes an eighth NMOS transistor, a first switch transistor and a low power logic unit; The gate of the eighth NMOS transistor is connected to the gate of the seventh NMOS transistor, the source of the eighth NMOS transistor is grounded, the drain of the eighth NMOS transistor is connected to the first end of the first switch transistor, the second end of the first switch transistor is connected to the drain of the seventh NMOS transistor, and the control end of the first switch transistor is connected to the low-power logic unit; The low-power logic unit is used to send a trigger instruction to the first switch tube to switch the first switch tube to a closed state when the regulated power supply switches to a low-power mode.

5. The voltage-stabilized power supply according to claim 3, wherein: The second feedback unit further includes a power-on logic unit, a second switch tube, a third switch tube and a third capacitor; One end of the third capacitor is connected to the second end of the second capacitor, and the other end of the third capacitor is grounded; The first end of the second switch is connected to the second end of the second capacitor, the second end of the second switch is connected to the first end of the third resistor, the first end of the third switch is connected to one end of the third capacitor, and the second end of the third switch is connected to the other end of the third capacitor; The control end of the second switch tube and the control end of the third switch tube are connected to the power-on logic unit.

6. The voltage-stabilized power supply according to claim 5, wherein: The power-on logic unit is used to control the second switch tube to be in an off state and the third switch tube to be in a closed state when the regulated power supply is powered on; and after the regulated power supply is powered on for a preset time length, the second switch tube is controlled to be in a closed state and the third switch tube is controlled to be in an off state.

7. The voltage-stabilized power supply according to claim 1, wherein: The error amplification unit further includes a fourth resistor and a fourth capacitor, one end of the fourth resistor is connected to the second end of the driving tube, the other end of the fourth resistor is connected to one end of the fourth capacitor, and the other end of the fourth capacitor is connected to the third end of the driving tube.

8. The voltage-stabilized power supply according to claim 7, wherein: The fourth resistor is a variable resistor and / or the fourth capacitor is a variable capacitor.

9. An electronic device, characterized in that: A voltage-stabilized power supply comprising any one of claims 1 to 8.

10. The electronic device according to claim 9, wherein The electronic device further includes a post-stage load circuit, which is connected to the output end of the regulated power supply.

Images