Adaptive DSP generation of read thresholds for solid state storage devices

Abstract

The present disclosure relates to adaptive DSP generation of read thresholds for a solid state storage device, which is at least one method, determines a level count difference based at least in part on an expected count of a plurality of cells in the solid state storage device and an observed count of the plurality of cells in the solid state storage device, wherein the observed count is obtained from a read performed on the solid state storage device using a previous read threshold. A next read threshold is determined based at least in part on the level count difference. A read is performed on the solid-state storage device using the next read threshold to obtain read data, and error correction decoding is performed on the read data.

Description

Background Art

[0001] In some types of solid-state storage devices (e.g., NAND flash memory devices), data is stored in a cell by incrementally injecting a predetermined amount of charge in the floating gate of a special type of transistor. After the memory cell is programmed (i.e., written), the floating gate gradually loses its charge over time (e.g., due to charge de-trapping and oxide leakage, more generally referred to as data retention noise). In some cases (e.g., solid-state storage devices, which have longer retention times, higher storage temperatures, and higher program / erase (PE) cycle counts, which exacerbate data retention noise), the number of errors in the read data may exceed the error correction capabilities of the code applied to the stored data. Selecting a better non-default / non-initial voltage threshold (sometimes referred to herein as a read threshold) for reading back data from a solid-state storage device can reduce the number of errors in the read data so that it is within the error correction capabilities of the code. However, prior art techniques for selecting or otherwise generating read thresholds assume an underlying Gaussian distribution (which is not always the case), have undesirably long delays, and / or have other unrealistic requirements or limitations. It would be desirable to have new techniques for selecting or otherwise generating better non-default / non-initial read thresholds that overcome these problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Various embodiments of the invention are disclosed in the following detailed description and accompanying drawings.

[0003] Figure 1 is a flow chart illustrating an embodiment of a process of reading back data from a solid-state storage device, including reading back data by determining a next read threshold.

[0004] Figure 2 is a diagram illustrating an embodiment of a distribution associated with state levels in a single-level cell (SLC) NAND flash memory device.

[0005] Figure 3 is a block diagram illustrating an embodiment of a solid-state storage device system with read thresholds generated using gradient descent and hard decision error correction decoding if required.

[0006] Figure 4 is a block diagram illustrating an embodiment of a solid-state storage device system with read thresholds generated using tracking aggregation and soft-decision error correction decoding if required.

[0007] Figure 5 is a diagram illustrating an embodiment of neighbor count differences used in tracking aggregation.

[0008] Figure 6is a flow chart illustrating an embodiment of a process of generating a read threshold using tracking aggregation and performing soft decision error correction decoding on read data. DETAILED DESCRIPTION

[0009] The present invention can be implemented in many ways, including as a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer-readable storage medium; and / or a processor, such as a processor configured to execute instructions stored on and / or provided by a memory coupled to the processor. In this specification, these implementations or any other form in which the present invention may take may be referred to as techniques. In general, the order of the steps of the disclosed process may be changed within the scope of the present invention. Unless otherwise stated, a component described as being configured to perform a task (such as a processor or memory) may be implemented as a general component that is temporarily configured to perform the task at a given time, or as a specific component manufactured to perform the task. As used herein, the term "processor" refers to one or more devices, circuits, and / or processing cores that are configured to process data (such as computer program instructions).

[0010] A detailed description of one or more embodiments of the present invention is provided below together with the accompanying drawings that illustrate the principles of the present invention. The present invention is described in conjunction with such embodiments, but the present invention is not limited to any embodiment. The scope of the present invention is limited only by the claims, and the present invention encompasses many alternatives, modifications and equivalents. Many specific details are set forth in the following description in order to provide a thorough understanding of the present invention. These details are provided for illustrative purposes, and the present invention can be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical materials known in the technical field related to the present invention have not been described in detail so that the present invention will not be unnecessarily obscured.

[0011] Various embodiments of techniques for determining a next read threshold to obtain or otherwise output decoded data are described herein. In some embodiments, the techniques include: determining a level count difference based at least in part on an expected count of cells in a solid-state storage device and an observed count of cells in the solid-state storage device, wherein the observed count is obtained from a read performed on the solid-state storage device using a previous read threshold; determining a next read threshold based at least in part on the level count difference; performing a read on the solid-state storage device using the next read threshold to obtain read data; and performing error correction decoding on the read data to obtain decoded data.

[0012] For example, at the beginning of the life of a solid-state storage device, (one or more) default read thresholds may be used to perform reads with good performance (e.g., relatively few errors in the read data that can be corrected by an error correction decoder). However, as the solid-state storage device ages, if data is stored for a relatively long time, the number of errors in the read data may increase due to wear on the memory cells (e.g., due to programming and erasing) and / or charge leakage. Determining a new non-default read threshold can return read data with fewer errors that the error correction decoder is able to correct. The following figures describe various embodiments of the technology.

[0013] Figure 1 is a flow chart illustrating an embodiment of a process for reading back data from a solid-state storage device, including reading back the data by determining a next read threshold. In some embodiments, the process is performed by a read controller when a default or previously used read threshold returns read data that fails error correction decoding and therefore cannot be passed up to an application that requested the data from the storage device. For example, when a solid-state storage device (e.g., a NAND flash storage device) is new and the data stored thereon has only been retained for a relatively short amount of time, the default or initial read threshold for reading the solid-state storage device may be sufficient to obtain read data with sufficiently few errors so that an error correction code (e.g., applied to the data prior to storage) can correct errors in the read data. However, as the solid-state storage device becomes older, more worn, and / or hotter, the default or initial read threshold may return read data with too many errors that the error correction code cannot correct. A better non-default and / or non-initial read threshold may be selected or generated that returns read data with fewer errors so that the error correction code can correct the errors, and the corrected data may be output or otherwise returned. In some embodiments, that Figure 1 Contexts and / or applications of the exemplary processes described in .

[0014] At 100, a level count difference (eg, D ) is determined based at least in part on an expected count of cells in a solid-state storage device and an observed count of cells in the solid-state storage device. i (t) ), where the observed count is obtained from using a previously read threshold (e.g., T i (t) ) obtained from a read performed on the solid-state storage device (e.g., a read at the tth iteration or count).

[0015] In some embodiments, the expected counts and / or observed counts used at step 100 are sums (e.g., expected sums, such as E(S)). i ), and / or cumulative observation counts, such as S i (t)) associated with the value. This may be desirable in embodiments where each cell stores two or more bits (i.e., b ≥ 2, such as a multi-level cell (MLC) memory device where b = 2, etc.) and multiple read thresholds are being determined. For example, with the (previous) read threshold T i (t) To perform a read will turn on or otherwise activate a state at or below the corresponding state level L i (most) cells, and using the cumulative count does not require a second read to distinguish cells at different state levels, and / or using the cumulative count permits multiple read thresholds to be determined or otherwise generated independently of each other.

[0016] At 102, a next read threshold is determined based at least in part on the level count difference. For example, this may include determining a direction of the next read threshold relative to a previous read threshold based at least in part on the level count difference, and (also) determining a magnitude of the next read threshold based at least in part on the level count difference. In one example (which will be described in more detail below), a next offset (e.g., ) to express or otherwise determine the next read threshold (e.g., T i (t+1) ):

[0017]

[0018] Where T i and Δ are fixed and / or predefined, and thus in such an embodiment, determining the next read threshold at step 102 includes determining the next offset (eg, ). (For the sake of clarity, and to explain the exemplary processes at least initially at a high level, the terms will be explained and described in more detail below.)

[0019] In one example described in more detail below, the (first) level count difference (e.g., D ) associated with the previous read at the tth iteration or count is used. i (t) ), and the (second) level count difference associated with the (t-1)th read (e.g., D i (t-1) ) to determine the next offset (for example, ):

[0020]

[0021] Among them, broadly speaking, is a positive value and corresponds to the amount to be offset from the previous offset (e.g. ) is the magnitude or value to add or subtract from the previous offset. Whether the magnitude is added or subtracted from the previous offset (and therefore whether the next offset is to the left or right of the previous offset) is determined by sign(D i (t) ) to decide, sign(D i (t) ) returns the previous offset D i (t) symbol.

[0022] It is noted that some types of solid-state storage devices store more than one bit per cell (i.e., b ≥ 2), and in such embodiments, determining the next read threshold (e.g., offset) at step 102 includes determining multiple read thresholds (e.g., offsets). For example, for a single-level cell (SLC) case where b=1, only a single next read threshold (e.g., T 0 (t+1) ), while for the multi-level (MLC) case where b=2, three next read thresholds (e.g., T 0 (t+1) 、T 1 (t+1) and T 2 (t+1) ). To more generally and / or formally express the next read threshold(s) T i (t+1) and the next offset(s) Step 102 may include determining T i (t+1) and / or where i = 0, ..., (2 b -2).

[0023] At 104, the next read threshold (eg, T i (t+1) )Perform a read on a solid-state storage device to obtain read data.

[0024] At 106, error correction decoding is performed on the read data. If the error correction decoding is successful (e.g., the errors contained in the read data are within the error correction capabilities of the decoder), the decoded data (e.g., output or generated at step 106) is passed up to the appropriate or requesting entity or block (e.g., the application that passed down the read instruction).

[0025] and Figure 1In contrast to the method described in , some other methods for finding the optimal read threshold perform several reads by shifting or scanning the read threshold in one direction (e.g., from right to left) and performing error correction decoding on each read data returned until the error correction decoding is successful. The recovered data is then compared to the read output to find the threshold that produces the lowest BER. However, this method requires performing error correction decoding, which significantly adds read latency and / or significantly degrades read throughput. In contrast, Figure 1 The exemplary process of can determine the next read threshold without having to perform error correction decoding, which is better for read latency and read throughput.

[0026] Some other methods for finding the optimal read threshold assume an underlying Gaussian distribution of voltage or charge levels for cells at various state levels. For example, one technique assumes a Gaussian distribution and uses progressive reads to estimate the mean and variance of the assumed Gaussian distribution, and then estimates or otherwise determines the optimal read threshold (e.g., the voltage at which adjacent assumed Gaussian distributions intersect each other) from the mean and variance. This assumption of a Gaussian distribution is not always a good assumption under which to generate the next or new read threshold. For example, if the data has been stored in a solid-state storage device for a long time (i.e., high retention time), the distribution is unlikely to be Gaussian-like. In addition, some of these techniques perform two reads at the very tail of the assumed Gaussian distribution (e.g., in order to achieve a tractable solution for mean and variance estimation), which can be problematic because the portion of the distribution that is considered to be the tail may not behave very much like the tail (e.g., because the distribution is not actually Gaussian and / or because of a small sample size).

[0027] Use specific examples to walk through Figure 1 The following figure shows a single-level cell (SLC) NAND flash example to illustrate how it can be performed. Figure 1 process (at least in some embodiments).

[0028] Figure 2 is a diagram illustrating an embodiment of a distribution associated with state levels in a single-level cell (SLC) NAND flash memory device. For simplicity and ease of explanation, an SLC example is shown in which the number of (information) bits (b) stored in each cell is 1 (i.e., b=1). Although this example shows an SLC example, the techniques described herein are not limited to SLC embodiments and can be extended to other types of memory devices (e.g., multi-level cell (MLC) memory devices in which b=2, triple-level cell (TLC) memory devices in which b=3, quad-level cell (QLC) memory devices in which b=4, etc.).

[0029] In this SLC example where b=1, there are two status levels: L 0 (e.g., cells written or programmed to hold a first lower amount of charge) and L 1 (e.g., a cell that is written or programmed to hold a second higher amount of charge). For example, a cell is written or otherwise programmed to be at a particular state level by incrementally injecting a predetermined amount of charge into the floating gate of a particular type of transistor. In general, if each cell stores b bits, the state level is {L i}, where i = 0, 1, ..., (2 b -1). The state levels correspond to different amounts or levels of charge stored, such that L 0 Corresponding to the smallest amount of charge, L 1 Corresponding to the ratio L 0 More charge, and so on (eg, assuming no noise, charge loss, etc.).

[0030] Even if the cells are programmed or written to be at the same state level, the cells with L retain slightly different amounts of charge. As such, the state levels are shown here as a distribution. For example, 0 The cells associated with the distributions (200 and 204) are all programmed to be in the first state level (ie, L 0 ), and with L 1 The cells associated with the distributions (202 and 206) are all programmed to be in the second state level (ie, L 1 ). Some other read threshold generation techniques assume a Gaussian distribution, in which case the state level distribution will be similar to the Gaussian L 0 Distribution (200) and Gaussian L 1 Distribution (202). In the real world (e.g., depending on data retention noise, data retention time, storage temperature, wear on the storage device (e.g., program / erase (PE) cycle count), etc.), the state level distribution may be noisy and / or non-Gaussian, such as a non-Gaussian L 0 Distribution (204) and non-Gaussian L 1 distribution (206). In some embodiments, the distribution starts out as a more Gaussian distribution (e.g., due to shorter data retention times and less worn cells with low program and erase counts) and decays to a non-Gaussian distribution (e.g., due to data retention times becoming longer and the cells becoming worn with larger program and erase counts).

[0031] Each (e.g., readback) status level is mapped or interpreted as a specific (e.g., payload) number, symbol, or value. 0 The status level is associated with or mapped to the value 1, and L 1A state level is associated with or mapped to the value 0. More generally, each state level L i Mapped to or corresponding to 0 to (2 b -1) range. Each value is related to L i The mapping between state levels (sometimes referred to as cell-level bit mapping) is typically vendor-specific and grayscale encoding is often used to minimize the number of bit errors due to the prevalence of crossover errors between adjacent state levels.

[0032] As used herein, a superscript (t) denotes a variable associated with the tth page read (eg, with respect to the read threshold generation technique). One such variable is the read threshold T 0 (0) (208), read threshold T 0 (0) (208) is associated with the read at iteration 0 (e.g., note that T 0 (0) superscript (0) in the , and its opening or otherwise activation has a value less than or equal to the read threshold T 0 (0) As such, at or below T 0 (0) The cell is read back as being in L 0 Status level (e.g., value 1), and has a value of 1 or L 0 The number or count of such units at the state level is l 0 (0) (212). With a value greater than T 0 (0) The other units of charge are l 1 (0) (214) to count. This means that when reading the threshold T 0 (0) (208) The non-Gaussian L on the right 0 The cells in the distribution (204) will be incorrectly read as 0 or L 1 status level, and at the reading threshold T 0 (0) (208) The non-Gaussian L on the left 1 The cells in the distribution (206) will be incorrectly read as 1 value or L 0 Status level.

[0033] In some embodiments, the one or more initial read thresholds are predefined values. For example, for a read at t=0, the read threshold(s) used at the 0th read (T i (0)) may be a read threshold and / or a recent estimate of an optimal read threshold from a previous read (e.g., the previous read that recently failed error correction decoding and thus triggered the read generation process). For the read at t=1, the read threshold(s) used (e.g., T i (1) ) is the read threshold (or thresholds) shifted to the left (eg, downward) by some predefined value (or values) from the read at t=0 (eg, T i (1) ←T i (0) - <predefined value>). The main effect of retention noise is to widen and shift the cell-level voltage distribution to the left (i.e., downward, since retention noise tends to be dominated by charge leakage rather than charge addition), and so shifting the read threshold at t=0 to the left by some amount may be a good estimate for that read threshold. In one example, a predefined (downward) shift σ is used i , that is, the i-th level from T i (0) to T i (1) The estimated standard deviation of the distribution of i It is the leading indicator of the tail distribution.

[0034] Returning to the observation count, use the read threshold T 0 (0) The reading of (208) produces an observation count of l 0 (0) (212), observation count l 0 (0) (212) is at the 0th read (for example, note that l 0 (0) The superscript (0) in the L 0 Status level (e.g., note l 0 (0) Similarly, the observation count l 1 (0) (214) is read as L at the 0th read 1 The number of cells at the state level. These observation counts include those from the read threshold T 0 (0) (208) The non-Gaussian L on the right 0 The cells in the distribution (204) and the read threshold T 0 (0) (208) The non-Gaussian L on the left 1 The read errors of the cells in the distribution (206). These counts (i.e., l 0 (0)and l 1 (0) )yes Figure 1 Example of observation counts at step 100 in . Using T 0 (0) The read of (208) also returns or otherwise permits the value l 1 (0) (214) because it is not turned on or read as a value of 1 (i.e., in L 0 state level) is read as having a value of 0 and / or has a value of 0 by elimination (i.e., in L 1 state level). More generally, l i (t) is obtained at the tth reading and is in (is read as being in) L i Observation counts for cells at the state level.

[0035] Return to the topic with the read threshold, without using an index (2 b -1) that turns on or otherwise activates cells at state levels up to and including the highest state level (i.e., it turns on or otherwise activates most, if not all, cells). Figure 2 In the SLC example, a single read threshold is sufficient to distinguish between the two state levels, and thus a read threshold T is not required. 1 (0) (e.g., it will read or otherwise turn on most, if not all, cells.) Similarly, for an MLC embodiment in which there are four state levels, only three read thresholds will be needed to distinguish between or otherwise read the four state levels, and the read thresholds T 3 (t) is unnecessary. Therefore, only b -2) The read thresholds for indices within the range are of interest: {T i (t)}, where i = 0, ..., (2 b -2).

[0036] When determining the next read threshold (e.g., Figure 1 The goal of step 102 in (210) is to determine a read threshold that is (closer) to the optimal read threshold (210). The optimal read threshold corresponds to two adjacent distributions (e.g., non-Gaussian L 0 and L 1 The voltage or charge level at which the distributions (204 and 206) cross each other, and the optimal read threshold is the read threshold that produces the smallest number of errors. As will be described in more detail below, Figure 1The process can be conceptually viewed as a gradient descent process that does not assume an underlying Gaussian distribution (an assumption that does not always hold) and does not require error correction decoding to be performed in order to generate the next read threshold (which is relatively time consuming and significantly adds to the overall read latency).

[0037] In this example, all read thresholds (such as the previous read threshold (e.g., T i (t) ) or the next read threshold (e.g., T i (t+1) )) is constrained to a value from a predefined or permitted set of values. For example, some solid-state systems have a fixed or predefined read threshold value that is associated with a particular state level and is referred to herein as a target (voltage) threshold value (T i ). These target thresholds cannot be changed or otherwise adjusted by the user and can be conceptually considered as default thresholds. If the user wants to use a value that is not equal to the corresponding target threshold (e.g., T i ) of the read threshold (e.g., T i (t) ), some solid-state storage devices permit reads using incremental offsets relative to a fixed target threshold. In some such embodiments, the read threshold (e.g., T i (t) ) is expressed as:

[0038]

[0039] Where T i is a (eg, fixed and / or predefined) target threshold, Δ is a (eg, fixed and / or predefined) minimum voltage increment supported by the solid-state storage device, and is a scalar parameter (eg, variable) referred to herein as a threshold offset. The currently described example has this configuration, and therefore attempts to find or otherwise determine the next threshold offset This is equivalent to determining the next read threshold (T i (t+1) As described above, with index (2 b -1) is not of interest, so {T i}, where i = 0, ..., (2 b –2), and where i = 0, ..., (2 b -2).

[0040] Back to Figure 1In addition to the observed number of cells, step 100 also uses the expected number of cells. In this example, the expected number of cells at each state level (sometimes referred to herein as the expected count) is the length of the read (data) (e.g., n) divided by the number of state levels (e.g., 2 b For example, if a word line in an SLC memory device is being read, then E(l 0 ) will be the length of the word line divided by 2, since there are only two state levels: L 0 and L 1 During the writing and / or encoding process, a scrambling process is (usually) performed on the data, which results in an even distribution of values ​​to be stored (e.g., an equal distribution or number of 0s and 1s to be stored for an SLC storage device). As a result, in many applications it is safe to assume that in an SLC storage device, half of the bits read back should be 1 values ​​(i.e., L 0 Status level), and half of the bits should be 0 value (i.e., L 1 Status level). E(l i ) is sometimes referred to herein as the expected count (e.g., i The expected value of the number of cells at the state level).

[0041] In describing how you can Figure 1 At step 100, the level count difference (eg, D i (t) and / or D in front i (t-1) ), it will be helpful to first define some other terms or variables. i (t) is referred to herein as the cumulative observation count, and is the number of states observed to be at (or read back to) up to and including state level L i The sum of the number of cells at the state level.

[0042] By definition:

[0043]

[0044] By definition, S 0 And therefore S 0 (t) is equal to 0, and l j (t) is the value at the t-th read and the j-th state level (e.g., L j ) associated with the observation count. We observe that the number of thresholds is 2 b -1, which correspond to S i , i=1、2、……、2 b -1. For Figure 2The SLC example shown in FIG. 1 , where b=2 and t=0, S 0 (0) = 0 and S 1 (0) = l 0 (0) The following table shows example cumulative observed counts for an MLC storage device where b=2 and there are four state levels.

[0045]

[0046] Table 1: Cumulative observation counts (S) of MLC storage devices i (t) ) example.

[0047] Note that each cumulative observation count in the table above corresponds to a cell that is turned on or activated (eg, observed) by a particular read threshold. i (t) Depends only on T i-1 (t) (For example, only T i-1 (t) For example, for S 1 (t) , with l 0 (t) The cells counted are all turned on and can be read using only the threshold T 0 (t) To count. For S 2 (t) , with l 0 (t) and l 1 (t) All the cells counted are turned on and can be read using only the threshold T 1 (t) to count, and so on. In some cases (e.g., for storage devices where b ≥ 2), it is possible to process the cumulative observation count instead of l i (t) Counting may be more convenient because a single read threshold (e.g., for a single state level) may be used to obtain the cumulative observed count from a single read. It may also be useful to eliminate dependencies on other read thresholds for other state levels, since those other read thresholds may (also) be in the process of being adjusted or otherwise refined to find the next better read threshold for those state levels, and it is desirable for the read threshold generation processes to be independent of each other.

[0048] Sum(E(S i The expected value of ) (sometimes referred to in this paper as the expected sum) is As described above, it is assumed that there is a scrambler in the write and / or encoding path to evenly distribute the values ​​stored and / or the state levels that the cells are in, and therefore the expected sum is assumed to be evenly distributed. The following table shows an example expected sum (E(S) for an MLC storage device: i )).

[0049]

[0050] Table 2: Expected sum of (E(S) for MLC storage devices i ))。

[0051] In the table above, n is the number of cells read or measured, and the scrambling is assumed to be (eg, perfectly) uniform. For example, if a word line is read, then n is equal to the length of the word line.

[0052] Level Count Difference D i (t) (For example, its Figure 1 is determined at step 100 in step 100) is defined as the cumulative observation count (S i (t) ) minus the expected sum (E(S i )):

[0053]

[0054] Assuming that the scrambler distributes the stored values ​​or state levels perfectly and evenly among the n cells, the following can be stated about the expected sum (E(S i )) and the associated standard deviation (σ 2 (S i )):

[0055]

[0056] σ 2 (S i )=ni2 -b (1-2 -b )

[0057] When the read offset is determined for t ≥ 2 , use the following:

[0058]

[0059] where {α (t)} is a positively damped sequence, such as This may be desirable in some applications, since without a positively damped sequence the iterations may oscillate.

[0060] As described above, the next threshold offset is determined (eg, ) is equivalent to (at least in this example) determining the next read threshold (e.g., T i (t+1) ),in In the above equation, sign(D i (t) )Return to D i (t) The sign of , and therefore determines whether the (t+1)th read offset (and correspondingly, the read threshold) is to the left or right of the tth read offset (and correspondingly, the read threshold). Specifies the next read offset Will be at the previous read offset In other words, determining the next read threshold includes: determining the next read threshold based at least in part on the level count difference (e.g., D i (t) ) and the second and older level count difference (e.g., D i (t-1) ) determines an offset for a next read threshold (e.g., relative to a previous read threshold), and determines whether to add or subtract the offset from the previous read threshold based at least in part on the sign of the level count difference. Generally speaking, this is like gradient descent, where the process attempts to follow the slope of the distribution downward.

[0061] It is noted that the exemplary technique described above for determining or otherwise generating the next read threshold does not assume an underlying Gaussian distribution, does not require lengthy error correction decoding, and does not require reading in a particular portion of the distribution (e.g., does not require reading in the tail). For these reasons, the exemplary technique may produce better results (e.g., because it does not assume a Gaussian distribution in situations where one does not exist), and / or may return results faster than some other techniques (e.g., because it does not perform error correction decoding, which may take a relatively long time).

[0062] Briefly return to Figure 1 In some embodiments, hard decision error correction decoding is performed at step 106. The following figure shows the execution Figure 1 An example block diagram of a solid-state storage device system of an exemplary process of the present invention, the exemplary process including hard decoding at step 106.

[0063] Figure 31 is a block diagram illustrating an embodiment of a solid-state storage device system having a read threshold generated using gradient descent and hard decision error correction decoding (if necessary). In this example, write data to be stored is passed to an error correction encoder (300), for example, from an application that wants to store data on a solid-state storage device, which is a NAND flash storage device (302) in this example. The encoder (300) applies an error correction code to the write data and performs scrambling (e.g., to evenly distribute the stored values ​​or cell state levels), and outputs the encoded and scrambled data, which is passed to a write controller (304). The write controller stores the encoded and scrambled data at a physical address in the NAND flash storage device and associates or otherwise maps the physical address with a logical address. The mapping information is stored in a memory (306) shared by and / or accessible to both the write controller (304) and the read controller (308).

[0064] To retrieve stored data (e.g., in response to a read request directed to a logical address), the read controller (308) accesses the shared memory (306) to determine the physical address associated with the logical address. In this example, the read controller will use one or more default, initial, and / or previous read thresholds (such as a target threshold (T i )) initially reads the NAND flash memory device (302) at the sought physical address. In this example, the read data (e.g., obtained using (one or more) default, initial, and / or previous read threshold values) has so many errors that the hard decision error correction decoder (310) is unable to correct the read data and therefore is unable to output corrected read data (e.g., to an application). For example, the NAND flash memory device (302) may be relatively old, have high program and erase counts, and / or data may have been stored in the NAND flash memory device for a relatively long time.

[0065] In response to a failure of the hard decision error correction decoder (310) to decode the read data, the read controller (308) uses Figure 1 The process for determining one or more new and / or non-default read thresholds (at least in this example) is as described above. Figure 1The process may use counts obtained from previous read thresholds attempted and / or by reading the solid-state storage device using various read thresholds, and this information may be stored in memory (306) and retrieved by the read controller (308) as needed / if required. Once the next read threshold(s) are determined, the read threshold(s) are used to read the appropriate physical address in the NAND flash storage device to obtain read data (e.g., with fewer errors and / or different error patterns that are correctable). The (new) read data is then passed to the hard decision error correction decoder (310) for another decoding attempt, and if the decoding is successful, the corrected read data is output (e.g., to the application that issued the read instruction or request). If unsuccessful, the attempt may be repeated (e.g., Figure 1 The process (e.g., until a predefined limit or maximum number of attempts is reached) stops. Figure 1 process).

[0066] In this example, the decoder (310) is a hard decision error correction decoder (sometimes referred to herein as a hard decoder), rather than a soft decision error correction decoder (sometimes referred to herein as a soft decoder). Although a soft decoder is able to decode some errors that a hard decoder is not able to decode, they tend to take longer. As such, in this example, a hard decoder is used (e.g., first). The following figure describes a similar system, where if hard decoding of read data obtained using the gradient descent technique described above continues to fail within some number of attempts, then a second technique (e.g., tracking aggregation) is used to determine a new and / or next read threshold, and soft decoding is performed on the read data.

[0067] Figure 4 is a block diagram illustrating an embodiment of a solid-state storage device system with read thresholds generated using tracking aggregation and soft-decision error correction decoding if required. Figure 4 Similar to Figure 3 , and for the sake of brevity, some blocks are not described in this article. Figure 3 As in the example of , the read controller (400) uses (one or more) default, initial and / or previous read thresholds (such as (one or more) target thresholds (T i )) to read the NAND flash memory device (402), and the read data is decoded using a hard decoder (404). If either the hard decoder (404) or the soft decoder (408) succeeds at any time, a multiplexer (406) selects the output from the successful decoder and outputs it as the corrected read data (e.g., to an application that issued a read instruction or read request).

[0068] If the hard decoder (404) fails to decode the read data obtained using (one or more) initial, default and / or previous read thresholds, the read controller (400) generates one or more new read thresholds using the gradient descent method as described above. As described in the above example, the (one or more) read thresholds at t=0 and t=1 are predefined, and the read data from those reads are not error corrected. Instead, the read data at t=0 and t=1 is used to generate the (one or more) next read thresholds according to the gradient descent example described above. However, hard decoding is performed on the read data obtained using the read thresholds (offsets) generated via the gradient descent technique described above. The (one or more) read thresholds generated by the gradient descent and the hard decoder are given a predefined and / or fixed number of attempts to successfully output the corrected read data, but in some other embodiments, different limits or maximum numbers of attempts are used.

[0069]

[0070]

[0071] Table 3: Figure 4 An example sequence of read threshold generation and error correction decoding combinations attempted by the system.

[0072] If the maximum number of attempts is reached, the read controller (400) switches to an aggregate tracking technique to generate the next read threshold(s) (e.g., expressed as offset(s)). To this end, the read controller (400) performs reads around the last read threshold(s) generated using gradient descent. More specifically, these reads are performed with increments Δ around the last read threshold (offset) generated by the gradient descent technique. Let (where i = 0, 1, 2, ..., (2 b -2)) is the latest read offset(s) generated using gradient descent, and nearby reads are performed along the following two sequences to the right and left of the latest read (threshold) offset(s), respectively:

[0073]

[0074]

[0075] where i = 0, 1, 2, ..., (2 b -2), Δ (as described above) is the minimum voltage increment supported by the solid-state storage device, and v 1 and v 2is a dynamically determined positive integer (this is described in more detail below). The read data from these reads is decoded by a hard decoder (404), and if the decoding is successful, the decoded data is output as the corrected read data, and the process ends.

[0076] In this example, the number of reads around the read threshold (offset(s)) generated by the last gradient descent (one or more) is not predefined, but is dynamically determined based on when a (stop) condition is met. In this example, the stop condition depends on c i (j) , c i (j) Is to use adjacent read offset and is read as on (i.e., in L i The difference between the number of cells at the state level or lower), where the case of j=0 is ignored. The following figure shows an example of adjacent count differences.

[0077] Figure 5 is a diagram illustrating an embodiment of adjacent count differences used in tracking aggregation. In this example, table 500 shows an increasing sequence of read offsets (e.g., ) is associated with adjacent count differences (c i (j) In this table, the top row (502) shows the voltages that are read as on (e.g., in L i The sequence of offsets increases in value, so the number of cells in the top row (502) will tend to (but not always) increase.

[0078] The bottom row (504) shows adjacent count differences between counts from adjacent read offsets in the top row (502). In this example, the predefined threshold (magnitude) is 200, and the first time the threshold is exceeded is for c i (4) =266, the c i (4) =266 and and Adjacent offsets are associated. Therefore, the reading process will be The read stops at the offset (at least in that direction).

[0079] Table 510 shows a decreasing sequence for read offsets (e.g., ). As before, the top row (512) shows the number of cells that were read as on for a given offset, and the bottom row (514) shows the adjacent count differences between adjacent offsets. In this case, the predefined threshold (amplitude) 200 is set earlier at c i (-3) = -216 is exceeded, the c i (-3) =-216 and and Adjacent read offsets are associated. Therefore, the read process will be The reading stops at the offset (at least in this direction). As described above, the case of j=0 is ignored.

[0080] Back to Figure 5 ,use Figure 5 Based on the exemplary adjacent difference count shown in , the following inverse weighted average is used in this aggregate tracking example to determine the next read threshold (offset):

[0081]

[0082] where (for example, in the second term) the minimum value is used is a trade-off for read noise, and is the last read offset (e.g., if this is the first iteration of trace aggregation, it is generated by the gradient descent process, or if this is the second or subsequent iteration of trace aggregation, it is the last offset generated by trace aggregation), Δ is the offset (e.g., the minimum voltage offset supported by the solid-state storage device system), and the range over which the summation is performed (e.g., from -v 2 to v 1 ) is determined by how far up and down the ascending and descending sequences are read. 0.5 is related to c i (j) The addition is to prevent precision overflow and make the minimum value of the second term at least is to make a tradeoff for read noise. The effect of the product of the two sums will depend on which difference count is smaller: the difference count associated with the ascending sequence to the right, or the difference count associated with the descending sequence to the left. Smaller difference counts carry more weight, while larger adjacent difference counts carry less weight (hence it is called an inverse weighted average). Intuitively or conceptually, the inverse weighted average attempts to insert more weight on reads that occur at valleys in the data distribution.

[0083] For example, if you use Figure 5 to find the next offset using the value shown in:

[0084]

[0085]

[0086]

[0087] Etc. As a practical matter, since Δ is the smallest voltage increment supported by the system, the next offset (or threshold) is rounded to the nearest integer multiple of Δ.

[0088] Returning briefly to Table 3, the read threshold(s) (offset(s)) generated using the tracking aggregation are (e.g., by Figure 4 The combination of tracking aggregation and soft decoding for generating read threshold(s) (offset(s)) may be repeated as many times as desired until the combination stops.

[0089] It should be noted that the sequences and combinations shown in the examples of Table 3 and other examples described herein are merely exemplary and are not intended to be limiting. In some other embodiments, different combination sequences, different combinations and / or different number of attempts may be used compared to the examples shown here. For example, soft decoding may be performed on the read data obtained using the read threshold generated using (one or more) gradient descents.

[0090] This example is more formally and / or generally described in the following flow chart.

[0091] Figure 6 is a flow chart illustrating an embodiment of a process of using tracking aggregation to generate a read threshold and perform soft decision error correction decoding on the read data (if necessary). In this example, Figure 6 continue Figure 1 (e.g., after some maximum number of attempts to generate new read threshold(s) at step 102, read at step 104, and perform error correction decoding at step 106 have been reached without success). In some embodiments, the decoding at step 106 includes and / or is limited to hard decision error correction decoding.

[0092] At 600, a plurality of reads are performed on a solid-state memory device in integer increments Δ to obtain a plurality of read data in increments Δ, where Δ is the minimum voltage increment supported by the solid-state memory device. Figure 5 500 in Table 500, and Figure 5 A read performed with a negative increment Δ (eg, to the left of the previously read threshold) in table 510 in FIG.

[0093] At 602, a second next read threshold is determined based at least in part on the inverse weighted average and the plurality of read data in increments Δ. Figure 5 In the example shown in FIG. , the adjacent difference count (c i (j) ), and those values ​​are then used for an inverse weighted average to determine the next read offset (threshold).

[0094] At 604, a read is performed on the solid-state storage device using the second next read threshold to obtain second read data. At 606, error correction decoding is performed on the second read data. For example, as shown in the example of Table 3, soft decoding can be performed on the read data, even though soft decoding tends to take longer than hard decoding. In this example, a new read threshold has been tried and subsequent error correction decoding has failed multiple times, and therefore it is acceptable (at least in some applications) to use a soft decoder, which may take longer, but is able to decode some errors that the hard decoder cannot decode.

[0095] Repeat as needed or if necessary Figure 6 The process shown in is continued until a timeout occurs or error correction decoding (either soft decoding or hard decoding) succeeds.

[0096] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways to implement the invention. The disclosed embodiments are illustrative rather than restrictive.

Claims

1. A system, include: a memory configured to store information associated with read threshold generation, including a second and earlier level count difference; and A read controller is coupled to the memory and is configured to: determining a level count difference based at least in part on (1) an expected count of a plurality of cells in the solid-state storage device and (2) an observed count of a plurality of cells in the solid-state storage device, wherein the observed count is associated with a number of cells in the solid-state storage device activated by performing a single read of the solid-state storage device using a previous read threshold; The method includes determining a next read threshold based at least in part on the level count difference by: determining a direction of a next read threshold relative to a previous read threshold based at least in part on the level count difference and independently of a second and earlier level count difference; and determining a magnitude of a next read threshold based at least in part on the level count difference and a second and earlier level count difference; performing a read on the solid-state storage device using a next read threshold to obtain read data, wherein error correction decoding is performed on the read data; performing a plurality of reads on the solid-state memory device in integer increments Δ to obtain a plurality of read data in increments Δ, wherein Δ is a minimum voltage increment supported by the solid-state memory device; determining a second next read threshold based at least in part on the plurality of read data in increments of Δ and the inverse weighted average; as well as A read is performed on the solid-state storage device using a second next read threshold to obtain second read data. 2 . The system of claim 1 , wherein determining the next read threshold is independent of an assumption that charge levels of the plurality of cells in the solid-state storage device have a Gaussian distribution.

3. The system of claim 1, further comprising a hard decision error correction decoder that performs hard decision error correction decoding on the read data. 4 . The system of claim 1 , further comprising a soft decision error correction decoder that performs soft decision error correction decoding on the read data.

5. The system according to claim 1, further comprising: include: a hard decision error correction decoder that performs hard decision error correction decoding on the read data; and A soft decision error correction decoder performs soft decision error correction decoding on the second read data.

6. The system according to claim 1, in: Each of the plurality of cells is configured to store at least two bits per cell; and Observation counts include cumulative observation counts, where: The accumulated observation count is associated with a plurality of cells in the solid-state storage device, the plurality of cells being read by using a previously read threshold activated by performing a single read on the solid-state storage device; The cumulative observation count is independent of other read thresholds; and Cumulative observation counts include: (1) with the 0th state level (L 0 ) The first number of cells associated and (2) with the first status level (L 1 ) associated with the second number of units 7. A method, include: storing in a memory information associated with read threshold generation, including a second and earlier level count difference; determining a level count difference based at least in part on (1) an expected count of a plurality of cells in the solid-state storage device and (2) an observed count of a plurality of cells in the solid-state storage device, wherein the observed count is associated with a number of cells in the solid-state storage device activated by performing a single read of the solid-state storage device using a previous read threshold; The method includes determining a next read threshold based at least in part on the level count difference by: determining a direction of a next read threshold relative to a previous read threshold based at least in part on the level count difference and independently of a second and earlier level count difference; and determining a magnitude of a next read threshold based at least in part on the level count difference and a second and earlier level count difference; performing a read on the solid-state storage device using a next read threshold to obtain read data, wherein error correction decoding is performed on the read data; The second next read threshold is determined by: performing a plurality of reads on the solid-state memory device in integer increments Δ to obtain a plurality of read data in increments Δ, wherein Δ is a minimum voltage increment supported by the solid-state memory device; as well as determining a second next read threshold based at least in part on the plurality of read data in increments of Δ and the inverse weighted average; as well as A read is performed on the solid-state storage device using a second next read threshold to obtain second read data. 8 . The method of claim 7 , wherein determining the next read threshold is independent of an assumption that the charge levels of the plurality of cells in the solid-state memory device have a Gaussian distribution.

9. The method of claim 7, further comprising performing hard decision error correction decoding on the read data using a hard decision error correction decoder.

10. The method of claim 7, further comprising performing soft decision error correction decoding on the read data using a soft decision error correction decoder.

11. The method according to claim 7, further comprising: include: performing hard decision error correction decoding on the read data using a hard decision error correction decoder; and Soft decision error correction decoding is performed on the second read data using a soft decision error correction decoder.

12. The method according to claim 7, in: Each of the plurality of cells is configured to store at least two bits per cell; and Observation counts include cumulative observation counts, where: The accumulated observation count is associated with a plurality of cells in the solid-state storage device, the plurality of cells being read by using a previously read threshold activated by performing a single read on the solid-state storage device; The cumulative observation count is independent of other read thresholds; and Cumulative observation counts include: (1) with the 0th state level (L 0 ) The first number of cells associated and (2) with the first status level (L 1 ) associated with the second number of units

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