Transmitting pulse generating circuit and transmitting pulse generating method

Abstract

The present invention discloses a transmission pulse generating circuit and a transmission pulse generating method, belonging to the field of display technology. The circuit includes: a clock signal input module, an inversion module, a first control module and a second control module; the clock signal input module outputs a first control signal based on a first clock signal, a second clock signal and a first transmission pulse; the inversion module outputs a second control signal based on a first transmission pulse and a third clock signal; the first control module outputs a third control signal based on the first control signal and the second control signal; the second control module outputs a second transmission pulse based on the second control signal and the third control signal; the first clock signal is opposite to the second clock signal in phase, and the phase of the third clock signal is used to adjust the pulse width of the second transmission pulse to an odd or even multiple of the line scanning time length. By adding a third clock signal to supplement the control, the pulse width can be adjusted to any multiple of the line scanning time length.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a transmission pulse generating circuit and a transmission pulse generating method. Background Art

[0002] In display panels using active-matrix organic light-emitting diodes (AMOLED) and the like, the generation of emission control EM signals is often based on two clock signals CLK and CLKB to delay the rising and falling edges of the EM signals. However, since the phases of CLK and CLKB are fixed, the pulse width of the EM signal in the circuit can only be an odd or even multiple of the row scanning time, and flexible adjustment cannot be achieved. Summary of the invention

[0003] The embodiments of the present application provide a transmission pulse generating circuit and a transmission pulse generating method to solve the technical problem of poor adjustability of pulse signal width.

[0004] According to one aspect of an embodiment of the present application, there is provided a transmission pulse generating circuit, comprising: a transmission pulse generating circuit, characterized in that the circuit comprises: a clock signal input module, an inverting module, a first control module and a second control module;

[0005] The first end of the clock signal input module is used to input a first clock signal, the second end of the clock signal input module is used to connect a first transmission pulse, the third end of the clock signal input module is used to input a second clock signal, and the fourth end of the clock signal input module is used to output a first control signal based on the first clock signal, the second clock signal and the first transmission pulse;

[0006] The first end of the inverting module is used to connect the first transmitting pulse, the second end of the inverting module is used to input the third clock signal, and the third end of the inverting module is used to output the second control signal based on the first transmitting pulse and the third clock signal;

[0007] The first end of the first control module is connected to the fourth end of the clock signal input module, the second end of the first control module is connected to the third end of the inversion module, and the third end of the first control module is used to output a third control signal based on the first control signal and the second control signal;

[0008] The first end of the second control module is connected to the third end of the inverting module, and the second end of the second control module is connected to the third end of the first control module; the third end of the second control module is used to output a second transmission pulse based on the second control signal and the third control signal;

[0009] Among them, the first transmitting pulse is a pulse in the previous stage of the second transmitting pulse; the first clock signal is opposite in phase to the second clock signal, and the phase of the third clock signal is used to adjust the pulse width of the second transmitting pulse to an odd or even multiple of the line scanning time length.

[0010] In a possible implementation, the clock signal input module includes a first transistor and a second transistor;

[0011] The gate of the second transistor serves as the first terminal of the clock signal input module; the gate of the first transistor serves as the second terminal of the clock signal input module; the first electrode of the first transistor serves as the third terminal of the clock signal input module; the second electrode of the first transistor is connected in parallel with the second electrode of the second transistor, serving as the fourth terminal of the clock signal input module;

[0012] The first electrode of the second transistor is used to connect to a high-level power supply line.

[0013] In a possible implementation manner, the first control module includes: a third transistor and a fourth transistor;

[0014] The gate of the fourth transistor serves as the first end of the first control module; the gate of the third transistor serves as the second end of the first control module and is connected to the third end of the inverting module; the second electrode of the third transistor is connected in parallel with the first electrode of the fourth transistor and serves as the third end of the first control module;

[0015] The first electrode of the third transistor is used to connect to a high-level power supply line, and the second electrode of the fourth transistor is used to connect to a low-level power supply line.

[0016] In a possible implementation manner, the second control module includes: a fifth transistor and a sixth transistor;

[0017] The gate of the fifth transistor is connected to the third end of the inverting module as the first end of the second control module; the gate of the sixth transistor is connected to the third end of the first control module as the second end of the second control module; the second electrode of the fifth transistor is connected in parallel with the first electrode of the sixth transistor as the third end of the second control module;

[0018] The first electrode of the fifth transistor is used to connect to a high-level power supply line, and the second electrode of the sixth transistor is used to connect to a low-level power supply line.

[0019] In a possible implementation, the inversion module includes: a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor;

[0020] The gate of the seventh transistor is connected in parallel with the gate of the ninth transistor to serve as the first end of the inverting module; the first electrode of the tenth transistor serves as the second end of the inverting module; the second electrode of the ninth transistor is connected in parallel with the second electrode of the tenth transistor to serve as the third end of the inverting module; the first electrode of the eighth transistor and the second electrode of the seventh transistor are connected to the gate of the tenth transistor;

[0021] The first electrode of the seventh transistor and the first electrode of the ninth transistor are used to connect to a high-level power supply line.

[0022] In a possible implementation, the circuit further includes: an eleventh transistor and a coupling capacitor;

[0023] The first electrode of the eleventh transistor is connected to the third end of the first control module through the coupling capacitor; the second electrode of the eleventh transistor is used to connect the third emission pulse, and the third emission pulse is a pulse in a later stage than the first emission pulse.

[0024] According to one aspect of an embodiment of the present application, a method for generating a transmission pulse is provided, which is applied to the transmission pulse generating circuit according to any one of the above aspects, and the method includes:

[0025] adjusting the phase of the third clock signal based on the pulse width required by the second transmit pulse;

[0026] Generate a second transmit pulse based on the first clock signal, the second clock signal, the third clock signal and the first transmit pulse in one generation cycle;

[0027] Among them, when the phase of the third clock signal is the same as the phase of the first clock signal, the pulse width of the second emission pulse is an odd multiple of the line scanning time length; when the phase of the third clock signal is the same as the phase of the second clock signal, the pulse width of the second emission pulse is an even multiple of the line scanning time length.

[0028] In a possible implementation, the generation cycle includes: a first stage, the duration of the first stage is a row scan duration;

[0029] In the first stage, the first clock signal is at a high level, the second clock signal is at a low level, the first emission pulse is at a predetermined low level, and the levels of the third control signal and the second emission pulse are reduced to a predetermined threshold.

[0030] In a possible implementation, after the first stage, the generation cycle further includes: a second stage; when the phase of the third clock signal is the same as the phase of the first clock signal, the duration of the second stage is three line scan durations; when the phase of the third clock signal is the same as the phase of the second clock signal, the duration of the second stage is two line scan durations;

[0031] In the second stage, the third control signal is discharged to a predetermined low level based on the low level of the third emission pulse, so that the level of the second emission pulse is reduced to the predetermined low level.

[0032] In a possible implementation, after the second stage, the generation cycle further includes: a third stage and a fourth stage, the duration of the third stage is one row scan duration, and the duration of the fourth stage is one row scan duration;

[0033] In the third stage, the level of the first transmitting pulse rises to a predetermined high level, and the third control signal is maintained at a predetermined low level, so that the second transmitting pulse is maintained at a predetermined low level;

[0034] In the fourth stage, the level of the third control signal rises to a predetermined high level, and the level of the second emission pulse rises to a predetermined high level.

[0035] The embodiment of the present application proposes a transmission pulse generation circuit and a transmission pulse generation method, the circuit comprising: a clock signal input module, an inversion module, a first control module and a second control module; the first end of the clock signal input module is used to input a first clock signal, the second end of the clock signal input module is used to connect a first transmission pulse, the third end of the clock signal input module is used to input a second clock signal, and the fourth end of the clock signal input module is used to output a first control signal based on the first clock signal, the second clock signal and the first transmission pulse; the first end of the inversion module is used to connect the first transmission pulse, the second end of the inversion module is used to input a third clock signal, and the third end of the inversion module is used to output a second control signal based on the first transmission pulse and the third clock signal; the first end of the first control module The first end of the first control module is connected to the fourth end of the clock signal input module, the second end of the first control module is connected to the third end of the inverting module, and the third end of the first control module is used to output a third control signal based on the first control signal and the second control signal; the first end of the second control module is connected to the third end of the inverting module, and the second end of the second control module is connected to the third end of the first control module; the third end of the second control module is used to output a second transmission pulse based on the second control signal and the third control signal; wherein the first transmission pulse is a pulse in the previous stage of the second transmission pulse; the first clock signal is opposite to the second clock signal in phase, and the phase of the third clock signal is used to adjust the pulse width of the second transmission pulse to an odd or even multiple of the row scanning time length. In this way, in the generation circuit based on the starting signal, i.e., the first transmitting pulse and two clock signals, a third clock signal supplementary control is added. Based on the phase adjustment of the third clock signal, it is possible to make up for the defect that the first clock signal and the second clock signal with opposite phases can only make the pulse width cover one of the odd or even multiples of the row scanning time length, thereby achieving the pulse width covering any multiples of the row scanning time length. By adjusting the phase of the third clock signal according to the required width, fine control and flexible adjustment of the pulse can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0037] Figure 1 It is a structural schematic diagram of a transmission pulse generating circuit provided in an embodiment of the present application;

[0038] Figure 2 It is a structural schematic diagram of a transmission pulse generating circuit provided in an embodiment of the present application;

[0039] Figure 3 It is a structural schematic diagram of a transmission pulse generating circuit provided in an embodiment of the present application;

[0040] Figure 4 It is a structural schematic diagram of a transmission pulse generating circuit provided in an embodiment of the present application;

[0041] Figure 5 It is a structural schematic diagram of a transmission pulse generating circuit provided in an embodiment of the present application;

[0042] Figure 6 is a schematic diagram of an inverter output signal provided in an embodiment of the present application;

[0043] Figure 7 It is a structural schematic diagram of a transmission pulse generating circuit provided in an embodiment of the present application;

[0044] Figure 8 It is a flow chart of a method for generating a transmission pulse provided in an embodiment of the present application;

[0045] Fig. 9 is a schematic diagram of various input and output signals provided in an embodiment of the present application;

[0046] Fig.10 is a schematic diagram of various input and output signals provided in an embodiment of the present application;

[0047] Fig.11 is a state diagram of a transmission pulse generating circuit provided by an embodiment of the present application;

[0048] Fig.12 is a state diagram of a transmission pulse generating circuit provided by an embodiment of the present application;

[0049] Fig.13 is a state diagram of a transmission pulse generating circuit provided by an embodiment of the present application;

[0050] Fig.14 It is a state diagram of a transmission pulse generating circuit provided in an embodiment of the present application.

[0051] Description of Reference Numerals

[0052] 1. Clock signal input module; 2. Inverting module; 3. First control module; 4. Second control module; 11. First transistor; 12. Second transistor; 13. Third transistor; 14. Fourth transistor; 15. Fifth transistor; 16. Sixth transistor; 17. Seventh transistor; 18. Eighth transistor; 19. Ninth transistor; 20. Tenth transistor; 21. Eleventh transistor; 22. Coupling capacitor. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0054] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0055] In this embodiment, a transmission pulse generating circuit is provided. Figure 1 Schematic diagram of a transmission pulse generating circuit provided in an embodiment of the present application. Figure 1 As shown, the transmission pulse generating circuit may include: a clock signal input module 1, an inversion module 2, a first control module 3 and a second control module 4;

[0056] The first end of the clock signal input module 1 is used to input the first clock signal, the second end of the clock signal input module 1 is used to connect the first transmission pulse, the third end of the clock signal input module 1 is used to input the second clock signal, and the fourth end of the clock signal input module 1 is used to output the first control signal based on the first clock signal, the second clock signal and the first transmission pulse;

[0057] The first end of the inverting module 2 is used to connect the first transmitting pulse, the second end of the inverting module 2 is used to input the third clock signal, and the third end of the inverting module 2 is used to output the second control signal based on the first transmitting pulse and the third clock signal;

[0058] A first end of the first control module 3 is connected to a fourth end of the clock signal input module 1, a second end of the first control module 3 is connected to a third end of the inversion module 2, and a third end of the first control module 3 is used to output a third control signal based on the first control signal and the second control signal;

[0059] The first end of the second control module 4 is connected to the third end of the inverting module 2, and the second end of the second control module 4 is connected to the third end of the first control module 3; the third end of the second control module 4 is used to output a second transmission pulse based on the second control signal and the third control signal;

[0060] Among them, the first transmitting pulse is a pulse in the previous stage of the second transmitting pulse; the first clock signal is opposite in phase to the second clock signal, and the phase of the third clock signal is used to adjust the pulse width of the second transmitting pulse to an odd or even multiple of the line scanning time length.

[0061] In this embodiment, the emission pulse generating circuit can be arranged in the display device, for example, to provide a second emission pulse for controlling light emission to a display module such as a display panel. The second emission pulse can be an emission control EM signal, which can be used to control the light emission of the OLED, the coordinated operation of the pixel capacitor, and the reduction of the number of sub-pixels. The first emission pulse is a pulse in the previous stage of the second emission pulse, and the third emission pulse is a pulse in the subsequent stage of the first emission pulse. For example, the second emission pulse is recorded as EM(n), the first emission pulse is recorded as EM(n-1), and the third emission pulse is recorded as EM(n+1). The display module can perform display control by row scanning, and the time used to scan each row is the row scanning time.

[0062] In one embodiment, when the second emission pulse to be output is the first pulse in the circuit, namely, EM(1), the first emission pulse EM(0) used may be a predetermined initial pulse.

[0063] In one embodiment, the first clock signal may be a CLK signal, the second clock signal may be a CLKB signal, the first clock signal and the second clock signal are signals with opposite phases. The first clock signal and the second clock signal may be used to delay the rising transition and the falling transition of the first transmitting pulse by one line scanning duration, respectively.

[0064] In one embodiment, the second end of the clock signal input module 1 is used to connect the first emission pulse, which can be used to input the first emission pulse. The clock signal input module 1 can include one or more transistors, such as a P-type thin film transistor (TFT). The level state of the first clock signal, the second clock signal, and the first emission pulse can change the conduction state of the transistor in the clock signal input module 1, thereby changing the level state of the output first control signal.

[0065] In one embodiment, the clock signal input module 1 can be used to synchronously generate the first control signal A(n) on the second clock signal CLKB during the period when the first transmit pulse EM(n-1) is at a low level. For example, the first transmit pulse is at a low level to turn on the transistor corresponding to the second end of the clock signal input module 1.

[0066] In one embodiment, the inverting module 2 may include one or more transistors, for example, the transistor may be a P-type TFT. The first end of the inverting module 2 is used to connect the first emission pulse, which may be used to input the first emission pulse. The third clock signal may be a CLKE signal, and the level state of the first emission pulse and the third clock signal may change the conduction state of the transistor in the inverting module 2, thereby changing the level state of the output second control signal.

[0067] In one embodiment, the second control signal QB(n) output by the inverting module 2 can be used to control the conduction state of the first control module 3 and the second control module 4. For example, the first control module 3 and the second control module 4 can each include one or more transistors, for example, the transistor can be a P-type TFT. The second control signal can be used to control the conduction state of one or more transistors in the first control module 3 and the second control module 4, thereby controlling the level state of the output third control signal Q(n) and the second emission pulse.

[0068] In one embodiment, the phase of the third clock signal CLKE may be the same as the phase of the first clock signal CLK, or the phase of the third clock signal CLKE may be the same as the phase of the second clock signal CLKB. When the phase of the third clock signal is the same as the phase of the first clock signal, the pulse width of the second emission pulse is an odd multiple of the row scanning time length; when the phase of the third clock signal is the same as the phase of the second clock signal, the pulse width of the second emission pulse is an even multiple of the row scanning time length. The phase of the third clock signal is adjustable, so that the pulse width can be switched by changing its phase, and full coverage of all multiples of the row scanning time length is achieved.

[0069] In one embodiment, the first end of the first control module 3 can input a first control signal through the fourth end of the clock signal input module 1, and the level state of the first control signal can control the conduction state of the transistor corresponding to the first end of the first control module 3. The second end of the first control module 3 can input a second control signal through the third end of the inverting module 2, and the level state of the second control signal can control the conduction state of the transistor corresponding to the second end of the first control module 3.

[0070] In one embodiment, the first end of the second control module 4 can input the second control signal QB(n) through the third end of the inverting module 2, and the level state of the second control signal can control the conduction state of the transistor corresponding to the first end of the second control module 4. The second end of the second control module 4 can input the third control signal Q(n) through the third end of the first control module 3, and the level state of the third control signal Q(n) can control the conduction state of the transistor corresponding to the second end of the second control module 4.

[0071] In this way, in the generation circuit based on the first transmission pulse and two clock signals, a third clock signal supplementary control is added. By changing the phase of the third clock signal, it can compensate for the defect that the first clock signal and the second clock signal with opposite phases can only make the pulse width cover one of the odd multiples or even multiples of the line scanning time. Thereby, the pulse width can cover any multiples of the line scanning time. By adjusting the phase of the third clock signal according to the required width, fine control and flexible adjustment of the pulse can be achieved.

[0072] In this embodiment, a transmission pulse generating circuit is provided. Figure 2 Schematic diagram of a transmission pulse generating circuit provided in an embodiment of the present application. Figure 2 As shown, the clock signal input module 1 in the circuit may include a first transistor 11 and a second transistor 12;

[0073] The gate of the second transistor 12 serves as the first end of the clock signal input module 1; the gate of the first transistor 11 serves as the second end of the clock signal input module 1; the first electrode of the first transistor 11 serves as the third end of the clock signal input module 1; the second electrode of the first transistor 11 is connected in parallel with the second electrode of the second transistor 12, serving as the fourth end of the clock signal input module 1; the first electrode of the second transistor 12 is connected to a high-level power supply line.

[0074] In one embodiment, the first electrode and the second electrode are the source and the drain in the transistor, respectively, wherein the first electrode can be the source and the second electrode can be the drain. Optionally, depending on the type of transistor or circuit, the first electrode can also be the drain and the second electrode can also be the source.

[0075] In one embodiment, the gate of the second transistor 12 inputs the first clock signal, the gate of the first transistor 11 inputs the first emission pulse, the first electrode of the first transistor 11, such as the source, inputs the second clock signal, and the first electrode of the second transistor 12, such as the source, is connected to a high-level power supply line for connecting a predetermined high level VGH. The second electrode of the first transistor 11 is connected in parallel with the second electrode of the second transistor 12 for outputting a first control signal A(n).

[0076] In one embodiment, the first clock signal is used to delay the rising edge of the first emission pulse, and the second clock signal is used to delay the falling edge of the first emission pulse. For example, the falling edge of the first emission pulse EM(n-1) is synchronized with the high pulse of the second clock signal CLKB.

[0077] In this way, the first transmit pulse can be converted to rise and fall through the first clock signal and the second clock signal with opposite phases, and the provided first control signal can facilitate further adjustment through the third clock signal to improve the second transmit pulse generation efficiency.

[0078] In this embodiment, a transmission pulse generating circuit is provided. Figure 3 Schematic diagram of a transmission pulse generating circuit provided in an embodiment of the present application. Figure 3 As shown, the first control module 3 in the circuit may include: a third transistor 13 and a fourth transistor 14;

[0079] The gate of the fourth transistor 14 serves as the first end of the first control module 3; the gate of the third transistor 13 serves as the second end of the first control module 3 and is connected to the third end of the inverting module 2; the second pole of the third transistor 13 is connected in parallel with the first pole of the fourth transistor 14, serving as the third end of the first control module 3; the first pole of the third transistor 13 is connected to a high-level power supply line, and the second pole of the fourth transistor 14 is connected to a low-level power supply line.

[0080] In one embodiment, the first control signal A(n) output by the clock signal input module 1 is input to the gate of the fourth transistor 14. For example, the gate of the fourth transistor 14 is connected to the second electrode of the first transistor 11 and the second electrode of the second transistor 12. The level state of the first control signal controls the conduction state of the fourth transistor 14.

[0081] In one embodiment, the second control signal QB(n) output by the inversion module 2 is input to the gate of the third transistor 13 , and the level state of the second control signal controls the conduction state of the third transistor 13 .

[0082] In one embodiment, the second electrode of the third transistor 13 is connected in parallel with the first electrode of the fourth transistor 14 to output the third control signal Q(n). The first electrode of the third transistor 13 is connected to the high-level power supply line for connecting the predetermined high-level VGH; the second electrode of the fourth transistor 14 is connected to the low-level power supply line for connecting the predetermined low-level VGL.

[0083] In this way, based on the second control signal corresponding to the third clock signal and the first control signal corresponding to the first clock signal and the second clock signal, the first control module 3 can further implement conduction control of high-low level conversion based on these two signals.

[0084] In this embodiment, a transmission pulse generating circuit is provided. Figure 4 Schematic diagram of a transmission pulse generating circuit provided in an embodiment of the present application. Figure 4 As shown, the second control module 4 in the circuit may include: a fifth transistor 15 and a sixth transistor 16;

[0085] The gate of the fifth transistor 15 is connected to the third end of the inverting module 2 as the first end of the second control module 4; the gate of the sixth transistor 16 is connected to the third end of the first control module 3 as the second end of the second control module 4; the second electrode of the fifth transistor 15 is connected in parallel with the first electrode of the sixth transistor 16 as the third end of the second control module 4;

[0086] A first electrode of the fifth transistor 15 is connected to a high-level power supply line, and a second electrode of the sixth transistor 16 is connected to a low-level power supply line.

[0087] In one embodiment, the second control signal QB(n) output by the inverting module 2 is input to the gate of the fifth transistor 15, and the level state of the second control signal can control the conduction state of the fifth transistor 15. The third control signal Q(n) output by the first control module 3 is input to the gate of the sixth transistor 16, and the level state of the third control signal can control the conduction state of the sixth transistor 16.

[0088] In one embodiment, the first electrode of the fifth transistor 15 is connected to the high-level power supply line for connecting the predetermined high-level VGH; the second electrode of the sixth transistor 16 is connected to the low-level power supply line for connecting the predetermined low-level VGL. The second electrode of the fifth transistor 15 is connected in parallel with the first electrode of the sixth transistor 16 for outputting the second emission pulse EM(n).

[0089] In this way, based on the third control signal and the second control signal, flexible conduction control can be achieved, and then based on the predetermined high level and the predetermined low level, the high and low levels of the second transmitting pulse can be flexibly converted to accurately control the pulse width and the rising and falling edge delays.

[0090] In this embodiment, a transmission pulse generating circuit is provided. Figure 5 Schematic diagram of a transmission pulse generating circuit provided in an embodiment of the present application. Figure 5 As shown, the inverting module 2 in the circuit includes: a seventh transistor 17, an eighth transistor 18, a ninth transistor 19 and a tenth transistor 20;

[0091] The gate of the seventh transistor 17 is connected in parallel with the gate of the ninth transistor 19, serving as the first end of the inverting module 2; the first electrode of the tenth transistor 20 serves as the second end of the inverting module 2; the second electrode of the ninth transistor 19 is connected in parallel with the second electrode of the tenth transistor 20, serving as the third end of the inverting module 2; the first electrode of the eighth transistor 18 is connected to the second electrode of the seventh transistor 17 and the gate of the tenth transistor 20; the first electrode of the seventh transistor 17 and the first electrode of the ninth transistor 19 are connected to a high-level power supply line.

[0092] In one embodiment, the inversion module 2 is used to invert the first transmission pulse, and generate a second control signal based on the output signal after the inversion process and the third clock signal. For example, the seventh transistor 17 and the eighth transistor 18 form an inverter, and the ninth transistor 19 and the tenth transistor 20 are used to output the second control signal QB(n) based on the output signal B(n) of the inverter and the third clock signal CLKE.

[0093] In one embodiment, the first electrode of the eighth transistor 18 and the second electrode of the seventh transistor 17 are connected to the gate of the tenth transistor 20, the second electrode of the eighth transistor 18 is connected to the low-level power supply line for inputting a predetermined low-level VGL, and the output signal after the inverter inverts the first emission pulse is output to the gate of the tenth transistor 20. The level state of the output signal can control the conduction state of the tenth transistor 20.

[0094] In one embodiment, the gate of the eighth transistor 18 is used to input the output signal B(n-1) of the previous stage of the inverter, and the level state of the output signal B(n-1) of the previous stage can control the conduction state of the eighth transistor 18. In this way, since the seventh transistor 17 is turned on during the low level of the first transmission pulse, the inverter path will be turned on to cause continuous power consumption. By introducing the output signal of the previous stage to control the conduction of the eighth transistor 18, since the B(n) signal is opposite to the first transmission pulse, B(n-1) is one row scanning time ahead of B(n), then Figure 6 As shown, the inverter path is turned on only during a row scanning period when B(n-1) enters a low level and the first transmitting pulse is at a low level, avoiding being turned on during the entire period when the first transmitting pulse is at a low level, thereby reducing the power consumption of the inverter.

[0095] In one embodiment, the gate of the seventh transistor 17 is connected in parallel with the gate of the ninth transistor 19 , and both receive the first emission pulse. The level of the first emission pulse can control the conduction state of the seventh transistor 17 and the ninth transistor 19 .

[0096] In one embodiment, the first electrode of the tenth transistor 20 is connected to the third clock signal CLKE. The first electrode of the ninth transistor 19 and the first electrode of the seventh transistor 17 are used to connect to the predetermined high level VGH. The second electrode of the eighth transistor 18 is connected to the low level power supply line and is used to connect to the predetermined low level VGL.

[0097] In one embodiment, the second electrode of the ninth transistor 19 and the second electrode of the tenth transistor 20 are used to output the second control signal QB(n). The level state of QB(n) can control the conduction state of the third transistor 13 and the fifth transistor 15.

[0098] In this way, the first transmitting pulse is processed by the inverter, and based on the low level state transition of the inverted output signal combined with the third clock signal, the output second control signal can be used to more accurately control the level transition of the second transmitting pulse.

[0099] In this embodiment, a transmission pulse generating circuit is provided. Figure 7 Schematic diagram of a transmission pulse generating circuit provided in an embodiment of the present application. Figure 7 As shown, the circuit may further include: an eleventh transistor 21 and a coupling capacitor 22;

[0100] The first electrode of the eleventh transistor 21 is connected to the third end of the first control module 3 through the coupling capacitor 22; the second electrode of the eleventh transistor 21 is used to connect the third transmission pulse, and the third transmission pulse is a pulse in the later stage of the first transmission pulse.

[0101] In one embodiment, the level state of the third control signal Q(n) can control the conduction state of the eleventh transistor 21. The coupling capacitor 22 can be used to connect the third emission pulse EM(n+1), and through the capacitive coupling effect from the falling edge of EM(n+1) to Q(n), EM(n) is completely pulled down to VGL. In this way, when EM(n) is pulled down but cannot be reduced to VGL due to the presence of a threshold voltage, the EM(n) level can be further pulled down to the required VGL through the coupling capacitor and the third emission pulse EM(n+1).

[0102] In one embodiment, the coupling capacitor 22 and the eleventh transistor 21 can also be used to reduce the coupling effect of the third control signal Q(n). When Q(n) and EM(n+1) are connected through the eleventh transistor 21, Q(n) is at a high level at the rising edge of EM(n+1), and the eleventh transistor 21 is turned off. Therefore, due to the small parasitic capacitance between the source and gate nodes of the eleventh transistor 21, the coupling capacitor 22 between Q(n) and E(n+1) becomes very low, thereby reducing the coupling effect of Q(n) when the pulse width is an even multiple and an odd multiple of the line scanning time length.

[0103] In this embodiment, a method for generating a transmission pulse is provided. Figure 8 FIG. 1 is a flow chart of a method for generating a transmission pulse provided in an embodiment of the present application. Figure 8 As shown, the transmission pulse generation method is applied to the transmission pulse generation circuit described in any of the above embodiments, comprising:

[0104] S10: adjusting the phase of the third clock signal based on the pulse width required by the second transmit pulse;

[0105] S20: Generate a second transmit pulse based on the first clock signal, the second clock signal, the third clock signal and the first transmit pulse within one generation cycle.

[0106] Among them, when the phase of the third clock signal is the same as the phase of the first clock signal, the pulse width of the second emission pulse is an odd multiple of the line scanning time length; when the phase of the third clock signal is the same as the phase of the second clock signal, the pulse width of the second emission pulse is an even multiple of the line scanning time length.

[0107] In one embodiment, when the phase of the third clock signal is the same as that of the first clock signal, the pulse width of the second transmission pulse is an odd multiple of the line scanning time length, and the phase diagram of each signal is as follows: Fig. 9 As shown; when the phase of the third clock signal is the same as that of the second clock signal, the pulse width of the second transmission pulse is an even multiple of the line scanning time length, and the phase diagram of each signal is as shown Fig.10 shown.

[0108] In one embodiment, before generating the second transmission pulse, step S10 may include: if the pulse width of the second transmission pulse is required to be an odd multiple of the row scanning time length, the phase of the third clock signal is set to be the same as the first clock signal; if the pulse width of the second transmission pulse is required to be an even multiple of the row scanning time length, the phase of the third clock signal is set to be the same as the second clock signal.

[0109] In some embodiments, a generation cycle may include four stages, which may be the first stage t1, the second stage t2, the third stage t3 and the fourth stage t4 in chronological order. The duration of the first stage may be a row scan duration, during which the first clock signal CLK is at a high level, the second clock signal CLKB is at a low level, the first emission pulse EM(n-1) is at a predetermined low level, and the levels of the third control signal Q(n) and the second emission pulse EM(n) are reduced to a predetermined threshold. Here, the predetermined threshold may be determined based on a predetermined low level VGL and a threshold voltage Vth of the transistor. For example, the predetermined threshold corresponding to the third control signal Q(n) may refer to the sum of a predetermined low level and twice the threshold voltage, i.e., VGL+2|Vth|; the predetermined threshold corresponding to the second emission pulse may refer to the sum of a predetermined low level and three times the threshold voltage, i.e., VGL+3|Vth|.

[0110] In one embodiment, since the second control signal QB(n) output by the inverting module 2 at the low voltage of EM(n-1) is at a high level, the third transistor 13 and the fifth transistor 15 are turned off. Specifically, Fig.11 As shown in the figure, the arrows indicate the current flow direction, T1-T11 in the figure refer to the first transistor-eleventh transistor respectively, and C is a coupling capacitor. The high level CLK and the low level CLKB discharge the first control signal A(n) and turn on the fourth transistor 14, thereby causing the Q(n) and EM(n) levels to decrease. Due to the threshold voltages of the first transistor 11, the fourth transistor 14, and the sixth transistor 16, A(n), Q(n), and EM(n) cannot be completely pulled down to VGL, and they are stabilized at VGL + |Vth|, VGL + 2|Vth|, and VGL + 3|Vth|, respectively, where Vth is the threshold voltage.

[0111] In one embodiment, since the falling edge of EM(n-1) is synchronized with the high level state of CLKB, and Q(n) is triggered to decrease in level when CLKB is in the low level state, the falling edge of EM(n) is always delayed by one row scanning time than the falling edge of EM(n-1).

[0112] In some embodiments, after the first stage, the generation cycle further comprises: a second stage;

[0113] When the phase of the third clock signal is the same as the phase of the first clock signal, the duration of the second stage is three line scan durations; when the phase of the third clock signal is the same as the phase of the second clock signal, the duration of the second stage is two line scan durations;

[0114] In the second stage, the third control signal is discharged to a predetermined low level based on the low level of the third emission pulse, so that the level of the second emission pulse is reduced to the predetermined low level.

[0115] In one embodiment, the specific Fig.12 As shown, the fourth transistor 14 remains in the off state, and since its source-gate voltage is lower than Vth, the third control signal Q(n) is in a floating state. Therefore, through the capacitive coupling of the coupling capacitor 22, the low level transition of EM(n+1) pulls Q(n) down to the predetermined low level VGL.

[0116] In one embodiment, the low level of Q(n) further turns on the sixth transistor 16 and allows EM(n) to be fully discharged and the level is reduced to a predetermined low level VGL. During the low level of EM(n-1), since QB(n) and Q(n) are maintained at a high level and a low level respectively, EM(n) can be maintained at VGL.

[0117] In one embodiment, Fig. 9 and Fig.10 As shown, when the phase of the third clock signal is the same as that of the first clock signal, the duration of the second stage is three line scan durations; when the phase of the third clock signal is the same as that of the second clock signal, the duration of the second stage is two line scan durations. In this way, it can be ensured that no matter what the phase of the third clock signal is, it is in a high level state when entering the third stage, so that after EM(n-1) enters a high level in the third stage, EM(n) still remains at a low level, satisfying the delay of one line scan duration between the first emission pulse and the second emission pulse.

[0118] In some embodiments, after the second stage, the generation cycle further includes: a third stage and a fourth stage, the duration of the third stage is one row scanning duration, and the duration of the fourth stage is one row scanning duration;

[0119] In the third stage, the level of the first transmitting pulse rises to a predetermined high level, and the third control signal is maintained at a predetermined low level, so that the second transmitting pulse is maintained at a predetermined low level;

[0120] In the fourth stage, the level of the third control signal rises to a predetermined high level, and the level of the second emission pulse rises to a predetermined high level.

[0121] In one embodiment, in the third stage, in order to generate a delay of one line time at the rising edge of EM(n-1), even during the high level period of EM(n-1), the low level of EM(n) must be maintained for one line time. Fig.13As shown, CLKE is set to a high level through the tenth transistor 20, and the third transistor 13 and the fifth transistor 15 are continuously turned off. Since EM(n-1) is at a high level, the first control signal A(n) is maintained at a predetermined high level VGH, the fourth transistor 14 is turned off, and Q(n) and EM(n) are maintained at a low level. During this period, CLKE needs to be set to a high level to turn off the third transistor 13 and the fifth transistor 15. Therefore, the phase of CLKE should be adjusted according to whether the pulse width is an odd multiple or an even multiple of the line scanning time length.

[0122] In one embodiment, in the fourth stage, the following may be performed: Fig.14 As shown, the low level state of CLKE turns on the third transistor 13 and the fifth transistor 15, so that the levels of Q(n) and EM(n) rise to a predetermined high level VGH.

[0123] In one embodiment, QB(n) follows the pulse level of CLKE, but since the fourth transistor 14 and the sixth transistor 16 are turned off, the high levels of Q(n) and EM(n) remain in a floating state during the high level of CLKE. At this time, the eleventh transistor 21 is turned off, and due to the small parasitic capacitance between the source and gate nodes of the eleventh transistor 21, the coupling effect between Q(n) and EM(n+1) is reduced.

[0124] In this way, based on the four stages in the generation cycle, based on the three clock signals and the level changes of the first transmitting pulse, multiple transistors in the circuit are turned on or off in succession, and the second transmitting pulse is controlled by multiple control signals. The pulse width fully covers odd and even multiples of the row scanning time, thereby improving the flexibility and accuracy of pulse control.

[0125] As a possible implementation, a method for generating a transmission pulse is provided, including:

[0126] The emission pulse generation circuit consists of 11 p-type TFTs (first transistor - eleventh transistor) and a coupling capacitor (capacitor C). VGH and VGL are the high and low supply voltages, respectively. CLK and CLKB are the two-phase clock signals for the scanning and electromagnetic pulse shift registers, respectively. CLKE is one of the two-phase clock signals, and the phase can be adjusted according to whether the pulse width is an odd or even multiple of the line scanning time.

[0127] The first transistor and the second transistor synchronously generate A(n) pulses on CLKB only during the low level period of EM(n-1); the third transistor and the fourth transistor control the rise and fall of Q(n); the fifth transistor and the sixth transistor control the rise and fall of EM(n); the seventh transistor to the tenth transistor constitute an inverter for generating QB(n) to control the third transistor and the fifth transistor. The eleventh transistor is between the current stage and the next stage of Q(n) and EM(n+1) to attenuate the coupling noise from EM(n+1). The coupling capacitor C enables EM(n) to be pulled down to VGL by coupling the falling edge of EM(n+1) to Q(n). The details of the entire operation are divided into four stages: 1) the first stage t1, pull-down; 2) the second stage t2, capacitive coupling; 3) the third stage t3, hold; 4) the fourth stage t4, pull-up. For even multiples of the line scan time, CLKE is set equal to CLKB; for odd multiples of the line scan time, CLKE is set equal to CLK. The high pulse width is controlled by adjusting the low pulse width because the frame cycle time is fixed.

[0128] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0129] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

[0130] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A transmission pulse generating circuit, characterized in that: The circuit comprises: a clock signal input module, an inversion module, a first control module and a second control module; The first end of the clock signal input module is used to input a first clock signal, the second end of the clock signal input module is used to connect a first transmission pulse, the third end of the clock signal input module is used to input a second clock signal, and the fourth end of the clock signal input module is used to output a first control signal based on the first clock signal, the second clock signal and the first transmission pulse; The first end of the inverting module is used to connect the first transmitting pulse, the second end of the inverting module is used to input the third clock signal, and the third end of the inverting module is used to output the second control signal based on the first transmitting pulse and the third clock signal; The first end of the first control module is connected to the fourth end of the clock signal input module, the second end of the first control module is connected to the third end of the inversion module, and the third end of the first control module is used to output a third control signal based on the first control signal and the second control signal; The first end of the second control module is connected to the third end of the inverting module, and the second end of the second control module is connected to the third end of the first control module; the third end of the second control module is used to output a second transmission pulse based on the second control signal and the third control signal; Among them, the first transmitting pulse is a pulse in the previous stage of the second transmitting pulse; the first clock signal is opposite in phase to the second clock signal, and the phase of the third clock signal is used to adjust the pulse width of the second transmitting pulse to an odd or even multiple of the line scanning time length.

2. The circuit according to claim 1, characterized in that The clock signal input module includes a first transistor and a second transistor; The gate of the second transistor serves as the first terminal of the clock signal input module; the gate of the first transistor serves as the second terminal of the clock signal input module; the first electrode of the first transistor serves as the third terminal of the clock signal input module; the second electrode of the first transistor is connected in parallel with the second electrode of the second transistor, serving as the fourth terminal of the clock signal input module; A first electrode of the second transistor is connected to a high-level power supply line.

3. The circuit according to claim 1, characterized in that The first control module includes: a third transistor and a fourth transistor; The gate of the fourth transistor serves as the first end of the first control module; the gate of the third transistor serves as the second end of the first control module and is connected to the third end of the inverting module; the second electrode of the third transistor is connected in parallel with the first electrode of the fourth transistor and serves as the third end of the first control module; A first electrode of the third transistor is connected to a high-level power supply line, and a second electrode of the fourth transistor is connected to a low-level power supply line.

4. The circuit according to claim 1, characterized in that The second control module includes: a fifth transistor and a sixth transistor; The gate of the fifth transistor is connected to the third end of the inverting module as the first end of the second control module; the gate of the sixth transistor is connected to the third end of the first control module as the second end of the second control module; the second electrode of the fifth transistor is connected in parallel with the first electrode of the sixth transistor as the third end of the second control module; A first electrode of the fifth transistor is connected to a high-level power supply line, and a second electrode of the sixth transistor is connected to a low-level power supply line.

5. The circuit according to claim 1, characterized in that The inversion module includes: a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; The gate of the seventh transistor is connected in parallel with the gate of the ninth transistor to serve as the first end of the inverting module; the first electrode of the tenth transistor serves as the second end of the inverting module; the second electrode of the ninth transistor is connected in parallel with the second electrode of the tenth transistor to serve as the third end of the inverting module; the first electrode of the eighth transistor and the second electrode of the seventh transistor are connected to the gate of the tenth transistor; The first electrode of the seventh transistor and the first electrode of the ninth transistor are connected to a high-level power supply line.

6. The circuit according to claim 1, characterized in that The circuit further includes: an eleventh transistor and a coupling capacitor; The first electrode of the eleventh transistor is connected to the third end of the first control module through the coupling capacitor; the second electrode of the eleventh transistor is used to connect the third emission pulse, and the third emission pulse is a pulse in a later stage than the first emission pulse.

7. A method for generating a transmission pulse, applied to the transmission pulse generating circuit according to any one of claims 1 to 6, characterized in that: The method comprises: adjusting the phase of the third clock signal based on the pulse width required by the second transmit pulse; Generate a second transmit pulse based on the first clock signal, the second clock signal, the third clock signal and the first transmit pulse in one generation cycle; Among them, when the phase of the third clock signal is the same as the phase of the first clock signal, the pulse width of the second emission pulse is an odd multiple of the line scanning time length; when the phase of the third clock signal is the same as the phase of the second clock signal, the pulse width of the second emission pulse is an even multiple of the line scanning time length.

8. The method according to claim 7, characterized in that The generation cycle includes: a first stage, the duration of the first stage is a row scanning duration; In the first stage, the first clock signal is at a high level, the second clock signal is at a low level, the first emission pulse is at a predetermined low level, and the levels of the third control signal and the second emission pulse are reduced to a predetermined threshold.

9. The method according to claim 8, characterized in that After the first stage, the generation cycle further includes: a second stage; when the phase of the third clock signal is the same as the phase of the first clock signal, the duration of the second stage is three line scan durations; when the phase of the third clock signal is the same as the phase of the second clock signal, the duration of the second stage is two line scan durations; In the second stage, the third control signal is discharged to a predetermined low level based on the low level of the third emission pulse, so that the level of the second emission pulse is reduced to the predetermined low level.

10. The method according to claim 9, characterized in that After the second stage, the generation cycle further includes: a third stage and a fourth stage, the duration of the third stage is one row scanning duration, and the duration of the fourth stage is one row scanning duration; In the third stage, the level of the first transmitting pulse rises to a predetermined high level, and the third control signal is maintained at a predetermined low level, so that the second transmitting pulse is maintained at a predetermined low level; In the fourth stage, the level of the third control signal rises to a predetermined high level, and the level of the second emission pulse rises to a predetermined high level.

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