A shortest path determination method based on nonlinear weight mapping of memristor

Abstract

The present specification discloses a shortest path determination method based on nonlinear weight mapping of memristors. In the shortest path determination method based on memristors provided in the present specification, the mapping value of the weight of each edge in the graph data is determined according to the input voltage of the voltage pulse signal to be applied, the threshold conversion voltage of the second memristor in the hardware circuit, the resistance value of the equivalent resistance of the transimpedance amplifier, the resistance value of the load resistor, and the high resistance value of the second memristor, and the conductance value of each first memristor in the synaptic array is set according to each mapping value. Thus, the calculation of the shortest path of the graph data is realized by using a hardware circuit based on a memristor and an in-memory calculation method, which speeds up the calculation efficiency of the shortest path algorithm compared to the shortest path algorithm implemented by software.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method for determining the shortest path based on nonlinear weight mapping of a memristor. Background Art

[0002] With the development of computer technology, business execution is increasingly dependent on the calculation results of algorithms. In the fields of network routing, map navigation, traffic planning, etc., the shortest path algorithm has a wide range of applications. Common shortest path algorithms include Dijkstra algorithm, Floyd algorithm, etc.

[0003] However, the existing shortest path algorithms have high time complexity and low computational efficiency because they need to traverse all nodes of the graph data during the calculation process. Although the computational efficiency can be improved through memristors, the existing shortest path algorithms are all based on traditional hardware algorithms with storage and computation separation, and cannot be directly implemented on memristors for acceleration. The hardware implementation algorithm based on memristors needs to be specially designed. Among them, a memristor is a nonlinear resistor with a memory function, and its resistance value can be dynamically adjusted according to the stimulation of external voltage or current. Due to the electrical characteristics of the variable resistance of the memristor, the memristor can be used as a storage unit to implement computing operations at the same time, realize in-memory computing, and improve computing efficiency.

[0004] Therefore, the present specification provides a shortest path determination method based on nonlinear weight mapping of a memristor. Summary of the invention

[0005] The present specification provides a shortest path method based on nonlinear weight mapping of a memristor to at least partially solve the above-mentioned problems existing in the prior art.

[0006] This manual adopts the following technical solutions:

[0007] The present specification provides a shortest path method based on nonlinear weight mapping of memristors, the method is implemented by a hardware circuit, the hardware circuit includes a synapse array and multiple neuron circuits, the synapse array is composed of multiple synapse circuits, the synapse circuit includes multiple first memristors, the neuron circuit includes a transimpedance amplifier, a second memristor and a load resistor, each of the first memristors is respectively connected to the input end of the neuron circuit corresponding to itself, the input end of each synapse circuit is respectively connected to the output end of the neuron circuit corresponding to each synapse circuit, the method includes:

[0008] Get graph data;

[0009] Determine the input voltage corresponding to the voltage pulse signal to be applied, and for each edge in the graph data, determine the mapping value of the weight of the edge according to the weight of the edge, the input voltage, the threshold conversion voltage of the second memristor, the resistance value of the equivalent resistance of the transimpedance amplifier, the resistance value of the load resistor, and the high resistance value of the second memristor;

[0010] Determine a mapping value of the weight of each edge in the graph data, determine a neuron circuit corresponding to each node in the graph data, determine a first memristor corresponding to the edge connected to the node among the first memristors included in the synaptic circuit connected to the neuron circuit corresponding to the node, and set the mapping value of the edge connected to the node to the conductance value of the first memristor corresponding to the edge connected to the node;

[0011] The voltage pulse signal is applied to the hardware circuit, and the shortest path is determined according to the activation sequence of each second memristor included in the hardware circuit.

[0012] Optionally, determining a mapping value of the weight of the edge according to the weight of the edge, the input voltage, a threshold conversion voltage of the second memristor, a resistance value of an equivalent resistor of the transimpedance amplifier, a resistance value of the load resistor, and a high resistance value of the second memristor specifically includes:

[0013] Determining a resistance sum according to the resistance value of the load resistor and the high resistance value of the second memristor;

[0014] Determining a voltage division ratio of the second memristor according to a ratio of a high resistance value of the second memristor to the sum of the resistances;

[0015] Determine a mapping parameter of the weight of the edge according to the negative natural exponential value of the weight of the edge;

[0016] Taking the product of the mapping parameter, the voltage division ratio, the input voltage and the resistance value of the equivalent resistance of the transimpedance amplifier as an intermediate value;

[0017] A mapping value of the weight of the edge is determined according to a ratio of the threshold conversion voltage of the second memristor to the intermediate value.

[0018] Optionally, determining the shortest path according to an activation sequence of each second memristor included in the hardware circuit specifically includes:

[0019] Taking any node in the graph data as a starting node, starting from the node next to the starting node, sequentially performing a round of determination process for each node other than the starting node in the graph data, taking the starting node as a target node of the round of determination process, and taking a synaptic circuit connected to a neuron circuit corresponding to the target node as a target synaptic circuit of the round of determination process;

[0020] Determine the second memristor activated in the round determination process according to the conductance value of each first memristor in the target synaptic circuit, and use the node corresponding to the neuron circuit where the second memristor activated in the round determination process is located as the successor node of the target node;

[0021] The voltage pulse signal is transmitted back to the synaptic circuit connected to the neuron circuit corresponding to the successor node through the output end of the neuron circuit where the second memristor activated in the round determination process is located, and the successor node is used as the target node of the next round determination process, and the synaptic circuit connected to the neuron circuit corresponding to the successor node is used as the target synaptic circuit of the next round determination process, and the next round determination process is continued until the second memristors corresponding to all nodes included in the graph data are activated;

[0022] The shortest path is determined according to the starting node and the nodes corresponding to the neuron circuits where the second memristors activated in sequence in each round of determination process are located.

[0023] Optionally, determining the second memristor activated in the round of determination process according to the conductance value of each first memristor in the target synaptic circuit specifically includes:

[0024] Respectively obtaining the inflow current of the neuron circuit connected to each first memristor in the target synaptic circuit;

[0025] Among the inflow currents, determine the inflow current with the largest current value;

[0026] The inflow current with the largest current value corresponds to the second memristor in the neuron circuit as the second memristor activated in the round determination process.

[0027] Optionally, determining the second memristor activated in the round of determination process according to the conductance value of each first memristor in the target synaptic circuit specifically includes:

[0028] For each first memristor in the target synaptic circuit, determining an outflow current of the first memristor according to a product of a conductance value of the first memristor and the input voltage;

[0029] The first memristor corresponds to the second memristor in the neuron circuit as the memristor to be activated;

[0030] determining an inflow voltage of the memristor to be activated according to a product of an outflow current of the first memristor and a resistance value of an equivalent resistance of the transimpedance amplifier;

[0031] Determining an equivalent voltage of the memristor to be activated according to a product of an inflow voltage of the memristor to be activated and the voltage division ratio;

[0032] determining an activation parameter according to a ratio of a threshold conversion voltage of the second memristor to an equivalent voltage of the memristor to be activated;

[0033] Taking the difference between 1 and the activation parameter as a true number, determining a natural logarithm value;

[0034] Determining an activation time of the memristor to be activated according to the natural logarithm value;

[0035] According to the activation time of the to-be-activated memristors corresponding to the first memristors in the round of determination process, among the to-be-activated memristors corresponding to the first memristors, determining the to-be-activated memristor with the shortest activation time;

[0036] The to-be-activated memristor with the shortest activation time is used as the second memristor activated in this round of determination process.

[0037] Optionally, the method may also be used for graph data classification, including:

[0038] Obtain each to-be-classified graph data, and determine the shortest path corresponding to each to-be-classified graph data by the shortest path determination method based on nonlinear weight mapping of memristor;

[0039] For each graph data to be classified, determine the weight of the edge between each node contained in the shortest path corresponding to the graph data to be classified as the length of each distance contained in the shortest path corresponding to the graph data to be classified;

[0040] Determine the path characteristics of the graph data to be classified according to the lengths of each distance contained in the shortest path corresponding to the graph data to be classified;

[0041] Determining the graph features of each of the graph data to be classified according to the path features of each of the graph data to be classified;

[0042] The graph features of each of the graph data to be classified are input into a classifier to obtain classification results of each of the graph data to be classified.

[0043] Optionally, determining the path feature of the graph data to be classified according to the lengths of each distance contained in the shortest path corresponding to the graph data to be classified specifically includes:

[0044] Among the distance lengths contained in the shortest path corresponding to the graph data to be classified, the distance lengths with the same size are taken as a distance set;

[0045] The path characteristics of the graph data to be classified are determined according to the number of distance lengths corresponding to each distance set.

[0046] Optionally, determining the graph features of each of the graph data to be classified according to the path features of each of the graph data to be classified specifically includes:

[0047] For each graph data to be classified, respectively determine the similarity between the path feature of the graph data to be classified and the path features of other graph data to be classified;

[0048] According to the determined similarities, the graph features of the graph data to be classified are determined.

[0049] Optionally, the classifier is trained according to the following method, wherein:

[0050] Obtaining each sample graph data to be trained and a classification label corresponding to each sample graph data;

[0051] Determine the shortest path corresponding to each sample graph data by the above-mentioned shortest path determination method;

[0052] For each sample graph data, determine the weight of the edge between each node included in the shortest path corresponding to the sample graph data as the length of each distance included in the shortest path corresponding to the sample graph data;

[0053] Determine the path characteristics of the sample graph data according to the lengths of each distance contained in the shortest path corresponding to the sample graph data;

[0054] Determining graph features of each sample graph data according to the path features of each sample graph data;

[0055] Inputting the graph features of each sample graph data into the classifier to be trained to obtain the predicted classification of each sample graph data;

[0056] The classifier is trained according to the difference between the predicted classification of each sample graph data and the classification label corresponding to each sample graph data.

[0057] The present specification provides a shortest path determination device based on nonlinear weight mapping of memristors, the device comprising a hardware circuit, the hardware circuit comprising a synaptic array and a plurality of neuron circuits, the synaptic array being composed of a plurality of synaptic circuits, the synaptic circuit comprising a plurality of first memristors, the neuron circuit comprising a transimpedance amplifier, a second memristor and a load resistor, each first memristor being respectively connected to an input end of a neuron circuit corresponding to itself, the input end of each synaptic circuit being respectively connected to an output end of a neuron circuit corresponding to each synaptic circuit, the device comprising:

[0058] Get module, get graph data;

[0059] A mapping value determination module determines the input voltage corresponding to the voltage pulse signal to be applied, and for the weight of each edge in the graph data, determines the mapping value of the weight of the edge according to the weight of the edge, the input voltage, the threshold conversion voltage of the second memristor, the resistance value of the equivalent resistance of the transimpedance amplifier, the resistance value of the load resistor, and the high resistance value of the second memristor;

[0060] A conductance value setting module determines a mapping value of the weight of each edge in the graph data, determines a neuron circuit corresponding to each node in the graph data, determines a first memristor corresponding to the edge connected to the node among the first memristors included in the synaptic circuit connected to the neuron circuit corresponding to the node, and sets the mapping value of the edge connected to the node to the conductance value of the first memristor corresponding to the edge connected to the node;

[0061] The shortest path determination module applies the voltage pulse signal to the hardware circuit, and determines the shortest path according to the activation sequence of each second memristor included in the hardware circuit.

[0062] At least one of the above technical solutions adopted in this specification can achieve the following beneficial effects:

[0063] In the memristor-based shortest path determination method provided in the present specification, the mapping value of the weight of each edge in the graph data is determined according to the input voltage of the voltage pulse signal to be applied, the threshold conversion voltage of the second memristor in the hardware circuit, the resistance value of the equivalent resistance of the transimpedance amplifier, the resistance value of the load resistor, and the high resistance value of the second memristor, and the conductance value of each first memristor in the synapse array is set according to each mapping value, so that the calculation of the shortest path of the graph data is realized through the memristor-based hardware circuit and the in-memory calculation method, which speeds up the calculation efficiency of the shortest path algorithm compared to the shortest path algorithm implemented by software. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The drawings described herein are used to provide a further understanding of this specification and constitute a part of this specification. The illustrative embodiments and descriptions of this specification are used to explain this specification and do not constitute an improper limitation on this specification. In the drawings:

[0065] Figure 1 A schematic diagram of a flow chart of a method for determining a shortest path based on nonlinear weight mapping of a memristor in this specification;

[0066] Figure 2 A schematic diagram of a hardware circuit provided in an embodiment of this specification;

[0067] Figure 3 A flowchart of a graph data classification method in this specification;

[0068] Figure 4 This is a schematic diagram of a shortest path determination device based on nonlinear weight mapping of a memristor provided in this specification. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical solutions and advantages of this specification more clear, the technical solutions of this specification will be clearly and completely described below in combination with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0070] The technical solutions provided by the embodiments of this specification are described in detail below in conjunction with the accompanying drawings.

[0071] Figure 1 This is a flow chart of a shortest path determination method based on nonlinear weight mapping of a memristor in this specification. This method is implemented by a hardware circuit based on a memristor, and the hardware circuit includes a synaptic array and multiple neuron circuits. The synaptic array is composed of multiple synaptic circuits, and the synaptic circuit includes multiple first memristors. The neuron circuit includes a transimpedance amplifier, a second memristor and a load resistor. Each first memristor is respectively connected to the input end of the neuron circuit corresponding to itself, and the input end of each synaptic circuit is respectively connected to the output end of the neuron circuit corresponding to each synaptic circuit. Specifically, the following steps are included:

[0072] S100: Acquire graph data.

[0073] All steps in the shortest path determination method based on memristor nonlinear weight mapping provided in this specification can be implemented by any electronic device with computing functions, such as terminals, servers and other devices. For the convenience of description, the shortest path determination method based on memristor provided in this specification is described below with the server as the execution subject, wherein the hardware circuit implementing this method is deployed on the processing chip of the server.

[0074] The preferred server obtains graph data, which is weighted graph data. In subsequent steps, the server will calculate the shortest path between nodes in the graph data through the hardware circuit.

[0075] The information of the graph data will be stored in the synaptic array of the hardware circuit. For each node in the graph data, the node corresponds to a neuron circuit in the hardware circuit, and each first memristor included in the synaptic circuit connected to the neuron circuit corresponding to the node represents each edge connected to the node in the graph data.

[0076] Figure 2is a schematic diagram of a hardware circuit provided in an embodiment of this specification. The shortest path determination method in this specification can be performed by Figure 2 The hardware circuit shown is implemented as follows, Figure 2 It is only used to illustrate the connection between some components of the hardware circuit. Figure 2 The connection method between the components not shown is not limited.

[0077] like Figure 2 As shown, the first memristors 200 included in the synaptic array are arranged in a 4×4 matrix, and the synaptic array includes four synaptic circuits 204. The neuron circuit 205 includes a transimpedance amplifier 202, a load resistor 203, a second memristor 201 and an analog-to-digital converter 206.

[0078] Among them, Figure 2 The synaptic circuit 204 and the neuron circuit 205 framed by dotted lines correspond to each other, the output end 208 of the neuron circuit 205 framed by dotted lines is connected to the input end 207 of the synaptic circuit 204 framed by dotted lines, and each first memristor 204 included in the synaptic circuit 204 framed by dotted lines is respectively connected to the input end 209 of each neuron circuit 205, and the voltage pulse signal can be transmitted along the row of the synaptic array through each first memristor 200 to activate the second memristor 201 in each neuron circuit 205.

[0079] The hardware circuit in this specification is a pulse neural network circuit. The first memristor in the hardware circuit is a synaptic device, which is a non-volatile memristor device, and the second memristor is a neuron device, which is a volatile gating device.

[0080] S102: Determine the input voltage corresponding to the voltage pulse signal to be applied, and for each edge in the graph data, determine the mapping value of the weight of the edge according to the weight of the edge, the input voltage, the threshold conversion voltage of the second memristor, the resistance value of the equivalent resistance of the transimpedance amplifier, the resistance value of the load resistor, and the high resistance value of the second memristor.

[0081] The server determines the mapping value of each weight according to the weight of each edge in the graph data, and sets the conductance value of each first memristor in the synaptic array according to the mapping value, thereby storing the information of the graph data in the synaptic array.

[0082] The mapping value of each weight in the graph data in this specification is determined by the following method.

[0083] First, the server determines the input voltage corresponding to the voltage pulse signal to be applied.

[0084] Secondly, for each edge of the graph data, the resistance sum is determined according to the weight of the edge, the resistance value of the load resistor in the hardware circuit and the high resistance value of the second memristor, and the voltage division ratio of the second memristor is determined according to the ratio of the high resistance value of the second memristor to the resistance sum.

[0085] Then, the voltage division ratio of the second memristor is determined according to the ratio of the high resistance value of the second memristor to the resistance sum, and the mapping parameter of the weight of the edge is determined according to the negative natural exponential value of the weight of the edge.

[0086] Finally, the server uses the product of the mapping parameter, the voltage division ratio, the input voltage and the resistance value of the equivalent resistance of the transimpedance amplifier as the intermediate value, and determines the mapping value of the weight of the edge according to the ratio of the threshold conversion voltage of the second memristor to the intermediate value.

[0087] Specifically, the mapping value of the weight of the edge can be determined according to the following formula:

[0088]

[0089] Among them, α represents the voltage division ratio of the second memristor, R int Indicates the resistance value of the load resistor, R off represents the high resistance value of the second memristor. W′ represents the mapping value of the weight of the edge, W represents the weight of the edge, V t represents the threshold switching voltage of the second memristor, V read Represents input voltage, R TIA represents the equivalent resistance of the transimpedance amplifier, “1-exp(-kW)” represents the mapping parameter, and “αV read R TIA (1exp(-kW))” represents the intermediate value. k is an adjustable parameter.

[0090] According to the above formula, it can be seen that the nonlinear mapping method is adopted in this specification, and the relationship between the weight and the mapping value is a nonlinear relationship. However, the larger the weight, the smaller the mapping value corresponding to the weight, that is, the mapping value is negatively correlated with the weight.

[0091] S104: Determine a mapping value of the weight of each edge in the graph data, determine a neuron circuit corresponding to each node in the graph data, determine a first memristor corresponding to the edge connected to the node among each first memristor included in a synaptic circuit connected to the neuron circuit corresponding to the node, and set the mapping value of the edge connected to the node to the conductance value of the first memristor corresponding to the edge connected to the node.

[0092] The server determines the mapping value of the weight of each edge in the graph data according to the above steps, and then sets the mapping value of the weight of each edge to the conductance value of each first memristor in the synaptic array. That is, G = W'. Where G represents the conductance value. The relationship between the weight and the conductance value in this specification is also a nonlinear relationship.

[0093] Specifically, the server determines, for each node in the graph data, a neuron circuit corresponding to the node, determines, among each first memristor included in a synaptic circuit connected to the neuron circuit corresponding to the node, a first memristor corresponding to an edge connected to the node, and sets the mapping value of the edge connected to the node to the conductance value of the first memristor corresponding to the edge connected to the node.

[0094] The server maps the weight of each edge in the graph data to the conductance value of each first memristor in the synaptic array. When a voltage pulse signal is applied, the voltage pulse signal can cause the current generated in the circuit to be transmitted to different neuron circuits along each first memristor in the synaptic circuit. Figure 2 As shown, when a voltage pulse signal is applied, taking the first column of synaptic circuits in the synaptic array as an example, the current can be transmitted horizontally to the right along the neuron circuits connected to the four first memristors included in the synaptic circuit.

[0095] S106: applying the voltage pulse signal to the hardware circuit, and determining the shortest path according to the activation sequence of each second memristor included in the hardware circuit.

[0096] In the shortest path determination method, the weight of the edge represents the distance between two nodes. A small weight indicates a short distance, and the activation time of the second memristor in the neuron circuit connected to the first memristor corresponding to the short distance weight is short. Therefore, in this specification, the order of each node in the shortest path can be determined by the activation order of each second memristor.

[0097] However, because the memristor is a nonlinear element, under a fixed voltage, the relationship between the conductance value of the first memristor and the activation time of the second memristor in this specification is a nonlinear relationship. The existing weight mapping method is usually a linear mapping, such as determining the conductance value according to a preset ratio of the weight, or according to a preset bias value of the weight. After mapping by the existing weight mapping method, because the relationship between the weight and the conductance value is a linear relationship, the relationship between the conductance value of the first memristor and the activation time of the second memristor is still a nonlinear relationship.

[0098] In this specification, the shortest path is determined according to the activation time of each second memristor. In the application scenario of the shortest path determination in this specification, the activation time of the second memristor needs to accurately reflect the size relationship of the weight in the graph data. If the weight and the activation time of each second memristor are not linearly related, it will cause errors in the shortest path determination.

[0099] Through the nonlinear weight mapping method in this specification, the relationship between the weight corresponding to the conductance value of the first memristor and the activation time of the second memristor can be transformed into a linear relationship, thereby increasing the accuracy of the hardware implementation of the shortest path algorithm. The description of the linear relationship will be described later.

[0100] After activating the second memristors corresponding to all nodes in the graph data, the server can determine the shortest path based on the start node and the activation order of each second memristor. The activation order of each second memristor is the order in which the nodes after the start node in the shortest path are connected in sequence.

[0101] After the conductance values ​​of the first memristors in the synaptic array are set, the server uses any node in the graph data as the starting node, and determines the order of the nodes in the shortest path through the activation order of the second memristors in the hardware circuit. In this specification, the activation process of a second memristor is regarded as the process of determining a node in the shortest path.

[0102] The server starts from the node next to the starting node, and sequentially performs the determination process for each round corresponding to each node other than the starting node in the graph data, and takes the starting node as the target node of this round of determination process, and takes the synaptic circuit connected to the neuron circuit corresponding to the target node as the target synaptic circuit of this round of determination process.

[0103] The target synaptic circuit of the round determination process and the neuron circuits corresponding to the first memristors in the target synaptic circuit constitute a voltage pulse signal transmission route in the round determination process.

[0104] The server applies a voltage pulse signal to the target synaptic circuit. The voltage pulse signal can be transmitted to each neuron circuit through each first memristor in the target synaptic circuit along the transmission route determined in the above steps, thereby activating the second memristor of each neuron circuit.

[0105] For a first memristor, the greater the conductance value of the first memristor, the smaller the resistance value of the first memristor. Under the same input voltage, the greater the current flowing through the first memristor. When the current flows into the neuron circuit connected to the first memristor, the greater the inflow current of the second memristor in the neuron circuit, and the corresponding inflow voltage of the second memristor is also greater. With the continuous application of the voltage pulse signal, the inflow voltage accumulates continuously inside the second memristor. When the accumulated voltage reaches the threshold conversion voltage of the second memristor, the second memristor is activated and emits a neural pulse signal. The emitted neural pulse signal can be used to select the synaptic circuit connected to the neuron circuit where the second memristor is located in the synaptic array, so that the applied voltage pulse signal continues to be transmitted along the synaptic circuit connected to the output end of the second memristor.

[0106] During the activation process of the second memristor, the greater the inflow current of the second memristor, the shorter the time it takes for the voltage accumulated inside the second memristor to reach the threshold conversion voltage, and the greater the conductance value of the first memristor connected to the input end of the neuron circuit, the earlier the second memristor in the neuron circuit is activated. That is, during an activation process, the inflow current of the second memristor is negatively correlated with the activation time of the second memristor, and the greater the inflow current, the shorter the activation time.

[0107] In one or more embodiments of the present specification, the server may respectively obtain the inflow currents of the neuron circuits connected to the first memristors in the target synaptic circuit, determine the inflow current with the largest current value among the inflow currents, and correspond the inflow current with the largest current value to the second memristor in the neuron circuit as the second memristor activated in the round determination process.

[0108] Each first memristor in the target synaptic circuit represents each edge connected to the target node in the round determination process, and the conductance value of each first memristor in the target synaptic circuit represents the weight of each edge.

[0109] As mentioned in step S104 , through the mapping method in step S102 , the relationship between the conductance value of the first memristor and the activation time of the second memristor is a linear relationship.

[0110] Because the relationship between the inflow current of each neuron circuit (the outflow current of each neuron circuit corresponding to the first memristor) and the conductance value of each first memristor in the target synaptic circuit is a linear relationship, the specific relationship is I out =GV read , I out represents the outflow current of the first memristor.

[0111] Therefore, the relationship between the inflow current of each neuron circuit and the activation time of the second memristor is also a linear relationship. Because the inflow current can be directly measured, the server can obtain the inflow current of each neuron circuit and determine the second memristor activated in the round of determination according to the size of the inflow current.

[0112] Then, the server uses the node corresponding to the neuron circuit where the second memristor activated in the round determination process is located as the successor node of the target node of the round determination process. The server can save the successor node of the target node of the round determination process. After the round determination process is completed, the server sequentially saves the starting node and the successor nodes determined in each round determination process. When the number of saved nodes is equal to the number of nodes included in the graph data, the shortest path is determined according to the order of the saved nodes.

[0113] When a second memristor in the hardware circuit is activated, a neural pulse signal is emitted. The neural pulse signal passes through the output end of the neuron circuit where the activated second memristor is located, and is converted into a control signal through the digital control circuit. The control signal controls the synaptic circuit connected to the neuron circuit corresponding to the successor node in the synaptic array, and starts the next round of determination process.

[0114] Therefore, the server uses the successor node as the target node of the next round of determination process, and uses the synaptic circuit connected to the neuron circuit corresponding to the successor node as the target synaptic circuit of the next round of determination process, and continues the next round of determination process until the second memristors corresponding to all nodes contained in the graph data are activated.

[0115] Based on the above Figure 1 The shortest path determination method shown determines the mapping value of the weight of each edge in the graph data according to the input voltage of the voltage pulse signal to be applied, the threshold conversion voltage of the second memristor in the hardware circuit, the resistance value of the equivalent resistance of the transimpedance amplifier, the resistance value of the load resistor, and the high resistance value of the second memristor, and sets the conductance value of each first memristor in the synaptic array according to each mapping value, thereby realizing the calculation of the shortest path of the graph data through a memristor-based hardware circuit and an in-memory calculation method, which speeds up the calculation efficiency of the shortest path algorithm compared to the shortest path algorithm implemented by software.

[0116] In the above step S106, the server may also calculate the activation time of the second memristor of each neuron circuit connected to each first memristor in the target synaptic circuit, determine the second memristor with the shortest activation time among the second memristors, and further determine the second memristor activated in this round of determination process.

[0117] First, the server determines, for each first memristor in the target synaptic circuit, an outflow current of the first memristor according to a product of a conductance value of the first memristor and an input voltage.

[0118] Specifically, the outflow current of the first memristor can be determined according to the following formula:

[0119] I out =GV read

[0120] Secondly, the server uses the second memristor in the neuron circuit corresponding to the first memristor as the memristor to be activated, and determines the inflow voltage of the memristor to be activated according to the product of the outflow current of the first memristor and the resistance value of the equivalent resistance of the transimpedance amplifier.

[0121] Specifically, the inflow voltage of the memristor to be activated can be determined according to the following formula:

[0122] V in =I out R TIA

[0123] Among them, V in represents the inflow voltage of the memristor to be activated, that is, the inflow voltage of the second memristor.

[0124] Thirdly, the server determines the equivalent voltage of the memristor to be activated according to the product of the inflow voltage of the memristor to be activated and the voltage division ratio.

[0125] Specifically, the equivalent voltage of the memristor to be activated can be determined according to the following formula:

[0126] U s =V in ×α

[0127] Among them, U s Represents the equivalent voltage of the memristor to be activated.

[0128] Then, the server determines an activation parameter according to the ratio of the threshold conversion voltage of the second memristor to the equivalent voltage of the memristor to be activated, takes the difference between 1 and the activation parameter as a true number, determines a natural logarithm value, and determines the activation time of the memristor to be activated according to the natural logarithm value.

[0129] Specifically, the activation time of the memristor to be activated can be determined according to the following formula:

[0130]

[0131] Among them, τ is an adjustable parameter.

[0132] Finally, the server determines the memristor to be activated with the shortest activation time among the memristors to be activated corresponding to the first memristors according to the activation time of the memristors to be activated corresponding to the first memristors in this round of determination process, and uses the memristor to be activated with the shortest activation time as the second memristor activated in this round of determination process.

[0133] The method in this embodiment calculates the activation time of each memristor to be activated, and determines the second memristor with the shortest activation time as the second memristor activated in the round determination process. The method in this embodiment is a method for directly determining the activation time, which is highly interpretable, but compared with the method for determining the second memristor activated in the round determination process in the above step S106, the calculation process is more complicated and the calculation efficiency is low.

[0134] According to the above formula, it can be deduced that t = τ × k × W. That is, the relationship between the activation time of the memristor to be activated and the weight corresponding to the conductance value of the first memristor is a linear relationship. Therefore, the activation time sequence of the second memristor in each neuron circuit can accurately represent the weight of each edge in the graph data.

[0135] Therefore, the method of determining the second memristor activated in the round of determination by the inflow current of each neuron circuit in the above step S106 has the same accuracy as the method of this embodiment. Because the calculation process of the method in the above step S106 is simpler and can achieve higher calculation efficiency, the determination method in the above step S106 is the preferred method.

[0136] The shortest path determination method provided in this specification can also be used for graph data classification. Figure 3 , the classification method of the graph data is explained. Figure 3 The following is a flow chart of a graph data classification method in this specification, which specifically includes the following steps:

[0137] S300: Acquire each to-be-classified graph data, and determine the shortest path corresponding to each to-be-classified graph data by the above-mentioned shortest path determination method based on nonlinear weight mapping of memristor.

[0138] Similarly, all steps in the graph data classification method provided in this specification can be implemented by any electronic device with computing functions, such as a terminal, a server, etc. For the sake of ease of description, the graph data classification method provided in this specification is described below with the server as the execution subject.

[0139] In the graph data classification method provided in this specification, the characteristics of each graph data are determined according to the shortest path of each graph data to classify each graph data.

[0140] Therefore, the server first determines each graph data to be classified, and determines the shortest path corresponding to each graph data to be classified through the shortest path determination method provided above.

[0141] S302: For each graph data to be classified, determine the weights of the edges between the nodes contained in the shortest path corresponding to the graph data to be classified as the lengths of the distances contained in the shortest path corresponding to the graph data to be classified.

[0142] The weight of each edge in the graph data to be classified represents a distance length between two nodes corresponding to each edge. For each graph data to be classified, the server determines the weight of the edge between each node included in the shortest path corresponding to the graph data to be classified as each distance length included in the shortest path corresponding to the graph data to be classified.

[0143] S304: Determine the path feature of the graph data to be classified according to the lengths of each distance included in the shortest path corresponding to the graph data to be classified.

[0144] In one or more embodiments of the present specification, the server uses the distance lengths of the same size as the distance set among the distance lengths contained in the shortest path corresponding to the graph data to be classified. According to the number of distance lengths corresponding to each distance set, the path feature of the graph data to be classified is determined. That is, in this embodiment, each element in the path feature is the number of distance lengths corresponding to each distance set.

[0145] This specification does not limit the specific arrangement of the number of distance lengths corresponding to each distance set in the path feature. The server can arrange the number of distance lengths corresponding to each distance set in order of magnitude to obtain the path feature. The number of distance lengths corresponding to each distance set can also be randomly arranged to obtain the path feature.

[0146] The above method of determining the path feature is not the only one. In one or more embodiments of the present specification, the server may also directly determine the path feature according to the order of the distance lengths of the edges contained in the shortest path corresponding to the graph data to be classified. That is, in the present embodiment, each element in the path feature is the order of the distance lengths of the edges.

[0147] S306: Determine the graph features of each of the graph data to be classified according to the path features of each of the graph data to be classified.

[0148] In one or more embodiments of the present specification, the server may directly use the path features of each to-be-classified graph data as the graph features of each to-be-classified graph data, that is, the server may directly use the path features as the feature representation of the graph data to perform subsequent classification steps.

[0149] In order to improve the accuracy of classification, in one or more embodiments of the present specification, the server determines the similarity between the path feature of each graph data to be classified and the path features of other graph data to be classified, and determines the graph feature of the graph data to be classified according to the determined similarities.

[0150] This specification does not limit the method for determining the similarity, and it can be determined based on cosine similarity, or based on vector distance, etc.

[0151] After the server determines the graph features, it can use the graph features as feature representations of the graph data to perform subsequent classification steps.

[0152] S308: Inputting the graph features of each of the graph data to be classified into a classifier to obtain classification results of each of the graph data to be classified.

[0153] After determining the graph features, the server inputs the graph features of each graph data to be classified into the classifier to obtain the classification results of each graph data to be classified.

[0154] The classifier can be trained according to the following steps.

[0155] First, the server obtains each sample graph data to be trained and the classification label corresponding to each sample graph data. Secondly, according to the method described in steps S300 to S306 above, the graph features of each sample graph data are determined. Then, the graph features of each sample graph data are input into the classifier to be trained to obtain the predicted classification of each sample graph data. The classifier is trained according to the difference between the predicted classification of each sample graph data and the classification label corresponding to each sample graph data.

[0156] Figure 4 A schematic diagram of a shortest path determination device based on nonlinear weight mapping of a memristor provided in this specification, the device includes a hardware circuit, the hardware circuit includes a synaptic array and multiple neuron circuits, the synaptic array is composed of multiple synaptic circuits, the synaptic circuit includes multiple first memristors, the neuron circuit includes a transimpedance amplifier, a second memristor and a load resistor, each first memristor is respectively connected to the input end of the neuron circuit corresponding to itself, and the input end of each synaptic circuit is respectively connected to the output end of the neuron circuit corresponding to each synaptic circuit, specifically including:

[0157] An acquisition module 400 is used to acquire graph data;

[0158] A mapping value determination module 402 is used to determine the input voltage corresponding to the voltage pulse signal to be applied, and for each edge in the graph data, determine the mapping value of the weight of the edge according to the weight of the edge, the input voltage, the threshold conversion voltage of the second memristor, the resistance value of the equivalent resistance of the transimpedance amplifier, the resistance value of the load resistor, and the high resistance value of the second memristor;

[0159] The conductance value setting module 404 is used to determine the mapping value of the weight of each edge in the graph data, determine the neuron circuit corresponding to each node in the graph data, determine the first memristor corresponding to the edge connected to the node among the first memristors included in the synaptic circuit connected to the neuron circuit corresponding to the node, and set the mapping value of the edge connected to the node to the conductance value of the first memristor corresponding to the edge connected to the node;

[0160] The shortest path determination module 406 is used to apply the voltage pulse signal to the hardware circuit, and determine the shortest path according to the activation sequence of each second memristor included in the hardware circuit.

[0161] Optionally, the mapping value determination module 402 is specifically used to determine the resistance sum according to the resistance value of the load resistor and the high resistance value of the second memristor, determine the voltage division ratio of the second memristor according to the ratio of the high resistance value of the second memristor to the resistance sum, determine the mapping parameter of the weight of the edge according to the negative natural exponent value of the weight of the edge, take the product of the mapping parameter, the voltage division ratio, the input voltage and the resistance value of the equivalent resistance of the transimpedance amplifier as the intermediate value, and determine the mapping value of the weight of the edge according to the ratio of the threshold conversion voltage of the second memristor to the intermediate value.

[0162] Optionally, the shortest path determination module 406 is specifically used to take any node in the graph data as the starting node, and start from the next node of the starting node, and sequentially perform the determination process corresponding to each node other than the starting node in the graph data in turn, take the starting node as the target node of the round of determination process, and take the synaptic circuit connected to the neuron circuit corresponding to the target node as the target synaptic circuit of the round of determination process, determine the second memristor activated in the round of determination process according to the conductance value of each first memristor in the target synaptic circuit, and take the node corresponding to the neuron circuit where the second memristor activated in the round of determination process is located as the target synaptic circuit of the round of determination process. The successor node of the target node transmits the voltage pulse signal back to the synaptic circuit connected to the neuron circuit corresponding to the successor node through the output end of the neuron circuit where the second memristor activated in the round of determination process is located, and uses the successor node as the target node of the next round of determination process, and uses the synaptic circuit connected to the neuron circuit corresponding to the successor node as the target synaptic circuit of the next round of determination process, and continues the next round of determination process until the second memristors corresponding to all nodes included in the graph data are activated, and the shortest path is determined according to the starting node and the nodes corresponding to the neuron circuit where the second memristor is located that are sequentially activated in each round of determination process.

[0163] Optionally, the shortest path determination module 406 is specifically used to respectively obtain the inflow currents of the neuron circuits connected to each first memristor in the target synaptic circuit, determine the inflow current with the largest current value among the inflow currents, and correspond the inflow current with the largest current value to the second memristor in the neuron circuit as the second memristor activated in this round of determination process.

[0164] Optionally, the shortest path determination module 406 is specifically used to determine, for each first memristor in the target synaptic circuit, the outflow current of the first memristor according to the product of the conductance value of the first memristor and the input voltage, and the second memristor in the neuron circuit corresponding to the first memristor is used as the memristor to be activated, and the inflow voltage of the memristor to be activated is determined according to the product of the outflow current of the first memristor and the resistance value of the equivalent resistance of the transimpedance amplifier, and the inflow voltage of the memristor to be activated is determined according to the product of the inflow voltage of the memristor to be activated and the voltage divider ratio. Equivalent voltage, determine the activation parameter according to the ratio of the threshold conversion voltage of the second memristor and the equivalent voltage of the memristor to be activated, take the difference between 1 and the activation parameter as a true number, determine the natural logarithm value, determine the activation time of the memristor to be activated according to the natural logarithm value, according to the activation time of the memristor to be activated corresponding to each first memristor in the round of determination process, determine the memristor to be activated with the shortest activation time among the memristors to be activated corresponding to each first memristor, and use the memristor to be activated with the shortest activation time as the second memristor activated in the round of determination process.

[0165] Optionally, the apparatus further comprises a classification module 408;

[0166] The classification module 408 is used to obtain each graph data to be classified, determine the shortest path corresponding to each graph data to be classified through the above-mentioned shortest path determination method based on memristor nonlinear weight mapping, and for each graph data to be classified, determine the weight of the edge between each node contained in the shortest path corresponding to the graph data to be classified as each distance length contained in the shortest path corresponding to the graph data to be classified, determine the path feature of the graph data to be classified according to the each distance length contained in the shortest path corresponding to the graph data to be classified, determine the graph feature of each graph data to be classified according to the path feature of each graph data to be classified, input the graph feature of each graph data to be classified into a classifier, and obtain the classification result of each graph data to be classified.

[0167] Optionally, the classification module 408 is specifically used to take distance lengths of the same size as distance sets among the distance lengths contained in the shortest path corresponding to the graph data to be classified, and determine the path characteristics of the graph data to be classified according to the number of distance lengths corresponding to each distance set.

[0168] Optionally, the classification module 408 is specifically used to determine, for each graph data to be classified, the similarity between the path feature of the graph data to be classified and the path features of other graph data to be classified, and determine the graph feature of the graph data to be classified based on the determined similarities.

[0169] Optionally, the classification module 408 is specifically used to obtain each sample graph data to be trained, and the classification label corresponding to each sample graph data, determine the shortest path corresponding to each sample graph data through the above-mentioned shortest path determination method, and for each sample graph data, determine the weight of the edge between each node contained in the shortest path corresponding to the sample graph data as each distance length contained in the shortest path corresponding to the sample graph data, determine the path feature of the sample graph data according to the each distance length contained in the shortest path corresponding to the sample graph data, determine the graph feature of each sample graph data according to the path feature of each sample graph data, input the graph feature of each sample graph data into the classifier to be trained to obtain the predicted classification of each sample graph data, and train the classifier according to the difference between the predicted classification of each sample graph data and the classification label corresponding to each sample graph data.

[0170] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0171] The above description is only an embodiment of this specification and is not intended to limit this specification. For those skilled in the art, this specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification should be included in the scope of the claims of this application.

Claims

1. A shortest path determination method based on nonlinear weight mapping of memristor, characterized in that: The method is implemented by a hardware circuit, wherein the hardware circuit comprises a synaptic array and a plurality of neuron circuits, wherein the synaptic array is composed of a plurality of synaptic circuits, wherein the synaptic circuit comprises a plurality of first memristors, wherein the neuron circuit comprises a transimpedance amplifier, a second memristor and a load resistor, wherein each first memristor is respectively connected to an input end of a corresponding neuron circuit, and an input end of each synaptic circuit is respectively connected to an output end of a neuron circuit corresponding to each synaptic circuit, and wherein the method comprises: Get graph data; Determine the input voltage corresponding to the voltage pulse signal to be applied, and for each edge in the graph data, determine the resistance sum according to the resistance value of the load resistor and the high resistance value of the second memristor; determine the voltage division ratio of the second memristor according to the ratio of the high resistance value of the second memristor to the resistance sum; determine the mapping parameter of the weight of the edge according to the negative natural exponential value of the weight of the edge; take the product of the mapping parameter, the voltage division ratio, the input voltage and the resistance value of the equivalent resistance of the transimpedance amplifier as the intermediate value; determine the mapping value of the weight of the edge according to the ratio of the threshold conversion voltage of the second memristor to the intermediate value; Determine a mapping value of the weight of each edge in the graph data, determine a neuron circuit corresponding to each node in the graph data, determine a first memristor corresponding to the edge connected to the node among the first memristors included in the synaptic circuit connected to the neuron circuit corresponding to the node, and set the mapping value of the edge connected to the node to the conductance value of the first memristor corresponding to the edge connected to the node; The voltage pulse signal is applied to the hardware circuit, and the shortest path is determined according to the activation sequence of each second memristor included in the hardware circuit.

2. The method according to claim 1, characterized in that Determining the shortest path according to the activation sequence of each second memristor included in the hardware circuit specifically includes: Taking any node in the graph data as a starting node, starting from the node next to the starting node, sequentially performing a round of determination process for each node other than the starting node in the graph data, taking the starting node as a target node of the round of determination process, and taking a synaptic circuit connected to a neuron circuit corresponding to the target node as a target synaptic circuit of the round of determination process; Determine the second memristor activated in the round determination process according to the conductance value of each first memristor in the target synaptic circuit, and use the node corresponding to the neuron circuit where the second memristor activated in the round determination process is located as the successor node of the target node; The voltage pulse signal is transmitted back to the synaptic circuit connected to the neuron circuit corresponding to the successor node through the output end of the neuron circuit where the second memristor activated in the round determination process is located, and the successor node is used as the target node of the next round determination process, and the synaptic circuit connected to the neuron circuit corresponding to the successor node is used as the target synaptic circuit of the next round determination process, and the next round determination process is continued until the second memristors corresponding to all nodes included in the graph data are activated; The shortest path is determined according to the starting node and the nodes corresponding to the neuron circuits where the second memristors activated in sequence in each round of determination process are located.

3. The method according to claim 2, characterized in that Determining, according to the conductance values ​​of the first memristors in the target synaptic circuit, the second memristors activated in the round of determination process specifically include: Respectively obtaining the inflow current of the neuron circuit connected to each first memristor in the target synaptic circuit; Among the inflow currents, determine the inflow current with the largest current value; The inflow current with the largest current value corresponds to the second memristor in the neuron circuit as the second memristor activated in the round determination process.

4. The method according to claim 2, characterized in that Determining, according to the conductance values ​​of the first memristors in the target synaptic circuit, the second memristors activated in the round of determination process specifically include: For each first memristor in the target synaptic circuit, determining an outflow current of the first memristor according to a product of a conductance value of the first memristor and the input voltage; The first memristor corresponds to the second memristor in the neuron circuit as the memristor to be activated; determining an inflow voltage of the memristor to be activated according to a product of an outflow current of the first memristor and a resistance value of an equivalent resistance of the transimpedance amplifier; Determining an equivalent voltage of the memristor to be activated according to a product of an inflow voltage of the memristor to be activated and the voltage division ratio; determining an activation parameter according to a ratio of a threshold conversion voltage of the second memristor to an equivalent voltage of the memristor to be activated; Taking the difference between 1 and the activation parameter as a true number, determining a natural logarithm value; Determining an activation time of the memristor to be activated according to the natural logarithm value; According to the activation time of the to-be-activated memristors corresponding to the first memristors in the round of determination process, among the to-be-activated memristors corresponding to the first memristors, determining the to-be-activated memristor with the shortest activation time; The to-be-activated memristor with the shortest activation time is used as the second memristor activated in this round of determination process.

5. The method according to any one of claims 1 to 4, characterized in that: The method is also used for graph data classification, including: Obtain each to-be-classified graph data, and determine the shortest path corresponding to each to-be-classified graph data by the method described in any one of claims 1 to 4 above; For each graph data to be classified, determine the weight of the edge between each node contained in the shortest path corresponding to the graph data to be classified as the length of each distance contained in the shortest path corresponding to the graph data to be classified; Determine the path characteristics of the graph data to be classified according to the lengths of each distance contained in the shortest path corresponding to the graph data to be classified; Determining the graph features of each of the graph data to be classified according to the path features of each of the graph data to be classified; The graph features of each of the graph data to be classified are input into a classifier to obtain classification results of each of the graph data to be classified.

6. The method according to claim 5, characterized in that Determining the path features of the graph data to be classified according to the lengths of the distances contained in the shortest path corresponding to the graph data to be classified, specifically includes: Among the distance lengths contained in the shortest path corresponding to the graph data to be classified, the distance lengths with the same size are taken as a distance set; According to the number of distance lengths corresponding to each distance set, the path characteristics of the graph data to be classified are determined.

7. The method according to claim 5, characterized in that Determining the graph features of each of the graph data to be classified according to the path features of each of the graph data to be classified specifically includes: For each graph data to be classified, respectively determine the similarity between the path feature of the graph data to be classified and the path features of other graph data to be classified; According to the determined similarities, the graph features of the graph data to be classified are determined.

8. The method according to claim 5, characterized in that The classifier is trained according to the following method, wherein: Obtaining each sample graph data to be trained and a classification label corresponding to each sample graph data; Determine the shortest path corresponding to each sample graph data by the method described in any one of claims 1 to 4 above; For each sample graph data, determine the weight of the edge between each node included in the shortest path corresponding to the sample graph data as the length of each distance included in the shortest path corresponding to the sample graph data; Determine the path characteristics of the sample graph data according to the lengths of each distance contained in the shortest path corresponding to the sample graph data; Determining graph features of each sample graph data according to the path features of each sample graph data; Inputting the graph features of each sample graph data into the classifier to be trained to obtain the predicted classification of each sample graph data; The classifier is trained according to the difference between the predicted classification of each sample graph data and the classification label corresponding to each sample graph data.

9. A shortest path determination device based on nonlinear weight mapping of memristor, characterized in that: The device comprises a hardware circuit, wherein the hardware circuit comprises a synaptic array and a plurality of neuron circuits, wherein the synaptic array is composed of a plurality of synaptic circuits, wherein the synaptic circuit comprises a plurality of first memristors, wherein the neuron circuit comprises a transimpedance amplifier, a second memristor and a load resistor, wherein each first memristor is respectively connected to an input end of a neuron circuit corresponding to itself, and an input end of each synaptic circuit is respectively connected to an output end of a neuron circuit corresponding to each synaptic circuit, wherein the device comprises: Get module, get graph data; A mapping value determination module determines the input voltage corresponding to the voltage pulse signal to be applied, and for the weight of each edge in the graph data, determines the resistance sum according to the resistance value of the load resistor and the high resistance value of the second memristor; determines the voltage division ratio of the second memristor according to the ratio of the high resistance value of the second memristor to the resistance sum; determines the mapping parameter of the weight of the edge according to the negative natural exponential value of the weight of the edge; takes the product of the mapping parameter, the voltage division ratio, the input voltage and the resistance value of the equivalent resistance of the transimpedance amplifier as the intermediate value; determines the mapping value of the weight of the edge according to the ratio of the threshold conversion voltage of the second memristor to the intermediate value; A conductance value setting module determines a mapping value of the weight of each edge in the graph data, determines a neuron circuit corresponding to each node in the graph data, determines a first memristor corresponding to the edge connected to the node among the first memristors included in the synaptic circuit connected to the neuron circuit corresponding to the node, and sets the mapping value of the edge connected to the node to the conductance value of the first memristor corresponding to the edge connected to the node; The shortest path determination module applies the voltage pulse signal to the hardware circuit, and determines the shortest path according to the activation sequence of each second memristor included in the hardware circuit.

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