Display panel and display device

Abstract

The application provides a display panel and a display device; the display panel comprises a substrate and a driving circuit layer; the driving circuit layer comprises a light shielding layer, a first active layer, a first gate layer and a second active layer; by making the light shielding layer comprise a first light shielding part and the first gate layer comprise a first gate of a compensation transistor, the first gate of the compensation transistor is arranged to correspond to an active pattern of the compensation transistor, the first light shielding part is arranged to correspond to an active pattern of a first initialization transistor, the bottom gate of the compensation transistor can be formed by using the first gate layer, the bottom gate of the first initialization transistor can be formed by using the light shielding layer, the distance between the first gate layer and the second active layer is small, the electrical property of the compensation transistor is improved, the space of the light shielding layer is large, the bottom gate of the first initialization transistor arranged on the light shielding layer will not cause a short circuit problem, and thus the yield of the display panel and the electrical property of the oxide thin film transistor are considered.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display devices, the requirements of existing display devices for power consumption and screen ratio are higher and higher. In order to reduce power consumption and improve screen ratio, the existing display devices will adopt Low Temperature Polysilicon Oxide (LTPO) technology. LTPO technology refers to the use of low temperature polysilicon thin film transistor and oxide thin film transistor at the same time, so that the driving circuit takes into account the advantages of low temperature polysilicon thin film transistor and oxide thin film transistor, thereby reducing power consumption and reducing leakage current. However, the existing display devices using LTPO technology have a large number of film layers, and accordingly a large number of mask plates are required, resulting in a complex process and high cost. In order to reduce the number of mask plates, the existing display devices will remove some gate layers and insulating layers, but this will cause the bottom gate of the oxide thin film transistor to be missing, and the photosensitivity and electrical properties of the thin film transistor to be poor. In order to improve the electrical properties of the oxide thin film transistor, the existing technology will use some film layers to form the bottom gate of the oxide thin film transistor, but there will be some problems, for example, the distance between some film layers and the active layer of the oxide thin film transistor is too far, resulting in a small effect of the bottom gate, and the distance between some film layers and the active layer of the oxide thin film transistor is close, but the space of the film layer is limited, which easily leads to short circuit failure.

[0003] Therefore, the existing display devices using LTPO technology have the technical problem of being unable to balance yield and electrical properties of oxide thin film transistors. SUMMARY

[0004] Embodiments of the present application provide a display panel and a display device to solve the technical problem that the existing display devices using LTPO technology are unable to balance yield and electrical properties of oxide thin film transistors.

[0005] Embodiments of the present application provide a display panel, which comprises a substrate and a driving circuit layer arranged on one side of the substrate, the driving circuit layer comprising a pixel driving circuit, the pixel driving circuit comprising a switching transistor, a driving transistor, a compensation transistor and a first initialization transistor, the switching transistor and the driving transistor being connected to a first node; one electrode of the compensation transistor and one electrode of the first initialization transistor being connected to a second node with the driving transistor, and the other electrode of the compensation transistor being connected to a third node with the driving transistor; wherein the driving circuit layer comprises:

[0006] a light shielding layer, the light shielding layer comprising a first light shielding part;

[0007] a first active layer disposed on a side of the light-shielding layer away from the substrate;

[0008] a first gate layer disposed on a side of the first active layer away from the substrate, the first gate layer comprising a first gate of the compensation transistor;

[0009] a second active layer disposed on a side of the first gate layer away from the substrate, the second active layer comprising an active pattern of the compensation transistor and an active pattern of the first initialization transistor;

[0010] wherein the first gate of the compensation transistor is disposed corresponding to the active pattern of the compensation transistor, and the first light-shielding portion is disposed corresponding to the active pattern of the first initialization transistor.

[0011] Meanwhile, the application provides a display device comprising the display panel as described in any of the above embodiments.

[0012] Beneficial effects: the application provides a display panel and a display device; the display panel comprises a substrate and a driving circuit layer, the driving circuit layer comprises a light-shielding layer, a first active layer, a first gate layer and a second active layer, by making the light-shielding layer comprise a first light-shielding portion and the first gate layer comprise a first gate of a compensation transistor, the first gate of the compensation transistor is disposed corresponding to an active pattern of the compensation transistor, and the first light-shielding portion is disposed corresponding to an active pattern of the first initialization transistor, then the first gate layer can be used to form a bottom gate of the compensation transistor, and the light-shielding layer can be used to form a bottom gate of the first initialization transistor, since the first gate layer is relatively close to the second active layer, the electrical property of the compensation transistor is improved, and since the light-shielding layer has a large space, the bottom gate of the first initialization transistor disposed on the light-shielding layer will not cause a short circuit problem, thereby taking into account the yield of the display panel and the electrical property of the oxide thin film transistor. BRIEF DESCRIPTION OF DRAWINGS

[0013] The technical solutions and other beneficial effects of the application will be apparent from the following detailed description of the specific embodiments of the application, combined with the accompanying drawings.

[0014] Figure 1 A first comparative display device provided by an embodiment of the application.

[0015] Figure 2 A second comparative display device provided by an embodiment of the application.

[0016] Figure 3 A third comparative display device provided by an embodiment of the application.

[0017] Figure 4 A film layer schematic diagram of a display panel provided by an embodiment of the application.

[0018] Figure 5 A circuit diagram of a pixel driving circuit of a display panel provided for an embodiment of the present application.

[0019] Figure 6 A stack diagram of each film layer of a display panel provided for an embodiment of the present application.

[0020] Figure 7 A display panel in Figure 6 A display panel in

[0021] Figure 8 A display panel in Figure 6 A display panel in

[0022] Figure 9 A display panel in Figure 6 A display panel in

[0023] Figure 10 A display panel in Figure 6 A display panel in

[0024] Figure 11 A display panel in Figure 6 A display panel in

[0025] Figure 12 A display panel in Figure 6 A display panel in

[0026] Figure 13 A display panel in Figure 6 A display panel in

[0027] Figure 14 A display panel in Figure 6 A display panel in

[0028] Figure 15 A display panel in Figure 6 A display panel in

[0029] Figure 16 A display panel in Figure 6 A display panel in

[0030] Figure 17 A display panel in Figure 6 A display panel in DETAILED DESCRIPTION

[0031] In the description of the application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application. In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0032] In the description of the application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application. In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0033] In the description of the application, it should be understood that the terms "installation", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0034] In the present application, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature to the second feature can include the direct contact of the first and second features, or the contact of the first and second features through another feature between them. Moreover, the "upper", "upper" and "upper" of the first feature to the second feature include the vertical direction of the first feature above and oblique above the second feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The "below", "below" and "below" of the first feature to the second feature include the vertical direction of the first feature below and oblique below the second feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0035] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplifying the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0036] Figure 1 The first schematic diagram of the contrast display device provided for the embodiment of the present application. Figure 2 The second schematic diagram of the contrast display device provided for the embodiment of the present application. Figure 3 The third schematic diagram of the contrast display device provided for the embodiment of the present application.

[0037] As shown in Figures 1 to 3 , as an introduction to the embodiment of the present application, some contrast display devices are provided to illustrate the principle of the technical problem to be solved by the embodiment of the present application. As shown in Figure 1 , a contrast display device using LTPO technology includes a substrate 101, a light shielding film 102, a barrier film 103, a buffer film 104, a low-temperature polysilicon film 105, a first gate insulating film 106, a first gate film 107, a second gate insulating film 108, a second gate film 109, a first interlayer insulating film 111, an oxide semiconductor film 112, a third gate insulating film 113, a third gate film 114, a second interlayer insulating film 115, a first source-drain film 116, a first planarization film 117, a second source-drain film 118, a second planarization film 119, a third source-drain film 121, a third planarization film 122, an anode film 123, a pixel definition film 124, and a support film 125. As can be seen from Figure 1 , the contrast display device includes three layers of source-drain films and three layers of gate films, so that the contrast display device needs to use 16 mask plates to form, the process is relatively complex, and the cost is relatively high.

[0038] In order to solve the problem of complex process of the contrast display device, another contrast display device removes one of the gate films and the insulating film, as shown in Figure 2 , it can be seen that the second gate film 109 and the second gate insulating film 108 are removed from the contrast display device, which can reduce the number of mask plates to 14, but still has the problem of too many mask plates, complex process, and high cost.

[0039] To further address the complex manufacturing process of contrast display devices, another type of contrast display device removes an additional source / drain film and insulating film, such as... Figure 3 As shown, by removing the third source / drain film 121 and the third planarization film 122, the number of mask layers can be reduced to 13; however, from Figure 2 , Figure 3 As can be seen, the lack of shielding under the oxide semiconductor film 112 leads to the absence of the bottom gate of the oxide thin film transistor, resulting in a deterioration in the photosensitivity and electrical properties of the thin film transistor.

[0040] In order to solve Figure 3 The comparative display devices shown exhibit a problem with missing bottom gates in oxide thin-film transistors (OTPs). Some comparative devices use a light-shielding film to form the bottom gate of the OTPs, enabling the transmission of signals from the high-potential power supply or the scan lines connected to the OTPs. However, due to the large distance between the light-shielding film and the oxide semiconductor film, the bottom gate effect is weak, resulting in poor electrical performance of the OTPs. In other comparative display devices, a first gate film is used to form the bottom gate of the OTPs. However, in these devices, both the scan lines and gate drive circuit signal lines are formed using the first gate film, which contains a large number of traces. Adding a bottom gate for the OTPs in this case is difficult. Since the bottom gate of the compensation transistor needs to be connected to the output of the gate drive circuit, this trace is prone to short-circuiting with other signal lines in the first gate film, leading to display failure. Therefore, existing display devices using LTPO technology suffer from a technical problem where both yield and the electrical performance of the OTPs cannot be simultaneously achieved.

[0041] This application provides a display panel and a display device to address the aforementioned technical problems.

[0042] Figure 4 This is a schematic diagram of the film layer of the display panel provided in an embodiment of this application. Figure 5 A circuit diagram of the pixel driving circuit of the display panel provided in an embodiment of this application. Figure 6 This is a stacked diagram of the various film layers of the display panel provided in the embodiments of this application. Figure 7 for Figure 6 An exploded view of the light-shielding layer of the display panel. Figure 8 for Figure 6 An exploded view of the first active layer of the display panel. Figure 9 for Figure 6 An exploded view of the first gate layer of the display panel. Figure 10 for Figure 6 An exploded view of the second active layer of the display panel. Figure 11 forFigure 6 exploded view of a second gate layer of the display panel in Figure 12 is Figure 6 exploded view of a first source-drain layer of the display panel in Figure 13 is Figure 6 exploded view of a second source-drain layer of the display panel in Figure 14 is Figure 6 exploded view of a first via of the display panel in Figure 15 is Figure 6 exploded view of a second via of the display panel in Figure 16 is Figure 6 exploded view of a third via of the display panel in Figure 17 is Figure 6 exploded view of a fourth via of the display panel in

[0043] As Figures 4 to 17 shown in the embodiments of the present application, a display panel 2 includes a substrate 201 and a driving circuit layer 22, the driving circuit layer 22 is arranged on one side of the substrate 201, the driving circuit layer 22 includes a light shielding layer 202, a first active layer 205, a first gate layer 207 and a second active layer 209, the light shielding layer 202 is arranged between the substrate 201 and the first active layer 205, the first active layer 205 is arranged between the light shielding layer 202 and the first gate layer 207, and the driving circuit layer 22 further includes a pixel driving circuit 31.

[0044] The pixel driving circuit 31 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3 and a first initialization transistor T4, the switching transistor T2 and the driving transistor T1 are connected to a first node A, one electrode of the compensation transistor T3 and one electrode of the first initialization transistor T4 are connected to a second node Q, and the other electrode of the compensation transistor T3 is connected to a third node B.

[0045] The second active layer 209 includes an active pattern T3A of the compensation transistor T3 and an active pattern T4A of the first initialization transistor T4, the light shielding layer 202 includes a first light shielding part 202a, the first gate layer 207 includes a first gate T3Ga of the compensation transistor T3, the first gate T3Ga of the compensation transistor T3 is arranged corresponding to the active pattern T3A of the compensation transistor T3, and the first light shielding part 202a is arranged corresponding to the active pattern of the first initialization transistor T4.

[0046] The display panel provided by the embodiments of the present application comprises a substrate and a driving circuit layer, the driving circuit layer comprises a light shielding layer, a first active layer, a first gate layer and a second active layer, the light shielding layer comprises a first light shielding part, the first gate layer comprises a first gate of a compensation transistor, the first gate of the compensation transistor is arranged corresponding to an active pattern of the compensation transistor, the first light shielding part is arranged corresponding to an active pattern of the first initialization transistor, the bottom gate of the compensation transistor can be formed by using the first gate layer, the bottom gate of the first initialization transistor can be formed by using the light shielding layer, the distance between the first gate layer and the second active layer is small, the electrical property of the compensation transistor is improved, the space of the light shielding layer is large, the bottom gate of the first initialization transistor arranged on the light shielding layer will not cause short circuit, and the yield of the display panel and the electrical property of the oxide thin film transistor are considered.

[0047] Specifically, in the embodiments of the present application, the light shielding part arranged corresponding to the active pattern of the transistor means that the light shielding part is arranged corresponding to at least the channel part of the transistor, the projection of the light shielding part on the substrate overlaps the projection of the channel part of the transistor on the substrate, it can be understood that the active pattern of each transistor comprises a doped part and a channel part, the channel part is easily affected by light to cause performance change, and the electrode arranged corresponding to the channel part can improve the gate control ability, therefore, the light shielding part can be arranged corresponding to the channel part of the transistor, specifically, for example, the first light shielding part arranged corresponding to the active pattern of the first initialization transistor means that the first light shielding part is arranged corresponding to at least the channel part of the first initialization transistor. Similarly, the first gate of the compensation transistor arranged corresponding to the active pattern of the compensation transistor means that the first gate of the compensation transistor is arranged corresponding to at least the channel part of the compensation transistor.

[0048] Specifically, compared with the case that the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor are respectively formed by the light shielding film in the comparative display device, and the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor are respectively input with the corresponding scan signal or the high potential power signal line, the distance of the bottom gate is far, and the effect of the bottom gate is weak. Compared with the case that the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor are respectively formed by the first gate film in the comparative display device, and the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor are respectively input with the corresponding scan signal, the space of the first gate film is small and difficult to realize, and short circuit is prone to occur. The embodiment of the present application considers that the electrical property of the compensation transistor has a greater impact on the display panel, and is particularly related to the characteristics of the display panel such as image sticking, flicker, service life, optical characteristics, and the function of the first initialization transistor is to reset the second node Q. Therefore, the bottom gate of the compensation transistor is formed by the first gate layer, the first light shielding part is formed by the light shielding layer, and the first light shielding part is arranged corresponding to the active pattern of the first initialization transistor, so that the space of the first gate layer and the light shielding layer can be considered to avoid short circuit, the electrical property of the compensation transistor is good, the characteristics of the display panel are good, and the yield of the display panel and the electrical property of the oxide thin film transistor are considered. In order to further avoid the short circuit problem caused by too many wires in each film layer, improve the electrical property of each wire and each electrode, the position of each wire, each connecting line and via hole is further designed, and the specific design is as follows.

[0049] Specifically, as shown in Figure 4 It can be seen that the driving transistor T1 uses part of the light shielding layer for light shielding, the compensation transistor T3 uses part of the first gate layer as the bottom gate of the compensation transistor, and the active pattern of the first initialization transistor T4 is arranged corresponding to part of the light shielding layer.

[0050] Specifically, the light shielding layer 202 is arranged on one side of the substrate 201, the first active layer 205 is arranged on the side of the light shielding layer 202 away from the substrate 201, the first gate layer 207 is arranged on the side of the first active layer 205 away from the light shielding layer 202, and the second active layer 209 is arranged on the side of the first gate layer 207 away from the first active layer 205.

[0051] In some embodiments, as shown in Figures 4 to 8As shown, the driving circuit layer 22 includes a plurality of repeating units 30 arranged in an array, each of the repeating units 30 includes two pixel driving circuits 31 arranged symmetrically, and in the repeating unit 30, the light shielding layer 202 further includes two second light shielding portions 202b and a connecting portion 202c arranged symmetrically in the corresponding regions of the two pixel driving circuits 31, the connecting portion 202c includes a first connecting portion 321 arranged along the first direction X, a second connecting portion 322 arranged along the first direction X, and a third connecting portion 323 arranged along the second direction Y, the first active layer 205 includes an active pattern T1A of a driving transistor T1, the second light shielding portion 202b is arranged correspondingly to the active pattern T1A of the driving transistor T1, the first connecting portion 321 connects adjacent first light shielding portions 202a, the second connecting portion 322 connects adjacent second light shielding portions 202b, one end of the third connecting portion 323 is connected to the first light shielding portion 202a, and the other end of the third connecting portion 323 is connected to the second light shielding portion 202b; the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. By making the light shielding layer further include the second light shielding portion and the connecting portion, and making the connecting portion include the first connecting portion, the second connecting portion, and the third connecting portion, the first connecting portion connects adjacent first light shielding portions, the second connecting portion connects adjacent second light shielding portions, one end of the third connecting portion is connected to the first light shielding portion, and the other end of the third connecting portion is connected to the second light shielding portion, thereby achieving the meshing of the light shielding layer, improving the electrical properties of the light shielding layer, and the first light shielding portion can serve as the bottom gate of the first initialization transistor, thereby improving the electrical properties of the first initialization transistor.

[0052] Specifically, it can be understood that the display panel includes a plurality of repeating units arranged in an array, and the pixel driving circuit in each repeating unit can refer to the design of a repeating unit described in the embodiments of the present application.

[0053] Specifically, it can be understood that in the display panel, two adjacent pixel units are arranged symmetrically to improve the aperture ratio, and in the embodiments of the present application, the light shielding portion is arranged symmetrically, and the first connecting portion, the second connecting portion, and the third connecting portion are arranged to connect the light shielding portions in each row and each column, thereby achieving the mesh structure of the light shielding layer, so that the voltage drops of each part of the light shielding layer are similar or even the same when signal input is performed, thereby improving the uniformity of the signal and improving the display effect.

[0054] Specifically, it can be understood that in order to illustrate the specific design of a film layer or a structure, the parts are named separately, but it can be understood that a plurality of parts of a film layer or a structure are formed at the same time, and when they are connected together, the same signal is transmitted, and they belong to the same structure. For example, as shown in the above embodiments, the first light shielding portion 202a and the second light shielding portion 202b are connected by the connecting portion 202c, and the first light shielding portion 202a and the second light shielding portion 202b are connected by the third connecting portion 323. In fact, the first light shielding portion 202a, the second light shielding portion 202b, the connecting portion 202c, and the third connecting portion 323 can be regarded as the same structure, and the same name can be used. Figure 7As shown, the first light shielding part 202a, the second light shielding part 202b, the first connecting part 321, the second connecting part 322, and the third connecting part 323 in the light shielding layer 202 are actually multiple parts of the same structure, and the light shielding parts and the connecting parts in the two repeating units are also multiple parts of the same structure, and each part is connected to each other. Without considering the voltage drop, the multiple parts of the same structure transmit the same signal, and the same name can be used, for example, each part can be named as a light shielding part. Similarly, for other film layers and other structures, please refer to the above description, which will not be repeated in the following embodiments.

[0055] Specifically, the second light shielding part can transmit the signal of the high potential power line, and the second light shielding part can be connected with the high potential power line.

[0056] Specifically, the first light shielding part can be used as the bottom gate of the first initialization transistor.

[0057] Specifically, as shown, Figure 7 As shown, it can be seen that the second light shielding part 202b in each repeating unit can be connected through the second connecting part 322, but the first light shielding part 202a in each repeating unit can not be connected.

[0058] In some embodiments, the light shielding layer 202 further includes a second light shielding part 202b, the first active layer 205 includes an active pattern T1A of a driving transistor T1, the second light shielding part 202b is arranged corresponding to the active pattern T1A of the driving transistor T1, and the first light shielding part 202a is arranged spaced apart from the second light shielding part 202b. By arranging the first light shielding part and the second light shielding part spaced apart, the first light shielding part can transmit the signal line of the scan line connected to the gate of the first initialization transistor, thereby improving the gate control ability of the first initialization transistor.

[0059] Specifically, when the first light shielding part and the second light shielding part are arranged in the light shielding layer, the first light shielding part and the second light shielding part can be arranged spaced apart, the first light shielding part and the second light shielding part transmit different signals, the first light shielding part transmits the signal of the scan line connected to the gate of the first initialization transistor, the first light shielding part is used as the bottom gate of the first initialization transistor, the electrical property of the first initialization transistor is improved, and the second light shielding part shields the active pattern of the driving transistor to prevent the active pattern of the driving transistor from being affected by light.

[0060] Specifically, the first light shielding part can be connected with the third scan signal line, the second light shielding part can transmit the signal of the high potential power line, and the second light shielding part can be connected with the high potential power line.

[0061] In some embodiments, the driving circuit layer 22 includes a plurality of pixel driving circuits 31 arranged in an array. A first light-shielding portion 202a is disposed along a first direction X in a corresponding area of ​​the pixel driving circuit 31, and a second light-shielding portion 202b is disposed along the first direction X in a corresponding area of ​​the pixel driving circuit 31. Along the first direction X, the first light-shielding portions 202a located in two adjacent pixel driving circuits 31 are connected, and the second light-shielding portions 202b located in two adjacent pixel driving circuits 31 are connected. The driving circuit layer 22 also includes a scan signal line (e.g., a first scan signal line Pscan), and the first direction X is the same as the setting direction of the scan signal line. By arranging the first light-shielding portion along the first direction and connecting the first light-shielding portions in two adjacent pixel driving circuits, and arranging the second light-shielding portion along the first direction and connecting the second light-shielding portions in two adjacent pixel driving circuits, rows of first light-shielding portions and rows of second light-shielding portions can be connected. This reduces the number of connections between the first light-shielding portion and the signal terminal, reduces the number of connections between the second light-shielding portion and the signal terminal, reduces vias in the display panel, and improves the stability of the display panel.

[0062] Specifically, the above embodiments are illustrated using the connection of light-shielding parts in different pixel driving circuits as an example. However, the embodiments of this application are not limited to this. The light-shielding parts in the corresponding areas of different pixel driving circuits can be set independently and are not connected.

[0063] In some embodiments, such as Figure 5 As shown, the gate of the switching transistor T2 is connected to the first scan signal line Pscan, the first electrode of the switching transistor T2 is connected to the data line DATA, and the second electrode of the switching transistor T2 is connected to the first electrode of the driving transistor T1 at the first node A; the gate of the compensation transistor T3 is connected to the second scan signal line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1; the gate of the first initialization transistor T4 is connected to the third scan signal line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node Q; the pixel driving circuit 31 further includes:

[0064] The first light-emitting control transistor T5 has its gate connected to the light-emitting control signal line EM, its first electrode connected to the high-potential power supply line VDD, and its second electrode connected to the first electrode of the driving transistor T1 at the first node A.

[0065] a second light emitting control transistor T6, a gate of the second light emitting control transistor T6 being connected with a light emitting control signal line EM, a first electrode of the second light emitting control transistor T6 being connected with a second electrode of the driving transistor T1 at a third node B;

[0066] a second initialization transistor T7, a gate of the second initialization transistor T7 being connected with a fourth scan signal line Pscan2, a first electrode of the second initialization transistor T7 being connected with a second initialization signal line VI-ANO, a second electrode of the second initialization transistor T7 being connected with a second electrode of the second light emitting control transistor T6 at a fourth node C;

[0067] a third initialization transistor T8, a gate of the third initialization transistor T8 being connected with the fourth scan signal line Pscan2, a first electrode of the third initialization transistor T8 being connected with a third initialization signal line VI3, a second electrode of the third initialization transistor T8 being connected with a first electrode of the driving transistor T1 at a first node A;

[0068] a storage capacitor Cst, one plate of the storage capacitor Cst being connected with the high potential power supply line VDD, the other plate of the storage capacitor Cst being connected with a gate of the driving transistor T1 at a second node Q;

[0069] a boost capacitor Cboost, one plate of the boost capacitor Cboost being connected with the first scan signal line, the other plate of the boost capacitor being connected with a second electrode of the first initialization transistor.

[0070] Specifically, as shown in Figure 4 , Figure 5 the display panel 2 further includes a light emitting layer 23, the light emitting layer 23 including a light emitting device LED, the light emitting device LED being connected with the pixel driving circuit, a positive electrode of the light emitting device LED being connected with a second electrode of the second initialization transistor T7, a negative electrode of the light emitting device LED being connected with the low potential power supply line VSS.

[0071] In some embodiments, as shown in Figure 4As shown, the driving circuit layer 22 further comprises a second gate layer 212, a first source-drain layer 214 and a second source-drain layer 216, the second active layer 209 is disposed between the first gate layer 207 and the second gate layer 212, the second gate layer 212 is disposed between the second active layer 209 and the first source-drain layer 214, and the first source-drain layer 214 is disposed between the second gate layer 212 and the second source-drain layer 216. By making the driving circuit layer comprise a first gate layer, a second gate layer, a first source-drain layer and a second source-drain layer, the process steps of the display panel can be reduced, and the mask plate required for forming the display panel can be reduced.

[0072] In some embodiments, as shown in Figure 4 、 Figure 6 、 Figure 8 As shown, the first active layer 205 comprises an active pattern T1A of a driving transistor T1, an active pattern T2A of a switching transistor T2, an active pattern T5A of a first light-emitting control transistor T5, an active pattern T6A of a second light-emitting control transistor T6, an active pattern T7A of a second initialization transistor T7 and an active pattern T8A of a third initialization transistor T8, the active pattern T1A of the driving transistor T1 is disposed along a first direction X, and the active pattern T1A of the driving transistor T1 is connected to the active pattern T2A of the switching transistor T2, the active pattern T5A of the first light-emitting control transistor T5 and the active pattern T6A of the second light-emitting control transistor T6, the active pattern T2A of the switching transistor T2 and the active pattern T5A of the first light-emitting control transistor T5 are disposed along a second direction Y, the active pattern T6A of the second light-emitting control transistor T6 and the active pattern T7A of the second initialization transistor T7 are disposed along the second direction Y, and the active pattern T6A of the second light-emitting control transistor T6 and the active pattern T7A of the second initialization transistor T7 are connected, the active pattern T8A of the third initialization transistor T8 is spaced apart from the active pattern T1A of the driving transistor T1, the active pattern T2A of the switching transistor T2, the active pattern T5A of the first light-emitting control transistor T5, the active pattern T6A of the second light-emitting control transistor T6 and the active pattern T7A of the second initialization transistor T7; the included angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0073] In some embodiments, as shown in Figures 4 to 6 、 Figure 9As shown, the first gate layer 207 includes a first scan signal line Pscan, a first plate Cst1 of a storage capacitor Cst, an emission control signal line EM, a fourth scan signal line Pscan2, a first initialization connection line L1, a gate T1G of a driving transistor T1, a gate T2G of a switching transistor T2, a gate T5G of a first emission control transistor T5, a gate T6G of a second emission control transistor T6, a gate T7G of a second initialization transistor T7, and a gate T8G of a third initialization transistor T8; the first scan signal line Pscan, the first gate T3Ga of the compensation transistor T3, the first plate Cst1 of the storage capacitor Cst, the emission control signal line EM, the fourth scan signal line Pscan2, and the first initialization connection line L1 are sequentially and spaced apart along the second direction Y. By arranging the first gate of the compensation transistor in the first gate layer, the first gate of the compensation transistor is arranged between the first plate of the storage capacitor and the first scan signal line, so that the spacing between the first gate of the compensation transistor and other electrodes is large, avoiding short circuit between the compensation transistor and other electrodes, and improving the yield of the display panel.

[0074] Specifically, as can be seen from Figure 9 It can be understood that, since the gates T2G of all switching transistors T2 in a row of pixel units are connected to the same first scan signal line Pscan, when the first scan signal line Pscan is formed, the part of the first scan signal line corresponding to the channel of the switching transistor T2 of each pixel unit serves as the gate of the switching transistor T2 of each pixel unit, so the same structure is identified by two labels. Similarly, the gate T1G of the driving transistor T1 serves as both the gate and the first plate Cst1 of the storage capacitor Cst, the part of the emission control signal line EM corresponding to the channel of the first emission control transistor T5 serves as the gate T5G of the first emission control transistor T5, the part of the emission control signal line EM corresponding to the channel of the second emission control transistor T6 serves as the gate T6G of the second emission control transistor T6, the part of the fourth scan signal line Pscan2 corresponding to the channel of the second initialization transistor T7 serves as the gate T7G of the second initialization transistor T7, and the part of the fourth scan signal line Pscan2 corresponding to the channel of the third initialization transistor T8 serves as the gate T8G of the third initialization transistor T8.

[0075] In some embodiments, as Figure 10As shown in FIG. 6, the second active layer 209 further includes a second plate Cst2 of the storage capacitor Cst, the active pattern T3A of the compensation transistor T3 is connected with the active pattern T4A of the first initialization transistor T4, the second plate Cst2 of the storage capacitor Cst is arranged on one side of the active pattern T3A of the compensation transistor T3 along the first direction X, and a via hole 331 is arranged on the second plate Cst2 of the storage capacitor Cst. By arranging the second active layer to form the second plate of the storage capacitor, the storage capacitor can be arranged in the pixel driving circuit, and the via hole arranged on the second plate of the storage capacitor enables the first electrode of the compensation transistor to be normally connected to the gate of the driving transistor.

[0076] Specifically, it can be understood that the second active layer forms the second plate of the storage capacitor, and thus the second plate of the storage capacitor needs to have good electrical properties. The second plate of the storage capacitor can be doped to keep the electrical properties of the second plate of the storage capacitor consistent with or even better than the electrical properties of the doped part of the active pattern, so that the electrical properties of the storage capacitor are good.

[0077] Specifically, by arranging the via hole on the second plate of the storage capacitor, the first electrode of the compensation transistor can pass through the second plate of the storage capacitor to be connected to the gate of the driving transistor, so that the pixel driving circuit can normally work.

[0078] Specifically, as shown in FIG. 6 and FIG. 7, Figure 9 , Figure 10 As shown in FIG. 6 and FIG. 7, the first gate layer 207 further includes a first plate Cboost1 of a boost capacitor Cboost, the second active layer 209 further includes a second plate Cboost2 of the boost capacitor Cboost, the overlapping part of the first scan signal line Pscan and the active pattern T4A of the first initialization transistor T4 is the first plate Cboost1 of the boost capacitor Cboost, and the overlapping part of the active pattern T4A of the first initialization transistor T4 and the first scan signal line Pscan is the second plate Cboost2 of the boost capacitor Cboost.

[0079] In some embodiments, as shown in FIG. 6 and FIG. 7, Figures 4 to 6 , Figure 11 As shown in FIG. 6 and FIG. 7, the second gate layer 212 includes a second scan signal line Nscan1, a third scan signal line Nscan2, a second initialization signal line VI-ANO, a second gate T3Gb of the compensation transistor T3, and a gate T4G of the first initialization transistor T4, and the third scan signal line Nscan2, the second scan signal line Nscan1, and the second initialization signal line VI-ANO are sequentially arranged along the second direction Y.

[0080] Specifically, the projection of the first light-shielding part on the substrate can overlap with the projection of the third scan signal line on the substrate, thereby reducing the coupling capacitance between the first light-shielding part and other signal lines. Even if the first light-shielding part is coupled to the third scan signal line, since the first light-shielding part is correspondingly set with the active pattern of the first initialization transistor, the potential of the first light-shielding part can be the potential of the third scan signal line, which can improve the gate control capability of the first initialization transistor.

[0081] Specifically, the first light-shielding part can be regarded as the first gate of the first initialization transistor, and correspondingly, the gate of the first initialization transistor located in the second gate layer is the second gate of the first initialization transistor.

[0082] Specifically, the projection of the first gate of the compensation transistor on the substrate can overlap with the projection of the second scan signal line on the substrate, thereby reducing the coupling capacitance between the first gate of the compensation transistor and other signal lines. When the first gate of the compensation transistor is coupled to the second scan signal line, both transmit the drive signal of the gate of the compensation transistor, which can improve the gate control capability of the first initialization transistor.

[0083] In some embodiments, such as Figures 4 to 6 , Figure 12 As shown, the first source-drain layer 214 includes a first initialization signal line VI-G, a first electrode T4S of switching transistor T2, a second electrode T2D of switching transistor T2, a first electrode T3S of compensation transistor T3, a second electrode T3D of compensation transistor T3, a first electrode T4S of first initialization transistor T4, a second electrode T4D of first initialization transistor T4, a first electrode T5S of first light-emitting control transistor T5, a second electrode T5D of first light-emitting control transistor T5, a first electrode T6S of second light-emitting control transistor T6, a second electrode T6D of second light-emitting control transistor T6, and a first electrode T7 of second initialization transistor T7. The system includes a first electrode T7S, a second electrode T7D of the second initialization transistor T7, a first electrode T8S of the third initialization transistor T8, a second electrode T8D of the third initialization transistor T8, a first adapter line L2, a first data connection line L3, a second adapter line L4, and a third initialization signal line VI3. The first adapter line L2 is connected to the first gate T3Ga of the compensation transistor T3 and the second scan signal line Nscan1. The second adapter line L4 is connected to the second initialization signal line VI-ANO and the first electrode T7S of the second initialization transistor T7. The third initialization signal line VI3 is connected to the first initialization connection line L1.

[0084] Specifically, the first gate of the compensation transistor is formed in the first gate layer, the second scan signal line is formed in the third gate layer, and the first transfer line is formed in the first source-drain layer. The first transfer line is connected to the second scan signal line and the first gate by close-range double punching, so that space can be saved, and the two sub-pixel units can share the same first transfer line and via hole, reducing the number of via holes, saving space, and improving the pixel density.

[0085] Specifically, the third initialization signal line is formed in the first source-drain layer, and the third initialization signal line is connected to the first initialization connection line, so that the connection of one row of third initialization signal lines is realized, and multiple input terminals are not required for signal input.

[0086] Specifically, as shown in Figure 12 , it can be understood that the electrodes of the transistors are connected together, but in actual design, in order to improve the aperture ratio, the electrodes of the transistors share the same structure, so in Figure 12 , the same structure is identified by multiple labels, for example, a structure is both the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4, and from Figure 5 , it can be seen that this is the position connected by the second node Q. Similarly, other structures can also be multiple electrodes, and the positions of the nodes can be determined accordingly.

[0087] Specifically, since some electrodes and / or signal lines are connected together, a structure may only be marked with one electrode or one signal line. It can be understood that the structure can also be other electrodes or signal lines connected to the electrode or signal line.

[0088] In some embodiments, as shown in Figures 4 to 6 , Figure 13 , the driving circuit layer 22 includes a plurality of repeating units 30 arranged in an array, each of the repeating units 30 includes two pixel driving circuits 31 arranged symmetrically, in the repeating unit 30, the second source-drain layer 216 includes two second data connection lines L5, two data lines DATA, two high-potential power supply lines VDD, and a second initialization connection line L6, the two second data connection lines L5 are arranged symmetrically, and the second data connection line L5 is provided with a break, the two data lines DATA are arranged symmetrically, the two high-potential power supply lines VDD are arranged symmetrically, and the second initialization connection line L6 is connected to the second initialization signal line VI-ANO.

[0089] Specifically, by providing a second initialization connection line in the second source-drain layer, the second initialization signal line is connected to the second initialization connection line, so that the grid of the second initialization signal line can be realized, and the voltage drop of the second initialization signal line can be reduced.

[0090] Specifically, it can be understood that due to the design of the partial pixel driving circuit in the display area shown in the embodiments of the present application, the connection of part of the wires can be located in other pixel driving circuits or outside the display area, so that part of the wires may not be connected together, but in fact, there will be a connection, for example, the data line DATA will be connected with part of the data lines by setting the fanout line in the display area (Fanout In AA, FIAA) technology, and the first data connection line L3 arranged along the first direction and the second data connection line L5 arranged along the second direction will be set, but the embodiments of the present application show the design of the partial pixel driving circuit, so the connection thereof is not shown, but in fact, there will be a connection.

[0091] Specifically, as shown in Figure 6 , Figure 10 , Figure 12 , Figure 13 , the first source-drain layer 214 further includes a first connection end K1 and a second connection end K2, the high-potential power supply line VDD is connected with the first connection end K1, the first connection end K1 is connected with the second connection end K2, and the second connection end K2 is connected with the second plate Cst2 of the storage capacitor Cst and the first electrode T5S of the first light-emitting control transistor T5, so as to realize the connection of the high-potential power supply line with the second plate of the storage capacitor and the first electrode of the first light-emitting control transistor. Since the high-potential power supply line and the first electrode of the first light-emitting control transistor do not overlap, and the high-potential power supply line cannot be directly punched and connected to the second plate of the storage capacitor due to the existence of other signal lines, the embodiments of the present application set the first connection end and the second connection end in the first source-drain layer, and connect the high-potential power supply line and the second plate of the storage capacitor through the first connection end and the second connection end, respectively, so as to realize the connection of the high-potential power supply line, the second plate of the storage capacitor and the first electrode of the first light-emitting control transistor.

[0092] Specifically, as shown in Figures 5 to 12 , the first source-drain layer 214 further includes a third connection end K3, and the first electrode T3S of the compensation transistor T3 is connected with the gate T1G of the driving transistor T1, so that the third connection end K3 can be set in the first source-drain layer, and the third connection end K3 is connected with the gate T1G of the driving transistor T1 through the through hole 331, so as to realize the connection of the gate of the driving transistor T1 and the first electrode T3S of the compensation transistor T3.

[0093] Specifically, as shown in Figures 5 to 13 , the second source-drain layer 216 further includes a fourth connection end K4, and the fourth connection end K4 is connected with the second electrode T6D of the second light-emitting control transistor T6 and one electrode of the light-emitting device.

[0094] Specifically, since the active parts of some transistors are connected together, some nodes and electrodes in the circuit diagram are not shown, for example, the first node A is a connection node of the first electrode of the driving transistor T1, the second electrode of the switch transistor T2 and the second electrode of the first light emitting control transistor T5, and the active parts of the driving transistor T1, the switch transistor T2 and the first light emitting control transistor T5 share the same structure, so the first electrode of the driving transistor T1, the second electrode of the switch transistor T2 and the second electrode of the first light emitting control transistor T5 do not need to be separately provided, and accordingly, the first node A does not exist in the exploded view of each film layer. It can be understood that the first node A is located at the connection of the active parts of the driving transistor T1, the switch transistor T2 and the first light emitting control transistor T5.

[0095] In some embodiments, as shown in Figure 14 Figure 14 The setting position of the first via hole 341 is shown, and the first via hole 341 refers to a via hole etched from the first source-drain layer to the first active layer or the first gate layer.

[0096] In some embodiments, as shown in Figure 15 Figure 15 The setting position of the second via hole 342 is shown, and the second via hole 342 refers to a via hole etched from the first source-drain layer to the second active layer or the second gate layer.

[0097] In some embodiments, as shown in Figure 16 Figure 16 The setting position of the third via hole 343 is shown, and the third via hole 343 refers to a via hole etched from the second source-drain layer to the first source-drain layer.

[0098] In some embodiments, as shown in Figure 17 Figure 17 The setting position of the fourth via hole 344 is shown, and the fourth via hole 344 refers to a via hole etched from the anode of the light emitting layer to the second source-drain layer.

[0099] In some embodiments, the first light shielding part is connected with the third scan signal line. By connecting the first light shielding part with the third scan signal line, the first light shielding part can serve as the bottom gate of the first initialization transistor, improving the electrical properties of the first initialization transistor.

[0100] Specifically, the first light shielding part and the third scan signal line can be connected through other connection lines, or can be directly connected by punching.

[0101] Specifically, in the above embodiments, when the transistor has a bottom gate and a top gate, the gate of the transistor refers to the first gate and the second gate of the transistor.

[0102] Specifically, as shown in​​​​Figure 4 As shown in FIG. 2, the driving circuit layer 22 further includes a barrier layer 203, a buffer layer 204, a first gate insulating layer 206, a first interlayer insulating layer 208, a second gate insulating layer 211, a second interlayer insulating layer 213, a first planarization layer 215, and a second planarization layer 217.

[0103] Specifically, as shown in FIG. 2, the display panel 2 further includes a light-emitting layer 23, which includes a pixel electrode layer 218, a pixel definition layer 219, a light-emitting material layer, a common electrode layer, and a support column 221. Figure 4

[0104] Specifically, the first electrode of the transistor in the above embodiment is the source electrode, and the second electrode is the drain electrode; or the first electrode of the transistor in the above embodiment is the drain electrode, and the second electrode is the source electrode.

[0105] Specifically, the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light-emitting control signal line EM can be connected to different gate driving circuits, and specifically, five groups of gate driving circuits can be used to output signals to the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light-emitting control signal line EM, respectively. The gate driving circuit connected to the first scan signal line Pscan can be double-side driving, and the other gate driving circuits can be single-side driving.

[0106] Specifically, the material of the first active layer includes a silicon semiconductor material, and specifically can be low-temperature polysilicon.

[0107] Specifically, the material of the second active layer includes an oxide semiconductor material, and specifically can be a metal oxide semiconductor material, and more specifically can be indium gallium zinc oxide.

[0108] Specifically, the material of the light-blocking layer can include a metal material.

[0109] Specifically, the driving transistor, the switching transistor, the first light-emitting control transistor, the second light-emitting control transistor, the second initialization transistor, and the third initialization transistor are P-type transistors, and the first initialization transistor and the compensation transistor are N-type transistors.

[0110] ​Specifically, the pixel driving circuit in the display panel, the film layer structure, the specific structure of each layer, the material, and the potential of the display panel are described in detail in the above embodiments. It can be understood that the embodiments can be combined when there is no conflict between the embodiments. For example, the light shielding layer further includes a second light shielding portion, the first active layer includes an active pattern of a driving transistor, the second light shielding portion is arranged corresponding to the active pattern of the driving transistor, and the first light shielding portion is arranged spaced apart from the second light shielding portion. The first light shielding portion is connected with the third scan signal line.

[0111] Meanwhile, the display device provided by the embodiments of the present application includes the display panel as described in any of the above embodiments.

[0112] In the above embodiments, the description of each embodiment has its own focus. The parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0113] The display panel and the display device provided by the embodiments of the present application are described in detail above. The principle and implementation of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core idea thereof. Those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents. The modification or replacement does not change the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, The substrate and the driving circuit layer arranged on one side of the substrate, the driving circuit layer comprising a pixel driving circuit, the pixel driving circuit comprising a switching transistor, a driving transistor, a compensation transistor and a first initialization transistor, the switching transistor and the driving transistor being connected to a first node; one electrode of the compensation transistor and one electrode of the first initialization transistor being connected to a second node with the driving transistor, the other electrode of the compensation transistor being connected to a third node with the driving transistor; wherein the driving circuit layer comprises: A light shielding layer, the light shielding layer comprising a first light shielding part, the light shielding layer forming a bottom gate of the first initialization transistor; A first active layer arranged on a side of the light shielding layer away from the substrate; A first gate layer arranged on a side of the first active layer away from the substrate, the first gate layer comprising a first gate of the compensation transistor, the first gate layer forming a bottom gate of the compensation transistor; A second active layer arranged on a side of the first gate layer away from the substrate, the second active layer comprising an active pattern of the compensation transistor and an active pattern of the first initialization transistor; Wherein the first gate of the compensation transistor is arranged corresponding to the active pattern of the compensation transistor, and the first light shielding part is arranged corresponding to the active pattern of the first initialization transistor. The driving circuit layer comprises a plurality of repeating units arranged in an array, each of the repeating units comprising two pixel driving circuits arranged symmetrically, in the repeating unit, the light shielding layer further comprises two second light shielding parts arranged symmetrically in the corresponding regions of the two pixel driving circuits and a connecting part, the connecting part comprises a first connecting part arranged along a first direction, a second connecting part arranged along the first direction and a third connecting part arranged along a second direction, the first active layer comprises an active pattern of the driving transistor, the second light shielding part is arranged corresponding to the active pattern of the driving transistor, the first connecting part connects adjacent first light shielding parts, the second connecting part connects adjacent second light shielding parts, one end of the third connecting part is connected to the first light shielding part, and the other end of the third connecting part is connected to the second light shielding part; 2. The display panel of claim 1, wherein, The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. The light shielding layer further comprises a second light shielding part, the first active layer comprises an active pattern of the driving transistor, the second light shielding part is arranged corresponding to the active pattern of the driving transistor, and the first light shielding part and the second light shielding part are arranged at intervals.

3. The display panel of claim 1, wherein, The driving circuit layer comprises a plurality of pixel driving circuits arranged in an array, the first light shielding part is arranged in the corresponding region of the pixel driving circuit along a first direction, the second light shielding part is arranged in the corresponding region of the pixel driving circuit along the first direction, in the first direction, the first light shielding parts located in adjacent two pixel driving circuits are connected, the second light shielding parts located in adjacent two pixel driving circuits are connected, and the driving circuit layer further comprises a scan signal line, the first direction is the same as the arrangement direction of the scan signal line.

4. The display panel of claim 3, wherein, ​ 5. The display panel of any one of claims 1 to 4, wherein, The gate of the switch transistor is connected with a first scan signal line, the first electrode of the switch transistor is connected with a data line, and the second electrode of the switch transistor is connected with the first electrode of the drive transistor at a first node; the gate of the compensation transistor is connected with a second scan signal line, the first electrode of the compensation transistor is connected with the gate of the drive transistor at a second node, and the second electrode of the compensation transistor is connected with the second electrode of the drive transistor; the gate of the first initialization transistor is connected with a third scan signal line, the first electrode of the first initialization transistor is connected with a first initialization signal line, and the second electrode of the first initialization transistor is connected with the gate of the drive transistor at the second node. The pixel drive circuit further comprises: a first light-emitting control transistor, the gate of the first light-emitting control transistor being connected with a light-emitting control signal line, the first electrode of the first light-emitting control transistor being connected with a high-potential power supply line, and the second electrode of the first light-emitting control transistor being connected with the first electrode of the drive transistor at the first node; a second light-emitting control transistor, the gate of the second light-emitting control transistor being connected with the light-emitting control signal line, the first electrode of the second light-emitting control transistor being connected with the second electrode of the drive transistor at a third node; a second initialization transistor, the gate of the second initialization transistor being connected with a fourth scan signal line, the first electrode of the second initialization transistor being connected with a second initialization signal line, and the second electrode of the second initialization transistor being connected with the second electrode of the second light-emitting control transistor at a fourth node; a third initialization transistor, the gate of the third initialization transistor being connected with the fourth scan signal line, the first electrode of the third initialization transistor being connected with a third initialization signal line, and the second electrode of the third initialization transistor being connected with the first electrode of the drive transistor at the first node; a storage capacitor, one plate of the storage capacitor being connected with the high-potential power supply line, and the other plate of the storage capacitor being connected with the gate of the drive transistor at the second node; a boosting capacitor, one plate of the boosting capacitor being connected with the first scan signal line, and the other plate of the boosting capacitor being connected with the second electrode of the first initialization transistor.

6. The display panel of claim 5, wherein, The drive circuit layer further comprises a second gate layer, a first source-drain layer and a second source-drain layer, the second active layer is arranged between the first gate layer and the second gate layer, the second gate layer is arranged between the second active layer and the first source-drain layer, and the first source-drain layer is arranged between the second gate layer and the second source-drain layer.

7. The display panel of claim 6, wherein, The first active layer comprises an active pattern of the driving transistor, an active pattern of the switching transistor, an active pattern of the first light-emitting control transistor, an active pattern of the second light-emitting control transistor, an active pattern of the second initialization transistor and an active pattern of the third initialization transistor, the active pattern of the driving transistor is arranged along a first direction, and the active pattern of the driving transistor is connected with the active pattern of the switching transistor, the active pattern of the first light-emitting control transistor and the active pattern of the second light-emitting control transistor, the active pattern of the switching transistor and the active pattern of the first light-emitting control transistor are arranged along a second direction, the active pattern of the second light-emitting control transistor and the active pattern of the second initialization transistor are arranged along the second direction, and the active pattern of the second light-emitting control transistor is connected with the active pattern of the second initialization transistor, and the active pattern of the third initialization transistor is spaced apart from the active pattern of the driving transistor, the active pattern of the switching transistor, the active pattern of the first light-emitting control transistor, the active pattern of the second light-emitting control transistor and the active pattern of the second initialization transistor. An angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

8. The display panel of claim 7, wherein, The first gate layer comprises the first scan signal line, the first plate of the storage capacitor, the light-emitting control signal line, the fourth scan signal line, the first initialization connection line, the gate of the driving transistor, the gate of the switching transistor, the gate of the first light-emitting control transistor, the gate of the second light-emitting control transistor, the gate of the second initialization transistor and the gate of the third initialization transistor; the first scan signal line, the first gate of the compensation transistor, the first plate of the storage capacitor, the light-emitting control signal line, the fourth scan signal line and the first initialization connection line are sequentially and spaced apart along a second direction.

9. The display panel of claim 8, wherein, The second active layer further comprises the second plate of the storage capacitor, the active pattern of the compensation transistor is connected with the active pattern of the first initialization transistor, the second plate of the storage capacitor is arranged on one side of the active pattern of the compensation transistor along a first direction, and a through hole is arranged on the second plate of the storage capacitor.

10. The display panel of claim 9, wherein, The second gate layer comprises the second scan signal line, the third scan signal line, the second initialization signal line, the second gate of the compensation transistor and the gate of the first initialization transistor, the third scan signal line, the second scan signal line and the second initialization signal line are sequentially arranged along the second direction.

11. The display panel of claim 10, wherein, The first source-drain layer comprises the first initialization signal line, the first electrode of the switch transistor, the second electrode of the switch transistor, the first electrode of the compensation transistor, the second electrode of the compensation transistor, the first electrode of the first initialization transistor, the second electrode of the first initialization transistor, the first electrode of the first light-emitting control transistor, the second electrode of the first light-emitting control transistor, the first electrode of the second light-emitting control transistor, the second electrode of the second light-emitting control transistor, the first electrode of the second initialization transistor, the second electrode of the second initialization transistor, the first electrode of the third initialization transistor, the second electrode of the third initialization transistor, a first jumper line, a first data connection line, a second jumper line, and the third initialization signal line, The first jumper line is connected with the first gate of the compensation transistor and the second scan signal line, the second jumper line is connected with the second initialization signal line and the first electrode of the second initialization transistor, and the third initialization signal line is connected with the first initialization connection line.

12. The display panel of claim 11, wherein, The driving circuit layer comprises a plurality of repetitive units arranged in an array, each of the repetitive units comprises two pixel driving circuits arranged symmetrically, in the repetitive unit, the second source-drain layer comprises two second data connection lines, two data lines, two high-potential power supply lines, and a second initialization connection line, the two second data connection lines are arranged symmetrically, and a break is arranged on the second data connection line, the two data lines are arranged symmetrically, the two high-potential power supply lines are arranged symmetrically, and the second initialization connection line is connected with the second initialization signal line.

13. The display panel of claim 5, wherein, The first light-shielding part is connected with the third scan signal line.

14. A display device comprising: The display panel comprises the display panel as claimed in any one of claims 1 to 13.

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