Metal-oxide-semiconductor field effect transistor (MOSFET) device based on F ion gate modulation and preparation method thereof

Abstract

The invention relates to an MOSFET device based on F ion gate modulation and a preparation method thereof. The device comprises a substrate layer, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer and a third N-type GaN layer which are sequentially arranged from bottom to top. The gate groove extends into the second N-type GaN layer from the two ends of the upper surface of the third N-type GaN layer; the side, close to the third N-type GaN layer, of the gate groove is a gate region, and the side, away from the third N-type GaN layer, of the gate region is a modulation region. The gate structure extends to the gate region from the upper surface of the third N-type GaN layer; a source recess; a source electrode; a drain electrode; and the F ion implantation region is located in the modulation region and extends into the second N-type GaN layer from the bottom of the gate groove. The F ion injection region is arranged in the modulation region, electrons on the surface of the third N-type GaN layer are exhausted, the electric field concentration phenomenon of the device is relieved, the breakdown voltage of the device is improved, and the voltage resistance of the device is ensured.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a MOSFET device based on F ion gate modulation and a preparation method thereof. Background Art

[0002] Compared with Si-based materials, GaN has excellent electrical properties such as large bandgap, high critical breakdown electric field, high saturation velocity, and good thermal conductivity, which makes the prepared devices have higher breakdown voltage, and under the same voltage resistance requirements, GaN-based devices have lower on-resistance, thus having great potential in the field of high-voltage and high-power power electronics. For GaN planar devices used in high-voltage environments, in order to increase the breakdown voltage of the device, the source-drain distance and the gate-drain distance must be increased so that the device has a larger voltage resistance space when blocked, but this method increases the size of the device, resulting in reduced wafer utilization and increased cost of a single device.

[0003] GaN trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET) uses a vertical drift layer to block the withstand voltage. Therefore, when the breakdown voltage of the device is increased, there is no need to increase the size of the device. It only needs to increase the thickness of the drift region of the device, which can effectively reduce the cost of a single device and improve the overall wafer utilization.

[0004] However, there is electric field concentration at the bottom corner of the trench of GaN trench gate MOSFET, which affects the voltage resistance performance of the device. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a MOSFET device based on F ion gate modulation and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] The present invention provides a MOSFET device based on F ion gate modulation and a preparation method thereof, comprising:

[0007] A substrate layer, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer and a third N-type GaN layer are sequentially arranged from bottom to top;

[0008] a gate groove extending from two ends of the upper surface of the third N-type GaN layer to the interior of the second N-type GaN layer; a side of the gate groove close to the third N-type GaN layer is a gate region, and a side of the gate region away from the third N-type GaN layer is a modulation region;

[0009] A gate structure extending from the upper surface of the third N-type GaN layer to the gate region;

[0010] A source groove extending from the upper surface of the third N-type GaN layer to the lower surface of the third N-type GaN layer;

[0011] A source electrode, located in the source groove;

[0012] A drain electrode located on an upper surface of the first N-type GaN layer on both sides of the second N-type GaN layer;

[0013] The F ion implantation region is located in the modulation region and extends from the bottom of the gate groove to the inside of the second N-type GaN layer.

[0014] In one achievable manner, the source electrode extends from the source groove to the upper surface of the third N-type GaN layer, and there is a gap between the source electrode and the gate structure.

[0015] In one achievable manner, the gate structure includes: a gate dielectric layer and a gate electrode, wherein:

[0016] The gate dielectric layer extends from the upper surface of the third N-type GaN layer to the gate region;

[0017] The gate electrode is located on the surface of the gate dielectric layer.

[0018] In an achievable manner, the material of the substrate layer includes one or more of Si, SiC, and sapphire;

[0019] The material of the gate dielectric layer includes Al2O3;

[0020] The material of the gate electrode includes Ni / Au;

[0021] The material of the source electrode includes Ti / Al / Ni / Au;

[0022] The material of the drain electrode includes Ti / Al / Ni / Au.

[0023] In a feasible manner, the length of the gate region is 2-10 μm.

[0024] In a feasible manner, the modulation region has a length of 3 to 10 μm.

[0025] In an achievable manner, the doping concentration of the first N-type GaN layer is 1.0×10 19 ~1×10 20 cm -3 , thickness is 1 to 2 μm;

[0026] The doping concentration of the second N-type GaN layer is 1.0×10 16 ~3×10 16 cm -3 , thickness is 3-5 μm;

[0027] The doping concentration of the P-type GaN layer is 1.0×10 17 ~1×10 18 cm -3 , thickness is 200~350nm;

[0028] The doping concentration of the third N-type GaN layer is 1.0×10 19 ~1×10 20 cm -3 , with a thickness of 200 to 300 nm.

[0029] In an achievable manner, the F ion implantation region has an implantation depth of 10 to 100 nm and an implantation concentration of 1.0×10 15 ~1×10 18 cm -3 .

[0030] A second aspect of the present invention provides a method for preparing a MOSFET device based on F ion gate modulation, comprising the following steps:

[0031] S1: obtaining a substrate layer, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer and a third N-type GaN layer arranged in sequence from bottom to top;

[0032] S2: etching at both ends of the third N-type GaN layer to form a gate groove extending from both ends of the upper surface of the third N-type GaN layer to the inside of the second N-type GaN layer; a side of the gate groove close to the third N-type GaN layer is a gate region, and a side of the gate region away from the third N-type GaN layer is a modulation region;

[0033] S3: preparing a gate structure on the upper surface of the third N-type GaN layer and in the gate region;

[0034] S4: etching the upper surface of the third N-type GaN layer to form a source groove extending from the upper surface of the third N-type GaN layer to the lower surface of the third N-type GaN layer;

[0035] S5: preparing a source electrode in the source groove, and preparing a drain electrode on the upper surface of the first N-type GaN layer on both sides of the second N-type GaN layer;

[0036] S6: performing ion implantation in the modulation region to form a F ion implantation region extending from the bottom of the gate groove to the inside of the second N-type GaN layer.

[0037] In one achievable manner, the specific steps of step S6 include:

[0038] The modulation area is plasma treated with CF4 gas by ICP process to form an F ion implantation area extending from the bottom of the gate groove to the inside of the second N-type GaN layer; wherein the plasma treatment time is 100 to 200 seconds, and the flow rate of the CF4 gas is 30 to 50 sccm.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] The MOSFET device based on F ion gate modulation of the present invention, by setting a F ion implantation area in the modulation area, depletes the electrons on the surface of the third N-type GaN layer, reduces the potential on the surface of the third N-type GaN layer, widens the electric field distribution range of the device, reduces the peak electric field strength of the device, thereby alleviating the electric field concentration phenomenon of the device, improving the breakdown voltage of the device, and ensuring the withstand voltage performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a structural schematic diagram of a MOSFET device based on F ion gate modulation provided by an embodiment of the present invention;

[0042] Figure 2a to Figure 2i It is a schematic diagram of the steps of a method for preparing a MOSFET device based on F ion gate modulation provided by an embodiment of the present invention.

[0043] Reference numerals:

[0044] 1: substrate layer; 2: first N-type GaN layer; 3: second N-type GaN layer; 4: P-type GaN layer; 5: third N-type GaN layer; 6: gate dielectric layer; 7: gate electrode; 8: source electrode; 9: drain electrode; 10: F ion implantation region. DETAILED DESCRIPTION

[0045] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0046] Embodiment 1

[0047] See also Figure 1 , Figure 1 It is a schematic structural diagram of a MOSFET device based on F ion gate modulation provided by an embodiment of the present invention.

[0048] The present embodiment provides a MOSFET device based on F ion gate modulation, comprising: a substrate layer 1, a first N-type GaN layer 2, a second N-type GaN layer 3, a P-type GaN layer 4, a third N-type GaN layer 5, a gate groove, a gate structure, a source groove, a source electrode 8, a drain electrode 9 and a F ion implantation region 10. Among them, the substrate layer 1, the first N-type GaN layer 2, the second N-type GaN layer 3, the P-type GaN layer 4 and the third N-type GaN layer 5 are arranged in sequence from bottom to top. The gate groove extends from both ends of the upper surface of the third N-type GaN layer 5 to the inside of the second N-type GaN layer 3, the side of the gate groove close to the third N-type GaN layer 5 is the gate region, and the side of the gate region away from the third N-type GaN layer 5 is the modulation region. The gate structure extends from the upper surface of the third N-type GaN layer 5 to the gate region. The source groove extends from the upper surface of the third N-type GaN layer 5 to the lower surface of the third N-type GaN layer 5. The source electrode 8 is located in the source groove. The drain electrode 9 is located on the upper surface of the first N-type GaN layer 2 on both sides of the second N-type GaN layer 3. The F ion implantation region 10 is located in the modulation region and extends from the bottom of the gate groove to the inside of the second N-type GaN layer 3.

[0049] Specifically, the gate structure extends from the upper surface of the third N-type GaN layer 5, through the side surface of the third N-type GaN layer 5 and the side surface of the P-type GaN layer 4 to the gate region, and the depth of the gate groove is greater than or equal to the sum of the thicknesses of the P-type GaN layer 4 and the third N-type GaN layer 5, so that the gate structure can fully control the channel and ensure that the carriers can smoothly enter the third N-type GaN layer 5. The F ion implantation region 10 is located in the modulation region, that is, the F ion implantation region 10 is located on the side of the gate structure away from the third N-type GaN layer 5. The F atoms introduced by the F ion implantation region 10 exist in the form of fixed negative charges after accepting electrons, forming a high-density acceptor-type trap, depleting the electrons in the third N-type GaN layer 5 near the gate structure, reducing the potential, slowing down the potential change, widening the electric field distribution range, and slowing down the electric field concentration phenomenon in the third N-type GaN layer 5 near the gate structure, thereby improving the device breakdown voltage.

[0050] In this embodiment, the source electrode 8 extends from the source groove to the upper surface of the third N-type GaN layer 5 , and there is a gap between the source electrode 8 and the gate structure.

[0051] In this embodiment, the gate structure includes: a gate dielectric layer 6 and a gate electrode 7 , wherein the gate dielectric layer 6 extends from the upper surface of the third N-type GaN layer 5 to the gate region. The gate electrode 7 is located on the surface of the gate dielectric layer 6 .

[0052] Specifically, the source electrode 8 covers the lower surface and the side surface of the source groove, and the two ends of the source electrode 8 extend to the upper surface of the third N-type GaN layer 5. Since the source groove extends from the upper surface of the third N-type GaN layer 5 to the lower surface of the third N-type GaN layer 5, the source electrode 8 covering the lower surface of the source groove contacts the P-type GaN layer 4. The gate dielectric layer 6 extends from the two ends of the upper surface of the third N-type GaN layer 5 to the gate region, and there is a gap between the gate dielectric layer 6 and the source electrode 8. It should be understood that the source electrode 8 is located at the center of the top of the device, the gate dielectric layer 6 is located on both sides of the source electrode 8, and the two gate dielectric layers 6 extend from both sides of the source electrode 8 to the gate region in the gate groove located at both ends of the third N-type GaN layer 5, and the gate electrode 7 covers the surface of the gate dielectric layer 6.

[0053] In this embodiment, the length of the gate region is 2-10 μm. The length of the modulation region is 3-10 μm. The implantation depth of the F ion implantation region 10 is 10-100 nm, and the implantation concentration is 1.0×10 15 ~1×10 18 cm -3 .

[0054] Specifically, the length of the gate region is the length of the gate electrode 7 on the surface of the second N-type GaN layer 3, and the length of the modulation region is the length of the F ion implantation region 10. Since the gate groove is located at both ends of the third N-type GaN layer 5, that is, the device provided in this embodiment has two gate grooves, which are located at the left and right ends of the device respectively. The length of the gate region in each gate groove is 2 to 10 μm, and the length of the modulation region in each gate groove is 3 to 10 μm. The total length of the two gate regions in the device is 4 to 20 μm, and the total length of the two modulation regions is 6 to 20 μm. The distance between the edge of the F ion implantation region 10 and the side wall of the second N-type GaN layer 3 is 0 to 1 μm, and the gate thickness is 300 to 450 nm. In this embodiment, adjusting the length of the modulation region can change the peak electric field strength of the device. Furthermore, the larger the length of the modulation region, the lower the peak electric field strength of the device.

[0055] In this embodiment, the material of the substrate layer 1 includes one or more of Si, SiC, and sapphire. The doping concentration of the first N-type GaN layer 2 is 1.0×10 19 ~1×10 20 cm -3 , with a thickness of 1 to 2 μm. The doping concentration of the second N-type GaN layer 3 is 1.0×10 16 ~3×10 16 cm -3 , with a thickness of 3 to 5 μm. The doping concentration of the P-type GaN layer 4 is 1.0×10 17 ~1×10 18 cm -3The thickness is 200-350 nm. The doping concentration of the third N-type GaN layer 5 is 1.0×10 19 ~1×10 20 cm -3 , with a thickness of 200 to 300 nm. The material of the gate dielectric layer 6 includes Al2O3. The material of the gate electrode 7 includes Ni / Au. The material of the source electrode 8 includes Ti / Al / Ni / Au. The material of the drain electrode 9 includes Ti / Al / Ni / Au. The doping ions of the first N-type GaN layer 2, the second N-type GaN layer 3 and the third N-type GaN layer 5 are all Si ions, and the doping ions of the P-type GaN layer 4 are Mg ions.

[0056] Specifically, Ni / Au is Ni and Au stacked from bottom to top, wherein the thickness of Ni is 30-50nm, and the thickness of Au is 300-450nm. Ti / Al / Ni / Au is Ti, Al, Ni, and Au stacked from bottom to top, wherein the thickness of Ti is 20-30nm, the thickness of Al is 140-180nm, the thickness of Ni is 40-60nm, and the thickness of Au is 30-50nm.

[0057] In this embodiment, the MOSFET device further includes a device isolation region located at two ends of the first N-type GaN layer 2. The depth of the device isolation region is 1-2 μm.

[0058] The MOSFET device provided in this embodiment has two PN junctions, specifically, a J1 junction formed by the third N-type GaN layer 5 and the P-type GaN layer 4, and a J2 junction formed by the P-type GaN layer 4 and the second N-type GaN layer 3. When no bias voltage is applied to the gate electrode 7, the source electrode 8, and the drain electrode 9 of the device, that is, when the gate voltage Vgate, the source voltage Vsource, and the drain voltage Vdrain are all 0, the N-type inversion channel inside the MOSFET is not turned on, the J1 junction and the J2 junction are both in a zero bias state, and no current is generated inside the device.

[0059] When no bias voltage is applied to the source electrode 8 and the gate electrode 7 of the device, and a forward voltage is applied to the drain electrode 9 (Vdrain>0, Vsource=0, Vgate=0), the J2 junction formed by the P-type GaN layer 4 and the second N-type GaN layer 3 is in a reverse bias state. The second N-type GaN layer 3 as the drift region of the device has a low doping concentration, and the P-type GaN layer 4 has a high doping concentration. Therefore, the depletion layer of the J2 junction when reverse biased mainly extends to the low-doped second N-type GaN layer 3. Therefore, the breakdown voltage of the MOSFET depends largely on the structural parameters of the second N-type GaN layer 3, such as the thickness and doping concentration of the drift region. In this embodiment, the doping concentration of the second N-type GaN layer 3 is set to 1.0×10 16 ~3×10 16 cm-3 , with a thickness of 3 to 5 μm, which can ensure that the device has a high breakdown voltage in this state.

[0060] When the source electrode 8 of the device does not apply a bias voltage, and the gate electrode 7 and the drain electrode 9 apply a forward voltage (Vdrain>0, Vsource=0, Vth>Vgate>0), where Vth is the threshold voltage when the device is turned on, when Vgate is greater than 0 but less than Vth, the holes on the surface of the P-type GaN layer 4 are transferred to the inside under the drive of the gate voltage, and some negatively charged acceptor Mg ions appear on the channel surface. At this time, the conduction channel between the source and the drain is still closed, and the device is in a blocking state. As Vgate continues to increase, when Vgate is greater than Vth (Vdrain>0, Vsource=0, Vgate>Vth), as the surface energy band of the P-type GaN layer 4 bends downward, a large number of minority carriers (electrons) appear on the side surface of the P-type GaN layer 4, forming an accumulation layer of electrons, that is, a strong inversion state appears. At this time, the part of the P-type GaN layer 4 close to the gate is equivalent to the N-type, thereby forming a current path between the third N-type GaN layer 5 and the second N-type GaN layer 3. Therefore, under the action of the forward biased drain electrode 9, electrons enter the inversion channel from the third N-type GaN layer 5, and then flow into the second N-type GaN layer 3 below in a direction perpendicular to the substrate layer 1, and are finally collected by the drain electrode 9, forming an output current between the source and the drain.

[0061] The present embodiment provides a MOSFET device based on F ion gate modulation, which depletes electrons on the surface of the third N-type GaN layer 5 by setting an F ion implantation region 10 in the modulation region, reduces the potential on the surface of the third N-type GaN layer 5, widens the electric field distribution range of the device, and reduces the peak electric field strength of the device, thereby alleviating the electric field concentration phenomenon of the device, improving the breakdown voltage of the device, and ensuring the voltage resistance performance of the device.

[0062] Embodiment 2

[0063] See also Figure 2a to Figure 2i , Figure 2a to Figure 2i It is a schematic diagram of the steps of a method for preparing a MOSFET device based on F ion gate modulation provided by an embodiment of the present invention.

[0064] This embodiment provides a method for preparing a MOSFET device based on F ion gate modulation, comprising the following steps:

[0065] S1: Obtain a substrate layer 1, a first N-type GaN layer 2, a second N-type GaN layer 3, a P-type GaN layer 4 and a third N-type GaN layer 5 arranged in sequence from bottom to top.

[0066] Specifically, Figure 2aAs shown, the material of the substrate layer 1 includes one or more of Si, SiC, and sapphire. The doping concentration of the first N-type GaN layer 2 is 1.0×10 19 ~1×10 20 cm -3 , with a thickness of 1 to 2 μm. The doping concentration of the second N-type GaN layer 3 is 1.0×10 16 ~3×10 16 cm -3 , with a thickness of 3 to 5 μm. The doping concentration of the P-type GaN layer 4 is 1.0×10 17 ~1×10 18 cm -3 The thickness is 200-350 nm. The doping concentration of the third N-type GaN layer 5 is 1.0×10 19 ~1×10 20 cm -3 The thickness is 200-300 nm. The doping ions of the first N-type GaN layer 2, the second N-type GaN layer 3 and the third N-type GaN layer 5 are all Si ions, and the doping ions of the P-type GaN layer 4 are Mg ions.

[0067] S2: etching is performed at both ends of the third N-type GaN layer 5 to form a gate groove extending from both ends of the upper surface of the third N-type GaN layer 5 to the inside of the second N-type GaN layer 3; the side of the gate groove close to the third N-type GaN layer 5 is the gate region, and the side of the gate region away from the third N-type GaN layer 5 is the modulation region.

[0068] Specifically, Figure 2b As shown, the etching gas is BCl3 / Cl2 by an inductively coupled plasma ICP process. The etching depth is 600-900 nm, so as to completely etch and remove the two ends of the P-type GaN layer 4 and the third N-type GaN layer 5, so that the bottom of the gate groove is located inside the second N-type GaN layer 3. In this embodiment, the length of each gate region is 2-10 μm. The length of each modulation region is 3-10 μm.

[0069] S3: preparing a gate structure on the upper surface of the third N-type GaN layer 5 and in the gate region.

[0070] In this embodiment, step S3 includes:

[0071] S301: Figure 2c As shown, by atomic layer deposition (ALD) process, Al2O3 with a thickness of 45 to 55 nm is grown on the surface of the gate groove and the third N-type GaN layer 5 to form a gate dielectric layer 6.

[0072] S302: Figure 2dAs shown, Ni / Au is sputtered on the surface of the gate dielectric layer 6 located at both ends of the upper surface of the third N-type GaN layer 5 and the surface of the gate dielectric layer 6 located in the gate region to form a gate electrode 7. The thickness of Ni is 30-50nm, and the thickness of Au is 300-450nm.

[0073] S302: Figure 2e As shown, the gate dielectric layer 6 not covered by the gate electrode 7 is removed by ICP etching. The etching gas is CF4 gas.

[0074] S4 : etching the upper surface of the third N-type GaN layer 5 to form a source groove extending from the upper surface of the third N-type GaN layer 5 to the lower surface of the third N-type GaN layer 5 .

[0075] Specifically, Figure 2f As shown, the ICP process is used to etch the center of the upper surface of the third N-type GaN layer 5 to form a source groove extending from the upper surface of the third N-type GaN layer 5 to the lower surface of the third N-type GaN layer 5. The etching gas is BCl3 / Cl2, and the etching depth is 200-300nm.

[0076] S5 : forming a source electrode 8 in the source groove, and forming a drain electrode 9 on the upper surface of the first N-type GaN layer 2 on both sides of the second N-type GaN layer 3 .

[0077] Specifically, Figure 2g As shown, the two ends of the second N-type GaN layer 3 are etched away by the ICP process to form a drain groove, and the two ends of the first N-type GaN layer 2 are etched by the ICP process to form a device isolation region. Figure 2h As shown, Ti / Al / Ni / Au is evaporated in the source groove and the drain groove, wherein the thickness of Ti is 20-30nm, the thickness of Al is 140-180nm, the thickness of Ni is 40-60nm, the thickness of Au is 30-50nm, the depth of the drain groove is 4-6μm, and the depth of the device isolation area is 1-2μm.

[0078] S6: performing ion implantation in the modulation region to form a F ion implantation region 10 extending from the bottom of the gate groove to the inside of the second N-type GaN layer 3 .

[0079] Specifically, Figure 2i As shown, the specific steps of step S6 include:

[0080] The ICP process is used to perform plasma treatment on the modulation area through CF4 gas to form a F ion implantation area 10 extending from the bottom of the gate groove to the inside of the second N-type GaN layer 3. The plasma treatment time is 100 to 200 seconds, the flow rate of CF4 gas is 30 to 50 sccm, the ICP coil power is 100 to 220 W, and the bias power is 40 to 70 W. The implantation depth of the F ion implantation area 10 is 10 to 100 nm, and the implantation concentration is 1.0×10 15 ~1×10 18 cm -3 .

[0081] The present embodiment provides a method for preparing a MOSFET device based on F ion gate modulation, wherein a F ion implantation region 10 is formed by plasma treatment of the modulation region to deplete electrons on the surface of the third N-type GaN layer 5, reduce the potential on the surface of the third N-type GaN layer 5, widen the electric field distribution range of the device, and reduce the peak electric field strength of the device, thereby alleviating the electric field concentration phenomenon of the device, improving the breakdown voltage of the device, and ensuring the voltage resistance performance of the device.

[0082] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A MOSFET device based on F ion gate modulation, characterized in that: include: A substrate layer (1), a first N-type GaN layer (2), a second N-type GaN layer (3), a P-type GaN layer (4) and a third N-type GaN layer (5) are arranged in sequence from bottom to top; a gate groove extending from two ends of the upper surface of the third N-type GaN layer (5) to the interior of the second N-type GaN layer (3); a side of the gate groove close to the third N-type GaN layer (5) is a gate region, and a side of the gate region away from the third N-type GaN layer (5) is a modulation region; A gate structure extending from the upper surface of the third N-type GaN layer (5) to the gate region; A source groove extending from the upper surface of the third N-type GaN layer (5) to the lower surface of the third N-type GaN layer (5); A source electrode (8), located in the source groove; A drain electrode (9) located on the upper surface of the first N-type GaN layer (2) on both sides of the second N-type GaN layer (3); The F ion implantation region (10) is located in the modulation region and extends from the bottom of the gate groove to the inside of the second N-type GaN layer (3).

2. A MOSFET device based on F ion gate modulation according to claim 1, characterized in that: The source electrode (8) extends from the source groove to the upper surface of the third N-type GaN layer (5), and there is a gap between the source electrode (8) and the gate structure.

3. A MOSFET device based on F ion gate modulation according to claim 1, characterized in that: The gate structure comprises: a gate dielectric layer (6) and a gate electrode (7), wherein: The gate dielectric layer (6) extends from the upper surface of the third N-type GaN layer (5) to the gate region; The gate electrode (7) is located on the surface of the gate dielectric layer (6).

4. A MOSFET device based on F ion gate modulation according to claim 3, characterized in that: The material of the substrate layer (1) includes one or more of Si, SiC, and sapphire; The material of the gate dielectric layer (6) includes Al2O3; The material of the gate electrode (7) includes Ni / Au; The material of the source electrode (8) includes Ti / Al / Ni / Au; The material of the drain electrode (9) includes Ti / Al / Ni / Au.

5. A MOSFET device based on F ion gate modulation according to claim 1, characterized in that: The length of the gate region is 2-10 μm.

6. A MOSFET device based on F ion gate modulation according to claim 1, characterized in that: The length of the modulation area is 3 to 10 μm.

7. A MOSFET device based on F ion gate modulation according to claim 1, characterized in that: The doping concentration of the first N-type GaN layer (2) is 1.0×10 19 ~1×10 20 cm -3 , thickness is 1 to 2 μm; The doping concentration of the second N-type GaN layer (3) is 1.0×10 16 ~3×10 16 cm -3 , thickness is 3-5 μm; The doping concentration of the P-type GaN layer (4) is 1.0×10 17 ~1×10 18 cm -3 , thickness is 200~350nm; The doping concentration of the third N-type GaN layer (5) is 1.0×10 19 ~1×10 20 cm -3 , thickness is 200~300nm.

8. A MOSFET device based on F ion gate modulation according to claim 1, characterized in that: The F ion implantation area (10) has an implantation depth of 10 to 100 nm and an implantation concentration of 1.0×10 15 ~1×10 18 cm -3 .

9. A method for preparing a MOSFET device based on F ion gate modulation, characterized in that: The following steps are involved: S1: obtaining a substrate layer (1), a first N-type GaN layer (2), a second N-type GaN layer (3), a P-type GaN layer (4), and a third N-type GaN layer (5) arranged in sequence from bottom to top; S2: etching at both ends of the third N-type GaN layer (5) to form a gate groove extending from both ends of the upper surface of the third N-type GaN layer (5) to the inside of the second N-type GaN layer (3); a side of the gate groove close to the third N-type GaN layer (5) is a gate region, and a side of the gate region away from the third N-type GaN layer (5) is a modulation region; S3: preparing a gate structure on the upper surface of the third N-type GaN layer (5) and in the gate region; S4: etching the upper surface of the third N-type GaN layer (5) to form a source groove extending from the upper surface of the third N-type GaN layer (5) to the lower surface of the third N-type GaN layer (5); S5: preparing a source electrode (8) in the source groove, and preparing a drain electrode (9) on the upper surface of the first N-type GaN layer (2) on both sides of the second N-type GaN layer (3); S6: performing ion implantation in the modulation region to form an F ion implantation region (10) extending from the bottom of the gate groove to the inside of the second N-type GaN layer (3).

10. The method for preparing a MOSFET device based on F ion gate modulation according to claim 9, characterized in that: The specific steps of step S6 include: The modulation area is plasma treated by CF4 gas using an ICP process to form an F ion implantation area (10) extending from the bottom of the gate groove to the inside of the second N-type GaN layer (3); wherein the plasma treatment time is 100 to 200 seconds and the flow rate of the CF4 gas is 30 to 50 sccm.

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