Sampling gate voltage bootstrapped switch capable of avoiding overvoltage

Abstract

The invention provides a sampling grid voltage bootstrapped switch capable of avoiding overvoltage, which relates to the technical field of power electronics and comprises a voltage multiplication module, a sampling voltage division module and a switching tube module, the voltage multiplication module is respectively connected with the sampling voltage division module and the switching tube module, and the sampling voltage division module is connected with the switching tube module. According to the invention, the stray capacitance on a pumping pressure path is reduced, and the nonlinearity of the stray capacitance is eliminated.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, and in particular to a sampling gate voltage bootstrap switch capable of avoiding overvoltage. Background Art

[0002] In modern electronic systems, the accuracy and speed of analog-to-digital converters (ADCs) have a crucial impact on the overall performance. As a key component in ADCs, the performance of sampling switches directly determines the accuracy of the sampled signal and the overall performance of the circuit. Although traditional sampling switches, such as single-tube switches or transmission gate switches, have simple structures, they have disadvantages such as large on-resistance and strong nonlinearity. These non-ideal effects will significantly affect the accuracy of the sampled signal.

[0003] In order to overcome these shortcomings, gate voltage bootstrap switches are widely used in analog-to-digital converter circuits. The gate voltage bootstrap technology uses a charge pump to boost the gate voltage of the sampling switch to a level that is one power supply voltage higher than the input signal, thereby achieving a constant gate-source voltage (VGS) of the sampling switch at the power supply voltage. This technology significantly reduces the on-resistance and nonlinearity, and improves the sampling speed and accuracy. However, in the process of boosting the gate voltage of the traditional gate voltage bootstrap switch, many devices on the path may face overvoltage problems, causing the transistor to work in an overvoltage state for a long time, accelerating its aging process and greatly reducing the service life of the product.

[0004] Therefore, a sampling gate voltage bootstrap switch which can avoid overvoltage is proposed. Summary of the invention

[0005] The present specification provides a sampling gate voltage bootstrap switch capable of avoiding overvoltage, reducing the parasitic capacitance on the pumping path, and eliminating the nonlinearity of the parasitic capacitance.

[0006] This specification provides a sampling gate voltage bootstrap switch capable of avoiding overvoltage, comprising: A voltage multiplier module, a sampling voltage divider module, and a switch tube module; the voltage multiplier module is connected to the sampling voltage divider module and the switch tube module respectively, and the sampling voltage divider module is connected to the switch tube module.

[0007] Optionally, the voltage multiplier module includes an inverter I1 and an inverter I2, the inverter I1 is respectively connected to the pumping capacitor C3 and the inverter I2, the pumping capacitor C3 is connected to the switch tube MN3, the switch tube MN3 is respectively connected to the switch tube MN2 and the switch tube MP4, the switch tube MN2 is respectively connected to the switch tube MN1 and the pumping capacitor C2, and the pumping capacitor C2 is connected to the inverter I2; the switch tube MP4 is respectively connected to the switch tube MP3, the switch tube MN9, and the power supply voltage AVDD, the switch tube MP3 is connected to the switch tube MN9, and the switch tube MN1 is respectively connected to the switch tube module and the sampling voltage divider module.

[0008] Optionally, the voltage multiplier module includes an inverter I1 and an inverter I2, the inverter I1 is connected to the pumping capacitor C3 and the inverter I2 respectively, the pumping capacitor C3 is connected to the Deep-Nwell tube, the Deep-Nwell tube is connected to the pumping capacitor C2, the switch tube module, and the sampling voltage divider module, and the pumping capacitor C2 is connected to the inverter I2.

[0009] Optionally, the switch tube module includes a pumping capacitor C1, which is respectively connected to the switch tube MN0 and the switch tube MP1, the switch tube MN0 is connected to the switch tube MN4, the switch tube MN4 is respectively connected to the switch tube MN5 and the switch tube MP0, the switch tube MP0 is connected to the switch tube MP1, the switch tube MP1 is connected to the sampling voltage divider module, the switch tube MN5 is connected to the switch tube MN6, the switch tube MN6 is connected to the sampling tube MNS, and the sampling tube MNS is connected to the capacitor CS.

[0010] Optionally, the sampling voltage-dividing module includes a switch tube MP2, and the switch tube MP2 is connected to the switch tube MN7 and the switch tube MN8 respectively.

[0011] Optional, including: When the power supply voltage AVDD is powered on, the body-source diodes of the switch tube MN2 and the switch tube MN3 are forward biased, and the node between the switch tube MN2 and the switch tube MN3 is charged to the power supply voltage AVDD.

[0012] Optional, including: When CLK is low and CLKB is high in the reset phase, the switch tubes MN2, MN1, MN0 and MN8 are turned on, vin_track and CLK_BS are 0, CLKBB is low, the switch tube MP0 is turned on, the switch tube MP1 is turned off, and the sampling tube MNS is turned off.

[0013] Optional, including: When CLK is high and CLKBB is high in the sampling phase, the switch tubes MN1 and MN2 are turned off, the switch tube MN4 is turned on, CLKB is low, the switch tubes MN0 and MN8 are turned off, the switch tube MP2 is turned on, the gate voltage of the switch tube MN7 is high, the switch tubes MN5 and MN6 are turned on, and the vin_track and N4 nodes are both charged to vin; the switch tube MN1 is turned off, the switch tube MP1 is turned on, and the switch tube MN7 is turned off, so that the VGS of the sampling tube MNS is AVDD.

[0014] In the present invention, the body terminals of the switch tubes MN2 and MN3 are connected to AVDD, which changes the body terminal potential of the NMOS tube that charges the pump capacitor and avoids the overvoltage problem. At the same time, the body terminal of the switch tube MN1 is connected to vin_track, which reduces the parasitic capacitance on the pump path and eliminates the nonlinearity of the parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A schematic diagram of a sampling gate voltage bootstrap switch that can avoid overvoltage; Figure 2 It is a waveform diagram of each node and signal inside the circuit.

[0017] The accompanying drawings illustrate: 10. Voltage multiplier module; 20. Sampling voltage divider module; 30. Switch tube module. DETAILED DESCRIPTION

[0018] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0019] The following is combined with Figure 1-2The exemplary embodiments of the present invention are described more fully. However, the exemplary embodiments can be implemented in various forms, and it should not be understood that the present invention is limited to the embodiments set forth herein. On the contrary, providing these exemplary embodiments can make the present invention more comprehensive and complete, and it is more convenient to fully convey the inventive concept to those skilled in the art. The same reference numerals in the figures represent the same or similar elements, components or parts, and thus their repeated description will be omitted.

[0020] Under the premise of being consistent with the technical concept of the present invention, the features, structures, characteristics or other details described in a specific embodiment do not exclude that they can be combined in one or more other embodiments in a suitable manner.

[0021] In the description of specific embodiments, the features, structures, characteristics or other details described in the present invention are intended to enable those skilled in the art to fully understand the embodiments. However, it does not exclude that those skilled in the art can practice the technical solutions of the present invention without one or more of the specific features, structures, characteristics or other details.

[0022] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0023] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0024] The term "and / or" or "and / or" includes all combinations of any one or more of the associated listed items.

[0025] The embodiment of this specification provides a sampling gate voltage bootstrap switch capable of avoiding overvoltage, including: Figure 1As shown, the voltage multiplier module, the sampling voltage divider module, and the switch tube module; the voltage multiplier module is connected to the sampling voltage divider module and the switch tube module respectively, and the sampling voltage divider module is connected to the switch tube module. The voltage multiplier module is to open the switch tube MN1 in the reset stage to charge the upper plate of the pump capacitor C1. The voltage multiplier module includes an inverter I1 and an inverter I2. The inverter I1 and the inverter I2 are used to generate CLKB, and the CLKBB signal controls the working state of the sampling voltage divider module and the switch tube module. The inverter I1 is connected to the pump capacitor C3 and the inverter I2 respectively, and the pump capacitor C3 is connected to the switch tube MN3. The upper plate of the capacitor is pumped to a higher voltage through the pump capacitor C3. The switch tube MN3 is connected to the switch tube MN2 and the switch tube MP4 respectively, and the initial voltage increase is achieved by alternately charging and discharging C2 and C3. The switch tube MN2 is connected to the switch tube MN1 and the pump capacitor C2 respectively. The pump capacitor C2 is connected to the inverter I2. The upper plate of the capacitor is pumped to a higher voltage through the pump capacitor C2. The switch tube MP4 is connected to the switch tube MP3, the switch tube MN9, and the power supply voltage AVDD respectively. The switch tube MP3 is connected to the switch tube MN9. The switch tube MN1 is connected to the switch tube module and the sampling voltage divider module respectively. It is worth noting that the body ends of the switch tubes MN1, MN2 and MN3 are all connected to the P-type substrate (P-sub). Since the switch tube N1 will be raised to vin+AVDD during operation, the switch tubes N2 and N3 will be raised to 2*AVDD during operation, and P-sub is grounded, the reverse bias voltage of the body-source diodes of the switch tubes MN1, MN2 and MN3 is too high, and there is a risk of breakdown. In summary, the voltage multiplier module achieves efficient voltage multiplication by cleverly utilizing switching tubes and pump capacitors. It has the advantages of high efficiency, low power consumption, small size, flexible design and high reliability.

[0026] The switch tube MN1 is replaced with a PMOS, the gate terminal is connected to the N5 node, and the body terminal is connected to the N1 node. The switch tubes MN2, MN3, pump capacitor C2, and pump capacitor C3 are all discarded. Although this also avoids the overvoltage problem, since the body end of the PMOS is an N-well (N-well), and the diode between the N-well and the P-sub has a large nonlinear capacitance, this capacitor is between the N1 node and the ground, which will cause a large nonlinearity in the sampling process. The voltage multiplier module includes an inverter I1 and an inverter I2. The inverter I1 is connected to the pump capacitor C3 and the inverter I2 respectively. The pump capacitor C3 is connected to the Deep-Nwell tube. The Deep-Nwell tube is connected to the pump capacitor C2, the switch tube module, and the sampling voltage divider module. The pump capacitor C2 is connected to the inverter I2. Under the control of the clock signal, the Deep-Nwell tubes MN2 and MN3 (as switches) are alternately turned on so that the pump capacitors C2 and C3 are connected to the power supply voltage AVDD or floating. When MN3 is turned on, the upper plate of C3 is charged to AVDD. At this time, MN2 is disconnected, so C2 is floating and the upper plate is pumped up to AVDD. When MN2 is turned on, the upper plate of C2 is charged to the power supply voltage. At this time, MN3 is disconnected, so C3 is floating and the upper plate of C3 is pumped up to AVDD.

[0027] The switch tube module includes a pumping capacitor C1. Since the switch state of MN1 is the same as that of MN2, when the upper plate of C2 is charged to AVDD, the upper plate of C1 is also charged to the same voltage; when the upper plate of C2 pumps AVDD upward, the upper plate of C1 will also pump AVDD upward to achieve that the N1 node is one AVDD higher than vin. The pumping capacitor C1 is connected to the switch tube MN0 and the switch tube MP1 respectively, the switch tube MN0 is connected to the switch tube MN4, the switch tube MN4 is connected to the switch tube MN5 and the switch tube MP0 respectively, the switch tube MP0 is connected to the switch tube MP1, the switch tube MP1 is connected to the sampling voltage divider module, the switch tube MN5 is connected to the switch tube MN6, the switch tube MN6 is connected to the sampling tube MNS, and the sampling tube MNS is connected to the capacitor CS.

[0028] The sampling voltage-dividing module includes a switch tube MP2 , and the switch tube MP2 is connected to the switch tube MN7 and the switch tube MN8 respectively.

[0029] like Figure 2 As shown, when the power supply voltage AVDD is powered on, the body-source diodes of the switch tube MN2 and the switch tube MN3 are forward biased, and the node between the switch tube MN2 and the switch tube MN3 is charged to the power supply voltage AVDD.

[0030] During the reset phase, when CLK is low and CLKB is high, the voltage of N3 is 2*AVDD, the switch tubes MN2, MN1, MN0 and MN8 are turned on, the voltages of N2 and N1 are AVDD, vin_track and CLK_BS are 0, CLKBB is low, the switch tube MP0 is turned on, the switch tube MP1 is turned off, the sampling tube MNS is turned off, and the voltage across the pump capacitor C1 is AVDD.

[0031] When CLK is high and CLKBB is high in the sampling phase, N2 is 2*AVDD, N3 is AVDD, switch tubes MN1 and MN2 are turned off, switch tube MN4 is turned on, CLKB is low, switch tubes MN0 and MN8 are turned off, switch tube MP2 is turned on, N7 node is AVDD, and the gate voltage of switch tube MN7 is high. AVDD will charge the N5 node through switch tubes MP2 and MN7. Switch tubes MN5 and MN6 are turned on, and vin_track and N4 nodes are both charged to vin; switch tube MN1 is turned off, and the N1 node is a high-resistance node. Due to the conservation of charge, the N1 voltage is raised to AVDD+vin, switch tube MP1 is turned on and VGS is AVDD, the charge of the N1 node flows to the N5 node, switch tube MN7 is turned off, CLK_BS is AVDD+vin, so that the VGS of the sampling tube MNS is AVDD.

[0032] In the present invention, the body terminals of the switch tubes MN2 and MN3 are connected to AVDD, which changes the body terminal potential of the NMOS tube that charges the pump capacitor and avoids the overvoltage problem. At the same time, the body terminal of the switch tube MN1 is connected to vin_track, which reduces the parasitic capacitance on the pump path and eliminates the nonlinearity of the parasitic capacitance.

[0033] The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the present invention is not inherently related to any specific computer, virtual device or electronic device, and various general devices can also implement the present invention. The above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

[0034] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0035] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A sampling gate voltage bootstrap switch capable of avoiding overvoltage, characterized in that: include: A voltage multiplier module (10), a sampling voltage divider module (20), and a switch tube module (30); the voltage multiplier module (10) is connected to the sampling voltage divider module (20) and the switch tube module (30) respectively, and the sampling voltage divider module (20) is connected to the switch tube module (30).

2. The sampling gate voltage bootstrap switch capable of avoiding overvoltage as claimed in claim 1, characterized in that: The voltage multiplier module (10) comprises an inverter I1 and an inverter I2, wherein the inverter I1 is connected to a pump capacitor C3 and the inverter I2 respectively, the pump capacitor C3 is connected to a switch tube MN3, the switch tube MN3 is connected to a switch tube MN2 and a switch tube MP4 respectively, the switch tube MN2 is connected to a switch tube MN1 and a pump capacitor C2 respectively, the pump capacitor C2 is connected to the inverter I2; the switch tube MP4 is connected to a switch tube MP3, a switch tube MN9 and a power supply voltage AVDD respectively, the switch tube MP3 is connected to the switch tube MN9, and the switch tube MN1 is connected to the switch tube module (30) and the sampling voltage divider module (20) respectively.

3. The sampling gate voltage bootstrap switch capable of avoiding overvoltage as claimed in claim 1, characterized in that: The voltage multiplier module (10) comprises an inverter I1 and an inverter I2, the inverter I1 being connected to a pump capacitor C3 and the inverter I2 respectively, the pump capacitor C3 being connected to a Deep-Nwell tube, the Deep-Nwell tube being connected to the pump capacitor C2, the switch tube module (30), and the sampling voltage divider module (20), and the pump capacitor C2 being connected to the inverter I2.

4. The sampling gate voltage bootstrap switch capable of avoiding overvoltage as claimed in claim 2 or 3, characterized in that: The switch tube module (30) comprises a pumping capacitor C1, the pumping capacitor C1 is respectively connected to the switch tube MN0 and the switch tube MP1, the switch tube MN0 is connected to the switch tube MN4, the switch tube MN4 is respectively connected to the switch tube MN5 and the switch tube MP0, the switch tube MP0 is connected to the switch tube MP1, the switch tube MP1 is connected to the sampling voltage dividing module (20), the switch tube MN5 is connected to the switch tube MN6, the switch tube MN6 is connected to the sampling tube MNS, and the sampling tube MNS is connected to the capacitor CS.

5. The overvoltage-avoiding sampling gate voltage bootstrap switch according to claim 4, characterized in that: The sampling voltage dividing module (20) comprises a switch tube MP2, and the switch tube MP2 is connected to the switch tube MN7 and the switch tube MN8 respectively.

6. The sampling gate voltage bootstrap switch capable of avoiding overvoltage as claimed in claim 2, characterized in that: include: When the power supply voltage AVDD is powered on, the body-source diodes of the switch tube MN2 and the switch tube MN3 are forward biased, and the node between the switch tube MN2 and the switch tube MN3 is charged to the power supply voltage AVDD.

7. The overvoltage-avoiding sampling gate voltage bootstrap switch according to claim 4, characterized in that: include: When CLK is low and CLKB is high in the reset phase, the switch tubes MN2, MN1, MN0 and MN8 are turned on, vin_track and CLK_BS are 0, CLKBB is low, the switch tube MP0 is turned on, the switch tube MP1 is turned off, and the sampling tube MNS is turned off.

8. The sampling gate voltage bootstrap switch capable of avoiding overvoltage as claimed in claim 4, characterized in that: include: When CLK is high and CLKBB is high in the sampling phase, the switch tubes MN1 and MN2 are turned off, the switch tube MN4 is turned on, CLKB is low, the switch tubes MN0 and MN8 are turned off, the switch tube MP2 is turned on, the gate voltage of the switch tube MN7 is high, the switch tubes MN5 and MN6 are turned on, and the vin_track and N4 nodes are both charged to vin; the switch tube MN1 is turned off, the switch tube MP1 is turned on, and the switch tube MN7 is turned off, so that the VGS of the sampling tube MNS is AVDD.

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