Dynamic visual sensor capable of adaptively adjusting frame rate

Abstract

A pixel array is composed of m * n pixel units, each pixel unit is connected to a column-level reading circuit through a row gating circuit module, the pixel array is connected with a row scanning chain array through a pre-comparison circuit array, the pre-comparison circuit array is composed of m * 1 pre-comparison units, and the m * 1 pre-comparison units are connected with the column-level reading circuit through a row gating circuit module. The line scanning chain array is composed of m * 1 line scanning chain units; the input end of each pre-comparison unit is connected with n pixel units in the corresponding row, the output end of each pre-comparison unit is connected with the input of the corresponding row scanning chain unit, and the output of each row scanning chain unit is connected with the row gating circuit module of each pixel unit in the corresponding row; each pre-comparison unit outputs the maximum value and the minimum value of the voltage change of the pixel unit, compares whether the maximum value and the minimum value trigger an event threshold value or not, and controls the corresponding line scanning chain unit; and each row scanning chain unit controls whether the column-level reading circuit reads data of the row pixel unit or not, so that frame rate self-adaptive adjustment is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuit design and image sensor, and more particularly to a dynamic vision sensor with adaptive frame rate adjustment. Background Art

[0002] Traditional frame-based complementary metal oxide semiconductor (CMOS) image sensors can output the light intensity information of the entire image line by line based on the absolute value of the light intensity information. Regardless of whether the pixel unit senses the change in light intensity or not, the pixel array information will be output in full frame, resulting in a large amount of data redundancy and power consumption loss.

[0003] However, the event-based dynamic vision sensor (DVS) can dynamically monitor the changes in light intensity information in the scene and only output the dynamic information in the scene, which solves the problem of static data redundancy. However, since the arbitration circuit can only process one event information at a time, if there are many pixels generating events and many row request signals, the later events may be reset, and the integrity of the image details will be difficult to guarantee. If a queuing mechanism is introduced in the arbitration circuit, the request signal of the arbitration event will introduce a queuing delay, and the real-time performance of the image will be difficult to guarantee. In order to ensure the integrity and real-time performance of the image details, a synchronous readout method based on row scanning is introduced, but the synchronous readout method will introduce unnecessary data redundancy, resulting in tight bandwidth of the back-end readout circuit. Therefore, how to avoid the reading of static information in the synchronous readout circuit is an urgent problem to be solved. Summary of the invention

[0004] In view of the problems of data redundancy and high power consumption in the synchronous readout mode of dynamic vision sensors, the present invention proposes a dynamic vision sensor with adaptive frame rate adjustment. By combining pre-judgment and scan chain, continuous multi-row skipping readout is realized to achieve adaptive frame rate adjustment, while reducing power consumption, greatly alleviating the shortage of back-end data bandwidth, and realizing high frame rate, low data redundancy and low power consumption readout.

[0005] The objectives of the present invention are achieved through the following technical solutions.

[0006] The present invention discloses a dynamic visual sensor with adaptive frame rate adjustment, comprising a pixel array, m×n row gating circuit modules, and a column-level readout circuit. The pixel array is composed of m×n pixel units, each of which is connected to a pixel input port of a corresponding column in the column-level readout circuit through a corresponding row gating circuit module. The pixel array is also connected to a row scan chain array through a pre-comparison circuit array, the pre-comparison circuit array is composed of m×1 pre-comparison units, the row scan chain array is composed of m×1 row scan chain units, and the m×1 pre-comparison units and the m×1 row scan chain units correspond to each other one by one. The input end of each pre-comparison unit is respectively connected to n pixel units of a corresponding row in the pixel array 1, the output end of each pre-comparison unit is respectively connected to the input end of the row scan chain unit corresponding to it, and the output end of each row scan chain unit is respectively connected to the row gating circuit module of each pixel unit in the corresponding row.

[0007] Furthermore, each of the pixel units converts the change in light intensity information into a change in voltage, and each of the pre-comparison units is used to output the maximum and minimum values ​​of the voltage change after conversion of the pixel units in the corresponding row, and then compares whether the maximum and minimum values ​​trigger the event threshold, thereby determining whether an OFF event or an ON event occurs, and controlling the row scan chain unit of the corresponding row based on the comparison result; each of the row scan chain units is used to control whether the column-level readout circuit reads the data of the pixel units in the row based on the output result of the pre-comparison unit of the corresponding row, thereby achieving adaptive adjustment of the frame rate.

[0008] Furthermore, each of the pre-comparison units includes a WTA circuit, an LTA circuit, and a comparison stage circuit. The WTA circuit includes a WTA differential amplifier circuit and a WTA output stage circuit. The LTA circuit includes an LTA differential amplifier circuit and an LTA output stage circuit. The positive input ends of the WTA differential amplifier circuit and the LTA differential amplifier circuit both input the differential amplifier output node voltages of the pixel units in the corresponding rows. The output ends of the WTA differential amplifier circuit and the LTA differential amplifier circuit are respectively connected to the input ends of the WTA output stage circuit and the LTA output stage circuit. The output end of the WTA output stage circuit is respectively connected to the negative input end of the WTA differential amplifier circuit and the input end of the comparison stage circuit. The output end of the LTA output stage circuit is respectively connected to the negative input end of the LTA differential amplifier circuit and the input end of the comparison stage circuit.

[0009] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0010] The present invention proposes a method for realizing continuous skip readout of multiple rows by pre-judgment control of the scan chain to improve the frame rate and reduce redundant data. By applying WTA and LTA in conjunction with the row scan chain circuit to the readout circuit of the pixel array, the light intensity change of each row of pixels can be pre-judged to determine whether the column-level readout circuit should read this row. Compared with the traditional synchronous readout method, the present invention can achieve the effects of high frame rate refresh and low data redundancy in scenarios of high-speed moving target recognition such as vehicle navigation and satellite positioning, and alleviate the back-end readout bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a diagram of the architecture of a dynamic visual sensor with adaptive frame rate adjustment according to the present invention.

[0012] Figure 2 This is a circuit structure diagram of a pixel unit in the present invention.

[0013] Figure 3 This is a circuit structure diagram of the pre-comparison unit in the present invention.

[0014] Figure 4 This is a structural diagram of the WTA differential amplifier circuit in the present invention.

[0015] Figure 5 This is a circuit structure diagram of the WTA output stage in the present invention.

[0016] Figure 6 This is a simplified circuit diagram of the WTA circuit in the present invention.

[0017] Figure 7 This is a structural diagram of the LTA differential amplifier circuit in the present invention.

[0018] Figure 8 This is a circuit structure diagram of the LTA output stage in the present invention.

[0019] Fig. 9 It is a structural diagram of the comparative circuit in the present invention.

[0020] Fig.10 It is a schematic diagram of the structure of the row scan chain array in the present invention.

[0021] Fig.11 It is a schematic diagram of the row scan chain unit circuit in the present invention.

[0022] Fig.12 This is a timing diagram of the operation of the row scan chain circuit in the present invention. DETAILED DESCRIPTION

[0023] The present invention will be further described below in conjunction with the accompanying drawings.

[0024] like Figure 1As shown, the dynamic visual sensor with adaptive frame rate adjustment of the present invention mainly includes a pixel array 1, m×n row gating circuit modules, a pre-comparison circuit array 2, a row scan chain array 3, and a column-level readout circuit 7. The pixel array 1 is composed of m×n pixel units 11, m represents the number of rows, and n represents the number of columns. Each of the pixel units 11 is connected to the pixel input port of the corresponding column in the column-level readout circuit 7 through the corresponding row gating circuit module. The pixel array 1 is also connected to the row scan chain array 3 through the pre-comparison circuit array 2, the pre-comparison circuit array 2 is composed of m×1 pre-comparison units 21, and the row scan chain array 3 is composed of m×1 row scan chain units 31. The m×1 pre-comparison units 21 and the m×1 row scan chain units 31 correspond to each other one by one, and correspond to the pixel units 11 row by row. The input end of each of the pre-comparison units 21 is respectively connected to the n pixel units 11 of the corresponding row in the pixel array 1, the output end of each of the pre-comparison units 21 is respectively connected to the input end of the corresponding row scan chain unit 31, and the output end of each of the row scan chain units 31 is respectively connected to the row selection circuit module of each pixel unit 11 of the corresponding row in the pixel array 1.

[0025] Each of the pixel units 11 converts the variation of the light intensity information into the variation of the voltage. Each of the pre-comparison units 21 is used to output the maximum and minimum values ​​of the voltage variation after the conversion of the pixel unit 11 in the corresponding row, and then compares whether the maximum and minimum values ​​trigger the event threshold, and then determines whether an OFF event and an ON event are generated, and controls the row scan chain unit 31 of the corresponding row according to the comparison result. Each of the row scan chain units 31 is used to control the column-level readout circuit 7 to read the data of the pixel unit 11 in the row according to the output result of the pre-comparison unit 21 in the corresponding row, thereby realizing adaptive adjustment of the frame rate.

[0026] In more detail, each of the pixel units 11 converts the change in light intensity information into a change in voltage. Once the threshold of the trigger event is reached, the comparator will flip and a corresponding event will be generated. The pre-comparison circuit array 2 is composed of m×1 pre-comparison units 21. Each pre-comparison unit 21 is composed of a WTA (winner take all, WTA), an LTA (loser take all, LTA), a comparator and a NAND gate. Its function is mainly to determine whether an ON or OFF event occurs in the row. Then, it is connected to a row scan chain array 3 composed of m×1 row scan chain units 31. The pre-comparison unit 21 generates a skip signal Skip_EN according to the judgment results of WTA and LTA, which is used to control whether the column-level readout circuit 7 reads out the pixel data of the row through the row scan chain unit 31, thereby realizing adaptive adjustment of the frame rate.

[0027] like Figure 2As shown, each of the pixel units 11 mainly includes a photodiode 111, a first MOS tube 112, a second MOS tube 113, a third MOS tube 114, a fourth MOS tube 115, a fifth MOS tube 116, a sixth MOS tube 117, a first capacitor 118, a seventh MOS tube 119, an eighth MOS tube 120, a ninth MOS tube 121, a second capacitor 122, a tenth MOS tube 123, an eleventh MOS tube 124, a twelveth MOS tube 125, a thirteenth MOS tube 126, a fourteenth MOS tube 127, etc.

[0028] Specifically, the positive electrode of the photodiode 111 is grounded GND, and the negative electrode is respectively connected to the source of the No. 1 MOS tube 112 and the gate of the No. 4 MOS tube 115. The drain and gate of the No. 1 MOS tube 112 are both connected to the source of the No. 2 MOS tube 113. The gate of the No. 2 MOS tube 113, the drain of the No. 3 MOS tube 114, the drain of the No. 4 MOS tube 115, and the gate of the No. 6 MOS tube 117 are all connected to the light receiving stage output node pr. The drain of the No. 2 MOS tube 113, the source of the No. 3 MOS tube 114, and the drain of the No. 6 MOS tube 117 are all connected to the voltage source VDD. The gate of the No. 3 MOS tube 114 inputs the light receiving stage bias voltage V bias_pr , gate input source follower bias voltage V of MOS tube 116 bias_sf The source of the fourth MOS tube 115 and the source of the fifth MOS tube 116 are both grounded GND, and the drain of the fifth MOS tube 116 and the source of the sixth MOS tube 117 are both connected to the drain of the eighth MOS tube 120 via the first capacitor 118 . The drain of the eighth MOS tube 120 is also connected to the drain of the ninth MOS tube 121 and the gate of the tenth MOS tube 123 respectively. A second capacitor 122 is connected between the drain and source of the ninth MOS tube 121. The source of the eighth MOS tube 120, the source of the ninth MOS tube 121, the drain of the tenth MOS tube 123, the drain of the seventh MOS tube 119, the gate of the eleventh MOS tube 124, and the gate of the fourteenth MOS tube 127 are all connected to the differential amplifier output node diff. The source of the tenth MOS tube 123, the source of the eleventh MOS tube 124, and the source of the fourteenth MOS tube 127 are all connected to the voltage source VDD. The drain of the eleventh MOS tube 124 and the drain of the fourteenth MOS tube 127 are respectively connected to the drain of the twelve MOS tube 125 and the drain of the thirteenth MOS tube 126. The source of the seventh MOS tube 119, the source of the twelve MOS tube 125, and the source of the thirteenth MOS tube 126 are all grounded GND. The gate of the ninth MOS tube 121 inputs the pixel internal reset signal nrst, the gate of the eighth MOS tube 120 inputs the global reset signal nrst_g, the gates of the seventh MOS tube 119, the twelfth MOS tube 125, and the thirteenth MOS tube 126 respectively input the switching capacitor amplifier bias voltage V ref , ON event comparator bias voltage Von , OFF event comparator bias voltage V off The drain of the twelfth MOS tube 125 and the drain of the thirteenth MOS tube 126 are simultaneously connected to the input port of the row selection circuit module corresponding to the pixel unit 11 to which they belong.

[0029] In the above circuit, the photodiode 111 senses the change of light intensity in real time, converts the light intensity into photocurrent, and then amplifies the light intensity voltage logarithmically into voltage V through the second MOS tube 113. pr , that is, the voltage of the light receiving stage output node pr. The main function of the first MOS tube 112 is to increase the photocurrent to the voltage V pr The gain of the circuit is further reduced, and the area of ​​the first capacitor 118 is further reduced. The third MOS tube 114 and the fourth MOS tube 115 form a negative feedback, which can not only increase the bandwidth of the circuit, but also clamp the positive end of the photodiode 111. The fifth MOS tube 116 and the sixth MOS tube 117 form a source follower to achieve circuit buffering. The seventh MOS tube 119, the eighth MOS tube 120, the ninth MOS tube 121, the second capacitor 122, the tenth MOS tube 123, the first capacitor 118, and the second capacitor 122 form a switched capacitor amplifier to convert the voltage V sf The change in the voltage at the source follower output node sf is amplified to produce the output voltage V diff (i.e., the voltage of the differential amplifier output node diff). The 11th MOS tube 124 and the 12th MOS tube 125 form an ON event comparator, and the 13th MOS tube 126 and the 14th MOS tube 127 form an OFF event comparator. Once the voltage V diff When the comparator threshold is reached, an event is triggered.

[0030] like Figure 3 As shown, each of the pre-comparison units 21 includes a WTA circuit, an LTA circuit, and a comparison stage circuit 213. The WTA circuit includes a WTA differential amplifier circuit 211 and a WTA output stage circuit 212. The LTA circuit includes an LTA differential amplifier circuit 214 and an LTA output stage circuit 215. The positive input terminals of the WTA differential amplifier circuit 211 and the LTA differential amplifier circuit 214 are both input with the differential amplifier output node voltage V of each pixel unit 11 in the corresponding row. diffThe output ends of the WTA differential amplifier circuit 211 and the LTA differential amplifier circuit 214 are connected to the input ends of the WTA output stage circuit 212 and the LTA output stage circuit 215, respectively. The output end of the WTA output stage circuit 212 is connected to the negative input end of the WTA differential amplifier circuit 211 and the input end of the comparison stage circuit 213, respectively. The output end of the LTA output stage circuit 215 is connected to the negative input end of the LTA differential amplifier circuit 214 and the input end of the comparison stage circuit 213. The above-mentioned entire circuit constitutes a negative feedback system. Since the WTA circuit and the LTA circuit have similar structures and working principles, the working process of the WTA circuit is described below.

[0031] The pre-comparison unit 21 is mainly composed of WTA and LTA. The main function of the WTA circuit is to output the maximum value of all input voltages for multiple input voltages, and the main function of the LTA circuit is to output the minimum value of all input voltages for multiple input voltages. Each row is equipped with a WTA and LTA circuit to respectively determine the V values ​​of all pixels in the row. diff The maximum and minimum values ​​of the node voltage. If the pixel in this row is determined by the WTA circuit to be V diff The maximum value of the node voltage is less than V b +Θ, indicating that all pixels in this row cannot generate OFF events. If the pixels in this row are judged by the LTA circuit to have V diff The minimum node voltage is greater than V b -Θ, indicating that all pixels in this row cannot generate an ON event. The comparison voltage can be achieved by two comparators, and finally a 2-bit code value is output. The 2-bit code value obtained by the WTA and LTA circuits for each row is processed by the digital circuit and transmitted to the row scan chain unit 31. Once no ON event and OFF event occur at the same time, the scan chain skip function will be triggered to control the column-level readout circuit to skip the event readout of the row, so that the column-level readout circuit 7 directly reads the next row. This can not only reduce data redundancy, but also improve the frame rate. The frame rate is determined by the number of rows skipped in each frame. The more rows are skipped, the higher the corresponding frame rate is, and the frame rate is adaptively adjusted.

[0032] Figure 4The schematic diagram of the WTA differential amplifier circuit 211 is given, which is mainly composed of a 15th MOS tube 42, a 16th MOS tube 45, a 17th MOS tube 46, an 18th MOS tube 47, a 19th MOS tube 44, a 20th MOS tube 43 and a 1st current source 41. Among them, the 1st current source 41 is respectively connected to the drain and gate of the 15th MOS tube 42, the voltage source VDD and the gate of the 16th MOS tube 45, and the source of the 15th MOS tube 42 and the source of the 16th MOS tube 45 are both grounded to GND; the 20th MOS tube 43 and the 19th MOS tube 44 are set to n groups, and n 20th MOS tubes 43 (such as Figure 4 Medium w1 -M wn ) are connected to the differential amplifier output nodes diff of the n pixel units in the corresponding row in the pixel array 1, and the sources are connected to the drain of the sixteenth MOS tube 45, and the n nineteenth MOS tubes 44 (such as Figure 4 Medium M1-M n ) are connected to the voltage source VDD, and the gates are connected to the gate of the 18th MOS tube 47. The drains of the 20th MOS tube 43 and the 19th MOS tube 44 in each group are connected to their corresponding WTA differential amplifier output nodes, namely, ow1-own. The source of the 18th MOS tube 47 is connected to the voltage source VDD, and the gate and drain are connected to the drain of the 17th MOS tube 46. The source of the 17th MOS tube 46 is connected to the drain of the 16th MOS tube 45.

[0033] In the above circuit, each group of 20 MOS tubes 43 and 19 MOS tubes 44 form a common source amplifier. Each pixel unit 11 corresponds to a common source amplifier. The differential amplification output node voltage V diffi (i=1…n) as the corresponding MOS tube 43 (i.e., corresponding to M in FIG. wi ) input, and the rightmost MOS tube 46 and MOS tube 47 form the output circuit. The function of the entire WTA differential amplifier circuit is to output all V diffi The maximum value in voltage.

[0034] Figure 5 The schematic diagram of the WTA output stage circuit 212 is given, which is mainly composed of a 21st MOS tube 51 and a 22nd MOS tube 52. The 22nd MOS tube 52 is set to n, and the n 22nd MOS tubes 52 (such as Figure 5 Medium p1 -M pn) are connected to the corresponding WTA differential amplifier output node ow1-own in the WTA differential amplifier circuit 211, the source is connected to the voltage source VDD, the drain is connected to the drain of the 22nd MOS tube 52, the source of the 22nd MOS tube 52 is grounded GND, and the gate of the 22nd MOS tube 52 is externally connected to the WTA bias voltage V BW In addition, the nth 22nd MOS tube 52 (ie, M pn )Drain(V out_W ) is also connected to the gate of the seventeenth MOS transistor 46 in the WTA differential amplifier circuit 211. The WTA differential amplifier output node voltage V generated by the WTA differential amplifier circuit 211 owi (i=1…n) is the input, and the whole constitutes a current drain inverter.

[0035] Figure 6 The simplified circuit diagram of WTA circuit is given. Assuming that all V diffi Medium V diff1 is the largest, then in the WTA differential amplifier circuit 211, in addition to V diff1 The corresponding first 19th MOS tube M1 and the first 20th MOS tube M w1 It is conducting, and the other 19th MOS tubes M2-M n And 20 MOS tube M w2 —M wn The working state is in the cut-off region or deep linear region, so there is basically no current flowing through these branches. At the same time, in the WTA output stage circuit 212, M p1 —M pn Only the first twenty-second MOS tube M p1 The branch is conducting, and the other branches are off. At this time, the circuit can be simplified as Figure 6 The circuit forms a negative feedback loop, and the output of the op amp is V ow1 , fed back to the input terminal V of the op amp through the feedback loop out_W Assume that V out_W Less than V diff1 , then V ow1 will decrease, V out_W is pulled high until V out_W Equal to V diff1 , forming a negative feedback.

[0036] Figure 7The schematic diagram of the LTA differential amplifier circuit 214 is given, which is mainly composed of a MOS tube 49 No. 23, a MOS tube 50 No. 24, a MOS tube 51 No. 25, a MOS tube 51 No. 26, a MOS tube 52 No. 27, a MOS tube 53 No. 28, a MOS tube 54 No. 2 and a current source 48 No. 2. Among them, the source of the MOS tube 49 No. 23 and the source of the MOS tube 50 No. 24 are connected to the voltage source VDD, and the drain of the MOS tube 49 No. 23 is connected to the current source 48 No. 2, the gate of the MOS tube 49 No. 23, and the gate of the MOS tube 50 No. 24. The MOS tube 53 No. 27 and the MOS tube 54 No. 28 are arranged in n groups, and the n MOS tubes 53 No. 27 (such as Figure 7 Medium d1 -M dn ) are connected to the differential amplifier output nodes diff of the n pixel units in the corresponding row in the pixel array 1, the sources of the n 27th MOS tubes 53 and the source of the 25th MOS tube 51 are connected to the drain of the 24th MOS tube 50, and the n 28th MOS tubes 54 (such as Figure 7 Medium N1-N n ) source, source of MOS tube 52 No. 26 and current source No. 28 are all grounded GND, and gates of n MOS tubes 54 No. 28 are all connected to gate of MOS tube 52 No. 26; drains of MOS tubes 53 No. 27 and MOS tubes 54 No. 28 in each group are all connected to their corresponding LTA differential amplifier output nodes, i.e., oL1-oLn. The drain of MOS tube 51 No. 25 is respectively connected to the gate and drain of MOS tube 52 No. 26. Since the function of LTA differential amplifier circuit 214 is similar to that of WTA differential amplifier circuit 211, it will not be described here.

[0037] Figure 8 The schematic diagram of the LTA output stage circuit 25 is given, which is mainly composed of a 29-number MOS tube 55 and a 30-number MOS tube 56. The 30-number MOS tube 56 is set to n, and the n 30-number MOS tubes 56 (such as Figure 8 Medium N1 -M Nn ) are all connected to the ground GND, and the drains are all connected to the drain of the 29th MOS tube 55. The source of the 29th MOS tube 55 is connected to the voltage source VDD, and the gate of the 29th MOS tube 55 is externally connected to the LTA bias voltage V BL The gates of the nth 30th MOS transistors 56 are respectively connected to the corresponding LTA differential amplifier output nodes oL1-oLn in the LTA differential amplifier circuit 214. In addition, the nth 30th MOS transistor 56 (ie, M Nn )Drain(V out_L) is also connected to the gate of the twenty-fifth MOS tube 51 in the LTA differential amplifier circuit 214. Since the function of the LTA output stage circuit 25 is similar to that of the WTA output stage circuit 215, it will not be described in detail here.

[0038] Fig. 9 The structure diagram of the comparison stage circuit 213 is given. The circuit is composed of a first comparator 61, a second comparator 62 and a NAND gate 63. The first comparator 61 has a positive input terminal and a negative input terminal respectively inputting the maximum setting threshold value V b +Θ and the output voltage V of the WTA output stage circuit 212 out_W (i.e. the nth 22nd MOS tube M pn The second comparator 62 has a positive input terminal and a negative input terminal that respectively input the output voltage V of the LTA output stage circuit 215. out_L (i.e. the nth MOS tube M Nn drain voltage) and the minimum set threshold V b -Θ. The output terminals of the first comparator 61 and the second comparator 62 are connected to the input terminals of the NAND gate 63 respectively. Assume that the ON and OFF events correspond to V diff The voltage change threshold of the node is set to Θ, and the corresponding V diff The reset voltage at V b , then an ON event is generated, V diff The node voltage needs to drop to at least V b -Θ, generates an OFF event, V diff The node voltage needs to rise to at least V b +Θ. If the pixel in this row is judged by the WTA circuit as V diff The maximum value of the node voltage V out_W <V b +Θ, and V determined by the LTA circuit diff The minimum value of the node voltage V out_L >V b -Θ, a skip signal Skip_EN will be generated, which is low valid.

[0039] Fig.10 The schematic diagram of the structure of the row scan chain array 3 is given, which is composed of row scan chain units 31 cascaded, and each of the m×1 row scan chain units 31 in the row scan chain array 3 is connected to each other through a Flag signal line. The row scan chain units 31 are transmitted step by step through a Flag signal, with Skip_EN k (k=1…m) signal is input, and output is row selection signal SEL k(k=1…m), thereby controlling whether the readout circuit reads the pixel light intensity information of the row. For example, the input of the k-th row scan chain unit 31 is connected to the output of the k-th pre-comparison unit 21, and the output SEL of the k-th row scan chain unit 31 is connected to the output of the k-th pre-comparison unit 21. k They are respectively connected to the inputs of n row gating circuit modules corresponding to the n pixel units 11 in the kth row of the pixel array 1 .

[0040] Fig.11 FIG. 3 is a circuit diagram of a row scan chain unit 31, which is composed of a control signal generating circuit 311, a reset circuit 312, a skip readout circuit 313 and a row selection signal generating circuit 314. The control signal generating circuit 311 generates a row selection signal based on the output signal Skip_EN of the pre-comparison unit 21. k (k=1…m), controls whether the skip readout circuit 313 and the row selection signal generating circuit 314 work. If the skip readout circuit 313 works, the column level readout circuit 7 does not read the row data; if the row selection signal generating circuit 314 works, the column level readout circuit 7 reads the row data. The reset circuit 312 performs a reset function on the row scan chain unit 31.

[0041] Fig.12 The working timing diagram of the row scan chain circuit is given. In the reset stage, the RST signal is high, and the control signal generating circuit 311 makes SKIP1 1 and SKIP2 0, pulling down PREV. Then after the rising edge of the clock, PRESENT and PAST are 0, completing the reset of the entire scan chain.

[0042] If an event is triggered in this row, Skip_EN is high at this time. After one clock cycle T, at time t0, PRESENT in the row selection signal generating circuit 314 becomes 1, NEXT becomes 1, and PAST becomes 0. After another clock cycle T, at time t1, PAST becomes 1, and the output SEL row selection signal is 1, thereby starting the event reading of this row. At the same time, the NEXT signal is 1, and the event scanning of the next row is performed.

[0043] If there is no event trigger in the row, Skip_EN is low, so that SKIP1 and SKIP2 in the control signal generating circuit 311 are both 1, and the transmission gates in the row selection signal generating circuit 314 are all closed. Therefore, there is no signal transmission in the row selection signal generating circuit 314. On the contrary, the skip logic circuit 313 is turned on, so that NEXT is 1, and the circuit does not generate a SEL signal, skipping the row and reading the next row.

[0044] Although the functions and working processes of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific functions and working processes. The above-mentioned specific implementation methods are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A dynamic visual sensor with adaptive frame rate adjustment, comprising a pixel array (1), m×n row gating circuit modules, and a column-level readout circuit (7), wherein the pixel array (1) is composed of m×n pixel units (11), and each of the pixel units (11) is connected to a pixel input port of a corresponding column in the column-level readout circuit (7) through a corresponding row gating circuit module, characterized in that: The pixel array (1) is also connected to a row scan chain array (3) via a pre-comparison circuit array (2); the pre-comparison circuit array (2) is composed of m×1 pre-comparison units (21); the row scan chain array (3) is composed of m×1 row scan chain units (31); the m×1 pre-comparison units (21) and the m×1 row scan chain units (31) correspond to each other one by one; the input end of each pre-comparison unit (21) is respectively connected to n pixel units (11) of a corresponding row in the pixel array (1); the output end of each pre-comparison unit (21) is respectively connected to the input end of the row scan chain unit (31) corresponding to it; and the output end of each row scan chain unit (31) is respectively connected to a row selection circuit module of each pixel unit (11) in the corresponding row.

2. The dynamic visual sensor with adaptive frame rate adjustment according to claim 1, characterized in that: Each of the pixel units (11) realizes the conversion of the variation of light intensity information into the variation of voltage. Each of the pre-comparison units (21) is used to output the maximum value and minimum value of the voltage variation after the conversion of the pixel unit (11) in the corresponding row, and then compare the maximum value and the minimum value to see whether an event threshold is triggered, thereby determining whether an OFF event and an ON event are generated, and controlling the row scan chain unit (31) in the corresponding row according to the comparison result. Each of the row scan chain units (31) is used to control the column-level readout circuit (7) to read the data of the pixel unit (11) in the corresponding row according to the output result of the pre-comparison unit (21) in the corresponding row, thereby realizing adaptive adjustment of the frame rate.

3. The dynamic visual sensor with adaptive frame rate adjustment according to claim 1, characterized in that: Each of the pre-comparison units (21) comprises a WTA circuit, an LTA circuit, and a comparison stage circuit (213); the WTA circuit comprises a WTA differential amplifier circuit (211) and a WTA output stage circuit (212); the LTA circuit comprises an LTA differential amplifier circuit (214) and an LTA output stage circuit (215); the positive input ends of the WTA differential amplifier circuit (211) and the LTA differential amplifier circuit (214) are both input with the differential amplifier output node voltage (V diff ), the output ends of the WTA differential amplifier circuit (211) and the LTA differential amplifier circuit (214) are respectively connected to the input ends of the WTA output stage circuit (212) and the LTA output stage circuit (215), the output end of the WTA output stage circuit (212) is respectively connected to the negative input end of the WTA differential amplifier circuit (211) and the input end of the comparison stage circuit (213), and the output end of the LTA output stage circuit (215) is respectively connected to the negative input end of the LTA differential amplifier circuit (214) and the input end of the comparison stage circuit (213).

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