Semiconductor memory device and forming method thereof

Abstract

The invention relates to a semiconductor memory device and a method of forming the same. A semiconductor memory device includes: an access transistor configured as a vertical transistor including a channel portion and a pair of source / drain regions; a storage capacitor connected to one of the pair of source / drain regions; a bit line connected to the other one of the pair of source / drain regions; and a first semiconductor layer disposed in the source / drain region, the bit line being connected to the first semiconductor layer. Preferably, the first semiconductor layer comprises SiGe (silicon germanium).

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with invention name “Semiconductor memory device and formation method thereof”, application number 202011535585.9, and application date December 23, 2020. Technical Field

[0003] The present application relates to a semiconductor memory device and a method for forming the same. Background Art

[0004] Recently, in semiconductor memory devices such as dynamic random access memories, it is desired to increase memory capacity, but it is difficult to increase memory capacity due to finer process sizes. Therefore, a technology has been proposed to achieve a reduction in the plane area of ​​a memory cell and an increase in memory capacity by a vertical structure of an access transistor in the memory cell. Summary of the invention

[0005] In one aspect, the present application provides a semiconductor memory device comprising: an access transistor configured as a vertical transistor including a channel portion and a pair of source / drain regions; a storage capacitor connected to one of the pair of source / drain regions; a bit line connected to the other of the pair of source / drain regions; and a first semiconductor layer disposed in the source / drain region, the bit line being connected to the first semiconductor layer.

[0006] On the other hand, the present application further provides a method for manufacturing a semiconductor memory device, which includes a pair of source / drain regions, a channel portion arranged between the source / drain regions and surrounded by an insulator, a vertical transistor including a gate electrode opposite to the channel portion via a gate insulating film, and a storage capacitor connected to one of the source / drain regions, the method including: forming a plurality of column structures extending along a first direction perpendicular to the semiconductor substrate on a semiconductor substrate, each column structure including a first semiconductor layer including one of the source / drain regions as a stacked structure, a second semiconductor layer including the channel portion, and a first insulator layer; removing the first insulator layer to expose the second semiconductor layer; forming the other of the source / drain regions by doping the exposed second semiconductor layer with impurities; forming a storage capacitor connected to the other of the source / drain regions and extending along the first direction; removing the semiconductor substrate by etching using the first semiconductor layer as an etching stopper to expose the first semiconductor layer; and forming a gate insulating film and a gate electrode in contact with the side surface of the second semiconductor layer.

[0007] On the other hand, the present application further provides a method for manufacturing a semiconductor memory device, which includes: forming a plurality of pillar structures extending along a first direction perpendicular to the semiconductor substrate on a semiconductor substrate, each pillar structure including a first semiconductor layer, a second semiconductor layer and a first insulator layer as a stacked structure; forming a second insulator layer and a shielding plate between the pillar structures; removing the first insulator layer to expose the second semiconductor layer; doping the second semiconductor layer with impurities to form a doped portion; forming a storage capacitor connected to the exposed second semiconductor layer and extending along the first direction; removing the semiconductor substrate by etching to expose the first semiconductor layer; forming a groove from the first semiconductor layer side to the doped portion between each of the second semiconductor layers and the shielding plate; forming a gate insulating film and a gate electrode in the trench; and forming a bit line connected to the first semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A and 1B is a diagram illustrating a schematic method of manufacturing a semiconductor memory device according to an embodiment. Figure 1A is a cross-sectional view showing a schematic configuration of a memory cell region in an exemplary processing stage. Figure 1B is a longitudinal sectional view showing a schematic configuration of a memory cell region in an exemplary process stage. Figure 1A is shown along Figure 1B A cross-sectional view of a schematic configuration of a portion of line AA. Figure 1B is shown along Figure 1A A longitudinal sectional view of the portion taken along line BB in the figure.

[0009] Figure 2A and 2B is a diagram showing a schematic method of manufacturing a semiconductor memory device according to an embodiment, and shows Figure 1A and 1B Schematic diagram of exemplary processing stages that follow. Figure 2A is a cross-sectional view showing a schematic configuration of a memory cell region. Figure 2B is a longitudinal sectional view showing a schematic configuration of a memory cell region. Figure 2A is shown along Figure 2B A cross-sectional view of a schematic configuration of a portion of line AA. Figure 2B is shown along Figure 2A A longitudinal sectional view of the portion taken along line BB in the figure.

[0010] Figure 3A and 3B is a diagram showing a schematic method of manufacturing a semiconductor memory device according to an embodiment, and shows Figure 2A and 2BSchematic diagram of exemplary processing stages that follow. Figure 3A is a cross-sectional view showing a schematic configuration of a memory cell region. Figure 3B is a longitudinal sectional view showing a schematic configuration of a memory cell region. Figure 3A is shown along Figure 3B A cross-sectional view of a schematic configuration of a portion of line AA. Figure 3B is shown along Figure 3A A longitudinal sectional view of the portion taken along line BB in the figure.

[0011] Figure 4A and 4B is a diagram showing a schematic method of manufacturing a semiconductor memory device according to an embodiment, and shows Figure 3A and 3B Schematic diagram of exemplary processing stages that follow. Figure 4A is a cross-sectional view showing a schematic configuration of a memory cell region. Figure 4B is a longitudinal sectional view showing a schematic configuration of a memory cell region. Figure 4A is shown along Figure 4B A cross-sectional view of a schematic configuration of a portion of line AA. Figure 4B is shown along Figure 4A A longitudinal sectional view of the portion taken along line BB in the figure.

[0012] Figure 5A and 5B is a diagram showing a schematic method of manufacturing a semiconductor memory device according to an embodiment, and shows Figure 4A and 4B Schematic diagram of exemplary processing stages that follow. Figure 5A is a cross-sectional view showing a schematic configuration of a memory cell region. Figure 5B is a longitudinal sectional view showing a schematic configuration of a memory cell region. Figure 5A is shown along Figure 5B A cross-sectional view of a schematic configuration of a portion of line AA. Figure 5B is shown along Figure 5A A longitudinal sectional view of the portion taken along line BB in the figure.

[0013] Fig. 6A and 6B is a diagram showing a schematic configuration and a schematic manufacturing method of a semiconductor memory device according to an embodiment, and shows Figure 5A and 5B Schematic diagram of exemplary processing stages that follow. Fig. 6A is a cross-sectional view showing a schematic configuration of a memory cell region. Figure 6B is a longitudinal sectional view showing a schematic configuration of a memory cell region.

[0014] Fig. 6A is shown along Figure 6B A cross-sectional view of a schematic configuration of a portion of line AA. Figure 6B is shown along Fig. 6A A longitudinal sectional view of the portion taken along line BB in the figure.

[0015] Figure 7 is a longitudinal section showing a schematic overall configuration of a semiconductor memory device according to the embodiment. DETAILED DESCRIPTION

[0016] Various embodiments of the present invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that illustrate specific aspects and embodiments of the present invention that can be practiced by means of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. It should be understood that other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0017] In the following we will refer to Figures 1A to 7 A semiconductor memory device and a manufacturing method thereof according to an embodiment are described. In the following description, a dynamic random access memory (hereinafter referred to as DRAM) is taken as an example of a semiconductor memory device 1. In addition, in the following description, the X direction is a direction parallel to the word line, and the Y direction is a direction perpendicular to the X direction and parallel to the bit line. In addition, the Z direction is a direction perpendicular to the XY plane defined as the plane of the semiconductor substrate 2, and is also referred to as a first direction or a vertical direction.

[0018] Hereinafter, a method of manufacturing the semiconductor memory device 1 according to the embodiment will be described.

[0019] like Figure 1A and 1B As shown in FIG, a first semiconductor layer 4, a second semiconductor layer 6, and a first insulator layer 8 are stacked on a semiconductor substrate 2. Next, patterning is performed using known photolithography and dry etching techniques to form a plurality of column structures K extending in a vertical direction and independently disposed on the semiconductor substrate 2. The column structure K is a stack of the first semiconductor layer 4, the second semiconductor layer 6, and the first insulator layer 8.

[0020] The semiconductor substrate 2 is, for example, a disk-shaped single-crystal silicon wafer having a main plane that has been mirror-finished. The first semiconductor layer 4 contains, for example, silicon germanium (SiGe). The first semiconductor layer 4 can be formed, for example, by epitaxial growth. The SiGe forming the first semiconductor layer 4 has a germanium (Ge) content of 20% to 30%. The first semiconductor layer 4 serves as one of a pair of source / drain regions of a DRAM access transistor described later. It should be noted that in DRAM, because the source and drain of the access transistor switch roles when writing and reading data, the pair of source and drain regions of the transistor are referred to as source / drain regions herein.

[0021] The second semiconductor layer 6 may include, for example, silicon (Si). The second semiconductor layer 6 may be formed, for example, by epitaxial growth. The first insulator layer 8 may include, for example, silicon nitride (SiN). The first insulator layer 8 is formed, for example, by chemical vapor deposition (hereinafter referred to as CVD). In the following description, chemical vapor deposition will be referred to as CVD. A gap 9 is provided between the column structure K including the first semiconductor layer 4, the second semiconductor layer 6 and the first insulator layer 8.

[0022] Next, as shown in 2A and 2B, a second insulator layer 10 and a shielding plate 12 are formed in each of the gaps 9 between the column structures K. The second insulator layer 10 includes, for example, silicon oxide (SiO2). The shielding plate 12 includes polycrystalline silicon (poly-Si) doped with phosphorus (P) as an impurity. The second insulator layer 10 and the shielding plate 12 can be formed, for example, by CVD. The shielding plate 12 is surrounded by the second insulator layer 10 inside each gap 9.

[0023] Next, if Figure 3A and 3B As shown, the first insulator layer 8 is selectively removed to expose the surface of the second semiconductor layer 6. For example, the first insulator layer 8 can be selectively removed by etching using a hot phosphoric acid solution. Thereafter, the doped portion 14 is formed by doping the exposed portion of the second semiconductor layer 6 with, for example, phosphorus (P) as an impurity. The doping of phosphorus can be achieved, for example, by ion implantation. As described later, the doped portion 14 serves as a source / drain region of a DRAM access transistor.

[0024] Next, a lower electrode 18, a capacitor insulating film 20 and an upper electrode 22 are formed. The lower electrode 18 and the upper electrode 22 include, for example, titanium nitride (TiN). The lower electrode 18 and the upper electrode 22 can be formed, for example, by CVD. The capacitor insulating film 20 includes a high-k film with a high dielectric constant. The high-k film includes, for example, a metal oxide containing a metal such as zirconium (Zr) or aluminum (Al).

[0025] By this arrangement, a storage capacitor 24 connected to the doped portion 14 and extending in the first direction is formed. Afterwards, a third insulator layer 26 is formed, and the storage capacitor 24 is covered by the third insulator layer 26. The third insulator layer 26 can be formed using, for example, a silicon oxide layer. The third insulator layer 26 is formed, for example, by CVD.

[0026] Next, if Figure 4A and 4B As shown, the semiconductor substrate 2 is turned back and forth or upside down, and the semiconductor substrate 2 is removed by etching. Note that Figure 4B and described later Figure 5B and 6B With respect to the reference in the foregoing description Figure 1B , 2B In the etching step, in the case where single wafer etching is not used, in other words, in the case where the semiconductor substrate 2 is immersed in an etching bath for etching, as long as the etching step described later is used, Figure 5A and 5B In the described steps, the front and back sides of the semiconductor substrate 2 may be reversed.

[0027] For example, tetramethylammonium hydroxide (TMAH) diluted in water or an aqueous ammonia solution (NH3(aq)) diluted in water is used to perform etching of the semiconductor substrate 2, in other words, etching of silicon. The etching of the semiconductor substrate 2 is stopped at the moment when the surface of the first semiconductor layer 4 is exposed. The etching amount of the semiconductor substrate 2 is controlled by the etching time.

[0028] Here, the first semiconductor layer 4 contains SiGe. In addition, the SiGe forming the first semiconductor layer 4 has a Ge content of 20% to 30%. By forming SiGe in this way, a high selectivity with respect to silicon can be set in silicon etching by TMAH diluted in water or an ammonia solution diluted in water. For this reason, SiGe acts as a good etching stopper in silicon etching by TMAH diluted in water or an ammonia solution. Therefore, etching of silicon can be performed uniformly, and variations in etching amount can be suppressed.

[0029] Next, if Figure 5A and 5B As shown, the doped portion 4a doped with phosphorus is formed by doping a portion of the first semiconductor layer 4 with, for example, phosphorus (P) as an impurity while the semiconductor substrate 2 is reversed front to back. The doping of phosphorus can be performed, for example, by ion implantation.

[0030] Next, a groove is formed between the second semiconductor layer 6 and the shielding plate 12, which reaches the doped portion 14 from the side of the first semiconductor layer 4. A groove 28 extending in the Z direction is formed. After that, phosphorus, for example, is implanted into the doped portion 14 at the bottom of the groove 28 by ion implantation, and an extended doped portion 15 is formed. The groove 28 can be formed using known photolithography and dry etching techniques. The doped portion 14 and the extended doped portion 15 serve as source / drain regions of an access transistor 33, which is a vertical transistor described later. The extended doped portion 15 serves as an extension of the source / drain region of the access transistor 33.

[0031] Next, a gate insulating film 30 and a gate electrode 32 are formed and buried in the trench 28. The gate insulating film 30 includes, for example, a silicon oxide film. The gate electrode 32 includes, for example, a conductive material such as titanium nitride. The gate insulating film 30 and the gate electrode 32 can be formed, for example, by CVD. With this arrangement, a gate electrode 32 in contact with the side surface of the second semiconductor layer 6 can be formed, the gate electrode serving as a channel portion passing through the gate insulating film 30.

[0032] Next, if Fig. 6A and 6B As shown, a plurality of bit lines 34 extending in the Y direction are formed. The bit lines 34 include a conductive material such as WSi, WN, W, etc. The bit lines 34 are electrically connected to the first semiconductor layer 4 by adjoining the first semiconductor layer 4 .

[0033] Through the above steps, a semiconductor memory device 1 including an access transistor 33 can be formed, wherein the access transistor has a configuration in which the first semiconductor layer 4, the doped portion 4a, the second semiconductor layer 6, the doped portion 14, and the extended doped portion 15 are arranged side by side in the Z direction. The access transistor 33 is formed as a vertical metal oxide semiconductor field effect transistor (MOSFET), and a channel portion formed in the second semiconductor layer 6 extends in the Z direction (i.e., the vertical direction). Hereinafter, a transistor in which a channel portion is formed in the vertical direction and source / drain regions are disposed above and below the channel portion is referred to as a vertical transistor.

[0034] In addition, through the above steps, a configuration can be realized in which the access transistor 33 and the storage capacitor 24 are stacked vertically in the Z direction. With this arrangement, the area occupied by the memory cell in the XY plane can be reduced, and a highly integrated semiconductor memory device 1 can be realized.

[0035] In addition, a DRAM access transistor 33 is formed through the above steps. The first semiconductor layer 4 including the doped portion 4a, and the extended doped portion 15 and the doped portion 14 are used as the source / drain region of the access transistor 33. The gate electrode 32 is used as the gate electrode of the access transistor 33. The gate electrode 32 is used as a word line of the semiconductor memory device 1. The second semiconductor layer 6 is used as the channel portion of the access transistor 33. The second semiconductor layer 6 forming the channel portion of the access transistor 33 is surrounded by an insulating film except for the portion connected to the first semiconductor layer 4 and the doped portion 14. Therefore, the access transistor 33 is a fully depleted or partially depleted SOI transistor. The shielding plate 12 is connected to a predetermined potential and serves as an insulator for electrically isolating the access transistor 33.

[0036] In the access transistor 33, the first semiconductor layer 4 used as the source / drain region contains SiGe. If SiGe is used to form the source / drain region of the access transistor 33 as a MOSFET, and the MOSFET has a structure in which the second semiconductor layer 6 used as the channel portion is surrounded by an insulator, the floating body effect of the channel portion can be suppressed. This is because the band gap of SiGe is narrower than the band gap of silicon, so even if holes are generated in the channel portion, the holes easily pass through the second semiconductor layer 6 and escape to the bit line 34, thereby reducing the degree of voltage drop in the channel portion. In other words, the provision of the SiGe layer on the bit line contact side lowers the barrier and suppresses the floating body effect of the access transistor 33. Therefore, in the case of using the access transistor 33 in which the first semiconductor layer 4 used as the source / drain region connected to the bit line 34 contains SiGe, the write characteristics and read characteristics of the semiconductor memory device 1 become good, and a high-performance semiconductor memory device 1 can be realized.

[0037] In addition, by forming the first semiconductor layer 4 using SiGe, the contact resistance with the bit line 34 can be reduced.

[0038] Furthermore, through the above steps, a memory cell structure having a bit line 34, a gate electrode 32, an access transistor 33, and a storage capacitor 24 is formed. The memory cell structure corresponds to the memory cell structure described later. Figure 7 The structure shown in E.

[0039] Figure 7 1 is a longitudinal sectional view schematically showing the overall configuration of a semiconductor memory device 1 including the above-described memory cell structure E. Figure 7 As shown, the semiconductor memory device 1 includes a memory cell structure E, a peripheral circuit portion F, and an interconnection portion G.

[0040] The memory cell structure E forms a memory cell portion of the semiconductor memory device 1 , and is provided with a plurality of gate electrodes 32 (word lines), bit lines 34 , access transistors 33 , and storage capacitors 24 . Figure 7 The memory cell structure E shown is relative to Fig. 6A and 6B The semiconductor memory device 1 is shown to be arranged upside down.

[0041] The peripheral circuit portion F is provided with a peripheral circuit for driving the memory cell. The peripheral circuit includes a CMOS transistor 38 formed on a semiconductor substrate 36. The surface of the semiconductor substrate 36 provides a surface parallel to the XY plane, and the CMOS transistor 38 is formed on the surface of the semiconductor substrate 36. The interconnection portion G is provided with a wiring layer including a plurality of interconnections.

[0042] The semiconductor memory device 1 is obtained by bonding the memory cell structure E and the peripheral circuit part F at the bonding surface D, and further forming the interconnection part G. In the semiconductor memory device 1 according to the embodiment, the peripheral circuit part F and the memory cell structure E are stacked in the Z direction. The channel direction of the access transistor 33 extends in a direction perpendicular to the semiconductor substrate 36. In addition, the longitudinal direction of the storage capacitor 24 is perpendicular to the semiconductor substrate 36. Therefore, the plane area occupied by the memory cell and the peripheral circuit can be reduced, and the chip area of ​​the semiconductor memory device 1 can be reduced. Therefore, a semiconductor memory device 1 with reduced cost can be provided.

[0043] As described above, DRAM is described as an example of the semiconductor memory device 1 according to the embodiment, but the above description is only an example and is not intended to be limited to DRAM. For example, other memory devices other than DRAM, such as static random access memory (SRAM), flash memory, erasable programmable read-only memory (EPROM), magnetoresistive random access memory (MRAM), and phase change memory, can also be applied as the semiconductor memory device 1. In addition, devices including logic ICs other than memories, such as microprocessors and application-specific integrated circuits (ASICs), are also suitable as the semiconductor memory device 1 according to the above-mentioned embodiments.

[0044] Although the present invention has been disclosed in the context of certain preferred embodiments and examples, it will be appreciated by those skilled in the art that the present invention can extend beyond the specifically disclosed embodiments to other alternative embodiments and / or the present invention and its obvious modifications and use of equivalents. In addition, based on this disclosure, other modifications within the scope of the present invention will be apparent to those skilled in the art. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be performed and still be within the scope of the present invention. It should be understood that the various features and aspects of the disclosed embodiments can be combined with each other or replace each other to form a variation pattern of the disclosed invention. Therefore, it is desired that the scope of at least some of the present invention disclosed herein should not be limited by the specific disclosed embodiments described above.

Claims

1. A semiconductor device comprising: bit line; A transistor comprising: A first semiconductor layer located on the bit line, the first semiconductor layer comprising a first doped portion; and a second semiconductor layer configured as a channel portion on the first semiconductor layer, the second semiconductor layer including a second doped portion opposite to the first doped portion; and A storage capacitor is coupled to the second doped portion. 2 . The semiconductor device according to claim 1 , wherein the first semiconductor layer comprises silicon germanium (SiGe). 3 . The semiconductor device according to claim 1 , wherein the transistor further includes a gate electrode that is in contact with a side surface of the channel portion through a gate insulating film. The semiconductor device according to claim 1 , wherein the second doped portion and the channel portion are in contact with each other. 5 . The semiconductor device of claim 4 , wherein the transistor further comprises an extended doped portion located between a portion of the second doped portion and a portion of the channel portion.

6. The semiconductor device according to claim 5, wherein: The first doped portion, the channel portion, the second doped portion, and the extended doped portion are arranged in a first direction, the first direction is perpendicular to the bit line extending in a second direction, and The storage capacitor extends in the first direction. 7 . The semiconductor device according to claim 1 , further comprising a shielding plate between the transistor and other transistors adjacent to the transistor. 8 . The semiconductor device according to claim 7 , wherein the shielding plate is located between the channel portion of the transistor and a gate electrode of another transistor. 9 . The semiconductor device of claim 7 , wherein the first doped portion, the second doped portion, and the shielding plate include phosphorus (P).

10. A method of manufacturing a semiconductor memory device, the semiconductor memory device comprising a transistor, the method comprising: forming a first semiconductor layer on a semiconductor substrate; forming a second semiconductor layer on the first semiconductor layer; forming a first insulating layer on the second semiconductor layer; forming a plurality of pillar structures including the first semiconductor layer, the second semiconductor layer, and the first insulating layer, and providing gaps between adjacent pillar structures among the plurality of pillar structures; removing the first insulating layer to expose the second semiconductor layer; doping the exposed second semiconductor layer with impurities to form a doped portion of the second semiconductor layer; forming a storage capacitor on the doped portion; inverting a stack structure including the semiconductor substrate, the first semiconductor layer, the second semiconductor layer, and the storage capacitor; and The semiconductor substrate is etched using the first semiconductor layer as an etch stopper.

11. The method according to claim 10, wherein: The first semiconductor layer includes silicon germanium (SiGe) having a germanium content of 20 wt % to 30 wt %, and Etching the semiconductor substrate is performed using tetramethylammonium hydroxide or an aqueous ammonia solution diluted in water. 12 . The method of claim 10 , further comprising forming a second insulating layer in the gap and a shielding plate in the second insulating layer. 13 . The method of claim 12 , further comprising doping the first semiconductor layer exposed by the etching with impurities to form a doped portion of the first semiconductor layer.

14. The method according to claim 13, further comprising: forming a groove between the channel portion and the shielding plate to reach the doped portion of the second semiconductor layer; and The exposed doped portion of the second semiconductor layer is doped with impurities to form an extended doped portion. The method of claim 14 , wherein forming the trench is performed using photolithography and dry etching. 16 . The method of claim 14 , wherein doping the exposed first semiconductor layer, the exposed second semiconductor layer, and the exposed doped portion of the second semiconductor layer with the impurity is performed by ion implantation. 17 . The method of claim 14 , wherein the impurity of the exposed first semiconductor layer, the exposed second semiconductor layer, the exposed doped portion, and the shielding plate is phosphorus. 18 . The method according to claim 14 , further comprising forming a gate insulating film and a gate electrode in the trench.

19. The method according to claim 18, wherein forming the gate insulating film and the gate electrode is performed by chemical vapor deposition (CVD).

20. A semiconductor device comprising: bit line; and A transistor comprising a first semiconductor layer coupled to the bit line and serving as a source / drain region, wherein The first semiconductor layer includes silicon germanium (SiGe), and a contact resistance between silicon germanium (SiGe) and the bit line is lower than a contact resistance between a semiconductor layer including silicon (Si) and the bit line. 21 . The semiconductor device according to claim 20 , wherein the bit line comprises any one conductive material including at least one of tungsten silicide (WSi), tungsten nitride (WN), or tungsten (W).

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