Array substrate, driving method and display device

Abstract

An array substrate, a driving method thereof and a display device. The array substrate is connected with two adjacent gate lines in each row of sub-pixels; at least one data line is connected with two adjacent columns of sub-pixels; the plurality of rows of sub-pixels comprise a plurality of groups of sub-pixels, each group of sub-pixels comprises a plurality of rows of sub-pixels, each row of sub-pixels comprises sub-pixels connected with the same gate line, and the charging time of the plurality of rows of sub-pixels overlaps; the plurality of rows of sub-pixels comprise a first plurality of rows of sub-pixels and a second plurality of rows of sub-pixels, the charging time of the second plurality of rows of sub-pixels is longer than that of the first plurality of rows of sub-pixels, in a first time period in which the charging time overlaps, the first plurality of rows of sub-pixels and the second plurality of rows of sub-pixels write the same data signal, and in a second time period in which the charging time does not overlap, the data signal written by the second plurality of rows of sub-pixels is at least partially the same as the data signal written in the first time period. The array substrate can realize the HST mode of the double-gate pixel driving structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to an array substrate, a driving method and a display device. BACKGROUND

[0002] In the field of display technology, a pixel array of a display panel such as a liquid crystal display panel or an organic light emitting diode (OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines arranged in cross with the gate lines. The driving of the gate lines can be achieved by a gate driving circuit. The driving of the data lines can be achieved by a source driving circuit. For example, the gate driving circuit provides a switching state voltage signal (gate signal) for the multiple rows of gate lines of the pixel array, thereby for example controlling the multiple rows of gate lines to be opened in sequence, and at the same time, a data signal is provided by the data lines to the pixel units of the corresponding row in the pixel array, so as to form a gray scale voltage required by each gray scale of the display image at each pixel unit, and thus display a frame of image. SUMMARY

[0003] At least one embodiment of the present disclosure provides an array substrate, including a pixel array formed by multiple rows and multiple columns of sub-pixels, multiple gate lines and multiple data lines intersecting to define the multiple rows and multiple columns of sub-pixels, each row of sub-pixels being connected with two adjacent gate lines in the multiple gate lines; at least one data line in the multiple data lines being connected with two adjacent columns of sub-pixels in the multiple columns of sub-pixels; the multiple gate lines being used to open the multiple rows of sub-pixels, and the multiple data lines being used to charge the multiple columns of opened sub-pixels; the multiple rows of sub-pixels including multiple groups of sub-pixels, each group of sub-pixels including part of the rows of sub-pixels in the multiple rows of sub-pixels, each row of sub-pixels in the part of the rows of sub-pixels including sub-pixels connected with the same gate line, and charging time of the part of the rows of sub-pixels overlapping; the part of the rows of sub-pixels including a first part of the rows of sub-pixels and a second part of the rows of sub-pixels, the charging time of the second part of the rows of sub-pixels being longer than the charging time of the first part of the rows of sub-pixels, in a first time period in which the charging time overlaps, the first part of the rows of sub-pixels and the second part of the rows of sub-pixels write the same data signal, and in a second time period in which the charging time does not overlap, the data signal written by the second part of the rows of sub-pixels is at least partially the same as the data signal written in the first time period.

[0004] For example, in the array substrate provided by an embodiment of the present disclosure, in the part of the rows of sub-pixels, the same data line is connected with multiple sub-pixels of the same color.

[0005] For example, in the array substrate provided by an embodiment of the present disclosure, the charging time of the first part of the rows of sub-pixels is the charging time of 1 row of sub-pixels, the charging time of the second part of the rows of sub-pixels is the charging time of 2 rows of sub-pixels, and the first part of the rows of sub-pixels and the second part of the rows of sub-pixels start charging at the same time.

[0006] For example, in the array substrate provided by an embodiment of the present disclosure, the same data line is connected to multiple groups of sub-pixels, and the multiple sub-pixels of the same color connected to the same data line are connected to the odd-numbered row of gate lines or the even-numbered row of gate lines.

[0007] For example, in the array substrate provided by an embodiment of the present disclosure, the same column of sub-pixels corresponds to the same color, the multiple sub-pixels corresponding to red are connected to the odd-numbered row of gate lines, the multiple sub-pixels corresponding to green are connected to the even-numbered row of gate lines, and the multiple sub-pixels corresponding to blue connected to the same data line are connected to the multiple odd-numbered rows of gate lines or the multiple even-numbered rows of gate lines; or the multiple sub-pixels corresponding to green are connected to the odd-numbered row of gate lines, the multiple sub-pixels corresponding to blue are connected to the even-numbered row of gate lines, and the multiple sub-pixels corresponding to red connected to the same data line are connected to the multiple odd-numbered rows of gate lines or the multiple even-numbered rows of gate lines; or the multiple sub-pixels corresponding to red are connected to the odd-numbered row of gate lines, the multiple sub-pixels corresponding to blue are connected to the even-numbered row of gate lines, and the multiple sub-pixels corresponding to green connected to the same data line are connected to the multiple odd-numbered rows of gate lines or the multiple even-numbered rows of gate lines.

[0008] For example, in the array substrate provided by an embodiment of the present disclosure, the same column of sub-pixels corresponds to the same color, the multiple sub-pixels corresponding to red connected to the same data line are connected to the multiple odd-numbered rows of gate lines or the multiple even-numbered rows of gate lines, the multiple sub-pixels corresponding to green connected to the same data line are connected to the multiple odd-numbered rows of gate lines or the multiple even-numbered rows of gate lines, and the multiple sub-pixels corresponding to blue connected to the same data line are connected to the multiple odd-numbered rows of gate lines or the multiple even-numbered rows of gate lines.

[0009] For example, in the array substrate provided by an embodiment of the present disclosure, one image frame includes a first display period and a second display period, two adjacent odd-numbered rows of gate lines are taken as a group, two adjacent even-numbered rows of gate lines are taken as a group, two rows of sub-pixels connected by each group of gate lines are taken as a group of sub-pixels, for the odd-numbered row of gate lines, multiple groups of odd-numbered rows of gate lines are sequentially turned on in the first display period; for the even-numbered row of gate lines, multiple groups of even-numbered rows of gate lines are sequentially turned on in the second display period, and in each group of gate lines, the gate line connected to the first part of rows of sub-pixels is turned on earlier than the gate line connected to the second part of rows of sub-pixels.

[0010] For example, in the array substrate provided by an embodiment of the present disclosure, two gate lines serve as a gate line group, two rows of sub-pixels connected with the two gate lines in the gate line group form a sub-pixel group, the sub-pixel group corresponds to sub-pixels of the same color connected with the same data line, and multiple groups of gate lines are sequentially turned on, wherein, for each group of gate lines, the gate lines connected with the first part of rows of sub-pixels are turned on earlier than the gate lines connected with the second part of rows of sub-pixels.

[0011] For example, in the array substrate provided by an embodiment of the present disclosure, the multiple gate lines include multiple first gate line groups, multiple groups of sub-pixels include multiple first sub-pixel groups, each first gate line group includes two adjacent gate lines, two rows of sub-pixels connected with each first gate line group form the first sub-pixel group, and two sub-pixels connected with the same data line in each first sub-pixel group correspond to the same color.

[0012] For example, in the array substrate provided by an embodiment of the present disclosure, the multiple groups of sub-pixels further include a second sub-pixel group, the second sub-pixel group includes multiple sub-pixels connected with the gate line turned on first in the multiple gate lines, and the multiple first sub-pixel groups include multiple rows of sub-pixels other than the sub-pixels included in the first second sub-pixel group.

[0013] Another embodiment of the present disclosure provides a driving method applied to the array substrate provided by any one of the embodiments of the present disclosure, and the method includes: turning on multiple gate lines connected with each group of sub-pixels; and charging, by multiple data lines, each group of sub-pixels during the turning on of the multiple gate lines of each group of sub-pixels.

[0014] For example, in the driving method provided by an embodiment of the present disclosure, multiple groups of sub-pixels are connected with the same data line, multiple sub-pixels of the same light-emitting color connected with the same data line are connected with odd-numbered rows of gate lines or even-numbered rows of gate lines, one image frame includes a first display period and a second display period, two adjacent odd-numbered rows of gate lines serve as a group, two adjacent even-numbered rows of gate lines serve as a group, two rows of sub-pixels connected with each group of gate lines serve as a group of sub-pixels, and sequentially turning on multiple gate lines connected with each group of sub-pixels includes: in the first display period, sequentially turning on the odd-numbered rows of gate lines; and in the second display period, sequentially turning on the even-numbered rows of gate lines, and for each group of gate lines, the gate lines connected with the first part of rows of sub-pixels are turned on earlier than the gate lines connected with the second part of rows of sub-pixels.

[0015] For example, in the driving method provided by an embodiment of the present disclosure, two gate lines are taken as a gate line group, and two rows of sub-pixels connected with the two gate lines in the gate line group form a sub-pixel group, the sub-pixel group and the sub-pixels connected with the same data line correspond to the same light-emitting color, and sequentially turning on the multiple gate lines connected with each group of sub-pixels includes sequentially turning on multiple groups of gate lines, wherein for each group of gate lines, the gate lines connected with the first part of rows of sub-pixels are turned on earlier than the gate lines connected with the second part of rows of sub-pixels.

[0016] For example, in the driving method provided by an embodiment of the present disclosure, the multiple gate lines include multiple first gate line groups, each group of sub-pixels is two adjacent rows of sub-pixels, each first gate line group includes two adjacent gate lines, and the two sub-pixels connected with the same data line in each first sub-pixel group correspond to the same color, and sequentially turning on the multiple gate lines connected with each group of sub-pixels includes sequentially turning on each gate line, and the gate lines connected with the first part of rows of sub-pixels in each group of sub-pixels are turned on earlier than the gate lines connected with the second part of rows of sub-pixels.

[0017] For example, in the driving method provided by an embodiment of the present disclosure, the charging time of the first part of rows of sub-pixels is the charging time of 1 row of sub-pixels, and the charging time of the second part of rows of sub-pixels is the charging time of 2 rows of sub-pixels, and the first part of rows of sub-pixels and the second part of rows of sub-pixels start charging at the same time.

[0018] Another embodiment of the present disclosure provides a display device, which includes the array substrate provided by any of the embodiments of the present disclosure.

[0019] For example, in the display device provided by an embodiment of the present disclosure, further comprising: an opposite substrate, the opposite substrate includes a color filter layer, the color filter layer includes multiple color resistances, the multiple color resistances include multiple blue color resistances, multiple red color resistances and multiple green color resistances, and the multiple color resistances one-to-one correspond to the multiple rows and multiple columns of sub-pixels.

[0020] For example, in the display device provided by an embodiment of the present disclosure, further comprising a circuit board, the circuit board is provided with a timing controller, the array substrate further includes a source driving chip, the timing controller is coupled with the source driving chip, and is configured to provide display data to the source driving chip; and the source driving chip is coupled with the multiple data lines, and is configured to provide the data signals to the multiple data lines according to the display data.

[0021] For example, in the display device provided by the embodiment of the present disclosure, the circuit board further comprises a level conversion unit, the array substrate further comprises a gate drive circuit, the level conversion unit is coupled with the timing controller, the gate drive circuit is connected with the level conversion unit and the plurality of gate lines, the level conversion unit is configured to receive a plurality of first clock signals provided by the timing controller, and convert the plurality of first clock signals into a plurality of second clock signals, and provide the plurality of second clock signals to the gate drive circuit, and the gate drive circuit is configured to provide a gate signal to the gate line according to the plurality of second clock signals, so as to control the gate line to be turned on. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only related to some embodiments of the present disclosure, and not limit the present disclosure.

[0023] Figure 1A A timing diagram of a conventional pixel driving mode is shown;

[0024] Figure 1B A timing diagram of an HSR pixel driving mode is shown;

[0025] Figure 2A A schematic diagram of an array substrate provided by at least one embodiment of the present disclosure is shown;

[0026] Figure 2B A schematic diagram of an array substrate provided by at least one embodiment of the present disclosure is shown; Figure 2A A timing diagram of the array substrate is shown;

[0027] Figure 3A A schematic diagram of another array substrate provided by some embodiments of the present disclosure is shown;

[0028] Figure 3B A schematic diagram of another array substrate provided by some embodiments of the present disclosure is shown;

[0029] Figure 3C A schematic diagram of another array substrate provided by some embodiments of the present disclosure is shown;

[0030] Figure 4 A timing diagram of another driving mode applied to the array substrate provided by some embodiments of the present disclosure is shown; Figure 2A and Figures 3A-3C A timing diagram of another driving mode applied to the array substrate provided by some embodiments of the present disclosure is shown;

[0031] Figure 5A A schematic diagram of another array substrate provided by at least one embodiment of the present disclosure is shown;

[0032] Figure 5BA timing diagram of a driving mode of the array substrate is shown. Figure 5A A timing diagram of a driving mode of the array substrate is shown.

[0033] Figure 6A A timing diagram of a driving mode of the array substrate is shown.

[0034] Figure 6B A timing diagram of a driving mode of the array substrate is shown. DETAILED DESCRIPTION

[0035] For the purpose of making the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present disclosure.

[0036] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The terms “first”, “second”, and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms “one”, “a”, or “the” or similar terms do not denote quantity restriction, but mean that there is at least one. The terms “include”, “contain”, or “comprise” or similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connect” or “connected” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper”, “lower”, “left”, “right”, and the like only represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0037] For example, the liquid crystal display is driven by row scanning, i.e. one row after another is turned on, and all columns of data lines transmit data signals to the pixels in the row. According to the number of rows turned on at a certain moment and the input of the corresponding pixel signals, the pixel driving structure can include a single-gate pixel driving structure, a double-gate pixel driving structure, and a three-gate pixel driving structure, etc. The single-gate pixel driving structure is that one row of sub-pixels is connected with one gate line and controlled by the gate line, and one column of sub-pixels is connected with one data line and controlled by the data line. For example, the 1G1D structure is a conventional single-gate pixel driving structure, i.e. only one row is turned on at a certain moment, and all columns of data lines transmit data signals to the pixels in the row. In the double-gate pixel driving structure, the number of row scanning lines is doubled, and the number of data lines is halved, so that the number of source driving chips can be reduced, thereby reducing the cost.

[0038] Hardware Super Resolution (HSR) is a scheme for realizing high refresh rate. The HSR technology usually advances the charging start time of one row of sub-pixels by 1T to realize 2T charging, and ensures that the charging time of the odd rows (or even rows) is compensated by the pre-charge function of the adjacent odd rows (or even rows). Thus, the charging time can be doubled with little loss of resolution, which is conducive to doubling the frequency.

[0039] Figure 1A The timing diagram of a conventional pixel driving mode is shown; Figure 1B The timing diagram of an HSR pixel driving mode is shown.

[0040] As shown in Figure 1A In the conventional pixel driving mode, a plurality of gate lines G1-G12 are turned on in turn, and during the turning on of each gate line, all columns of data lines write data signals to each row of sub-pixels in turn. For example, during the turning on of the gate line G1, the data lines write data signal 1 to one row of sub-pixels controlled by the gate line G1; after the gate line G1 is turned off, the data lines write data signal 2 to another row of sub-pixels controlled by the gate line G2, and so on.

[0041] As shown in Figure 1BAs shown, when the HSR mode is enabled, the timing of the gate driving circuit is not changed, and the even rows are charged, and the data of the odd rows is the integration of the data of the adjacent two rows, so that the charging time of the data of the even rows is doubled. For example, during the period when the gate lines G1 and G2 are both in the enabled state, the data line writes a data signal 1 to the one row of sub-pixels controlled by the gate line G1, and writes a data signal 1 to the other row of sub-pixels controlled by the gate line G2; after the gate line G2 is disabled, the data line writes a data signal 2 to the two rows of sub-pixels controlled by the gate lines G3 and G4, respectively, and so on. The HSR pixel driving mode shown in the example can ensure that the even rows are charged in the same way as in the conventional mode, so that the frequency is doubled.

[0042] At present, HSR has been widely applied to products with a single-gate pixel driving structure, but it is difficult to implement in a double-gate pixel driving structure.

[0043] Embodiments of the present disclosure provide an array substrate capable of implementing super-resolution frequency doubling technology in a double-gate. The array substrate includes a pixel array formed by a plurality of rows and a plurality of columns of sub-pixels, a plurality of gate lines and a plurality of data lines intersecting to define the plurality of rows and the plurality of columns of sub-pixels, each row of sub-pixels including two adjacent sub-pixels connected to two adjacent gate lines among the plurality of gate lines, at least one data line among the plurality of data lines connected to two adjacent columns of sub-pixels among the plurality of columns of sub-pixels, the plurality of gate lines used to enable the plurality of rows of sub-pixels, and the plurality of data lines used to charge the plurality of columns of enabled sub-pixels, the plurality of rows of sub-pixels including a plurality of groups of sub-pixels, each group of sub-pixels including a part of rows of sub-pixels among the plurality of rows of sub-pixels, and charging times of the part of rows of sub-pixels overlapping, the part of rows of sub-pixels including a first part of rows of sub-pixels and a second part of rows of sub-pixels, the charging time of the second part of rows of sub-pixels being longer than the charging time of the first part of rows of sub-pixels, the same data signal being written to the first part of rows of sub-pixels and the second part of rows of sub-pixels in a first time period in which the charging times overlap, and the data signal written to the second part of rows of sub-pixels being at least partially the same as the data signal written in the first time period in a second time period in which the charging times do not overlap. In this embodiment, the super-resolution frequency doubling technology is implemented in a double-gate. In other embodiments of the present disclosure, not only the super-resolution frequency doubling technology is implemented in a double-gate, but also the technical problem of color crosstalk caused by the application of the super-resolution frequency doubling technology in a double-gate is alleviated. Since in a double-gate pixel driving structure, each data line controls two columns of sub-pixels, directly using HSR may cause color crosstalk. For example, a data line controls one column of sub-pixels on the left side of the data line and one column of sub-pixels on the right side of the data line, a first sub-pixel (for example, a red sub-pixel) in a first row of sub-pixels on the left side of the data line and a second sub-pixel (for example, a green sub-pixel) in the first row of sub-pixels on the right side of the data line are connected to a first gate line and a second gate line, respectively, and when the first gate line and the second gate line are in the enabled state at the same time, the data line writes data signals to the first sub-pixel and the second sub-pixel, causing color crosstalk in which green is displayed at the same time when red is displayed.

[0044] Figure 2A A schematic diagram of an array substrate is shown according to an embodiment of the present disclosure; Figure 2B A timing diagram of the array substrate is shown according to an embodiment of the present disclosure. Figure 2A A timing diagram of the array substrate is shown according to an embodiment of the present disclosure.

[0045] As shown in Figure 2A The array substrate 100 includes a pixel array formed by a plurality of rows and a plurality of columns of sub-pixels. A plurality of gate lines and a plurality of data lines cross to define the plurality of rows and the plurality of columns of sub-pixels. The plurality of gate lines may, for example, include gate lines G1-G8. The plurality of data lines may, for example, include data lines D1-D7.

[0046] It should be noted that although Figure 2A only 8 gate lines and 7 data lines are shown in the example, this is merely an example. The array substrate can include fewer or more gate lines and data lines than the example. Figure 2A The array substrate can include fewer or more sub-pixels than the example. Figure 2A

[0047] Each sub-pixel requires polarity inversion driving. In the example, the pixel polarity inversion driving mode is a column inversion driving mode, i.e., the polarity of adjacent data lines is opposite. For example, the data signal on the first data line is positive polarity, the data signal on the second data line is negative polarity, the data signal on the third data line is positive polarity, and so on. Figure 2A

[0048] As shown in Figure 2A Each row of sub-pixels in the array substrate 100 is connected to two adjacent gate lines of the plurality of gate lines.

[0049] For example, the i-th row of sub-pixels is connected to the N-th gate line and the N+1-th gate line (N is a positive integer), the i+1-th row of sub-pixels is connected to the N+2-th gate line and the N+3-th gate line, and so on. Each row of sub-pixels is connected to two gate scan signal lines. Taking the first row of sub-pixels as an example, for example, from left to right, there are a first sub-pixel (located in the first column), a second sub-pixel (located in the second column), a third sub-pixel (located in the third column), a fourth sub-pixel (located in the fourth column), and so on. The gate line G1 is connected to the first sub-pixel, the third sub-pixel, the fourth sub-pixel, the seventh sub-pixel, the ninth sub-pixel, and the tenth sub-pixel in the row. The gate line G2 is connected to the second sub-pixel, the fifth sub-pixel, the sixth sub-pixel, the eighth sub-pixel, the eleventh sub-pixel, and the twelfth sub-pixel in the row. The connection relationship of other rows of sub-pixels and other gate lines is the same.

[0050] ​​In other embodiments of this disclosure, for example, two gate lines connected to sub-pixels in the same row include gate lines connected to one of the even-numbered and odd-numbered sub-pixels in the corresponding row, and a gate line connected to the other. Embodiments of this disclosure do not limit the connection relationship between each row of sub-pixels and its two adjacent gate lines.

[0051] like Figure 2A As shown, at least one of the multiple data lines in the array substrate 100 is connected to two adjacent columns of sub-pixels in the multiple columns of sub-pixels.

[0052] For example, the j-th data line is connected to the M-th and M+1-th sub-pixels (M is a positive integer), the j+1-th data line is connected to the M+2-th and M+3-th sub-pixels, and so on. For example, as shown in Figure 2, the second data line D2 is connected to the second and third sub-pixels; the third data line D3 is connected to the fourth and fifth sub-pixels, and the connection relationships of other data lines with other columns of sub-pixels are similar. In this embodiment, the array substrate 100 may include data lines connected to two adjacent columns of sub-pixels in multiple columns, as well as data lines connected to only one column of sub-pixels. For example, the first data line is connected to the first column of sub-pixels, and the last data line is connected to the last column of sub-pixels.

[0053] Multiple gate lines G1 to G8 in the array substrate 100 are used to enable multiple rows of sub-pixels, and multiple data lines D1 to D7 are used to charge multiple columns of enabled sub-pixels, that is, to write data signals to multiple columns of enabled sub-pixels.

[0054] like Figure 2A As shown, in the embodiments of this disclosure, Rx represents the red sub-pixel of the x-th row, where x is an integer greater than or equal to 1, for example, x = 1, and R1 represents the red sub-pixel of the first row. Similarly, Gx represents the green sub-pixel of the x-th row, and Bx represents the blue sub-pixel of the x-th row.

[0055] In the array substrate 100, the multi-row sub-pixels include multiple groups of sub-pixels, each group of sub-pixels includes a portion of the row sub-pixels in the multi-row sub-pixels, each row of sub-pixels in the portion of the row sub-pixels includes a sub-pixel connected to the same gate line, and the charging times of the portion of the row sub-pixels overlap.

[0056] In embodiments of this disclosure, multiple sub-pixels with overlapping charging times are grouped as a set of sub-pixels. Overlapping charging times refer to a situation where, within a certain time period, the data line simultaneously writes data signals to two rows of sub-pixels. Figure 2B Examples illustrating overlapping charging times, such as Figure 2BAs shown, during time period t1, the data lines simultaneously write data signals to the sub-pixels in the first row controlled by gate line G1 and the sub-pixels in the third row controlled by gate line G3. This time period t1 is the overlapping charging time period (i.e., the high levels of G1 and G3 overlap). During time period t2, gate line G1 is turned off, and the data lines no longer write data signals to the sub-pixels in the first row controlled by gate line G1. The data lines still write data signals to the sub-pixels in the third row controlled by gate line G3. This time period t2 is the non-overlapping charging time period (i.e., the high levels of G1 and G3 do not overlap, and the high level corresponding to G3 charges the data signal). Time period t1 is an example of the first time period. Time period t2 is an example of the second time period.

[0057] For example, such as Figure 2B As shown, the charging times of multiple sub-pixels connected to gate line G1 overlap with those of multiple sub-pixels connected to gate line G3. Therefore, these multiple sub-pixels connected to gate line G1 and gate line G3 are considered as a group of sub-pixels. In this example, gate line G1 and gate line G3 are grouped together, and the multiple sub-pixels connected to these two gate lines are each grouped as a sub-pixel. In this example, some rows of sub-pixels are selected from the first row of sub-pixels connected to gate line G1 (the first, third, fourth, seventh, ninth, and tenth sub-pixels in the first row) and the third row of sub-pixels connected to gate line G3 (the first, third, fourth, seventh, ninth, and tenth sub-pixels in the third row).

[0058] A portion of row sub-pixels includes a first portion of row sub-pixels and a second portion of row sub-pixels, with the charging time of the second portion of row sub-pixels being longer than that of the first portion of row sub-pixels. For example, in an example where gate lines G1 and G3 are grouped together, and multiple sub-pixels connected to these two gate lines are grouped together, the first, third, fourth, seventh, ninth, and tenth sub-pixels in the first row are the first portion of row sub-pixels, and the first, third, fourth, seventh, ninth, and tenth sub-pixels in the third row are the second portion of row sub-pixels.

[0059] In some embodiments of this disclosure, each group of subpixels includes two rows of subpixels, the first part of the row of subpixels being at least some of the subpixels in one of the two rows of subpixels, and the second part of the row of subpixels being at least some of the subpixels in the other of the two rows of subpixels.

[0060] In some other embodiments of this disclosure, each group of subpixels may include more than two rows of subpixels or one row of subpixels. This disclosure does not limit the number of subpixels in each group of subpixels.

[0061] In the array substrate 100, during a first time period in which the charging times overlap, the first part of the row sub-pixels and the second part of the row sub-pixels write the same data signal. During a second time period in which the charging times do not overlap, the data signal written by the second part of the row sub-pixels is at least partially the same as the data signal written during the first time period.

[0062] like Figure 2B As shown, during the overlapping charging time period t1, multiple sub-pixels connected to gate line G1 in the first row of sub-pixels (hereinafter referred to as "G1 sub-pixels") and multiple sub-pixels connected to gate line G3 in the third row of sub-pixels (hereinafter referred to as "G3 sub-pixels") write data signal DA; during the non-overlapping charging time period t2, the data signal written by G3 sub-pixels is also data signal DA.

[0063] In other embodiments of this disclosure, during the non-overlapping charging time period t2, the data signal written by the G3 sub-pixel may include data signal 1 and other data signals. That is, during the non-overlapping charging time period t2, the data signal written by the second portion of the row sub-pixels may be exactly the same as the data signal written during the first time period, or it may be the same for part of the time and different for another part. Figure 2B The diagram illustrates the case where the data signal written to the second row of sub-pixels can be exactly the same as the data signal written in the first time period.

[0064] In the above example, the first row of sub-pixels and the third row of sub-pixels are used as a pixel group for illustration. The charging time and charging method of other pixel groups in the array substrate 100 are similar to those of this pixel group, and will not be described again.

[0065] In other embodiments of this disclosure, each pair of adjacent gate lines corresponding to two rows of sub-pixels can be considered as a pixel group, for example, the first row of sub-pixels and the second row of sub-pixels can be considered as a pixel group. Except for overlapping charging times, this disclosure does not limit the rules for dividing pixel groups.

[0066] In some embodiments of the present disclosure, the charging time of the second part of rows of sub-pixels is twice the charging time of the first part of rows of sub-pixels. For example, the charging time of the first part of rows of sub-pixels is 1 row of sub-pixels, the charging time of the second part of rows of sub-pixels is 2 rows of sub-pixels, and the first part of rows of sub-pixels and the second part of rows of sub-pixels start charging at the same time. For example, the charging time of the first row of sub-pixels is 1 row of sub-pixels 1H, and the charging time of the third row of sub-pixels is 2 rows of sub-pixels 2H, for example, refer to Figure 2B , the charging time corresponding to t1 is 1H, and the charging time corresponding to t2 is 1H, so for G3, the time of charging the B2 data signal is 2H, and for high-resolution products, the charging rate of the display panel can be improved.

[0067] In some embodiments of the present disclosure, in the part of rows of sub-pixels, the same data line is connected to sub-pixels of the same color. For example, the same data line in the part of rows of sub-pixels is connected to red sub-pixels or green sub-pixels or blue sub-pixels, which can alleviate the above-mentioned color mixing problem and at the same time realize the function of HSR.

[0068] It should be noted that in the embodiments of the present disclosure, the same color or the same color means that the color corresponding to the color resistance is the same. Here, the color resistance can be arranged on the opposite substrate or on the array substrate (COA technology, the color film layer is arranged on the side of the array substrate).

[0069] For example, in the timing diagram shown in Figure 2B , two gate lines are taken as a gate line group, and two rows of sub-pixels connected to the two gate lines in the gate line group form a sub-pixel group, and the sub-pixels connected to the same data line in the sub-pixel group correspond to the same color to alleviate the color mixing problem.

[0070] For example, as shown in Figure 2A and 2B , the gate line G1 and the gate line G3 form a gate line group, and the G1 sub-pixel and the G3 sub-pixel form a sub-pixel group, and the two sub-pixels connected to the same data line in the sub-pixel group correspond to the same color. For example, in the sub-pixel group, the sub-pixel 201 and the sub-pixel 203 connected to the data line D1 are both red sub-pixels; the sub-pixel 202 and the sub-pixel 204 connected to the data line D2 are both blue sub-pixels, and other data lines are similar to the data line D1 and the data line D2.

[0071] In the examples of Figure 2A and 2B , a plurality of groups of gate lines are sequentially turned on, and for each group of gate lines, the gate line connected to the first part of rows of sub-pixels is turned on earlier than the gate line connected to the second part of rows of sub-pixels. For example, in Figure 2BIn the example shown in FIG. 1, every two adjacent odd-numbered row gate lines are taken as an odd-numbered gate line group, and every two adjacent even-numbered row gate lines are taken as an even-numbered gate line group. The odd-numbered gate line groups and the even-numbered gate line groups are alternated. The first gate line group (gate line G1 and gate line G3), the second gate line group (gate line G2 and gate line G4), and the sixth gate line group (gate line G10 and gate line G12) are sequentially turned on. For each gate line group, for example, gate line G1 and gate line G3, the gate line G1 to which the second part row sub-pixels (i.e., G1 sub-pixels) are connected is turned on earlier than the gate line G3 to which the second part row sub-pixels (i.e., G3 sub-pixels) are connected.

[0072] Figure 2A The array substrate shown in FIG. 1 adopts a double-gate pixel driving structure. Figure 2B The timing shown in FIG. 1 can alleviate the color streak problem of the double-gate pixel driving structure when the HSR mode is applied.

[0073] The main reason for the color streak of the double-gate pixel driving structure when the HSR mode is applied is that the colors corresponding to the sub-pixels controlled by the adjacent two rows of gate lines on the same data line are different. Therefore, the colors corresponding to the sub-pixels controlled by the adjacent two rows of gate lines on the same data line can be made the same by changing the scanning order of the gate lines, that is, the HSR display mode can be realized. As shown in FIG. 1, in the array substrate 100, for example, the same column is a sub-pixel of the same color, for example, the first column is a red sub-pixel, the second column is a green sub-pixel, and the third column is a blue sub-pixel, and then the order of the red sub-pixel, the green sub-pixel, and the blue sub-pixel is cycled. The normal gate line turn-on order is G1→G2→G3→G4→G5→G6→G7→G8, for example, for the data line D2, the corresponding sub-pixel turn-on order is B1→G1→B2→G2→B3→G3→B4→G4……, at this time, since the colors corresponding to the adjacent two turned-on sub-pixels are different, directly turning on the HSR display mode will cause the color streak problem. Figure 2A Figure 2B As shown in FIG. 1, in the embodiment of the present disclosure, the gate line turn-on order is G1→G3→G2→G4→G5→G7→G6→G8……, for example, for the data line D2, the corresponding sub-pixel turn-on order is B1 (blue sub-pixel)→B2 (blue sub-pixel)→G1 (green sub-pixel)→G2 (green sub-pixel)→B3 (blue sub-pixel)→B4 (blue sub-pixel)→G3 (green sub-pixel)→G4 (green sub-pixel)……, at this time, the colors corresponding to the adjacent two turned-on sub-pixels are the same, and only need to ensure that B2, G2, B4, G4…… are charged to turn on the HSR mode, and the color streak problem will not occur, thereby realizing the HSR display mode of the double-gate pixel driving structure.

[0074] ​In some embodiments of the present disclosure, the same data line is connected to multiple groups of sub-pixels, and the multiple sub-pixels of the same color connected on the same data line are connected to the gate lines of the odd rows or the gate lines of the even rows. It should be noted that the odd and even rows are not absolute, and can refer to two adjacent rows of gate lines, one of which is an odd row and the other of which is an even row.

[0075] For example, the multiple green sub-pixels connected on the same data line D2 are connected to the gate lines of the even rows, and the multiple blue sub-pixels connected on the same data line D2 are connected to the gate lines of the odd rows.

[0076] In some embodiments of the present disclosure, the multiple sub-pixels corresponding to red are connected to the gate lines of the odd rows, the multiple sub-pixels corresponding to green are connected to the gate lines of the even rows, and the multiple sub-pixels corresponding to blue connected on the same data line are connected to the gate lines of the multiple odd rows or the gate lines of the multiple even rows. For example, as shown in FIG. 2, all the red sub-pixels are connected to the gate lines of the odd rows and controlled by the gate lines of the odd rows, all the green sub-pixels are connected to the gate lines of the even rows and controlled by the gate lines of the even rows, and the blue sub-pixels on the same data line are connected to the gate lines of the odd rows or the gate lines of the even rows and controlled by the gate lines of the odd rows or the gate lines of the even rows. Figure 2A For example, as shown in FIG. 2, all the red sub-pixels are connected to the gate lines of the odd rows and controlled by the gate lines of the odd rows, all the green sub-pixels are connected to the gate lines of the even rows and controlled by the gate lines of the even rows, and the blue sub-pixels on the same data line are connected to the gate lines of the odd rows or the gate lines of the even rows and controlled by the gate lines of the odd rows or the gate lines of the even rows.

[0077] Figure 3A FIG. 3 shows a schematic diagram of another array substrate provided by some embodiments of the present disclosure.

[0078] For example, as shown in FIG. 3, the multiple sub-pixels corresponding to green are connected to the gate lines of the odd rows and controlled by the gate lines of the odd rows, the multiple sub-pixels corresponding to blue are connected to the gate lines of the even rows and controlled by the gate lines of the even rows, and the multiple sub-pixels corresponding to red connected on the same data line are connected to the gate lines of the multiple odd rows or the gate lines of the multiple even rows and controlled by the gate lines of the multiple odd rows or the gate lines of the multiple even rows. Figure 3A For example, as shown in FIG. 3, the multiple sub-pixels corresponding to green are connected to the gate lines of the odd rows and controlled by the gate lines of the odd rows, the multiple sub-pixels corresponding to blue are connected to the gate lines of the even rows and controlled by the gate lines of the even rows, and the multiple sub-pixels corresponding to red connected on the same data line are connected to the gate lines of the multiple odd rows or the gate lines of the multiple even rows and controlled by the gate lines of the multiple odd rows or the gate lines of the multiple even rows.

[0079] Figure 3B FIG. 4 shows a schematic diagram of another array substrate provided by some embodiments of the present disclosure.

[0080] For example, as shown in FIG. 4, the multiple sub-pixels corresponding to green are connected to the gate lines of the odd rows and controlled by the gate lines of the odd rows, the multiple sub-pixels corresponding to blue are connected to the gate lines of the even rows and controlled by the gate lines of the even rows, and the multiple sub-pixels corresponding to red connected on the same data line are connected to the gate lines of the multiple odd rows or the gate lines of the multiple even rows and controlled by the gate lines of the multiple odd rows or the gate lines of the multiple even rows. Figure 3BAs shown in the embodiment, the sub-pixels corresponding to the same color in the same column are connected to the same data line, and the sub-pixels corresponding to red are connected to the odd-numbered gate lines or the even-numbered gate lines. For example, the fourth column of sub-pixels are red sub-pixels, and the red sub-pixels in the fourth column are connected to the even-numbered gate lines; the first column of sub-pixels are red sub-pixels, and the red sub-pixels in the first column are connected to the odd-numbered gate lines. For example, the second column of sub-pixels are green sub-pixels, and the green sub-pixels in the second column are connected to the odd-numbered gate lines; the fifth column of sub-pixels are green sub-pixels, and the green sub-pixels in the fifth column are connected to the even-numbered gate lines. For example, the third column of sub-pixels are blue sub-pixels, and the blue sub-pixels in the third column are connected to the odd-numbered gate lines; the sixth column of sub-pixels are blue sub-pixels, and the blue sub-pixels in the sixth column are connected to the even-numbered gate lines.

[0081] Figure 3C A schematic diagram of another array substrate provided by some embodiments of the present disclosure is shown.

[0082] As Figure 3C shown in the embodiment, the sub-pixels corresponding to the same color in the same column are connected to the same data line, and the sub-pixels corresponding to red are connected to the odd-numbered gate lines or the even-numbered gate lines. For example, the fourth column of sub-pixels are red sub-pixels, and the red sub-pixels in the fourth column are connected to the even-numbered gate lines; the first column of sub-pixels are red sub-pixels, and the red sub-pixels in the first column are connected to the odd-numbered gate lines. For example, the second column of sub-pixels are green sub-pixels, and the green sub-pixels in the second column are connected to the odd-numbered gate lines; the fifth column of sub-pixels are green sub-pixels, and the green sub-pixels in the fifth column are connected to the even-numbered gate lines. For example, the third column of sub-pixels are blue sub-pixels, and the blue sub-pixels in the third column are connected to the odd-numbered gate lines; the sixth column of sub-pixels are blue sub-pixels, and the blue sub-pixels in the sixth column are connected to the even-numbered gate lines.

[0083] Figures 3A-3C The array substrates shown can be driven by the timing diagram shown. Figure 2B

[0084] Figure 4 A timing diagram of another driving mode applied to the array substrate shown in some embodiments of the present disclosure is shown. Figure 2A and Figures 3A-3C

[0085] ​​In this example, an image frame is divided into a first display period and a second display period. Two adjacent odd-numbered rows of grid lines are grouped together, and two adjacent even-numbered rows of grid lines are grouped together. The two rows of sub-pixels connected by each group of grid lines are grouped together as sub-pixels. For odd-numbered rows of grid lines, multiple groups of odd-numbered rows of grid lines are turned on sequentially in the first display period; for even-numbered rows of grid lines, multiple groups of even-numbered rows of grid lines are turned on sequentially in the second display period. In each group of grid lines, the grid lines connected to the sub-pixels of the first part of the rows are turned on earlier than the grid lines connected to the sub-pixels of the second part of the rows.

[0086] In some embodiments of this disclosure, the first display period and the second display period have the same duration. For example, an image frame is divided into a first half-frame and a second half-frame, with the first half-frame's display period being the first display period and the second half-frame's display period being the second display period. Optionally, a display frame may include the first display period, the second display period, and a blanking period; this is not limited here. In other embodiments of this disclosure, the first display period and the second display period have different durations.

[0087] For example, such as Figure 2A and Figures 3A-3C As shown, the odd-numbered rows of grid lines include grid lines G1, G3, G5, G7, G9, and G11. Each pair of adjacent odd-numbered rows of grid lines forms a group; for example, grid lines G1 and G3 form one group, G5 and G7 form another, and G9 and G11 form yet another. Multiple groups of odd-numbered rows of grid lines are activated sequentially in the first half of the frame. Similarly, the even-numbered rows of grid lines include grid lines G2, G4, G6, G8, G10, and G12. Each pair of adjacent even-numbered rows of grid lines forms a group; for example, grid lines G2 and G4 form one group, G6 and G8 form another, and G10 and G12 form yet another. Multiple groups of even-numbered rows of grid lines are activated sequentially in the second half of the frame.

[0088] like Figure 4As shown, in the display period of the former half frame, the gate lines G1, G3, G5, G7, G9 and G11 are sequentially turned on, and the gate lines G2, G4, G6, G8, G10 and G12 remain in the closed state. In the display period of the latter half frame, the gate lines G1, G3, G5, G7, G9 and G11 remain in the closed state, and the gate lines G2, G4, G6, G8, G10 and G12 are sequentially turned on. In the former half frame, the STV1A initial trigger signal is turned on, and in the latter half frame, the STV1B initial trigger signal is turned on. The initial trigger signal is used for the input module of the first row or the first few rows of the gate driving circuit, and is used for turning on the first row or the first few rows of the gate driving circuit. For example, STV1A can turn on the G1 row, or simultaneously turn on the G1 and G3 rows; for example, STV1B can turn on the G2 row, or simultaneously turn on the G21 and G4 rows, and the like, which is not limited herein.

[0089] For each group of gate lines, the first part of the row sub-pixels are the sub-pixels with the previous serial number, and the second part of the row sub-pixels are the sub-pixels with the subsequent serial number. For example, in the gate line group composed of the gate line G5 and the gate line G7, the gate line G5 is the first part of the row sub-pixels, and the gate line G7 is the second part of the row sub-pixels; in the gate line group composed of the gate line G2 and the gate line G4, the gate line G2 is the first part of the row sub-pixels, and the gate line G4 is the second part of the row sub-pixels, and the remaining gate line groups are similar.

[0090] In the example of Figure 4 , the odd rows are turned on in the former half frame, and the even rows are turned on in the latter half frame. In another embodiment of the present disclosure, the even rows can be turned on in the former half frame, and the odd rows can be turned on in the latter half frame.

[0091] For the Figure 2A and Figures 3A-3C pixel architecture, when only the odd rows or the even rows of the gate lines are turned on, the sub-pixels connected on the same data line correspond to the same color, and when the HSR mode is turned on for the odd rows and the even rows of the gate lines respectively, there is no color mixing problem. Therefore, for example, a frame of time is divided into a former half frame and a latter half frame, the odd rows of the gate lines are turned on in the former half frame, and the even rows of the gate lines are turned on in the latter half frame, and then the HSR display mode is turned on for the odd rows and the even rows respectively (the timing is shown in Figure 4 ), so that the double-gate pixel driving structure can apply the HSR display mode.

[0092] In the example of Figure 2A , the gate lines connected to the odd rows and the gate lines connected to the even rows are controlled respectively, so that the odd rows can be driven in the HSR mode in the former half frame, and the even rows can be driven in the HSR mode in the latter half frame. Since the sub-pixels of the same color connected on each data line are controlled by the odd rows of the gate lines or the even rows of the gate lines, the color mixing problem can be alleviated. Reference is made to Figures 3A-3C, the G1 and G3 high level overlap time, the charged data signal 1, the G1 and G3 high level non-overlapping time, the charged data signal is also 1, that is, the same data signal is charged, optionally, the G1 and G3 high level overlap time is 1H (one row charging time), the G1 and G3 high level non-overlapping time, the charging time is also 1H, that is, 3 charged data signal 1 can charge 2H time in total, improve the display charging time, improve the problem of insufficient charging rate. Other odd rows or even rows are similar and will not be repeated here.

[0093] It should be noted that, Figure 2A The array substrate shown is similar to the array substrate shown in the embodiment of the present disclosure in other structures except that the way of connecting the gate lines of the red sub-pixels, the blue sub-pixels and the green sub-pixels is different. Figures 3A-3C The array substrate shown is similar to the array substrate shown in the embodiment of the present disclosure in other structures except that the way of connecting the gate lines of the red sub-pixels, the blue sub-pixels and the green sub-pixels is different.

[0094] Figure 2B A schematic diagram of another array substrate 500 provided by at least one embodiment of the present disclosure is shown. Figure 5A A schematic diagram of another array substrate 500 provided by at least one embodiment of the present disclosure is shown. Figure 5A A timing diagram of the driving mode of the array substrate 500 shown.

[0095] As shown in the embodiment of the present disclosure, Figure 2B The array substrate 500 includes a plurality of gate lines G1-G8. The plurality of gate lines G1-G8 includes a plurality of first gate line groups, each first gate line group includes two adjacent gate lines, and each first gate line is connected to two rows of sub-pixels to form a first sub-pixel group.

[0096] In the example shown, Figure 6A In the same row, the sub-pixels in the odd columns are connected to the same gate line, and the sub-pixels in the even columns are connected to the same gate line. For example, in the first row, the sub-pixels in the odd columns are connected to the gate line G1, and the sub-pixels in the even columns are connected to the gate line G2; in the second row, the sub-pixels in the odd columns are connected to the gate line G4, and the sub-pixels in the even columns are connected to the gate line G3. For example, the gate line G2 and the gate line G3 form a first gate line group, and a plurality of sub-pixels in the first row connected to the gate line G2 (a plurality of sub-pixels in the even columns) and a plurality of sub-pixels in the second row connected to the gate line G3 (a plurality of sub-pixels in the even columns) form a first sub-pixel group; the gate line G4 and the gate line G5 form a first gate line group, and a plurality of sub-pixels in the second row connected to the gate line G4 (a plurality of sub-pixels in the odd columns) and a plurality of sub-pixels in the third row connected to the gate line G5 (a plurality of sub-pixels in the odd columns) form a first sub-pixel group, and other first gate line groups and first sub-pixel groups are similar to the above.

[0097] It should be noted that, in the embodiments of the present disclosure, the odd columns and the even columns are relative, one of the two adjacent columns is an odd column and the other is an even column, and the odd columns and the even columns in the pixel array are alternating.

[0098] In Figure 6A the example, the colors corresponding to the two sub-pixels connected with the same data line in each first sub-pixel group are the same. For example, for the first gate line group formed by the gate line G2 and the gate line G3, the sub-pixel 501 in the second column in the first row connected with the gate line G2 and the sub-pixel 502 in the second column in the second row connected with the gate line G3 are connected with the same data line, and the sub-pixel 501 and the sub-pixel 502 are both green sub-pixels. That is, in the embodiment of the present disclosure, for example, the DNth data line connects the Pn and P(n+1) columns of sub-pixels, and the gate line Gi, the gate line Gi+1 (here i is greater than or equal to 2), the gate line Gi+3 and the gate line Gi+4 connect the DNth data line. The gate line Gi and the gate line Gi+1 correspond to the P(n+1) column of sub-pixels with the same color, the gate line Gi+3 and the gate line Gi+4 correspond to the Pn column of sub-pixels with the same color, and the like; or, the gate line Gi and the gate line Gi+1 correspond to the Pn column of sub-pixels with the same color, the gate line Gi+3 and the gate line Gi+4 correspond to the P(n+1) column of sub-pixels with the same color, and the like.

[0099] In Figure 6B the example, the plurality of groups of sub-pixels can further include a second group of sub-pixels, the second group of sub-pixels including a plurality of sub-pixels connected with a first gate line of the plurality of gate lines, and the plurality of first groups of sub-pixels including a plurality of rows of sub-pixels other than the sub-pixels included in the second group of sub-pixels. For example, as shown in Figure 2A , the first gate line of the plurality of gate lines is the gate line G1, and the plurality of sub-pixels connected with the gate line G1 (the plurality of sub-pixels located in the odd columns) is the second group of sub-pixels. In addition to the plurality of sub-pixels connected with the gate line G1, the plurality of rows of sub-pixels are divided into the plurality of first groups of sub-pixels.

[0100] As shown in Figure 2A , the HSR display mode can be applied from the gate line G2, that is, the HSR display mode is applied after the gate line G1 is turned on and the data signal 1 is written into the second group of sub-pixels. In the HSR display mode, the plurality of gate lines are turned on in sequence, and the gate line connected with the first part of rows of sub-pixels in each group of sub-pixels is turned on earlier than the gate line connected with the second part of rows of sub-pixels. For example, the gate line G2 is turned on earlier than the gate line G3, the gate line G4 is turned on earlier than the gate line G5, and the like. For example, referring to Figure 6BWhen G1 is opened, a data signal is charged to the first row of pixels, data signal 1, and the time of charging the data signal can be 2H, i.e. 2H pixel charging time (it should be noted that the data signal written to the first row of pixels can also be 1H, which is not limited herein), and the mode of opening HSR from the second row of gate lines and the subsequent gate lines, i.e. G2 is opened to charge data signal 2, the time of charging data signal 2 is 1H, and after G3 is opened, the part of G3 that does not overlap with G2 in time charges data signal 2, and the time is also 1H, i.e. G3 charges data signal 2H in total, and other G4 and G5, G6 and G7 are charged in the same way as G2 and G3, and details are not repeated.

[0101] As shown in ​ , for each group of sub-pixels, the data line simultaneously starts to write the same data signal to each group of sub-pixels, for example, the same data signal 2 is written to the pixel group corresponding to the gate line G2 and the gate line G3. For example, the charging time of the plurality of sub-pixels connected by the gate line G2 is 1H, and the charging time of the plurality of sub-pixels connected by the gate line G3 is 2H, and there is an overlap of 1H in the charging time.

[0102] In the examples of ​ and ​ , the sequence of opening the gate lines is G1→G2→G3→G4→G5→G6→G7→8……, for example, for the data line D2, the opening sequence of the plurality of sub-pixels is B1→R1→R2→B2→B3→R3→R4, at this time, the colors corresponding to the two sub-pixels that are opened adjacently are the same, and only the charging of the R2, B3, and R4 sub-pixels needs to be opened in the HSR mode to avoid the problem of color mixing, thereby realizing the application of the HSR display mode in the double-gate pixel driving structure.

[0103] Another aspect of the present disclosure provides a driving method. The driving method is applied to the array substrate provided in any of the embodiments of the present disclosure. The driving method includes opening a plurality of gate lines connected to each group of sub-pixels, and charging each group of sub-pixels by a plurality of data lines during the opening of the plurality of gate lines of each group of sub-pixels. In this embodiment, the double-gate super-division frequency doubling technology is realized. In other embodiments of the present disclosure, not only the double-gate super-division frequency doubling technology can be realized, but also the technical problem of color mixing caused by the application of the super-division frequency doubling technology in the double-gate can be alleviated.

[0104] Some embodiments of the present disclosure provide a driving method applied to, for example, the above ​ and ​ . As shown in ​ and ​ , a plurality of groups of sub-pixels are connected to the same data line, and the plurality of sub-pixels with the same light-emitting color connected to the same data line are connected to the odd-numbered rows of gate lines or the even-numbered rows of gate lines.

[0105] In this example, one image frame is divided into a first display period and a second display period, two adjacent odd-numbered rows of gate lines are taken as a group, two adjacent even-numbered rows of gate lines are taken as a group, and two rows of sub-pixels connected by each group of gate lines are taken as a group of sub-pixels. In the first display period, the odd-numbered rows of gate lines are sequentially turned on, and in the second display period, the even-numbered rows of gate lines are sequentially turned on. In each group of gate lines, the gate line connected to the first part of the rows of sub-pixels is turned on earlier than the gate line connected to the second part of the rows of sub-pixels.

[0106] In some embodiments of the present disclosure, the time lengths of the first display period and the second display period are the same. For example, one image frame is divided into a first half frame and a second half frame on average, the display period of the first half frame is the first display period, and the display period of the second half frame is the second display period. In other embodiments of the present disclosure, the time lengths of the first display period and the second display period are different.

[0107] The driving method is driven, for example, according to the timing diagram shown in FIG. 8. For example, in the display period of the first half frame, the gate lines G1, G3, G5, G7, G9, and G11 are sequentially turned on, and the gate lines G2, G4, G6, G8, G10, and G12 remain in a closed state. In the display period of the second half frame, the gate lines G1, G3, G5, G7, G9, and G11 remain in a closed state, and the gate lines G2, G4, G6, G8, G10, and G12 are sequentially turned on. ​

[0108] For each group of gate lines, the first part of the rows of sub-pixels are the sub-pixels with earlier serial numbers, and the second part of the rows of sub-pixels are the sub-pixels with later serial numbers. For example, in the gate line group composed of the gate lines G5 and G7, the gate line G5 is the first part of the rows of sub-pixels, and the gate line G7 is the second part of the rows of sub-pixels; in the gate line group composed of the gate lines G2 and G4, the gate line G2 is the first part of the rows of sub-pixels, and the gate line G4 is the second part of the rows of sub-pixels, and the remaining gate line groups are similar.

[0109] In the example shown in FIG. 8, the odd-numbered rows are turned on in the first half frame, and the even-numbered rows are turned on in the second half frame. In other embodiments of the present disclosure, the even-numbered rows can be turned on in the first half frame, and the odd-numbered rows can be turned on in the second half frame. ​ For the pixel architecture shown in FIG. 1, only the odd-numbered rows or the even-numbered rows of gate lines are turned on, the sub-pixels connected on the same data line correspond to the same color, and there is no cross-color problem when the HSR mode is turned on for the odd-numbered rows of gate lines and the even-numbered rows of gate lines respectively. Therefore, for example, one frame of time is divided into a first half frame and a second half frame, the odd-numbered rows of gate lines are turned on in the first half frame, the even-numbered rows of gate lines are turned on in the second half frame, and then the HSR display mode is turned on for the odd-numbered rows and the even-numbered rows respectively (the timing diagram is shown in FIG. 9).

[0110] ​ ​ For the pixel architecture shown in FIG. 1, only the odd-numbered rows or the even-numbered rows of gate lines are turned on, the sub-pixels connected on the same data line correspond to the same color, and there is no cross-color problem when the HSR mode is turned on for the odd-numbered rows of gate lines and the even-numbered rows of gate lines respectively. Therefore, for example, one frame of time is divided into a first half frame and a second half frame, the odd-numbered rows of gate lines are turned on in the first half frame, the even-numbered rows of gate lines are turned on in the second half frame, and then the HSR display mode is turned on for the odd-numbered rows and the even-numbered rows respectively (the timing diagram is shown in FIG. 9).​​​​ ), i.e. to realize the double-gate pixel driving structure to apply the HSR display mode.

[0111] In some embodiments of the present disclosure, the charging time of the first part of the row sub-pixels is 1 row sub-pixel, the charging time of the second part of the row sub-pixels is 2 row sub-pixels, and the first part of the row sub-pixels and the second part of the row sub-pixels start charging at the same time.

[0112] In some embodiments of the present disclosure, another driving method is provided, which is applied to, for example, the array substrate shown in the above ​ and ​ As shown in the above ​ and ​ , two gate lines are taken as a gate line group, and the two rows of sub-pixels connected with the two gate lines in the gate line group form a sub-pixel group, and the sub-pixels in the sub-pixel group have the same light-emitting color as the sub-pixels connected with the same data line.

[0113] The driving timing of the driving method is, for example, the timing shown in the above ​ . The gate lines are sequentially turned on, and for each group of gate lines, the gate line connected with the first part of the row sub-pixels is turned on earlier than the gate line connected with the second part of the row sub-pixels.

[0114] In some embodiments of the present disclosure, a driving method is provided, which is applied to, for example, the array substrate shown in the above ​ .

[0115] For the array substrate shown in the above ​ , the plurality of gate lines includes a plurality of first gate line groups, each sub-pixel group is two adjacent rows of sub-pixels, each first gate line group includes two adjacent gate lines, and the colors of the two sub-pixels connected with the same data line in each first sub-pixel group are the same. The driving timing of the driving method is, for example, the timing shown in the above ​ . Each gate line is sequentially turned on, and in each sub-pixel group, the gate line connected with the first part of the row sub-pixels is turned on earlier than the gate line connected with the second part of the row sub-pixels.

[0116] The various features described above with respect to the driving method provided by the embodiments of the present disclosure and the array substrate described above are described with respect to the driving method, and the relevant description with respect to the array substrate is not repeated here.

[0117] Some other embodiments of the present disclosure further provide a display device. The display device includes the array substrate provided by any of the embodiments of the present disclosure.

[0118] ​ A schematic diagram of a display device 600 provided by at least one embodiment of the present disclosure is shown.

[0119] As shown in the above ​As shown, the display device 600 includes an array substrate 610, which can be the array substrate provided in any of the above embodiments.

[0120] The display device 600 includes, in addition to the array substrate 610, an opposite substrate 620. The opposite substrate 620 is arranged opposite to the array substrate 610. For example, when the display device is a liquid crystal display device, a liquid crystal layer is further included, which is arranged between the opposite substrate and the array substrate. The opposite substrate includes a color filter layer, which includes a plurality of color resist, the plurality of color resist including a plurality of columns of blue color resist, a plurality of red color resist, and a plurality of green color resist, the plurality of columns of color resist being arranged corresponding to the plurality of columns of sub-pixels.

[0121] ​ A schematic diagram of another display device 700 provided by at least one embodiment of the present disclosure is shown.

[0122] The display device 700 includes, in addition to the array substrate 610, a circuit board 710, which is electrically connected with the array substrate (it is to be noted that the electrical connection in the present case can be direct electrical connection or indirect electrical connection, i.e., other components or elements are further arranged therebetween, which is not limited herein). The circuit board 710 includes a timing controller 711, which can be a PCB printed circuit board. The array substrate 610 further includes a source driving chip 611, i.e., the optional source driving chip is bound to the non-display area of the array substrate (COG technology), which is configured to provide a data signal to the data lines of the display area, or the source driving chip is arranged on a flexible circuit board, which is bound to the binding area of the non-display area of the array substrate to achieve electrical connection (COF process). The timing controller 711 is coupled with the source driving chip 611 and configured to provide display data to the source driving chip 611. The source driving chip 611 is coupled with a plurality of data lines DA (e.g., the data lines D1-D6 in FIG. 1) and configured to provide a data signal to the plurality of data lines DA according to the display data. ​

[0123] The source driving chip 611 can be arranged in a plurality of numbers, and different source driving chips are coupled with different data lines. For example, as shown in FIG. 1, the source driving chip 611 can be arranged in two numbers, one of which is coupled with half of the data lines, and the other of which is coupled with the other half of the data lines. Of course, the source driving chip 611 can also be arranged in three numbers, four numbers, or more numbers, which can be designed and determined according to the actual application requirements, which is not limited herein.

[0124] ​The timing controller 711 sends display data to the source driving chip 611, so that the source driving chip 611 loads data signals (i.e. data voltages) to the data lines in the array substrate according to the received display data, thereby charging the sub-pixels, filling each sub-pixel with a corresponding target data voltage, and realizing the picture display function.

[0125] The circuit board 710 can further include a level conversion unit 712 in addition to the timing controller 711, and the array substrate 610 further includes a gate driving circuit 612.

[0126] The level conversion unit 712 is coupled to the timing controller 711, and the gate driving circuit 623 is connected to the level conversion unit 712 and the plurality of gate lines GA (e.g. gate lines G1-G8 in the array substrate 610). ​ The level conversion unit 712 is configured to receive a plurality of first clock signals provided by the timing controller 711, convert the plurality of first clock signals into a plurality of second clock signals, and provide the plurality of second clock signals to the gate driving circuit 623. The gate driving circuit 623 is configured to provide a plurality of gate signals to the gate lines GA according to the plurality of second clock signals, so as to control the gate lines to be turned on. ​ It is shown in FIG. 6 that the gate driving circuit is arranged on both sides of the non-display area of the display panel, and the gate driving circuits on both sides can drive the same gate lines in the display area, or one side of the gate driving circuit drives the odd-numbered gate lines and the other side of the gate driving circuit drives the even-numbered gate lines. Alternatively, the gate driving circuit can be arranged only on one side of the non-display area of the display panel, which is not limited herein.

[0127] The optional display device further comprises a system chip SOC, the system chip is electrically connected with the timing controller, for example, in the case of enabling the HSR function, the display line charging rate is improved, and the data signals of at least part of the display lines are charged for 2H. In order to realize that the data signals of at least part of the lines are charged for 2H, the following modes can be used, but are not limited to the following modes, for example, the system control chip deletes part of the data, or the timing controller deletes part of the data, or the source driving chip deletes part of the data. The deleted data can be, for example, half of the data of each frame is deleted, the deleted data can be interlaced deletion, for example, only the data of odd lines is reserved in each frame, and the data of even lines is deleted; or, only the data of even lines is reserved in each frame, and the data of odd lines is deleted; or, in adjacent two frames, the data of odd lines is reserved in the former frame, and the data of even lines is deleted, the data of even lines is reserved in the latter frame, and the data of odd lines is deleted, for example, only the data of 1, 3, 5, 7, 9 and the like of the gate line is reserved in the first frame, and only the data corresponding to 2, 4, 6, 8, 10 and the like of the gate line is reserved in the second frame; or, in adjacent two frames, the data of even lines is reserved in the former frame, and the data of odd lines is deleted, the data of odd lines is reserved in the latter frame, and the data of even lines is deleted, for example, only the data of 2, 4, 6, 8, 10 and the like of the gate line is reserved in the first frame, and only the data corresponding to 1, 3, 5, 7, 9 and the like of the gate line is reserved in the second frame. The "line" here refers to the corresponding pixels connected by each gate line, which correspond to a line, and different gate lines correspond to different lines. This is not limited here.

[0128] The level conversion unit 712 can be implemented as a level conversion circuit or a chip for level conversion. The level conversion unit 712 may, for example, change the period or amplitude of each of the plurality of first clock signals to obtain a plurality of second clock signals. For example, the level conversion unit 712 increases the voltage amplitude and period of the plurality of first clock signals. The level conversion unit 712 can convert the p first clock signals provided by the timing controller 711 into q second clock signals, p is an integer greater than or equal to 1, q is an integer greater than or equal to 2, and q is greater than or equal to p. For example, the array substrate includes 8 gate lines as a cycle group, and q can be equal to 8.

[0129] The following points need to be explained:

[0130] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0131] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined to obtain new embodiments.

[0132] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An array substrate, comprising a pixel array formed by a plurality of rows of a plurality of columns of sub-pixels, a plurality of gate lines and a plurality of data lines intersecting to define the plurality of rows of the plurality of columns of sub-pixels, each row of sub-pixels being connected to two adjacent gate lines of the plurality of gate lines, at least one data line of the plurality of data lines being connected to two adjacent columns of sub-pixels of the plurality of columns of sub-pixels, the plurality of gate lines being configured to turn on the plurality of rows of sub-pixels, and the plurality of data lines being configured to charge the plurality of columns of turned-on sub-pixels, the plurality of rows of sub-pixels comprising a plurality of groups of sub-pixels, each group of sub-pixels comprising a part of rows of sub-pixels of the plurality of rows of sub-pixels, each row of sub-pixels of the part of rows of sub-pixels comprising sub-pixels connected to a same gate line, and charging times of the part of rows of sub-pixels overlapping, the part of rows of sub-pixels comprising a first part of rows of sub-pixels and a second part of rows of sub-pixels, the charging time of the second part of rows of sub-pixels being longer than the charging time of the first part of rows of sub-pixels, in a first time period in which the charging times overlap, the first part of rows of sub-pixels and the second part of rows of sub-pixels being written with a same data signal, in a second time period in which the charging times do not overlap, the second part of rows of sub-pixels being written with a data signal at least partially same as the data signal written in the first time period, two gate lines serving as a gate line group, a sub-pixel group being formed by two rows of sub-pixels connected to the two gate lines of the gate line group respectively, the sub-pixel group corresponding to sub-pixels connected to a same data line having a same color, a plurality of gate line groups being sequentially turned on, wherein for each gate line group, a gate line connected to the first part of rows of sub-pixels is turned on earlier than a gate line connected to the second part of rows of sub-pixels, in the part of rows of sub-pixels, a plurality of sub-pixels connected to a same data line correspond to a same color, the charging time of the first part of rows of sub-pixels is a charging time of 1 row of sub-pixels, the charging time of the second part of rows of sub-pixels is a charging time of 2 rows of sub-pixels, and the first part of rows of sub-pixels and the second part of rows of sub-pixels start charging at the same time, a same data line connects a plurality of groups of sub-pixels, a plurality of sub-pixels connected to a same data line and corresponding to a same color are connected to odd-numbered rows of gate lines or even-numbered rows of gate lines, a same column of sub-pixels correspond to a same color, a plurality of sub-pixels corresponding to red are connected to odd-numbered rows of gate lines, a plurality of sub-pixels corresponding to green are connected to even-numbered rows of gate lines, a plurality of sub-pixels corresponding to blue connected to a same data line are connected to a plurality of odd-numbered rows of gate lines or a plurality of even-numbered rows of gate lines, or a plurality of sub-pixels corresponding to green are connected to odd-numbered rows of gate lines, a plurality of sub-pixels corresponding to blue are connected to even-numbered rows of gate lines, a plurality of sub-pixels corresponding to red connected to a same data line are connected to a plurality of odd-numbered rows of gate lines or a plurality of even-numbered rows of gate lines, or a plurality of sub-pixels corresponding to red are connected to odd-numbered rows of gate lines, a plurality of sub-pixels corresponding to blue are connected to even-numbered rows of gate lines, and a plurality of sub-pixels corresponding to green connected to a same data line are connected to a plurality of odd-numbered rows of gate lines or a plurality of even-numbered rows of gate lines. ​ ​ ​ ​ ​ ​ ​ wherein ​ ​ 2. The array substrate according to claim 1, wherein, ​ 3. The array substrate according to claim 1 or 2, wherein, ​ 4. The array substrate of claim 1, wherein, ​ 5. The array substrate according to claim 4, wherein, ​ ​ ​ ​ 6. The array substrate according to claim 4, wherein, The same column of sub-pixels corresponds to the same color, and the multiple sub-pixels corresponding to the red color connected to the same data line are connected to the multiple odd-numbered row gate lines or the multiple even-numbered row gate lines, the multiple sub-pixels corresponding to the green color connected to the same data line are connected to the multiple odd-numbered row gate lines or the multiple even-numbered row gate lines, and the multiple sub-pixels corresponding to the blue color connected to the same data line are connected to the multiple odd-numbered row gate lines or the multiple even-numbered row gate lines.

7. The array substrate according to claim 4, wherein, One image frame includes a first display period and a second display period, two adjacent odd-numbered row gate lines are taken as a group, two adjacent even-numbered row gate lines are taken as a group, and two rows of sub-pixels connected by each group of gate lines are taken as a group of sub-pixels, For the odd-numbered row gate lines, multiple groups of odd-numbered row gate lines are sequentially turned on in the first display period; For the even-numbered row gate lines, multiple groups of even-numbered row gate lines are sequentially turned on in the second display period, Wherein, in each group of gate lines, the gate line connected to the first part of the row sub-pixels is turned on earlier than the gate line connected to the second part of the row sub-pixels.

8. The array substrate of claim 1, wherein, The multiple gate lines include multiple first gate line groups, the multiple groups of sub-pixels include multiple first sub-pixel groups, each first gate line group includes two adjacent gate lines, and two rows of sub-pixels connected by each first gate line group form the first sub-pixel group, and two sub-pixels connected to the same data line in each first sub-pixel group correspond to the same color.

9. The array substrate of claim 8, wherein, The multiple groups of sub-pixels further include a second sub-pixel group, the second sub-pixel group includes multiple sub-pixels connected to the first turned-on gate line in the multiple gate lines, and the multiple first sub-pixel groups include multiple rows of sub-pixels except for the sub-pixels included in the second sub-pixel group.

10. The array substrate according to claim 8 or 9, wherein, The multiple gate lines are sequentially turned on, and in each group of sub-pixels, the gate line connected to the first part of the row sub-pixels is turned on earlier than the gate line connected to the second part of the row sub-pixels.

11. A driving method applied to the array substrate of claim 1, the method comprising: turning on the multiple gate lines connected to each group of sub-pixels; and charging each group of sub-pixels by the multiple data lines during the turning on of the multiple gate lines of each group of sub-pixels. The same data line connects multiple groups of sub-pixels, multiple sub-pixels with the same light-emitting color connected on the same data line are connected to the odd-numbered row gate lines or the even-numbered row gate lines, one image frame includes a first display period and a second display period, two adjacent odd-numbered row gate lines are taken as a group, two adjacent even-numbered row gate lines are taken as a group, and two rows of sub-pixels connected by each group of gate lines are taken as a group of sub-pixels, 12. The method of claim 11, wherein, Sequentially turning on the multiple gate lines connected to each group of sub-pixels includes: in the first display period, sequentially turning on the odd-numbered row gate lines; in the second display period, sequentially turning on the even-numbered row gate lines, wherein, in each group of gate lines, the gate line connected to the first part of the row sub-pixels is turned on earlier than the gate line connected to the second part of the row sub-pixels. Two gate lines are taken as a gate line group, two rows of sub-pixels connected to the two gate lines in the gate line group form a sub-pixel group, and sub-pixels connected to the same data line in the sub-pixel group correspond to the same light-emitting color, 13. The method of claim 11, wherein, Sequentially turning on the multiple gate lines connected to each group of sub-pixels includes: ​ The multiple groups of gate lines are sequentially turned on, and for each group of gate lines, the gate line connected to the first part of row sub-pixels is turned on earlier than the gate line connected to the second part of row sub-pixels.

14. The method of claim 11, wherein, The multiple gate lines include multiple first groups of gate lines, each group of sub-pixels is adjacent two rows of sub-pixels, and each first group of sub-pixels includes adjacent two gate lines, and the colors corresponding to the two sub-pixels connected to the same data line in each first group of sub-pixels are the same, The multiple gate lines connected to each group of sub-pixels are sequentially turned on, and for each group of sub-pixels, the gate line connected to the first part of row sub-pixels is turned on earlier than the gate line connected to the second part of row sub-pixels. The charging time of the first part of row sub-pixels is 1 row of sub-pixels, the charging time of the second part of row sub-pixels is 2 rows of sub-pixels, and the first part of row sub-pixels and the second part of row sub-pixels start charging at the same time.

15. The method of any one of claims 11-14, wherein, 16. A display device, comprising the array substrate of any one of claims 1-10. The array substrate further comprises a color filter layer, the color filter layer comprises a plurality of color resist, the plurality of color resist comprises a plurality of blue color resist, a plurality of red color resist and a plurality of green color resist, and the plurality of color resist one-to-one corresponds to the multiple rows and multiple columns of sub-pixels.

17. The display device of claim 16, further comprising:

18. The display device of claim 16 or 17, further comprising a circuit board, the circuit board is provided with a timing controller, the array substrate further comprises a source driving chip, The timing controller is coupled to the source driving chip, and is configured to provide display data to the source driving chip; The source driving chip is coupled to the multiple data lines, and is configured to provide the data signal to the multiple data lines according to the display data. The circuit board further comprises a level conversion unit, and the array substrate further comprises a gate driving circuit, 19. The display device of claim 18, wherein, The level conversion unit is coupled to the timing controller, and the gate driving circuit is connected to the level conversion unit and the multiple gate lines, The level conversion unit is configured to receive multiple first clock signals provided by the timing controller, convert the multiple first clock signals into multiple second clock signals, and provide the multiple second clock signals to the gate driving circuit, The gate driving circuit is configured to provide a gate signal to the gate line according to the multiple second clock signals, so as to control the gate line to be turned on. ​

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