Display device, control method and power supply voltage adjusting method

Abstract

The invention provides a display device, a control method and a power supply voltage adjusting method. The display device comprises a display panel, a power supply circuit (13), at least one processor (250) and a backlight assembly (20), the backlight assembly (20) comprises a driving circuit (201) and a lamp panel (30), the lamp panel (30) comprises lamp beads (301) distributed in an array mode, the at least one lamp bead (301) is electrically connected to form a light-emitting unit group, the driving circuit (201) comprises at least one driving chip (202), the power supply end (VP) of each driving chip (202) is electrically connected with the power supply circuit (13), and the power supply end (VP) of each driving chip (202) is electrically connected with the power supply circuit (13). Each driving end is electrically connected with a plurality of light-emitting unit groups, the plurality of light-emitting unit groups are respectively and correspondingly electrically connected with a plurality of power supply ends, and the driving chip (202) can supply power to the light-emitting unit groups electrically connected with the driving chip according to a preset power supply sequence based on a power supply signal provided by the power supply circuit (13). And corresponding driving signals are output at each driving end based on driving data provided by at least one processor (250) so as to drive different light-emitting unit groups to generate corresponding light intensities.

Description

Display device, control method, and supply voltage adjustment method

[0001] This application claims the following: Application No. 2023102800551 filed on March 21, 2023; Application No. 2024101784490 filed on February 8, 2024; Application No. 2024101784467 filed on February 8, 2024; Application No. 2024101784471 filed on February 8, 2024; Application No. 2024101784481 filed on February 8, 2024 81420; Chinese patent applications filed on February 8, 2024, with application numbers 2024101781488; Chinese patent applications filed on February 8, 2024, with application numbers 2024202906039; Chinese patent applications filed on February 8, 2024, with application numbers 2024202905905; Chinese patent applications filed on February 8, 2024, with application numbers 2024101784448, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to a display device, a control method and a method for adjusting a power supply voltage. Background Art

[0003] A display device is a device that displays images and / or user interfaces. It includes at least one processor, a display panel, and a backlight assembly. The backlight assembly includes a driver circuit and a light board. The light board includes an array of LEDs, with at least one LED electrically connected to form a light-emitting unit group (zone). The driver circuit drives each zone to emit light.

[0004] As the display quality of display devices improves, the number of partitions on the light board increases, and improving the driving capability of the driving circuit becomes a research topic.

[0005] Display devices may also include a power supply circuit and a motherboard. The power supply circuit provides power signals to both the motherboard and the backlight assembly via a stepped power supply. When the display device is in standby mode, the backlight assembly generates leakage current based on the power signal, resulting in power loss. Therefore, reducing the power loss in the backlight assembly during standby mode has become a research topic.

[0006] During the power supply circuit's power supply process, at least one processor generates driving data based on acquired data to adjust the current provided by each driver chip to the corresponding light string. Furthermore, based on the electrical signals fed back by the driver chips, the processor controls the power supply circuit to provide voltage to the multiple light strings, thereby causing them to illuminate. Ensuring the accuracy of supply voltage regulation while reducing the number of signals transmitted within the display device has become a research topic.

[0007] To improve the smoothness and clarity of display images, some LCD devices use variable refresh rate (VRR) technology. This dynamically adjusts the display cycle of the display panel and backlight assembly based on the current frame rate to enhance display quality. Black frame insertion (BFI) technology based on variable refresh rate can address the image smearing phenomenon caused by the slow response of liquid crystal molecules in display panels.

[0008] Since the black insertion duration in the display period corresponding to different refresh rates is fixed, the black insertion ratio corresponding to different refresh rates is different, causing the screen display to flicker. Therefore, solving the flicker problem of screen storage has become a research topic.

[0009] As the integration of the backlight assembly increases, the temperature of the internal components in each area increases with the increase in integration, and excessively high temperature will affect the life of the components.

[0010] In the related art, a temperature threshold of a component is set. When the temperature reaches the temperature threshold, the output current is controlled to be reduced to a lower value, which may cause the image displayed by the display device to flicker and the accuracy and reliability of the backlight control to be low.

[0011] Summary of the Invention

[0012] An embodiment of the present application provides a display device, which includes: a display panel; a power supply circuit electrically connected to the display panel; at least one processor electrically connected to the display panel and the power supply circuit; a backlight assembly electrically connected to the at least one processor and the power supply circuit, the backlight assembly including a driving circuit and a light board; the light board including lamp beads distributed in an array, at least one lamp bead electrically connected to form a light-emitting unit group; the driving circuit includes at least one driving chip, each of the driving chips is provided with a power supply end, at least one driving end and multiple power supply ends, the power supply end is electrically connected to the power supply circuit, each of the driving ends is electrically connected to multiple light-emitting unit groups, and the multiple light-emitting unit groups are respectively electrically connected to the multiple power supply ends; wherein different driving ends are electrically connected to different light-emitting unit groups.

[0013] An embodiment of the present application also provides a control method for a display device, which is applied to a driving circuit in a display device. The display device may also include: a display panel, a power supply circuit, at least one processor and multiple lamp beads, at least one lamp bead is electrically connected to form a light-emitting unit group; the driving circuit is provided with an input end, at least one driving end and multiple power supply ends, the input end is electrically connected to the at least one processor, each of the driving ends corresponds to multiple light-emitting unit groups, and the multiple light-emitting unit groups respectively correspond to the multiple power supply ends; wherein different driving ends correspond to different light-emitting unit groups; the method includes: obtaining a power signal provided by the power supply circuit and driving data provided by the at least one processor; based on the driving data, sequentially outputting the power signal from the power supply end, outputting the corresponding driving signal from the driving end, and driving the light-emitting unit groups corresponding to the power supply end and the driving end to emit light.

[0014] An embodiment of the present application also provides a control method for a display device, which is applied to at least one processor in the display device. The display device may also include: a display panel, a power supply circuit, multiple lamp beads and a driving circuit, at least one lamp bead is electrically connected in series to form a light-emitting unit group; the driving circuit is provided with an input end, at least one driving end and multiple power supply ends, the input end is electrically connected to the at least one processor, each of the driving ends corresponds to multiple light-emitting unit groups, and the multiple light-emitting unit groups respectively correspond to the multiple power supply ends, wherein different driving ends correspond to different light-emitting unit groups; the method includes: outputting driving data so that the driving circuit obtains the driving data and the power signal output by the power supply circuit, and then, based on the driving data, sequentially outputs the power signal from the power supply end, outputs the corresponding driving signal from the driving end, and drives the power supply end and the light-emitting unit group corresponding to the driving end to emit light.

[0015] An embodiment of the present application also provides a display device, which includes: a display panel; at least one processor electrically connected to the display panel, which can be configured to output driving data; a backlight assembly, including: at least one power supply control circuit, a driving circuit and multiple lamp beads, at least one lamp bead is electrically connected to form a light-emitting unit group; the driving circuit includes at least one driving chip; the input port of the power supply control circuit is electrically connected to the at least one processor, its first output end is electrically connected to the power supply end of the corresponding at least one driving chip, and its second output end is coupled to the data input end of the at least one driving chip; the power supply control circuit can be configured to output a chip power supply signal from its first output end and output the driving data from its second output end when receiving the driving data; the power supply control circuit can also be configured to stop outputting the chip power supply signal and the driving data when not receiving the driving data; the driving chip is electrically connected to at least one light-emitting unit group, and can be configured to drive the light-emitting unit group to emit light based on the driving data and the chip power supply signal.

[0016] An embodiment of the present application also provides a display control method, which is applied to a power supply control circuit of a display device. The display device may further include a display panel, at least one processor, a driving circuit and at least one lamp bead. The at least one processor is coupled to an input port of the power supply control circuit, and an output end of the power supply control circuit is electrically connected to the driving circuit. The method includes: when receiving driving data, supplying power to the driving circuit based on the driving data, outputting the driving data, so that the driving circuit drives the at least one lamp bead to emit light based on the driving data; when not receiving the driving data, stopping supplying power to the driving circuit, stopping providing the driving data, so that the driving circuit stops driving the light-emitting unit group to emit light. The driving data is data generated by the at least one processor based on backlight data in a frame of image data.

[0017] An embodiment of the present application also provides a display control method, which is applied to at least one processor of a display device. The display device may also include a display panel, a driving circuit, at least one lamp bead and a power supply control circuit. The at least one processor is coupled to the input port of the power supply control circuit, and the output end of the power supply control circuit is electrically connected to the driving circuit. The method includes: obtaining a frame of image data, wherein the image data includes backlight data; outputting driving data based on the backlight data, so that when the power supply control circuit receives the driving data, it supplies power to the driving circuit based on the driving data, outputs the driving data, and controls the driving circuit to drive at least one lamp bead to emit light based on the driving data; when the driving data is not received, the power supply to the driving circuit and the provision of the driving data are stopped, and the driving circuit is controlled to stop driving the light-emitting unit group to emit light.

[0018] An embodiment of the present application also provides a display device, which includes: a display panel; at least one processor coupled to the display panel, and can be configured to: obtain image data of a frame and a frame start trigger signal; the image data includes backlight data; in response to the frame start trigger signal, no driving data is output during the black insertion period in the current frame display period; initial dimming data is determined based on the backlight data during at most two light-emitting periods in the current frame display period; the driving data is output based on the initial dimming data; the driving data includes current values ​​corresponding to each of the light-emitting periods; the average current value of the current values ​​corresponding to the at most two light-emitting periods during the current frame display period is the product of the initial dimming data and the light-emitting ratio; the backlight assembly coupled to the at least one processor can be configured to provide backlight based on the driving data.

[0019] An embodiment of the present application also provides a backlight control method for a display device, the method being applied to at least one processor of the display device, and the display device may further include a display panel and a backlight assembly coupled to the at least one processor, the method including: obtaining image data of a frame and a frame start trigger signal; the image data including backlight data; in response to the frame start trigger signal, not outputting driving data during a black insertion period in a current frame display period; determining initial dimming data based on the backlight data during at most two luminous periods in the current frame display period; outputting the driving data based on the initial dimming data so that the backlight assembly provides backlight based on the driving data; the driving data including current values ​​corresponding to each of the luminous periods; the average current value of the current values ​​corresponding to the at most two luminous periods during the current frame display period is the product of the initial dimming data and the luminous ratio.

[0020] An embodiment of the present application also provides a display device, which includes: a display panel; at least one processor coupled to the display panel, which can be configured to: obtain image data of a frame, a display period of the current frame and a black insertion ratio, wherein the image data includes backlight data; based on the black insertion ratio, divide the display period of the current frame into at least one black insertion period and at least one luminous period; the total duration of the at least one black insertion period is the product of the duration of the display period of the current frame and the black insertion ratio; within the at least one luminous period, output drive data based on the backlight data; and a backlight assembly coupled to the at least one processor can be configured to provide backlight based on the drive data.

[0021] An embodiment of the present application also provides a backlight control method for a display device, the display device comprising: a display panel, a backlight assembly, and at least one processor; the method is applied to the at least one processor, and the method comprises: obtaining image data of a frame, a display period of the current frame, and a black insertion ratio; the image data comprises backlight data; based on the black insertion ratio, dividing the display period of the current frame into at least one black insertion period and at least one luminous period; the total duration of the at least one black insertion period is the product of the duration of the display period of the current frame and the black insertion ratio; within the at least one luminous period, outputting driving data based on the backlight data, so that the backlight assembly coupled to the at least one processor provides backlight based on the driving data.

[0022] An embodiment of the present application also provides a method for adjusting the power supply voltage, which is applied to at least one processor of a display device. The display device may also include a backlight assembly and a power supply circuit, wherein the backlight assembly includes multiple driver chips and array-distributed lamp beads, at least one lamp bead is electrically connected to form a light-emitting unit group, and each driver chip corresponds to at least one light-emitting unit group; the method includes: obtaining a frame of image data and a current-voltage relationship of the light-emitting unit group; the image data includes backlight data, and the current-voltage relationship of the light-emitting unit group represents a mapping relationship between a current value flowing through the light-emitting unit group and a corresponding supply voltage value when different supply voltage values ​​are applied to the light-emitting unit group; based on the backlight data, generating driving data corresponding to each of the light-emitting unit groups; the driving data includes a current value and a duty cycle; the current value corresponding to each of the light-emitting unit groups is the same; based on the current-voltage relationship and the current value, determining the corresponding supply voltage value; controlling the power supply circuit to output a supply voltage with a voltage value of the supply voltage value to the light-emitting unit group. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a schematic diagram of an operation scenario between a display device and a control apparatus according to some embodiments;

[0024] FIG2 is a schematic structural diagram of a display device according to some embodiments;

[0025] FIG3 is a schematic structural diagram of a display device according to some other embodiments;

[0026] FIG4 is a schematic diagram of a circuit structure of a backlight assembly according to some embodiments;

[0027] FIG5A is a schematic structural diagram of a backlight assembly according to some other embodiments;

[0028] FIG5B is a schematic structural diagram of a backlight assembly according to some other embodiments;

[0029] FIG6 is a schematic flow chart of a method for controlling a display device according to some embodiments;

[0030] FIG7 is a schematic diagram of hybrid dimming according to an embodiment;

[0031] FIG8 is a schematic flow chart of a method for controlling a display device according to other embodiments;

[0032] FIG9 is a schematic structural diagram of a driver chip according to some embodiments;

[0033] FIG10 is a schematic structural diagram of a driver chip according to some embodiments;

[0034] FIG11A is a schematic structural diagram of the connection relationship between a driver chip and its corresponding lamp beads according to some embodiments;

[0035] FIG11B is a schematic structural diagram of the connection relationship between a driver chip and its corresponding lamp beads according to other embodiments;

[0036] FIG11C is a schematic structural diagram of the connection relationship between a driver chip and its corresponding lamp beads according to some other embodiments;

[0037] FIG12 is a schematic diagram showing coating positions of an insulating layer and a conductive layer for a jumper wire in an exemplary embodiment;

[0038] FIG13 is a schematic diagram showing coating positions of an insulating layer and a conductive layer for a jumper wire in another exemplary embodiment;

[0039] FIG14 is a schematic diagram showing coating positions of an insulating layer and a conductive layer for a jumper wire in another exemplary embodiment;

[0040] FIG15 is a schematic diagram showing coating positions of an insulating layer and a conductive layer for a jumper wire in another exemplary embodiment;

[0041] FIG16 is a schematic diagram showing coating positions of an insulating layer and a conductive layer for a jumper wire in another exemplary embodiment;

[0042] FIG17 is a schematic diagram showing coating positions of an insulating layer and a conductive layer for a jumper wire in another exemplary embodiment;

[0043] FIG18 is a waveform diagram of driving data in an example;

[0044] FIG19 is a waveform diagram of another exemplary driving data;

[0045] FIG20 is a waveform diagram of another exemplary driving data;

[0046] FIG21 is a waveform diagram of another exemplary driving data;

[0047] FIG22 is a waveform diagram of another exemplary driving data;

[0048] FIG23 is a schematic structural diagram of a backlight assembly according to some other embodiments;

[0049] FIG24 is a schematic diagram of a circuit structure of a power supply according to some embodiments;

[0050] FIG25 is a schematic structural diagram of a backlight assembly according to some embodiments;

[0051] FIG26A is a schematic structural diagram of a backlight assembly according to some embodiments;

[0052] FIG26B is a schematic structural diagram of a backlight assembly according to some other embodiments;

[0053] FIG26C is a schematic structural diagram of a backlight assembly according to some other embodiments;

[0054] FIG26D is a schematic structural diagram of a backlight assembly according to some other embodiments;

[0055] FIG27 is a display control method according to some embodiments;

[0056] FIG28 is a schematic structural diagram of a power supply control circuit according to some embodiments;

[0057] FIG29A is a schematic structural diagram of a power supply control circuit according to some other embodiments;

[0058] FIG29B is a schematic structural diagram of a power supply control circuit according to some other embodiments;

[0059] FIG30 is a schematic structural diagram of a backlight assembly according to some other embodiments;

[0060] FIG31 is a schematic structural diagram of a power supply control circuit according to some other embodiments;

[0061] FIG32 is a schematic diagram of the structure of an address unit according to some embodiments;

[0062] FIG33 is a schematic structural diagram of a driving circuit according to some embodiments;

[0063] FIG34 is a schematic structural diagram of a backlight assembly according to some other embodiments;

[0064] FIG35 is a schematic structural diagram of a backlight assembly according to some other embodiments;

[0065] FIG36 is a schematic structural diagram of a backlight assembly according to some other embodiments;

[0066] FIG37 is a schematic structural diagram of a power supply control circuit according to other embodiments;

[0067] FIG38 is a waveform diagram of driving data according to some embodiments;

[0068] FIG39 is a waveform diagram of driving data according to some embodiments;

[0069] FIG40 is a waveform diagram of driving data according to some embodiments;

[0070] FIG41 is a schematic structural diagram of a display device according to some other embodiments;

[0071] FIG42 is a schematic structural diagram of a backlight assembly according to some other embodiments;

[0072] FIG43 is a schematic structural diagram of a backlight assembly according to some other embodiments;

[0073] FIG44 is a schematic diagram of a demodulation circuit according to some embodiments;

[0074] FIG45 is a schematic diagram showing the positional relationship between lamp beads and liquid crystal molecules according to some embodiments;

[0075] FIG46 is a schematic diagram illustrating the response of liquid crystal molecules according to some embodiments;

[0076] FIG47 is a waveform diagram of a variable refresh rate according to some embodiments;

[0077] FIG48 is a schematic flow chart of a backlight control method for a display device according to some embodiments;

[0078] FIG49 is a waveform diagram of a variable refresh rate according to some other embodiments;

[0079] FIG50 is a waveform diagram of a variable refresh rate according to some other embodiments;

[0080] FIG51 is a waveform diagram of a variable refresh rate according to some other embodiments;

[0081] FIG52 is a waveform diagram of a variable refresh rate according to some other embodiments;

[0082] FIG53 is a waveform diagram of a variable refresh rate according to some other embodiments;

[0083] FIG54 is a waveform diagram of a variable refresh rate according to some other embodiments;

[0084] FIG55 is a schematic flow chart of a backlight control method for a display device according to some embodiments;

[0085] FIG56 is a flowchart illustrating a method for dividing a display time period according to some embodiments;

[0086] FIG57 is a waveform diagram of a variable refresh rate according to some other embodiments;

[0087] FIG58 is a waveform diagram of a variable refresh rate according to some other embodiments;

[0088] FIG59 is a waveform diagram of a variable refresh rate according to some other embodiments;

[0089] FIG60 is a waveform diagram of a variable refresh rate according to some other embodiments;

[0090] FIG61 is a waveform diagram of a variable refresh rate according to some other embodiments;

[0091] FIG62 is a flowchart illustrating a method for adjusting a power supply voltage according to some embodiments;

[0092] FIG63 is a flowchart of a method for acquiring voltage-current sampling data according to some embodiments;

[0093] FIG64 is a flowchart of a method for acquiring voltage-current sampling data according to other embodiments;

[0094] FIG65 is a schematic structural diagram of a driving circuit according to some embodiments;

[0095] FIG66 is a schematic structural diagram of a driving circuit according to some other embodiments;

[0096] FIG67 is a schematic structural diagram of a driving circuit according to some other embodiments;

[0097] FIG68 is a schematic diagram of a temperature threshold control method according to some embodiments;

[0098] FIG69 is a schematic diagram showing the current and temperature variation of a small window with continuous highlight according to some embodiments;

[0099] FIG70 is a schematic diagram illustrating a small window brightness variation current and temperature change according to some embodiments;

[0100] FIG71 is a schematic diagram illustrating current temperature variation according to some embodiments;

[0101] FIG72 is a schematic structural diagram of a display device provided in an embodiment of the present application;

[0102] FIG73 is a schematic structural diagram of another display device provided in an embodiment of the present application;

[0103] FIG74 is a schematic structural diagram of a driving circuit provided in an embodiment of the present application;

[0104] FIG75 is a schematic diagram of the structure of another driving circuit provided in an embodiment of the present application;

[0105] FIG76 is a schematic diagram illustrating a coupling between a plurality of driver chips and at least one controller;

[0106] FIG77A is a first structural diagram of a driving circuit provided in an embodiment of the present application;

[0107] FIG77B is a schematic structural diagram of a driving circuit in the related art;

[0108] FIG78 is a second structural diagram of a driving circuit provided in an embodiment of the present application;

[0109] FIG79A is a first structural diagram of a driver chip provided in an embodiment of the present application;

[0110] FIG79B is a second structural diagram of a driver chip provided in an embodiment of the present application;

[0111] FIG80A is a third structural diagram of a driving circuit provided in an embodiment of the present application;

[0112] FIG80B is a fourth structural diagram of a driving circuit provided in an embodiment of the present application;

[0113] FIG80C is a fifth structural diagram of a driving circuit provided in an embodiment of the present application;

[0114] FIG81A is a schematic diagram of the structure of a driver chip with a physical address in an example;

[0115] FIG81B is a schematic structural diagram of a driver chip with a physical address in another example;

[0116] FIG82 is a schematic structural diagram of a driver chip in another example;

[0117] FIG83 is a schematic diagram showing the structure of a driver chip for setting an address calibration circuit in an example;

[0118] FIG84 is a schematic diagram showing the structure of a drive group according to some embodiments of the present disclosure;

[0119] FIG85 is a schematic diagram showing the structure of a drive group according to some embodiments of the present disclosure;

[0120] FIG86 is a schematic diagram showing the structure of a drive group according to some embodiments of the present disclosure;

[0121] FIG87A is a schematic diagram illustrating the structure of a light panel according to some embodiments of the present disclosure;

[0122] FIG87B is a schematic diagram illustrating the structure of a light panel according to some embodiments of the present disclosure;

[0123] FIG88 is a schematic diagram showing the structure of a driving circuit according to some embodiments of the present disclosure;

[0124] FIG89 is a schematic diagram showing the structure of a driving circuit according to some embodiments of the present disclosure;

[0125] FIG90 is a schematic structural diagram of a display device provided in an embodiment of the present application;

[0126] FIG91 is a flow chart of a data communication method provided by the present application;

[0127] FIG92 is a schematic structural diagram of a driving circuit in one embodiment;

[0128] FIG93 is a structural diagram 1 of the driving data of the driving group;

[0129] FIG94 is a second structural diagram of the driving data of the driving group;

[0130] FIG95 is a third structural diagram of the driving data of the driving group;

[0131] FIG96 is a fourth structural diagram of the driving data of the driving group;

[0132] FIG97 is a fifth structural diagram of the driving data of the driving group. DETAILED DESCRIPTION

[0133] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0134] It should be noted that the brief descriptions of terms in this application are only for the purpose of facilitating the understanding of the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their ordinary and usual meanings.

[0135] In the specification and claims of this application and the drawings, the terms "first," "second," and the like are used to distinguish similar or similar objects or entities and are not necessarily intended to limit a particular order or precedence, unless otherwise indicated. It should be understood that the terms used in this manner are interchangeable where appropriate, for example, the embodiments of this application can be implemented in an order other than that shown or described in the drawings.

[0136] In addition, the terms "including" and "having" and any variations thereof are intended to cover, but not exclude, inclusion. For example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such product or device. The term "circuitry" as used in this application refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that is capable of performing the function associated with that element.

[0137] FIG1 is a schematic diagram of an operation scenario between a display device and a control device according to some embodiments. As shown in FIG1 , a user can operate a display device 200 through a smart device 300 or a control device 100 .

[0138] In some embodiments, the control device 100 may be a remote controller. Communication between the remote controller and the display device may include infrared protocol communication, Bluetooth protocol communication, or other short-range communication methods, and the display device 200 may be controlled wirelessly or wired. The user may control the display device 200 by inputting user commands through buttons on the remote controller, voice input, control panel input, and the like.

[0139] In some embodiments, a smart device 300 (such as a mobile terminal, tablet computer, computer, laptop computer, etc.) can also be used to control the display device 200. For example, the display device 200 can be controlled using an application running on the smart device.

[0140] In some embodiments, the display device may not use the aforementioned smart device or control device to receive instructions, but may receive user control through touch or gestures.

[0141] In some embodiments, the display device 200 can also be controlled in a manner other than the control device 100 and the smart device 300. For example, the user's voice command control can be directly received through a module for obtaining voice commands configured inside the display device 200, or the user's voice command control can be received through a voice control device set outside the display device 200.

[0142] In some embodiments, the display device 200 also communicates data with the server 400. The display device 200 may be communicatively coupled via a local area network (LAN), a wireless local area network (WLAN), or other networks. The server 400 may provide various content and interactions to the display device 200. The server 400 may be a single cluster or multiple clusters, and may include one or more types of servers.

[0143] FIG. 2 is a schematic structural diagram of a display device 200 according to some embodiments.

[0144] In some embodiments, the display device 200 includes at least one processor 250, and the at least one processor 250 can be configured to receive a video input signal or an image input signal, obtain backlight data and display data from the video input signal or the image input signal, perform format conversion, timing control and other processing on the backlight data and display data, and then output them.

[0145] In some embodiments, at least one processor 250 may include multiple processors, for example, may include a processor (System On Chip, abbreviated as SOC), which can be configured to obtain a video input signal or an image input signal (hereinafter referred to as input signal) from an external input port or a network port, and perform format conversion, data processing, image rendering and other operations on the input signal.

[0146] In some embodiments, at least one processor may include a timing controller (Tcon), which may be configured to perform timing control on the data obtained by the processor.

[0147] In some embodiments, the timing processor may be further configured to perform data format conversion.

[0148] In some embodiments, at least one processor 250 may include a backlight controller (Bcon) or at least one dimming processor (DCON), which may be configured to obtain processed data associated with backlight data, generate and output driving data based on the processed data.

[0149] In some embodiments, the display device 200 may include a display panel 10 coupled to at least one processor. The display panel 10 may include liquid crystal molecules configured to deflect based on received processed display data.

[0150] In some embodiments, the display device 200 may include a backlight assembly 20 coupled to at least one processor 250 , and the backlight assembly 20 may be configured to emit light based on driving data. The display panel 10 may display images based on the backlight provided by the backlight assembly 20 .

[0151] In some embodiments, the backlight assembly 20 may include a driving circuit 201 coupled to at least one processor 250 . The driving circuit 201 includes a plurality of driving chips 202 . The driving chips 202 may be configured to generate driving signals based on driving data.

[0152] In some embodiments, the backlight assembly 20 may further include a lamp board 30, which includes lamp beads 301 distributed in an array, at least one lamp bead is electrically connected to form a light-emitting unit group, and the light-emitting unit group is electrically connected to a driving end of the driving chip 202, and can be configured to emit light based on a driving signal.

[0153] In some embodiments, the backlight assembly 20 may further include a plurality of light bars, each of which includes a plurality of lamp beads 301 .

[0154] In some embodiments, the plurality of lamp beads 301 on the light bar are a string of lamp beads driven by the same driving signal.

[0155] In some embodiments, a string of light beads on a light strip is connected in series.

[0156] In other embodiments, a string of light beads on the light bar is connected in parallel.

[0157] In some embodiments, in the light emitting unit group, at least one lamp bead is connected in series to form a light string;

[0158] In other embodiments, in the light emitting unit group, at least one lamp bead is connected in parallel;

[0159] In other embodiments, in the light-emitting unit group, at least one lamp bead is connected in series to form a lamp string, and at least one lamp string is electrically connected in parallel.

[0160] Among them, the light string is a light string composed of lamp beads connected in series from left to right or from right to left, or a light string composed from top to bottom or from bottom to top, or a light string composed of lamp beads connected in series in a preset order (for example: rotating, bending, etc.).

[0161] Among them, the lamp beads can be composed of MiniLED, MicroLED, WLED, RGB-LED, GB-rLED or QLED (quantum dots).

[0162] In one embodiment, the display device 200 may include a power supply circuit 13, which is respectively coupled to at least one processor 250, the backlight assembly, and the display panel 10. The power supply circuit 13 may be configured to provide corresponding power signals to the at least one processor 250, the display panel 10, and / or the backlight assembly 20.

[0163] In some embodiments, the power supply circuit 13 is coupled to the power supply end of each light-emitting unit group in the backlight assembly 20 and can be configured to provide a backlight power supply signal VLED so that the light-emitting unit group emits light when it obtains the backlight power supply signal VLED and the driving signal provided by the driving chip 202.

[0164] In some embodiments, the driver chip 202 samples the supply voltage of the light-emitting unit group to determine the power supply status of the light-emitting unit group, including an undervoltage state or an overvoltage state. The power supply status is fed back to the at least one processor 250, so that the at least one processor provides a final feedback signal to the power supply circuit 13 based on the feedback signal. The power supply circuit 13 adjusts the supply voltage based on the final feedback signal.

[0165] In some embodiments, the driver chip 202 may transmit a feedback signal via a wire between its data output terminal Dout and the at least one processor 250 .

[0166] In other embodiments, the driver chip 202 may utilize its driving data transmission wires to transmit the feedback signal in reverse to at least one processor.

[0167] A schematic diagram of the physical structure of the backlight assembly 20 and the display panel 10 is shown in FIG3 . The display panel 10 is placed on the upper side of the backlight assembly, and the upper side of the display panel 10 can display images.

[0168] In some embodiments, backlight assembly 20 can include a backplate 407 , which can be configured as a substrate that provides support.

[0169] In some embodiments, the backlight assembly 20 may include a lamp board 30 , on which lamp beads are disposed, and may be configured to provide backlight.

[0170] In some embodiments, the backlight assembly 20 may include: a reflective sheet 404 , which may be configured to reflect backlight from the light panel toward the diffuser plate;

[0171] In some embodiments, the backlight assembly 20 may include: a bracket 403 , which may be configured to support the diffuser plate 402 , the membrane 401 , etc., to maintain an optical spacing between the light panel and the diffuser plate;

[0172] In some embodiments, the backlight assembly 20 may include: a film 401;

[0173] In some embodiments, the backlight assembly 20 may include: a diffuser plate 402;

[0174] The diaphragm 401 and the diffuser plate 402 may be configured to improve the reflective efficiency of the backlight generated by the backlight assembly, uniformly guide light, increase brightness and color saturation, and adjust the light so that the brightness distribution of the entire display panel is more uniform.

[0175] In some embodiments, the arrangement order of the components in the backlight assembly 20 from top to bottom is: diaphragm 401 , diffuser 402 , bracket 403 , reflector 404 , lamp board 30 , and backboard 407 .

[0176] In other embodiments, the backlight assembly 20 may further include a honeycomb panel 405 and a vibrator 406, which are placed between the light panel 30 and the back panel 407 and may be configured to drive the backlight assembly 20 and the display panel 10 to vibrate and produce sound based on a sound signal.

[0177] In some embodiments, taking a micro-LED display device as an example, a plurality of lamp boards 30 are provided in the backlight assembly 20. After being spliced ​​together, the plurality of lamp boards 30 jointly emit light to provide backlight to the display panel 10. Each lamp board 30 may include a plurality of light-emitting areas, and each light-emitting area (also called a partition) may include a plurality of micro lamp beads, which are micron-level lamp beads such as miniLED and microLED.

[0178] The light board 30 is electrically connected to the driving circuit, which may include one or more driving chips. The driving chip of each partition receives the processed backlight data sent by Bcon or Dcon, and drives the corresponding lamp beads to emit light based on the processed backlight data, thereby realizing local backlight control of the backlight component, that is, realizing Local dimming, thereby achieving more accurate regional light control and making the screen brightness more uniform and harmonious.

[0179] FIG. 4 is a schematic structural diagram of a backlight assembly 20 according to some embodiments.

[0180] In some embodiments, the backlight assembly 20 may include a plurality of lamp beads 301 distributed in an array. At least one electrically connected lamp bead forms a light emitting unit group. In some embodiments, the light emitting unit group is called a partition.

[0181] In some embodiments, the backlight assembly 20 may include a driving circuit 201. The driving circuit 201 may include a plurality of driving chips 202. The driving chips 202 are provided with a data input terminal DIN. The data input terminal DIN is coupled to at least one processor and may be configured to receive driving data.

[0182] The driver chip 202 is further provided with a power supply terminal VP connected to the power supply circuit 13 , and the power supply terminal VP can be configured to receive a power supply signal VCC;

[0183] The driver chip 202 is also provided with at least one driver end, which is electrically connected to the negative pole of the corresponding light-emitting unit group, and the positive pole of the light-emitting unit group is connected to the power supply circuit 13. The light-emitting unit group can be configured to obtain a power signal VLED from the power supply circuit 13, obtain a drive signal from the driver chip 202, and emit light based on the drive signal and the power signal.

[0184] To improve the display quality of a display device, the number of zones on the backlight assembly can generally be increased, thereby increasing the number of adjustable light-emitting unit groups within each unit area of ​​the backlight assembly. While providing the same brightness per unit area, at least one processor can adjust more light-emitting unit groups to achieve the target brightness. Adjusting the number of light-emitting unit groups increases the adjustment accuracy of the at least one processor, thereby improving the quality of the displayed image.

[0185] As the number of partitions increases, the size of individual lamp beads 301 can be reduced, and the bare lamp beads 301 can be mounted on the lamp board to increase the number of lamp beads 301 per unit area on the backlight assembly 20, thereby increasing the number of partitions and reducing the production cost of the backlight assembly 20. The lamp board equipped with lamp beads 301 can adapt to the increase in the number of partitions and improve wiring accuracy, with little difference in production cost.

[0186] As the number of partitions increases, the number of driver terminals of each driver chip 202 provided in the backlight assembly 20 or the number of driver chips 202 also increases, so that each driver chip 202 in the driver circuit 201 can meet the driving requirements of each partition. However, increasing the number of driver terminals of the driver chip 202 or the number of driver chips 202 significantly increases the production cost of the backlight assembly. Therefore, how to cost-effectively improve the driving capability of the driver circuit in the backlight assembly as the number of partitions increases has become a research focus.

[0187] To this end, some embodiments of the present application provide a control method for a display device and a display device, wherein the display device may include a display panel, a power supply circuit, at least one processor, a light board and a driving circuit, the driving circuit is provided with at least one driving end and multiple power supply ends, each driving end corresponds to multiple light-emitting unit groups, and the multiple light-emitting unit groups correspond to the multiple power supply ends respectively. When the driving circuit obtains driving data provided by at least one processor, power signals are output sequentially from the multiple power supply ends to supply power to the multiple light-emitting unit groups connected to each power supply end in turn, and then corresponding driving signals are output through each driving end to drive different light-emitting unit groups to generate corresponding light intensities. Based on the above connection relationship and control logic, the number of light-emitting unit groups driven by each driving end of the driving circuit increases exponentially. When the number of partitions on the light board of the display device increases, the driving requirements of the partitions can be met without adding a large number of driving ends and corresponding driving circuit structures, thereby achieving a low-cost improvement in the driving capability of the driving circuit in the backlight assembly.

[0188] The following embodiments of the present application are described in detail in conjunction with specific examples. The following specific examples can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0189] FIG5A is a schematic structural diagram of a display device in a display device provided in some embodiments of the present application. As shown in FIG5A , in some embodiments, the display device may include a power supply circuit 13 , which may be configured to provide a power signal;

[0190] In some embodiments, the display device may include at least one processor, which may be configured to obtain display data and backlight data, wherein the display data is data for controlling the rotation angle of liquid crystal molecules in the display panel, and the backlight data is data for controlling the backlight assembly to provide backlight.

[0191] In some embodiments, the at least one processor is configured to provide processed backlight data.

[0192] In some embodiments, at least one processor is configured to further output driving data corresponding to each light-emitting unit group based on backlight data, the driving data including current value and duty cycle; the current value corresponding to each light-emitting unit group is the same.

[0193] At least one processor adjusts the brightness of the corresponding light-emitting unit group in the backlight assembly by adjusting the duty cycle, wherein the larger the duty cycle, the brighter the brightness; the smaller the duty cycle, the lower the brightness.

[0194] Figure 43 is a dimming schematic diagram provided by the present application, including driving data corresponding to the four rows and five columns of light-emitting unit groups. The current value of each backlight sub-unit is the same, which is 70mA. The duty cycle of each backlight sub-unit is different. Among them, the brighter the brightness, the greater the duty cycle, and the darker the brightness, the smaller the duty cycle.

[0195] In the process of displaying different frames, at least one processor adjusts the current value accordingly based on different backlight data.

[0196] In some embodiments, the display device may include a backlight assembly 20 that may be configured to emit light based on the processed backlight data.

[0197] In some embodiments, the display device may include a backlight assembly 20 configured to emit light based on the processed backlight data.

[0198] In some embodiments, the backlight assembly 20 may further include a plurality of light bars, each of which includes a plurality of lamp beads 301 .

[0199] In some embodiments, the plurality of lamp beads 301 on the light bar are a string of lamp beads driven by the same driving signal.

[0200] In some embodiments, a string of light beads on a light strip is connected in series.

[0201] In other embodiments, a string of light beads on the light bar is connected in parallel.

[0202] In some embodiments, the backlight assembly 20 includes a lamp board including a plurality of lamp beads 301 distributed in an array.

[0203] In some embodiments, at least one lamp bead 301 is electrically connected to form a light-emitting unit group.

[0204] In some embodiments, a single lamp bead 301 constitutes a light-emitting unit group;

[0205] In some embodiments, at least two lamp beads 301 are electrically connected in series to form a light-emitting unit group;

[0206] In some embodiments, at least two lamp beads 301 are electrically connected in series to form at least one lamp string, and at least one lamp string is electrically connected in parallel to form a light-emitting unit group.

[0207] In the above embodiment, at least two lamp beads electrically connected in series or in parallel can be lamp beads arranged in rows; they can also be lamp beads arranged in columns; they can also be lamp beads arranged in a preset order, and the lamp beads can form regular or irregular patterns.

[0208] In some embodiments, the backlight assembly 20 may include a driving circuit 201;

[0209] In some embodiments, the driving circuit 201 is provided with a plurality of power supply terminals;

[0210] In some embodiments, the driving circuit 201 is provided with a power supply terminal VP;

[0211] In some embodiments, the driving circuit 201 is provided with at least one driving terminal;

[0212] In some embodiments, the driving circuit 201 is provided with a data input terminal DIN;

[0213] In some embodiments, the power supply terminal VP is coupled to the power supply circuit 13 and may be configured to obtain a power signal obtained by the power supply circuit 13 .

[0214] In the circuit structure shown in FIG5A , each data input terminal DIN is coupled to at least one processor, each data input terminal DIN corresponds to an address information, and at least one processor can be configured to transmit corresponding driving data to each data input terminal DIN based on the address information.

[0215] In some embodiments, each output terminal of the driving circuit 202 corresponds to and is electrically connected to multiple light emitting unit groups. The multiple light emitting unit groups correspond to multiple power supply terminals, where the number of power supply terminals is determined by the number of light emitting unit groups corresponding to each driving terminal.

[0216] In some embodiments, the number of power supply terminals is greater than or equal to the number of light emitting unit groups electrically connected to each driving terminal, and the power supply terminal can provide a power signal to each light emitting unit group accordingly;

[0217] In other embodiments, each power supply terminal is electrically connected to the input terminal of the gating device, and the output terminal of the gating device is electrically connected to the light-emitting unit group electrically connected to each driving terminal, wherein the total number of output terminals of the gating device electrically connected to each power supply terminal is greater than or equal to the number of light-emitting unit groups electrically connected to each driving terminal.

[0218] The driving circuit 201 can be configured to obtain power signals and driving data, and based on the driving data, sequentially output power signals from the power supply end and output corresponding driving signals from the driving end to drive the light strings corresponding to the power supply end and the driving end to emit light.

[0219] FIG6 is a flow chart of a control method for a display device exemplarily provided in this application. As shown in FIG6 , the method may include:

[0220] S101. At least one processor outputs driving data.

[0221] S102 , based on the driving data, the driving circuit sequentially outputs power signals from the power supply end and outputs corresponding driving signals from the driving end, thereby driving the light-emitting unit groups corresponding to the power supply end and the driving end to emit light.

[0222] FIG8 is a flow chart of a control method for a display device provided by the present application. As shown in FIG8 , the method includes:

[0223] S201: At least one processor obtains backlight data.

[0224] S202. At least one processor outputs driving data corresponding to each light-emitting unit group to a driving chip based on backlight data. The driving data includes a current value and / or a duty cycle. The current values ​​of each light-emitting unit group electrically connected to the driving end are the same.

[0225] S203, the driver chip obtains the power signal provided by the power supply circuit, and based on the driving data, sequentially outputs the power signal from the power supply end and the corresponding driving signal from the driving end, driving the light-emitting unit group corresponding to the power supply end and the driving end to emit light.

[0226] Taking FIG. 5A as an example, the control method of the display device provided in this application is further explained.

[0227] In some embodiments, the driving circuit 201 may include a plurality of driving chips 202 , each of which is provided with at least one driving terminal.

[0228] In some embodiments, each driver chip 202 is provided with a plurality of power terminals, and the number of the light emitting unit groups connected to the driver terminals is less than or equal to the number of the power terminals.

[0229] In some embodiments, when the number of the plurality of light emitting unit groups connected to the driving end is the same as the number of the power supply ends, the plurality of light emitting unit groups and the plurality of power supply ends are electrically connected correspondingly.

[0230] In some embodiments, when the number of the driving end connected to at least one light-emitting unit group is smaller than the number of the power supply end, the at least one light-emitting unit group may be electrically connected to a corresponding number of the power supply end based on a preset light-emitting logic.

[0231] The preset light-emitting logic is a light-emitting sequence of a plurality of light-emitting unit groups corresponding to the driver chip, and the light-emitting unit groups are connected to corresponding driving terminals and power terminals based on their positions in the light-emitting sequence.

[0232] In some embodiments, the driving end may be left floating and not connected to the light emitting unit group.

[0233] In some embodiments, the light emitting unit group can be electrically connected to multiple power terminals at the same time. When the multiple power terminals supply power, the light emitting unit group can emit light according to the corresponding driving signal obtained during the power supply period of one power terminal.

[0234] In some embodiments, the driving end is electrically connected to at least two light-emitting unit groups. In the example shown in Figure 5A, the driving circuit 201 includes three driving chips 202, and each driving end of each driving chip 202 is electrically connected to two light-emitting unit groups: a first light-emitting unit group and a second light-emitting unit group, wherein the first and second are only used to distinguish different light-emitting unit groups and have no order meaning.

[0235] In some embodiments, the driver chip 202 is provided with a power supply terminal V1 and a power supply terminal V2, the power supply terminal V1 is electrically connected to the first light emitting unit group, and the power supply terminal V2 is electrically connected to the second light emitting unit group;

[0236] In other embodiments, each driver chip 202 includes a power supply terminal V1, which is electrically connected to an input terminal of a two-to-one selector. The two-to-one selector includes an input terminal and two output terminals, with the two output terminals being electrically connected to the first light-emitting unit group and the second light-emitting unit group, respectively. At any given time, only one output terminal of the two-to-one selector is electrically connected to the input terminal.

[0237] In some embodiments, the driver chip is provided with 4 driver ends, and the driver chip can drive up to 8 light-emitting unit groups, each driver end is electrically connected to the driver ends of two light-emitting unit groups, and the power supply ends of the two light-emitting unit groups are electrically connected to the corresponding power supply ends.

[0238] In some embodiments, the light-emitting unit group may include a lamp string composed of multiple lamp beads electrically connected in series, the driving end is electrically connected to the negative poles of the two lamp strings, and the positive poles of the two lamp strings are electrically connected to the corresponding two power supply ends or the two output ends of the two-to-one selector.

[0239] In this embodiment, when the driver chip drives 8 light-emitting unit groups, the driver chip selects a row of light-emitting unit groups that need to emit light based on the power supply end for its corresponding two rows and four columns of light-emitting unit groups, and drives the row of light strings based on the driving signals provided by different driving ends in accordance with the corresponding relationship with the driving ends to generate brightness corresponding to the driving signal, thereby realizing the control of each light string by the driver chip.

[0240] In some embodiments, the plurality of driving chips 202 in the driving circuit 201 are distributed in an array. When the display panel is scanned row by row, the plurality of driving chips 202 driving the plurality of light emitting unit groups in the same row form a driving group.

[0241] In some embodiments, the data input terminals of the multiple driver chips 202 in each driver group are respectively electrically connected to the output terminals of at least one processor. As shown in FIG5A , each driver chip 202 is provided with address information, which may include a physical address or a memory address. At least one processor is respectively electrically connected to the data input terminals of each driver chip 202 through a data line. At least one processor broadcasts data including address information to the data line. The driver chip 202 corresponding to the address information obtains driving data from the data line to drive its corresponding light-emitting unit group to emit light.

[0242] In one embodiment, the driver chips 202 in the driver group are electrically connected in series based on the data line, and the driver chip 202 is also provided with a data output terminal DOUT. As shown in FIG5B , the data input terminal DIN of the first driver chip 202 is electrically connected to the output terminal of at least one processor, and the data input terminal DIN of the other driver chips 202 is electrically connected to the data output terminal DOUT of the previous driver chip 202.

[0243] In some embodiments, the driving data may further include a memory address of each driving chip, and the driving chip obtains the data end corresponding to its memory address from the driving data based on its memory address;

[0244] In other embodiments, the size of the data ends obtained by each driver chip is the same, and the driver chips read data segments of the same data length from the driving data one by one. After the reading of their data segments is completed, the remaining driving data is automatically moved forward to the reading position, so that the subsequent driver chips can read the remaining data segments of the driving data from the reading position.

[0245] When there are at least two drive groups, the first drive chip 202 in each drive group is provided with a physical address as the physical address of the drive group in which it is located. When at least one processor transmits drive data, the physical address of each drive group is provided in the drive data. Each drive group can simultaneously obtain the drive data transmitted by at least one processor. When the physical address of the drive data is consistent with its corresponding physical address, the drive data is transmitted one by one along the arrangement order of the drive chips 202 in the drive group to ensure the accuracy of data transmission.

[0246] In some embodiments, when the driver chip 202 has multiple power supply terminals, a power switch is provided between the power supply terminal and each power supply terminal. The driver chip controls the output of the power signal of each power supply terminal by controlling the conduction of the power switch.

[0247] In some embodiments, the driver chip 202 may include a control unit 2021 and multiple power switches, and the multiple power switches correspond to multiple power supply terminals: the first ends of the multiple power switches are electrically connected to the power supply terminal VP of the driver chip, and the second ends of the multiple power switches are respectively coupled to the corresponding power supply terminals.

[0248] FIG9 is a schematic diagram of the structure of a driver chip 202 according to some embodiments. As shown in FIG9 , the driver chip 202 may include a first power switch K1 and a second power switch K2. The second end of the first power switch K1 is electrically connected to the power supply terminal V1, and the second end of the second power switch K2 is electrically connected to the power supply terminal V2. The first ends of the first power switch K1 and the second power switch K2 are coupled to the power supply terminal VP of the driver chip 202.

[0249] In some other embodiments, the first terminals of the plurality of power switches are electrically connected to the power terminal VP, and the second terminals of the plurality of power switches are correspondingly coupled to the plurality of power supply terminals.

[0250] FIG10 is a schematic diagram of the structure of a driver chip 202 according to some embodiments. As shown in FIG10 , the driver chip 202 may include a first power switch K1 and a second power switch K2. The second end of the first power switch K1 is coupled to a power supply terminal V1, and the second end of the second power switch K2 is coupled to a power supply terminal V2. The first ends of the first power switch K1 and the second power switch K2 are electrically connected to a power supply terminal VP of the driver chip 202.

[0251] In some embodiments, the power switch may include a high-side switch, a first end of which serves as an input end of the power switch, a second end of which serves as an output end of the power switch, and a control end of which serves as a control end of the power switch.

[0252] In some embodiments, the high-side switch may be a transistor or a field-effect transistor.

[0253] The control unit 2021 is connected to the control terminals of the plurality of power switches respectively.

[0254] In some embodiments, when the driver chip 202 may further include a multi-select selector, the power supply terminal VP of the driver chip 202 is electrically connected to the input terminal of the multi-select selector, the multiple output terminals of the multi-select selector are electrically connected to the first terminals of the multiple power switches, and the control terminal of the multi-select selector is electrically connected to the control unit 2021.

[0255] The control unit 2021 may be further configured to drive each output terminal of the multiple-to-one gate to be connected to the input terminal in a preset gate sequence based on the driving data.

[0256] In some embodiments, the multi-select selector can be equivalent to multiple power switches, and the input end of the multi-select selector is electrically connected to the power supply end VP of the driver chip 202, and each output end is electrically connected to the corresponding power supply end.

[0257] The driver chip 202 can be configured to receive the power signal VLED provided by the power supply circuit 13 from the power supply terminal and sequentially control the multiple power switches to conduct so that the multiple power supply terminals sequentially output power signals. It is worth noting that the multiple power supply terminals cannot output power signals at the same time.

[0258] In some embodiments, the driver chip 202 may be configured to obtain driving data from at least one processor 250 and determine to output a control signal to each power switch based on the driving data.

[0259] In some embodiments, the driving data obtained by the driving circuit 201 may include multiple pulse signal segments, and the multiple pulse signal segments correspond to multiple power supply terminals. The driving circuit 201 may be configured to output a power signal from a corresponding power supply terminal within a power supply period corresponding to the pulse signal segment based on the multiple pulse signal segments; the display cycle may include multiple power supply periods, and the multiple power supply periods do not intersect with each other; the multiple pulse signal segments correspond to multiple power supply periods, and the multiple power supply periods correspond to multiple power supply terminals;

[0260] In each power supply period, a driving signal is output based on the pulse signal segment to drive the light-emitting unit group electrically connected to the driving end to emit light.

[0261] The driver chip adjusts the conduction state of each power switch according to the acquired state of the pulse signal segment, thereby adjusting the power supply state of each power supply end.

[0262] Taking the example of a driver chip 202 having two power supply terminals, the driving data obtained by the driver chip is a waveform diagram shown in Figure 19. The control unit 2021 outputs a control signal based on the rising edge state of the pulse signal obtained by it, that is, when the control unit obtains the rising edge of the first pulse signal, it outputs the conduction control signal of the power switch connected to the power supply terminal V2, so that the power switch is turned on, and the power signal VLED obtained by the power supply terminal of the driver chip is output from the power supply terminal V2. Until the control unit obtains the rising edge of the second pulse signal, it stops outputting the conduction control signal to the power switch connected to the power supply terminal V2, and outputs the conduction control signal to the power switch connected to the power supply terminal V1, so that the power signal VLED obtained by the power supply terminal of the driver chip is output from the power supply terminal V1.

[0263] In some embodiments, a frame display period may include multiple pulse periods, and the pulse period may include power supply periods corresponding to multiple light-emitting unit groups.

[0264] In some embodiments, the pulse periods are different so as to adjust the electric signal corresponding to the driving process in periods of different lengths.

[0265] In some embodiments, the pulse periods are the same to simplify the driving process;

[0266] In some embodiments, a delay register is provided in the driver chip 202. After the driver chip obtains the software effectiveness command, the delay register performs timing. When the statistical time reaches the corresponding pulse delay time, the driver chip opens the corresponding channel; when the statistical time has not reached the corresponding pulse delay time, the driver chip does not open the corresponding channel.

[0267] In some embodiments, the delay register is clocked based on a clock signal;

[0268] In other embodiments, the delay register performs timing based on counting the number of pulses output by the driving end of the driving chip.

[0269] In some embodiments, the driver chip 202 may be further configured to obtain multiple pulse delay times of the driver end; the pulse delay time is the time difference between the start time of each pulse signal segment output by the target driver end within the pulse cycle and the start time of the pulse cycle;

[0270] Based on the pulse delay time, a plurality of power supply time periods are determined.

[0271] In some embodiments, the driver chip 202 can also be configured to provide multiple pulse signal segments from the target driver end based on the driving data within multiple power supply time periods of each pulse cycle to make the corresponding light-emitting unit group emit light; the pulse signal segments correspond to multiple power supply time periods, and each pulse signal segment corresponds to multiple light-emitting unit groups connected to each power supply end.

[0272] In some embodiments, the driver chip 202 may be configured to determine the duty cycle and amplitude of the pulse signal segment output by the target driver end during each power supply period based on the driving data; the driving data may include the current value and the duty cycle;

[0273] During the power supply period, a corresponding pulse signal segment is output from the target driving end based on the light-emitting duty cycle and amplitude.

[0274] In some embodiments, the driver chip 202 may include a first register, which may be configured to store a current value;

[0275] In some embodiments, the driver chip 202 may include a second register configured to store a duty cycle.

[0276] When the driving chip 202 outputs a pulse signal segment, the waveform of the driving signal output by its target driving end is shown in Figure 19. Taking the case where its driving end is electrically connected to two light-emitting unit groups as an example, the two pulse signals output by the target driving end are two pulse signals output by the driving chip during a scan process. The first pulse signal is a pulse signal obtained by the light-emitting unit group electrically connected to the first power supply end and the target driving end when the first power supply end supplies power, and the second pulse signal is a pulse signal obtained by the light-emitting unit group electrically connected to the second power supply end and the target driving end when the second power supply end supplies power.

[0277] In some embodiments, the driver chip 202 may include a pulse number register, which may be configured to count the number of pulse outputs.

[0278] When the driver chip 202 determines that the pulse statistics number reaches the preset pulse number, it turns off the driving channel.

[0279] In some embodiments, the driver chip 202 may include a third register, which may be configured to adjust the output current value of the driver chip to the current value of the drive signal of the second drive channel when the number of pulses output by the first drive channel counted by the pulse number register reaches a preset pulse number.

[0280] The driver chip 202 cyclically provides multiple sets of pulse signals during multiple scanning processes, so that the two light-emitting unit groups electrically connected to the target driving end thereof cyclically emit light.

[0281] The wave generation conditions of other driving ends of the driving chip 202 are similar to the wave generation conditions of the target driving end, and will not be described in detail here.

[0282] In some embodiments, the driving signal pulse signals output by each driving chip in the backlight assembly during a frame of image display have the same period, the same duty cycle, and the same amplitude. Then, the driving end of each driving chip adjusts the number of pulses output within a frame of display period based on the driving data to adjust the luminous brightness of the light-emitting unit group it drives.

[0283] In some embodiments, the driver chip 202 may be further configured as:

[0284] When the current value or the voltage value is not within the corresponding preset range, the state of the light emitting unit group driven by it is sampled; the state of the light emitting unit group may include an undervoltage state or an overvoltage state.

[0285] Feedback status to the processor.

[0286] In some embodiments, the driver chip 202 may be further configured to sample the state of the light emitting unit group when the current value is less than a preset current value;

[0287] In some embodiments, the driver chip 202 may be further configured to sample the state of the light-emitting unit group when the voltage value is greater than a preset voltage value.

[0288] When the driving chip 202 drives the plurality of light emitting unit groups, the plurality of light emitting unit groups electrically connected to the driving chip 202 correspond to the plurality of liquid crystal molecule groups on the display panel; each liquid crystal molecule group may include a plurality of liquid crystal molecules displayed simultaneously on the display panel.

[0289] The scanning direction of the liquid crystal molecule groups on the display panel may include a first scanning direction and a second scanning direction. The multiple liquid crystal molecule groups arranged along the first scanning direction are displayed based on the same phase, and the multiple liquid crystal molecule groups arranged along the second scanning direction are displayed based on different phases. For example, when the liquid crystal molecule groups are scanned row by row from left to right and from top to bottom, the first scanning direction is from left to right, and the second scanning direction is from top to bottom. When the liquid crystal molecules are scanned column by column from top to bottom and from left to right, the first scanning direction is from top to bottom, and the second scanning direction is from left to right.

[0290] The plurality of light-emitting element groups electrically connected to each driver chip 202 are distributed based on the first scanning direction and the second scanning direction of the plurality of liquid crystal molecule groups. There are various configurations for connecting the driver chip 202 and the light-emitting element groups, as well as for arranging the light-emitting element groups on the backlight assembly 20. These configurations are explained below using various embodiments.

[0291] In some embodiments, the plurality of light emitting unit groups electrically connected to each driving chip 202 are arranged in a plurality in the first scanning direction and in a single light emitting unit group in the second scanning direction.

[0292] In some embodiments, the display panel is scanned row by row, and all the light-emitting unit groups driven by the driver chip 202 are arranged in a row.

[0293] In some embodiments, the display panel is scanned column by column, and all the light-emitting unit groups driven by the driver chip 202 are arranged in one column.

[0294] According to the number of power supply terminals and the number of driving terminals set by the driving chip 202, all the light-emitting unit groups electrically connected to the driving chip 202 are divided into multiple groups, and the negative pole of each light-emitting unit group is connected to the same driving terminal. In each light-emitting unit group, the positive pole of each light-emitting unit group is connected to each power supply terminal accordingly.

[0295] FIG11A is a schematic diagram illustrating the connection relationship between a driver chip 202 and a light-emitting unit group. As shown in FIG11A , the driver chip 202 is electrically connected to eight light-emitting unit groups. The driver chip 202 is provided with four driver terminals and two power supply terminals. The light-emitting unit groups are divided into two groups. The negative electrodes of the two light-emitting unit groups are connected to the same driver terminal, and the positive electrodes of the two light-emitting unit groups are connected to two power supply terminals, respectively. Different driver terminals correspond to different light-emitting unit groups. For the convenience of description below, the two light-emitting unit groups in the same group are set as the first light-emitting unit group and the second light-emitting unit group, respectively. The first light-emitting unit group is connected to the power supply terminal V1, and the second light-emitting unit group is connected to the power supply terminal V2.

[0296] When the driver chip 202 is driving, upon obtaining driving data for the second light-emitting element group in each light-emitting element group, the driver chip 202 outputs a power signal from the power supply terminal V1 based on the data, and outputs corresponding driving signals from each driver terminal, so that the second light-emitting element group in each light-emitting element group emits light based on the driving signal. When the driver chip 202 obtains driving data for the first light-emitting element group in each light-emitting element group, the driver chip 202 outputs a power signal from the power supply terminal V2 based on the data, and outputs corresponding driving signals from each output terminal, so that the first light-emitting element group in each light-emitting element group emits light based on the driving signal.

[0297] The circuit connection relationship provided in this embodiment can keep the original row scanning or column scanning mode of the backlight component unchanged. Only in the process of regulation of each driver chip 202, the luminous effect of the luminous process of a light-emitting unit group electrically connected to a driver end in the related technology is distributed to two light-emitting unit groups. Compared with the luminous effect in the related technology, the luminous regulation process of this embodiment is more precise.

[0298] In other embodiments, the number of the plurality of light emitting unit groups electrically connected to each driving chip arranged in the second scanning direction is at least two, and the number of the at least two arranged groups is less than or equal to the number of the power supply terminals.

[0299] The number of the plurality of light emitting unit groups electrically connected to each driving end arranged in the second scanning direction is one.

[0300] In some embodiments, the display panel is scanned row by row, all light-emitting unit groups driven by the driver chip 202 are arranged in multiple rows, and each driving end is electrically connected to multiple light-emitting unit groups arranged in a row;

[0301] In some embodiments, the display panel is scanned column by column, all light emitting unit groups driven by the driver chip 202 are arranged in multiple columns, and multiple light emitting unit groups electrically connected to each driving end are arranged in one column.

[0302] The plurality of light emitting unit groups connected to the driver chip 202 are divided into multiple groups according to the division method of the previous embodiment. The connection method between each light emitting unit group and the driver chip 202 is the same as that of the previous embodiment and will not be repeated here.

[0303] Regarding the arrangement of each light-emitting unit group, in one case, each light-emitting unit group in each light-emitting unit group is arranged in a row, and in another case, each light-emitting unit group in each light-emitting unit group is arranged in at least two rows. Since the negative pole of a group of light-emitting unit groups is connected to the same driving end, each light-emitting unit group can emit light in the same time period. More specifically, in each light-emitting unit group, each light-emitting unit group cyclically emits light in a preset order within the same time period until the end of the time period.

[0304] FIG11B is a schematic diagram illustrating an exemplary arrangement of light-emitting cell groups. In FIG11B , a group of light-emitting cell groups may include two light-emitting cell groups, which are arranged in a row of a backlight assembly. When driving the light-emitting cell groups, the driver chip 202 may control multiple light-emitting cell groups in the first row to emit light during the same period, and control multiple light-emitting cell groups in the second row to emit light during the same period. When multiple rows of liquid crystal molecules in the display panel are scanned row by row from top to bottom, the start time of the light-emitting period of the first row is earlier than the start time of the light-emitting period of the second row. The delay between the start time of the second row and the start time of the first row is the scanning delay between the second row of liquid crystal molecules and the first row of liquid crystal molecules. When the backlight assembly needs to perform black insertion based on the response delay of the liquid crystal molecules, the delay is the sum of the scanning delay and the insertion time.

[0305] The circuit connection relationship provided in this embodiment can be controlled by a group of driver chips to control multiple rows of light-emitting unit groups to provide backlight to multiple rows of liquid crystal molecules in the display panel row by row, or by a group of driver chips to control multiple columns of light-emitting unit groups to provide backlight to multiple columns of liquid crystal molecules in the display panel column by column, which simplifies the processor's calculation and control of the row-by-row delay or column-by-column delay of multiple groups of driver chips.

[0306] In other embodiments, the number of the plurality of light emitting unit groups electrically connected to each driving end in the second scanning direction is at least two, and the number of the at least two light emitting unit groups is less than or equal to the number of the power supply ends.

[0307] In some embodiments, the display panel is scanned row by row, all the light-emitting unit groups driven by the driver chip 202 are arranged in multiple rows, and the light-emitting unit groups electrically connected to the driving ends are arranged in multiple rows.

[0308] In some embodiments, the display panel is scanned column by column, all light-emitting unit groups driven by the driver chip 202 are arranged in multiple columns, and the light-emitting unit groups electrically connected to each driving end are arranged in multiple columns.

[0309] FIG11C is a schematic diagram illustrating another exemplary arrangement of light-emitting element groups. In FIG11C , two light-emitting element groups within a light-emitting element group are arranged in two rows. The two rows of light-emitting element groups connected to the driver chip 202 emit light during the same period. The period during which the two rows of light-emitting element groups emit light corresponds to the scanning period of the two corresponding rows of liquid crystal molecules.

[0310] The circuit connection relationship provided in this embodiment utilizes multiple rows of light-emitting unit groups to simultaneously provide backlight to multiple rows of liquid crystal molecules in the display panel, or utilizes multiple columns of light-emitting unit groups to simultaneously provide backlight to multiple columns of liquid crystal molecules in the display panel. The control logic is simpler than the aforementioned embodiment and is suitable for display devices that do not have very high requirements for image quality.

[0311] In the above three connection diagrams of the driving chip 202 and the light-emitting unit group, there is always a situation where wires are jumped. In one case, two wires transmitting power signals are jumped, and in the other case, a wire transmitting power signals and a wire transmitting driving signals are jumped.

[0312] Figure 12 shows the positional relationship of jumper wires on a light board. When a horizontal wire needs to be connected to a vertical wire A, the vertical wire is divided into two segments, B1 and B2, by wire A. Two solder pads are then provided on either side of wire A, connected to wires B1 and B2, respectively. In related art, jumper devices are typically connected to the two solder pads to address the issue of wire jumpering on light boards. However, due to the large number of LEDs and light-emitting unit groups in light boards based on miniLEDs or microLEDs, a large number of jumper wires are required, resulting in high manufacturing costs for the light boards.

[0313] This application provides a method for bridging two wires. The following describes the method for bridging two wires. Wire A is defined as the wire to be bridged, and wires B1 and B2 are the bridge wires to be connected via bridge wire A. In one embodiment, the two wires are copper wires. An insulating layer is applied to the copper wire to be bridged, and a conductive layer is applied over the insulating layer to provide electrical continuity between the bridge wires.

[0314] In some embodiments, the conductive layer is a copper paste.

[0315] In other embodiments, the conductive layer is solder paste.

[0316] For printed circuit boards with wire jumpers, with the side where the device pins are soldered as the upper side, the board can include copper wires and insulation layers from bottom to top. The copper wires can include jumper wires and jumpered wires, which are located on the same layer of the printed circuit board.

[0317] The specific arrangement of the insulating layer and the conductive layer in the bridging area is explained below.

[0318] In some embodiments, the insulating layer is coated on the outside of the jumpered wire, and the conductive layer is coated on the side of the insulating layer away from the jumpered wire.

[0319] In some embodiments, the insulating layer and the conductive layer within the jumper region are arranged as shown in FIG12 , where the insulating layer C is completely coated on the upper side of the jumper conductor A along the routing direction of the jumper conductor A, and the width of the insulating layer C is greater than the width of the jumper conductor A. A conductive layer E is then coated on top of the insulating layer C, and the conductive layer E connects to the corresponding pads D1 and D2 of the jumper conductors B1 and B2.

[0320] In some embodiments, solder resist ink is applied to the wires of the printed circuit board to protect them and prevent solder paste from affecting them during soldering. The printed circuit board is desoldered on both sides of the jumpered wires and at the end points of the jumpered wires, exposing the end points of the jumpered wires, which serve as solder pads.

[0321] In some embodiments, solder resist ink is coated on the jumpered wires to serve as an insulating layer.

[0322] In some embodiments, the conductive layer covers the two pads and the insulating layer between the pads.

[0323] In some embodiments, with the side where the device pins are welded as the upper side, when producing a printed light board, a conductive layer, an insulating layer and a wire are stacked from bottom to top in the jumper area, the insulating layer wraps the jumper wire A, and the conductive layer is connected to the jumper wires placed on both sides of the jumper wire.

[0324] In some embodiments, the insulating layer and the conductive layer in the jumper region are arranged as shown in FIG13 , wherein the insulating layer C is completely coated on the upper side of the jumper conductor A along the routing direction of the jumper conductor A. An adsorbent material is coated on the insulating layer C, and the conductive layer E is coated on the adsorbent material. The adsorbent material is coated on the area D3, and the adsorbent material is an insulating material.

[0325] In some embodiments, the adsorbent material is applied along at least one predetermined cross-over path.

[0326] The coating area D3 of the adsorption material coated along a preset bridging path is shown in FIG13 ;

[0327] The coating area D3 of the adsorption material along a plurality of predetermined cross-linking paths (eg, two) is shown in FIG. 15 .

[0328] In some embodiments, the jumper wire B1 is provided with a pad D1 at one end close to the jumpered wire A, and the jumper wire B2 is provided with a pad D2 at one end close to the jumpered wire A. The area where the pad is located may include a first exposed area and a second exposed area, and one end of the adsorption material covers the first exposed area of ​​the corresponding pad.

[0329] In some embodiments, the conductive layer E is further coated on the second exposed area.

[0330] When the conductive layer E is made of solder paste, the solder paste is heated and soldered onto the second exposed areas corresponding to the two pads and the adsorption material, so that a path is formed between the jumper wires B1 and B2 after the solder paste melts.

[0331] The adsorption material not only increases the solder paste coating amount in region D3 but also increases the coating area, thereby reducing the impedance of the bridging region. Therefore, the larger the surface area of ​​the adsorption material, the greater the solder paste coating amount. Therefore, the adsorption material coating area D3 shown in Figure 15 is larger than the adsorption material coating area shown in Figure 13 , and the coating area is also larger. With a larger solder paste coating amount, the impedance of the bridging region shown in Figure 15 is smaller than that of the bridging region shown in Figure 13 .

[0332] In some embodiments, the conductive layer E is further coated on the insulating layer surrounding the adsorption material, so that the width of the conductive layer E is greater than the width of the pad, which helps to increase the amount of solder paste coated between the two pads.

[0333] The conductive layer E has a width direction perpendicular to the connection direction between the two pads, and the width direction of the pads is consistent with the width direction of the conductive layer E.

[0334] In some embodiments, solder resist ink is not printed on the lower side of the adsorption area within the coating area D3, so that the adsorption material is in direct contact with the copper foil or the plate body on the printed lamp board to increase the adhesion of the adsorption material, thereby increasing the adhesion of the conductive layer on the printed lamp board.

[0335] If there is only one coating area D3 within the jumper region, the insulation layer provided on the jumper conductor A can be divided into three insulating coating areas C1, D3, and C2 along the routing direction of the conductor. Solder resist ink can be applied to insulating coating areas C1 and C2. The distribution of the insulating coating areas can be shown in an example in FIG14 .

[0336] When there are multiple coating areas D3 in the bridging area, the areas coated with solder resist ink and the areas coated with adsorption material are spaced apart.

[0337] Taking the jumper region with two coating regions D3 as an example, the distribution of coating regions is explained. As shown in Figure 15, within the jumper region, along the top-to-bottom routing direction of the jumpered conductor A, there are five insulating coating regions C1, D3, C3, D3, and C2. Solder resist ink can be applied to insulating coating regions C1, C3, and C2, while adsorption material can be applied to insulating coating region D3.

[0338] In some embodiments, the insulating layer and the conductive layer in the jumper region are arranged as shown in FIG16 , wherein the insulating layer C is completely coated on the upper side of the jumper wire A along the routing direction of the jumper wire A. An adsorbent material is coated on the insulating layer C. The adsorbent material is a conductive material and provides electrical connection between the jumper wires B1 and B2.

[0339] In some embodiments, the jumper wire B is provided with a pad D1 at one end close to the jumpered wire A, and the jumper wire B2 is provided with a pad D2 at one end close to the jumpered wire A, and both ends of the adsorption material cover the corresponding pads.

[0340] In some embodiments, when the first jumper wire B1 and the second jumper wire B2 are not arranged in the same row, the coating direction of the wire layer is the direction of the straight line connecting the first pad D1 and the second pad D2.

[0341] In some embodiments, the adsorption material is coated according to a set coating position during the light board printing process, and the adsorption material is solidified through a curing operation.

[0342] In some embodiments, during the lamp panel welding process, a conductive layer is printed on the adsorption material, and the conductive layer is attached to the adsorption material through the original heating welding process.

[0343] The above-mentioned wire jumper method simplifies the subsequent circuit board processing cost without significantly increasing the cost, so as to realize the circuit connection method of the backlight assembly provided by the present application.

[0344] More specifically, on a printed circuit board, the signals transmitted by the wires are different, and the corresponding wire widths are also different. Generally, the width of the wire transmitting power is greater than the width of the wire transmitting the driving signal.

[0345] The following explains the wire connection relationship between the light emitting unit groups and the driver chip by taking an example in which a driver chip including four driver terminals and two power supply terminals drives eight light emitting unit groups.

[0346] In the wire jumper schematic diagram shown in Figure 11A, the horizontal wires are wires for transmitting power supply signals for multiple light-emitting unit groups, and the vertical wires are wires for transmitting power supply signals for a single light-emitting unit group. On the basis of ensuring stable transmission of electrical signals, the horizontal wires are thicker than the bus wires to save the printing cost of the wires.

[0347] In this case, the narrower wire (longitudinal wire) can be determined as the jumpered wire, and the wider wire (transverse wire) can be determined as the jumper wire. Since the width of the jumpered wire is narrower, the distance between the pads on both sides of the jumpered wire is smaller, so less copper paste is used during printing, which can reduce the printing cost of the copper paste.

[0348] Because copper paste has a high impedance, using copper paste to connect power-transmitting wires has little effect on the current flowing through them. However, if copper paste is used to connect drive signal wires, the copper paste's impedance may significantly reduce the drive signal's current, leading to abnormalities during the drive process.

[0349] In the wire jumper schematic diagram shown in Figure 11B, the horizontal wire is a wire that transmits the power supply signals of multiple light-emitting unit groups, the first and second vertical wires from the left are wires that transmit the power supply signals of multiple light-emitting unit groups, and the remaining vertical wires are wires that transmit the power supply signals of a single light-emitting unit group; the width of the first and second wires from the left is equal to the width of the horizontal wire, and the width of the horizontal wire is greater than the width of the remaining vertical wires.

[0350] For the jumpering of two wires of the same width, any one wire can be selected as the jumpered wire and the other wire can be used as the jumper wire. Regardless of which wire is used as the jumper wire, the corresponding PCB manufacturing cost is the same, and the impedance effect of the coated copper paste on the jumper wire is the same.

[0351] For the jumpering of two wires of different widths, the jumpering is performed according to the jumpering method shown in Figure 11A. The jumpering method of the jumper point wire can be referred to as shown in Figure 17. The longitudinal wire is used as the jumper wire A, and an insulating layer is coated on it. The transverse wires B2 and B1 are used as jumper wires, and copper paste is coated between the pad D2 connected to the transverse wire B2 and the pad D1 connected to the transverse wire B1.

[0352] In the wire jumper diagram shown in FIG11C , the horizontal wires are wires that transmit power supply signals for multiple light-emitting unit groups, and the vertical wires are wires that transmit power supply signals for a single light-emitting unit group. Each vertical wire jumps over a second horizontal wire, and the jumper wire diagram is shown in FIG17 . The jumper connection method for the jumper point has been explained in the embodiment shown in FIG11B and will not be repeated here.

[0353] The following explains a method for controlling a backlight assembly in a display device. Figure 18 is a schematic diagram of the waveform of drive data output by a processor for the backlight assembly shown in Figure 4, according to related art. As shown in Figure 18, in response to the frame start signal Vsync1, the processor determines the delay duration of the light-emitting unit group driven by the driver chip, thereby determining the light-emitting period of the light-emitting unit group. During the light-emitting period, the processor obtains backlight data from the obtained display data and generates drive data based on the backlight data.

[0354] In some embodiments, the driving data may include a pulse signal segment, and the pulse signal segment may include a plurality of continuous pulse signals, each pulse signal having the same pulse period. The processor determines the amplitude and duty cycle of the pulse signal segment based on the backlight data.

[0355] Each driving chip in the backlight assembly obtains driving data from the processor, and generates a driving signal based on the driving data to drive the light-emitting unit group to emit light.

[0356] In some embodiments, when the driving data may include a pulse signal segment, the driving chip determines the amplitude of the current provided to the light-emitting unit group based on the amplitude of the pulse signal.

[0357] In a frame display period, the brightness of the light-emitting unit group corresponding to the driving end is adjusted by adjusting the number of pulses output by the driving end.

[0358] The light emitting unit group determines the light emitting brightness based on the magnitude and duration of the current in the driver chip obtained by it.

[0359] When the connection relationship of the backlight component of the display device is the connection relationship of the backlight component provided in this application, the processor can no longer drive the light-emitting unit group to emit light correctly based on the waveform diagram shown in Figure 18, and the processor needs to provide corresponding driving signals for multiple light-emitting unit groups connected to the same output end.

[0360] The processor 250 can be configured to obtain backlight data from the display data, and then provide multiple pulse signal segments within the luminous period within each frame display cycle based on the backlight data; the pulse signal segments correspond to multiple power supply periods, and each pulse signal segment corresponds to multiple light-emitting unit groups connected to each power supply end.

[0361] The driving circuit 201 may be configured to drive the light-emitting unit group corresponding to the pulse signal segment to emit light based on the pulse signal segment transmitted by the processor.

[0362] More specifically, processor 250 obtains the pulse period corresponding to each driver end; the pulse period is the pulse period used to drive a light-emitting unit group when the driver end of the driver chip is connected to the light-emitting unit group, i.e., the pulse period shown in Figure 18. Similar to the corresponding processing method in Figure 20, the processor determines the light-emitting duty cycle and amplitude of the pulse signal within the pulse period of the current frame based on the backlight data.

[0363] Based on the luminous duty cycle and amplitude determined above, the processor divides each pulse period into a preset number of pulse sub-periods (i.e., power supply periods) within the luminous period. The preset number of power supply periods corresponds to the multiple power supply ends of each driver chip. The preset number of power supply periods are arranged within each pulse period of the display period according to the preset power supply sequence of the multiple power supply ends.

[0364] During each power supply period, the driver chip outputs a pulse signal segment. The light-emitting duty cycle of the pulse signal segment within its pulse sub-period is the same as the duty cycle of the pulse signal within the pulse period, and the amplitude of the pulse sub-signal is the same as the amplitude of the pulse signal. This pulse signal segment can be a single pulse signal or multiple pulse signals, which is not specifically limited here.

[0365] The driver chip supplies power to the corresponding multiple light-emitting unit groups through each power supply end based on a preset power supply sequence. In each pulse cycle, for each power supply end, the driver chip drives the corresponding light-emitting unit group to emit light based on the pulse signal segment in the power supply period corresponding to the power supply end.

[0366] In one embodiment, the pulse signal segment may include at least one first level signal and / or at least one second level signal;

[0367] The driver chip may be configured to output current from the driver end based on the first level signal in the pulse signal segment during each power supply period, thereby driving the light-emitting unit group electrically connected to the driver end to emit light;

[0368] and / or

[0369] In each power supply period, based on the second level signal in the pulse signal segment, no current is output from the driving end, and the light emitting unit group electrically connected to the driving end is driven not to emit light.

[0370] In some embodiments, since the liquid crystal molecules on the display panel are scanned in a predetermined sequence, the light-emitting unit groups on the backlight assembly also emit light in a corresponding sequence. For example, if the liquid crystal molecules in the display panel are scanned row by row from top to bottom, the light-emitting unit groups on the backlight assembly also provide backlight row by row. Therefore, the processor 250 can be configured to transmit the driving data for each light-emitting unit group row by row after receiving the frame scan signal, according to the delay duration corresponding to each row of light-emitting unit groups.

[0371] The processor 250 may also be configured to obtain a frame start signal and a delay time of a liquid crystal molecule group corresponding to a light emitting unit group;

[0372] The start time of the display cycle corresponding to the light-emitting unit group is determined based on the frame start signal and the delay time. The delay time of the liquid crystal molecule group may include the start time of the liquid crystal molecule scanning of the current row and the delay time relative to the acquisition time of the frame start signal. The sum of the frame start signal and the delay time is the start time of the display cycle corresponding to the current light-emitting display group.

[0373] The following uses the circuit connection shown in FIG11C as an example to explain the waveform of the drive data output by the processor. Since the cathodes of the light-emitting unit groups in the same group are connected to the same driving terminal in FIG11C, the delay period of the two rows of light-emitting unit groups relative to the moment when the frame start signal Vsync is obtained is the same. In FIG11C, since the driver chip has two power supply terminals, each pulse cycle can be evenly divided into two pulse sub-periods. When the driver chip shown in FIG11C provides a power signal at the power supply terminal, it always provides the power signal in the order of power supply terminal V2 and power supply terminal V1. Then, the waveform diagram of the drive data provided by the processor is shown in FIG19.

[0374] In each pulse sub-period, the duty cycle of the pulse signal in the pulse sub-period is the same as the duty cycle shown in Figure 18, and the amplitude is also the same. When the driver chip obtains the first pulse signal in each pulse period, it controls the power supply terminal V2 to output the power signal VLED, so that the positive electrode of the first row of light-emitting unit groups obtains the power signal. The driver chip then outputs a drive signal from the driver terminal based on the pulse signal to make the light-emitting unit groups in the first row emit light. When the driver chip obtains the second pulse signal in each pulse period, it controls the power supply terminal V2 to stop providing the power signal, controls the power supply terminal V1 to provide the power signal, and then outputs the drive signal based on the drive data. Then, the light-emitting unit groups in the first row do not emit light, and the light-emitting unit groups in the second row emit light. This cycle repeats until the light-emitting period ends.

[0375] Since the power supply for the light-emitting unit group connected to the driver chip is provided by the driver chip itself, during the driving process of the driver chip, it is only necessary to calibrate the pulse sequence of the driving signals corresponding to the multiple light-emitting unit groups connected to the same driving end within each frame display cycle. In the related art, PM driving adopts a unified power supply method to provide power signals for the left and right light-emitting unit groups in the backlight assembly, which has high requirements on the power supply accuracy of the power signal and requires calibration of the pulse sequence of all driver chips in the driving circuit. Therefore, the control method of the present application simplifies the control difficulty.

[0376] In some embodiments, the power switch in the driver chip is a controllable transistor, such as a CMOS. Since the on and off processes of the controllable transistor also generate significant power consumption, and the power consumption during the on process is relatively small, the power consumption of the driver chip can be reduced by reducing the number of times the controllable transistor is turned on and off.

[0377] It is set that within the display period of each frame, the power supply end that is powered at the end of any pulse cycle is the same as the power supply end that is powered at the beginning of the next pulse cycle, and the power supply end that is powered at the end of any pulse cycle remains powered until the second power supply end of the next pulse cycle powers on.

[0378] For the circuit shown in Figure 11C, when the driver chip drives the light-emitting unit group to emit light during the light-emitting period, it can control the two power supply terminals to provide power signals in the order of power supply terminal V2 and power supply terminal V1 within the first pulse cycle, and provide driving signals in this order to sequentially drive the first row of light-emitting unit groups and the second row of light-emitting unit groups to emit light; within the second pulse cycle, the power switch corresponding to the power supply terminal V1 is controlled not to be turned off at the end of the first pulse cycle, then within the second pulse cycle, the two power supply terminals are controlled to provide power signals in the order of power supply terminal V1 and power supply terminal V2, and the provision of driving signals is adjusted according to this order to sequentially drive the second row of light-emitting unit groups and the first row of light-emitting unit groups to emit light, and at the end of the second pulse cycle, the power switch corresponding to the power supply terminal V2 is kept in the on state, so that within the third pulse cycle, the two power supply terminals are controlled to provide power signals in the order of power supply terminal V2 and power supply terminal V1 to sequentially drive the first row of light-emitting unit groups and the second row of light-emitting unit groups to emit light, and so on until the end of the light-emitting period. The waveform generated by the processor 250 is shown in Figure 20.

[0379] In some embodiments, considering that the state of the liquid crystal molecules is unstable during the initial period of the display period, the display period is divided into a black insertion period and a light emitting period. The black insertion period may include an unstable state period of the liquid crystal molecules.

[0380] Among them, the unstable period of the liquid crystal molecule group is during the angle adjustment process of the liquid crystal molecules from the deflection angle applied when displaying the previous frame to the deflection angle applied to the current frame. When the rotation angle is greater than or equal to the product of the preset ratio and the deflection angle difference, the liquid crystal molecules are determined to be in a stable period; when the rotation angle is less than the product of the preset ratio and the deflection angle difference, the liquid crystal molecules are determined to be in an unstable period.

[0381] The processor controls the light-emitting unit group not to emit light during the unstable period of the liquid crystal molecule group to achieve black insertion operation, thereby preventing the occurrence of ghosting between two adjacent frames.

[0382] To improve the smoothness and clarity of display images, some LCD devices employ variable refresh rate (VRR) technology. This technology dynamically adjusts the display cycle of the display panel and backlight assembly based on the current frame rate to adjust the image refresh rate. Processor 250 controls the backlight assembly to perform black insertion only at the beginning of a frame. This results in different refresh rates with the same black insertion time and different light-on times, causing flickering when the refresh rate changes.

[0383] To address the above problem, the processor 250 can also be configured to split the display cycle of the light-emitting unit group into a black insertion period and at most two light-emitting periods, not outputting driving data during the black insertion period, and outputting driving data during the light-emitting period, so that the backlight component maintains a consistent average brightness in each frame of the picture display based on the control signal, thereby reducing the flickering phenomenon in the picture display.

[0384] In some embodiments, when the refresh rate applied to the current frame image is equal to the maximum refresh rate of the display panel, the processor 250 maintains the original wave-generating state unchanged. Taking the waveform shown in Figure 19 as an example, when the current refresh rate is the maximum refresh rate of the display panel, the waveform output by the processor 250 is still the waveform shown in Figure 19.

[0385] In some embodiments, when the refresh rate applied to the current frame image is less than the maximum refresh rate of the display panel, the processor 250 splits the light-emitting period into a first light-emitting sub-period and a second light-emitting sub-period, wherein the first light-emitting sub-period is the same as the light-emitting period corresponding to the maximum refresh rate, and the amplitude of the second light-emitting sub-period is the product of a preset ratio and the amplitude in the first light-emitting sub-period.

[0386] Taking the waveform shown in FIG19 as an example, when the refresh rate is less than the maximum refresh rate of the display panel, the waveform output by the processor 250 is shown in FIG21. The amplitude of the second light-emitting sub-period is the product of the amplitude of the first light-emitting sub-period and the black insertion ratio, where the black insertion ratio is the quotient of the black insertion duration divided by the sum of the black insertion duration and the first light-emitting sub-period within the display cycle.

[0387] In other embodiments, the processor may also repeat the wave transmission according to the wave transmission situation corresponding to the maximum refresh rate. When the remaining duration after excluding the duration of at least one light-emitting period corresponding to the maximum refresh rate is less than the duration of the light-emitting period corresponding to the maximum refresh rate, the duty cycle of the pulse wave of the remaining duration is adjusted to the black insertion ratio.

[0388] Taking the waveform shown in FIG19 as an example, when the refresh rate is less than the maximum refresh rate of the display panel, the waveform output by the processor 250 is shown in FIG22. The duration of each pulse in the second light-emitting sub-period is the product of the duration of the pulse in the first light-emitting sub-period and the black insertion ratio, where the black insertion ratio is the quotient of the black insertion duration divided by the sum of the black insertion duration and the first light-emitting sub-period within the display cycle.

[0389] In some embodiments, the processor 250 adopts joint dimming, that is, during the display of a frame of picture, the amplitude of the current in the driving data provided by the processor 250 is the same, and different duty cycles correspond to different luminous durations, thereby corresponding to different numerical values ​​in the backlight data. Among them, the larger the numerical value in the backlight data, the brighter the brightness provided by the light-emitting unit group in the backlight assembly, and the larger the duty cycle in the driving data provided by the processor for the light-emitting unit group; the smaller the numerical value in the backlight data, the smaller the duty cycle in the driving data provided by the processor for the light-emitting unit group.

[0390] When the processor 250 uses joint dimming to display different frames, the amplitudes of the drive data generated based on the backlight data are not exactly the same. Applying joint dimming can make the backlight provided by the control method provided by the application more delicate, and the display device using the backlight assembly has better display quality.

[0391] In some embodiments, the processor 250 obtains the power supply status of the light-emitting unit group through the driving circuit and controls the power supply circuit to adjust the voltage value provided based on the power supply status. To simplify the circuit structure, the current-voltage relationship of the light-emitting unit group is pre-stored in the processor 250 or a memory accessible thereto; the image data may include backlight data, and the current-voltage relationship of the light-emitting unit group represents the current value flowing through the light-emitting sub-unit when different power supply voltage values ​​are applied;

[0392] In some embodiments, based on the backlight data, driving data corresponding to each light-emitting sub-unit is generated; the driving data may include a current value and a duty cycle; the current value corresponding to each light-emitting sub-unit is the same;

[0393] In some embodiments, based on the current-voltage relationship, a supply voltage value corresponding to the current value is determined, and a supply voltage having a voltage value corresponding to the target current value is output to the light-emitting unit group.

[0394] In some embodiments, when determining the current-voltage relationship of the light-emitting unit group, the processor determines the minimum supply voltage that can be provided by the power supply circuit, and determines the current value at which each light-emitting unit group is in an overvoltage state based on the minimum supply voltage as the first sampling point of the fitting relationship;

[0395] The processor controls the driving circuit to provide at least one preset current value and adjusts the supply voltage so that the voltage value is the minimum voltage value of the overvoltage of each light-emitting unit group;

[0396] Based on the multiple current-voltage sampling points, the current-voltage relationship is fitted. This eliminates the need for the power supply circuit to obtain feedback signals related to the light-emitting unit group from the driver circuit when determining the supply voltage. Consequently, the drive data transmission path or the provision of separate data lines is no longer required, ensuring the transmission rate of drive data and the simplicity of the circuit structure. Furthermore, because the current-voltage relationship of the light-emitting sub-units is pre-fitted, the consistency of the backlight circuit based on the combined dimming ensures the accuracy of the supply voltage determination, thereby ensuring display accuracy.

[0397] In some embodiments, the backlight assembly is further provided with a power supply control chip 251, which is respectively connected to the power supply output terminal of the power supply circuit, the power supply terminal of the driving circuit, and the output terminal of the processor 250. The circuit connection relationship is shown in FIG23. The power supply control chip 251 can be configured to supply power to the corresponding driving chip and output the driving signal when receiving the driving signal, so that the driving chip drives the light string to emit light based on the driving signal.

[0398] The power supply control chip 251 can also be configured to stop supplying power and providing driving signals to the corresponding driver chip when it does not receive a driving signal, so that the driver chip stops driving the light string to emit light, thereby reducing leakage current and reducing losses during the standby process of the display device.

[0399] FIG44 is a schematic diagram of a circuit structure of a power supply according to some embodiments.

[0400] In some embodiments, the power supply circuit 13 includes a filtering and rectifying circuit 131 , which is configured to obtain AC power, filter the AC power, perform voltage rectification on the AC power, and output a DC signal.

[0401] In some embodiments, the power supply circuit 13 includes a power factor correction (PFC) circuit 132. The PFC circuit is configured to compensate and correct the power factor of the DC power signal based on the power currently generated by the load to improve the utilization rate of the power. The output signal is a corrected signal.

[0402] In some embodiments, the power supply circuit 13 includes an LLC isolated voltage conversion circuit 133, which is configured to convert the corrected electrical signal after power factor correction into a voltage and output the voltage value required for the normal operation of the mainboard 80 and the accompanying audio and backlight components.

[0403] In some embodiments, the mainboard 80 includes at least one of a tuner, a communicator, a detector, an external device interface, a processor, an audio output interface, a memory, and a user interface.

[0404] In some embodiments, the LLC isolation voltage conversion circuit 133 includes at least two LLC circuits.

[0405] Taking the LLC isolation voltage conversion circuit 133 including two LLC circuits as an example, its power supply process is explained.

[0406] The LLC isolation voltage conversion circuit 133 includes a first LLC circuit and a second LLC circuit. The first LLC circuit is a circuit for powering the mainboard 80 and the accompanying sound circuit, and the second LLC circuit is a circuit for powering the backlight assembly 20. The first LLC circuit generates an electrical signal such as 12V or 16V / 24V based on the output electrical signal of the power factor correction circuit 132, and the second LLC circuit generates an electrical signal of 10V~15V based on the output electrical signal of the power factor correction circuit 132.

[0407] The two LLC circuits are dimmed separately, and the second LLC circuit can be controlled not to provide an electrical signal when the display device is in standby mode, so that the backlight assembly does not generate loss due to leakage current during the standby mode.

[0408] However, with the increasing complexity of the local dimming function, in order to improve the response speed of the front-end power supply to the current and voltage of the backlight and reduce the power supply cost, the relevant technology applies stepped power supply, that is, the high-voltage side circuit of the LLC isolation voltage conversion circuit 133 corresponds to at least two low-voltage side circuits. Through the transformer voltage conversion, the voltage obtained on the low-voltage side is different, and the output end provides electrical signals with different voltage values. Its circuit structure is shown in the LLC isolation voltage conversion circuit 133 of Figure 44.

[0409] In the circuit structure shown in FIG44 , an LLC isolated voltage conversion circuit 133 is provided with a high-voltage side circuit and multiple low-voltage side circuits. The multiple low-voltage side circuits all obtain electrical energy from the high-voltage side circuit through a transformer. When a power supply signal is obtained at the input end of the high-voltage side circuit, corresponding voltage values ​​can be provided to the mainboard 80, the audio and the backlight assembly 20 at the same time.

[0410] In some embodiments, the backlight assembly 20 includes a driving circuit and a light board, and the LLC isolation voltage conversion circuit 133 is configured to provide a power signal VLED to the driving circuit and provide a power signal VCC to the light board.

[0411] Since the components and circuit structures in the driving circuit and the light board are different, the voltage values ​​of the power signals used by the driving circuit and the light board are different. Generally, two low-voltage side circuits in the LLC isolation voltage conversion circuit 133 are required to provide the power signal.

[0412] In some embodiments, in order to simplify the circuit structure, a low-dropout regulator (LDO) may be added to the backlight assembly 20 , and its circuit connection relationship in the backlight assembly 20 is shown in FIG. 25 .

[0413] In the backlight assembly shown in FIG25 , the input of a low-dropout linear regulator 40 is electrically connected to the output of the power supply circuit 13, while the output is electrically connected to the power supply terminal of the driver chip 202 in the driver circuit. Low-dropout linear regulator 40 is configured to convert the power signal VLED into the power signal VCC. Therefore, the LLC isolation voltage conversion circuit only requires a low-voltage side circuit to provide the power signal to the backlight assembly.

[0414] When the display device is in standby mode, since the mainboard requires a power signal but the driver chip in the backlight assembly does not, the LLC isolation voltage conversion circuit cannot be completely shut down and the backlight assembly can still obtain a power signal.

[0415] Since the low-voltage difference linear regulator 40 arranged before the power supply end of each driver chip can only change the voltage but cannot control the conduction and shutdown of the electrical signal, even when the backlight component 20 stops emitting light, the driver chip 202 in the backlight component 20 still has leakage current. Even if the leakage current of each driver chip is small, the large number of driver chips 202 in the micro-LED backlight component 20 will still cause the backlight component 20 to generate a considerable leakage current when the display device is in standby mode, thereby resulting in non-negligible power loss during the standby process.

[0416] To this end, an embodiment of the present application provides a power supply control circuit, a driver chip and a display device. By setting a power supply control circuit between the driver circuit and the processor of the display device, when the driver circuit drives the light board to emit light, the power supply control circuit supplies power to the driver chip based on the driving data provided by the processor, and provides driving data so that the driver chip drives the light string on the backlight assembly to emit light. During the standby process of the display device, when the power supply control circuit obtains a low-power command, it stops providing backlight to the driver chip, so that the driver chip can reduce leakage current and reduce losses during the standby process of the display device.

[0417] The following detailed description of the technical solution of the present application is provided in conjunction with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0418] In some embodiments, the display device 200 includes a backlight assembly 20, which includes at least one power supply control circuit 60. An input port of the power supply control circuit 60 is electrically connected to the processor 250, a first output terminal of the power supply control circuit 60 is electrically connected to a power supply terminal of a driving circuit, and a second output terminal of the power supply control circuit 60 is electrically connected to a data input terminal of the driving circuit.

[0419] In some embodiments, the power supply control circuit 60 is configured to supply power to the driving circuit and output the driving data when receiving the driving data provided by the processor 250 from the input interface, so that the driving circuit drives the light-emitting unit group to emit light based on the driving data;

[0420] The power supply control circuit 60 is configured to stop supplying power to the driving circuit and providing driving data when receiving a low power command from the input interface, so that the driving circuit stops driving the light-emitting unit group to emit light. The low power command can be an operation to stop sending data or control data to control low power consumption.

[0421] In some embodiments, the driving circuit includes at least one driving chip 202, the power supply control circuit 60 corresponds to at least one driving chip 202, the first output end of the power supply control circuit 60 is electrically connected to the power supply end VCC of each driving chip 202, and the second output end is electrically connected to the data input end DIN of each driving chip 202.

[0422] In some embodiments, the power supply control circuit 60 is configured to supply power to the corresponding driver chip 202 and output the driving data when receiving the driving data provided by the processor 250, so that the driver chip 202 drives the light-emitting unit group to emit light based on the driving data;

[0423] The power supply control circuit 60 is further configured to stop supplying power and providing driving data to the corresponding driver chip 202 when the driver data provided by the processor 250 is not received, so that the driver chip 202 stops driving the light-emitting unit group to emit light.

[0424] In some embodiments, at least one driver chip 202 corresponding to the power supply control circuit 60 is electrically connected in parallel. The electrical connection relationship diagram is shown in Figures 26A and 6B. The second output end of the power supply control circuit 60 is electrically connected to the data input end DIN of each driver chip 202.

[0425] Each driver chip 202 is provided with address information. The power supply control circuit 60 is configured to broadcast data including the address information to the data line. The driver chip 202 corresponding to the address information obtains driving data from the data line to drive its corresponding light-emitting unit group to emit light.

[0426] In other embodiments, at least one driver chip 202 corresponding to the power supply control circuit 60 is electrically connected in series. The connection relationship diagram is shown in Figures 26C and 6D. The driver chip 202 is provided with an input terminal DI and an output terminal DO. The data input terminal DI of the first driver chip 202 is electrically connected to the output terminal of the processor 250, and the data input terminal DI of other driver chips 202 is electrically connected to the data output terminal DO of the previous driver chip 202. Each driver chip 202 is configured to obtain driving data from its input terminal DI, and after obtaining its corresponding driving data segment therefrom, output the driving data from its output terminal DO.

[0427] In some embodiments, the power supply control circuit 60 is configured to supply power to the corresponding driver chip based on the driving data when receiving the driving data, and output the driving data after a preset time period.

[0428] In some embodiments, the power supply control circuit 60 is further configured to obtain a power supply signal, and when the voltage values ​​of the power supply signal and the power supply signal of the driver chip 202 are inconsistent, convert the voltage value of the power supply signal into the voltage value of the power supply signal.

[0429] That is, upon receiving a control signal, the power supply control circuit 60 determines whether it needs to supply power to the driver chip and transmit data based on the control signal. If power is determined to be supplied to the driver chip, it may also perform voltage conversion, if necessary, to ensure that the driver chip outputs the operating voltage required by the driver chip. After receiving the power signal, the driver chip may perform operations such as power-on initialization. These operations are performed for a duration less than a preset time to ensure that the driver chip is stably powered before receiving the driver data transmitted by the processor. This prevents the driver chip from incompletely acquiring driver data due to power supply delays, which could affect backlight brightness and, consequently, the display quality of the display device.

[0430] In some embodiments, the power supply control circuit 60 may be integrated into a power supply control chip or may be a discrete circuit, which is not specifically limited here.

[0431] FIG7 is a display control method according to some embodiments, as shown in FIG7 , including:

[0432] S101. When the power supply control circuit receives driving data, it supplies power to the driving circuit based on the driving data and outputs the driving data, so that the driving circuit drives the light panel to emit light based on the driving data.

[0433] S102 : When the power supply control circuit receives the low power consumption command, it stops supplying power to the driving circuit and stops providing driving data, so that the driving circuit stops driving the light-emitting unit group to emit light.

[0434] The schematic diagram of the power supply control circuit 60 is shown in FIG28 . The power supply signal obtained by the power supply control circuit 60 includes, but is not limited to, a power supply signal obtained from the power supply circuit and a power supply signal obtained from the drive data transmitted by the processor. The following explains the two cases respectively.

[0435] In some embodiments, when the power signal obtained by the power supply control circuit 60 is a power signal obtained from the power supply circuit 13 , the input port of the power supply control circuit 60 is electrically connected to the power supply circuit 13 .

[0436] More specifically, the input port of the power supply control circuit 60 includes an input terminal and a power supply terminal. The input terminal of the power supply control circuit 60 is electrically connected to the processor 250, and the power supply terminal of the power supply control circuit 60 is electrically connected to the power supply circuit 13 and the power supply terminal of the light board. The connection relationship of the power supply control circuit 60 in the backlight assembly is shown in Figures 26B and 26D.

[0437] The power supply control circuit 60 is configured to obtain a first power supply signal from the power supply circuit 13 , and when obtaining corresponding driving data, output the first power supply signal based on the driving data as a chip power supply signal.

[0438] In some embodiments, the power supply control circuit 60 is configured to convert the first power supply signal into a chip power supply signal based on the driving data to supply power to the driving chip 202 .

[0439] In some embodiments, the power supply control circuit 60 includes a control unit 602, an input terminal of the control unit 602 being coupled to an input terminal of the power supply control circuit 60, and configured to receive driving data during a non-standby period of the display device, and generate a first control signal and a second control signal based on the driving data, wherein a start time of the first control signal is earlier than a start time of the second control signal by a preset time period;

[0440] In some embodiments, the control unit 602 is further configured to not accept driving data and not generate the first control signal and the second control signal during a standby period of the display device.

[0441] In some embodiments, the control unit 602 includes a delay circuit (e.g., an RC circuit). The delay circuit is configured to receive the first control signal and output a second control signal after a preset time period. The delay period is determined based on delay characteristic parameters of components in the delay circuit. For example, in an RC circuit, the delay period is determined based on the resistance of the resistor and the capacitance of the capacitor.

[0442] In some embodiments, the power supply control circuit 60 includes a DC voltage conversion unit 601, whose input end is coupled to the power supply end of the power supply control circuit 60, whose output end is electrically connected to the first output end of the power supply control circuit 60, and whose control end is electrically connected to the first output end of the control unit 602.

[0443] The DC voltage conversion unit 601 is configured to obtain a first control signal from the control unit 602, obtain a first power supply signal from its input terminal, and output the first power supply signal as a chip power supply signal based on the first control signal.

[0444] In some embodiments, the DC voltage conversion unit 601 is configured to convert the first power supply signal into a chip power supply signal based on the first control signal, and output the chip power supply signal, as shown in FIG28 .

[0445] When the first power supply signal is a power supply signal for the light emitting unit group, the first power supply signal is a power supply signal VLED, and the chip power supply signal is a power supply signal VCC, as shown in FIG. 29A and FIG. 29B .

[0446] In some embodiments, the DC voltage conversion unit 601 includes a low-voltage difference linear regulator LDO and a controllable switching device. The controllable switching device is connected in series between the input end of the DC voltage conversion unit 601 and the input end of the low-voltage difference linear regulator LDO. The DC voltage conversion unit 601 is configured to control the conduction state of the controllable switching device based on a first control signal. When the switching device is turned on, the power signal VLED obtained at the input end of the LDO is converted into a chip power supply signal.

[0447] In some embodiments, the DC voltage conversion unit 601 includes a DCDC conversion circuit (eg, a Buck circuit), and the first control signal is configured to control a switch device in the DCDC conversion circuit to conduct to perform voltage conversion.

[0448] In some embodiments, the power supply control circuit 60 also includes a driving data transmission unit 603, whose input end is coupled to the input end of the power supply control circuit 60, whose output end is electrically connected to the second output end of the power supply control circuit 60, and whose control end is electrically connected to the second output end of the control unit 602.

[0449] The driving data transmission unit 603 is configured to obtain the second control signal from the control unit 602 and the driving data from the processor 250 , and its conduction state is controlled by the second control signal. When it is conducted, it outputs the driving data.

[0450] In some embodiments, the driving data transmission unit 603 includes a controllable switch device or a buffer amplifier Buffer. The controllable switch device includes but is not limited to a field effect transistor and a triode.

[0451] The controllable switch device and the buffer amplifier are configured to be turned on when receiving the second control signal, and output the driving data received at their input terminals.

[0452] Among them, when the driving data transmission unit includes a controllable switching device, the circuit structure of the power supply control circuit 60 is shown in Figure 29A; when the driving data transmission unit includes a buffer amplifier Buffer, the circuit structure of the power supply control circuit 60 is shown in Figure 29B.

[0453] In some embodiments, address information is set in the power supply control circuit 60, and the processor 250 outputs driving data based on the address information.

[0454] In some embodiments, the power supply control circuit 60 includes an address unit 604 , a schematic diagram of which is shown in FIG30 . The address unit 604 is configured to set an address of the power supply control circuit 60 .

[0455] In some embodiments, the processor 250 is configured to send driving data to the power supply control circuit 60 based on the address of the power supply control circuit 60 , where the driving data includes the address of the power supply control circuit.

[0456] The power supply control circuit 60 is configured to receive driving data, and based on the driving data, output a circuit power supply signal from its first output terminal, and output driving data from its second output terminal, so that the backlight driving circuit electrically connected to the power supply control circuit 60 generates a driving signal based on the driving data to drive the corresponding lamp bead 301 to emit light.

[0457] In some embodiments, the backlight driving circuit may be packaged as a driving chip 202 , and the circuit power supply signal generated by the power supply control circuit 60 is a chip power supply signal.

[0458] In some embodiments, the power supply control circuit 60 is further configured to stop outputting circuit power supply signals and driving data when receiving a low power consumption command.

[0459] In the above technical solution, the power supply control circuit arranged between the processor and the backlight driving circuit can supply power to the driving chip based on the driving data provided by the processor, and provide driving data so that the driving chip drives the light string on the backlight assembly to emit light. During the standby process of the display device, when the power supply control circuit obtains a low-power command, it stops providing backlight to the driving chip, so that the driving chip reduces leakage current and reduces losses during the standby process of the display device. In addition, the corresponding address is set in the power supply control circuit so that when multiple power supply control circuits are connected to the same output end of the processor, the corresponding driving data can be distinguished based on their corresponding addresses, thereby reducing the use of data lines on the backlight assembly, simplifying the circuit structure, and improving the control capability of the processor.

[0460] In some embodiments, the address unit 604 includes an address configuration circuit 6041. An input terminal of the address configuration circuit 6041 serves as an input terminal of the power supply control circuit 60 and is electrically connected to the processor 250. The address configuration circuit 6041 is set with its corresponding physical address and is configured to obtain driving data sent by the processor 250.

[0461] When the address information of the power supply control circuit 60 in the driving data is the same as the physical address, a conduction control signal is generated;

[0462] When the address information of the power supply control circuit 60 in the drive data is different from the physical address, no conduction control signal is generated.

[0463] In some embodiments, the address unit 604 further includes a transmission circuit 6042, whose input terminal is electrically connected to the processor 250 via the input terminal of the power supply control circuit 60, and whose control terminal is electrically connected to the output terminal of the address configuration circuit 6041. An exemplary circuit connection relationship between the transmission circuit 6042 and the address configuration circuit 6041 is shown in FIG31.

[0464] The transmission circuit 6042 is configured to obtain driving data from its input terminal, output driving data when a conduction control signal is obtained at its control terminal, and stop outputting driving data when no conduction control signal is obtained at its control terminal.

[0465] In some embodiments, the address configuration circuit 6041 includes a multi-input AND gate circuit, which is configured to output a first level as a conduction control signal when obtaining an address corresponding to the physical address set by the address unit 604 from its input terminal;

[0466] When other addresses are obtained from its input terminal, the second level is output.

[0467] The address is an address composed of at least one digital electrical signal, and the digital electrical signal includes a high-level electrical signal or a low-level electrical signal.

[0468] The multi-input AND gate circuit performs a logic operation on at least one digital electrical signal corresponding to the address, and determines the electrical signal with the output target level as the conduction control signal.

[0469] In some embodiments, the address set by the address unit 604 is an address composed of three-digit digital electrical signals, for example: 011, and an example circuit structure diagram of a multi-input AND gate circuit corresponding to the physical address is shown in Figure 32, including two AND gates and a NOT gate, wherein the NOT gate inverts the electrical signal obtained from the first input terminal of the first AND gate, the output terminal of the first AND gate is electrically connected to the first input terminal of the second AND gate, and the output terminal of the second AND gate is configured to output a conduction control signal.

[0470] The circuit structure shown in FIG32 includes three input terminals, which are coupled to the processor 250 and correspondingly obtain three-bit address information of the address unit 604 .

[0471] In some embodiments, the three input terminals of the multi-input AND gate circuit determine their corresponding physical addresses according to a preset order, and the processor 250 is configured to output the levels corresponding to the physical addresses based on the preset order, so that the multi-input AND gate circuit outputs a high-level electrical signal.

[0472] The high-level electrical signal is a conduction control signal output by the multi-input AND gate circuit, and the low-level electrical signal is another electrical signal output when the multi-input AND gate circuit does not output a conduction control signal.

[0473] For example, if the three input terminals of a multi-input AND gate circuit determine their corresponding physical addresses in order from top to bottom, then when processor 250 outputs low-level, high-level, and high-level electrical signals based on the physical addresses, the multi-input AND gate circuit outputs a high-level electrical signal as the conduction control signal. If the level of any bit of the physical address output by processor 250 is inconsistent with the aforementioned levels, the multi-input AND gate circuit outputs a low-level electrical signal, indicating that address configuration circuit 6041 has not outputted a conduction control signal.

[0474] In some embodiments, the digital signal transmitted by the processor 250 includes 0 and 1, 0 corresponds to a low-level electrical signal, and 1 corresponds to a high-level electrical signal. For the circuit structure shown in Figure 32, the digital signal corresponding to the physical address set by the address configuration circuit 6041 is 011.

[0475] In some embodiments, the input end of the multi-input AND gate circuit obtains not only the address but also other control signals, and the conduction control signal outputted by the multi-input AND gate circuit is a signal generated by the multi-input AND gate circuit based on the address and other control signals.

[0476] In some embodiments, a serial-to-parallel circuit is electrically connected in series between the processor 250 and the address configuration circuit 6041. The serial-to-parallel circuit is configured to transmit the serially transmitted digital signal in parallel to the input end of the address configuration circuit 6041, so that the address configuration circuit 6041 processes multiple digital electrical signals transmitted by the processor 250.

[0477] In other embodiments, the address configuration circuit 6041 may further include a reference circuit for generating a preset voltage value and a voltage comparator. The output of the reference circuit is electrically connected to the first input of the voltage comparator, and the output of the processor 250 is electrically connected to the second input of the voltage comparator.

[0478] The processor 250 is configured to output a first voltage signal as an address corresponding to the target driver chip.

[0479] The address configuration circuit 6041 is configured to obtain a first voltage signal and a preset voltage value. When the output voltage value is less than the preset voltage threshold, it indicates that the address output by the processor 250 matches the address set by the address configuration circuit 6041, and the output voltage value is determined as the conduction control signal.

[0480] When the output voltage value is greater than the preset voltage threshold, it indicates that the address output by the processor 250 does not match the address set by the address configuration circuit 6041 , and the output voltage value is determined as other signals output by the address configuration circuit 6041 .

[0481] In some embodiments, the transmission circuit 6042 includes a controllable transmission circuit, such as the transmission gate shown in FIG. 32 .

[0482] In some embodiments, the enable end of the transmission gate serves as the control end of the transmission circuit 6042 and is electrically connected to the output end of the address configuration circuit 6041. The input end of the transmission gate is electrically connected to the output end of the processor 250 and is configured to be turned on based on the conduction control signal output by the address configuration circuit 6041, and output the driving data obtained at its input end.

[0483] In some embodiments, in the power supply control circuit 60, the input end of the control unit 602 and the output end of the transmission unit 6042 are electrically connected, and the control unit 602 is configured to obtain driving data from the transmission unit 6042 and generate a first control signal based on the driving data to control the driving data transmission unit 603 to be turned on.

[0484] The control unit 602 is further configured to generate a second control signal based on the driving data to control the DC voltage conversion unit 601 to perform level conversion and output a circuit power supply signal for the backlight driving circuit.

[0485] The driving data transmission unit 603 is electrically connected to the output end of the transmission circuit 6042 and is configured to obtain driving data from the transmission circuit 6042 and output the driving data when the driving data transmission unit 603 is turned on.

[0486] In some embodiments, when the power supply control circuit 60 shown in FIG. 31 is used to construct a backlight assembly of a display device, the backlight assembly includes multiple drive units and multiple data lines, and each drive unit is connected to the processor 250 via a corresponding data line. Each drive unit includes multiple drive groups, and each drive group includes a power supply control circuit as shown in FIG. 31 and at least one driver chip. The address of the power supply control circuit is the address of the drive group, and different drive groups in the same drive unit have different addresses.

[0487] The structure of the backlight assembly provided by the present application is explained using the structure shown in Figure 33. The processor 250 has three output terminals DIN1, DIN2, and DIN3. The output terminal DIN1 is connected to the corresponding first drive unit 21a via a data line 22, the output terminal DIN2 is connected to the corresponding second drive unit 21b via a data line 22, and the output terminal DIN3 is connected to the corresponding third drive unit 21c via a data line 22.

[0488] The internal structure and connection relationship of the drive unit will be explained below by taking the first drive unit 21a as an example.

[0489] The first driving unit 21 a includes three driving groups corresponding to the three groups of liquid crystals displayed on the display panel 10 .

[0490] In the structure shown in Figure 33, taking the first row drive group as an example, each drive group includes a power supply control circuit 60 and multiple drive chips 202, and the input end of the power supply control circuit 60 and the output end of the processor 250 are electrically connected, as shown in the first schematic structure in the order from left to right in Figure 33.

[0491] The power supply terminal VCC of each driver chip 202 is electrically connected to the output terminal of the DC voltage conversion unit 601 in the power supply control circuit 60. The data input terminal DI of each driver chip 202 is coupled to the output terminal of the driving data transmission unit 603 in the power supply control circuit 60.

[0492] In some embodiments, in the driving group, the data input terminal DI of each driving chip 202 is connected to the output terminal of the driving data transmission unit 603 in the power supply control circuit 60, as shown in FIG26B.

[0493] In some embodiments, in the driving group, the data input terminal DI of the first driving chip 202 among the driving chips 202 is connected to the output terminal of the driving data transmission unit 603 in the power supply control circuit 60, and its data output terminal DO is connected to the data input terminal of the next driving chip 202, as shown in Figure 26D.

[0494] In some embodiments, in each driving unit, the addresses of each driving group are different, so that the processor 250 transmits corresponding driving data based on the address of each driving group.

[0495] In some embodiments, in each driving group, the address of the power supply control circuit 60 serves as the address of the driving group to which it belongs.

[0496] In some embodiments, each driver chip 202 is configured to obtain each corresponding data segment based on its corresponding internal address to generate a driving signal to drive the corresponding lamp bead 301 to emit light. The circuit structure of the power supply control circuit 60 is shown in FIG31 .

[0497] In some embodiments, when the processor 250 transmits driving data to the target driver chip, the processor 250 is configured to send the driving data to the target power supply control circuit in the driver group based on the address of the driver group where the target driver chip is located; the address includes the address of the power supply control circuit;

[0498] The target power supply control circuit is configured to output a circuit power supply signal and driving data based on the address, so that the target driving chip drives the corresponding lamp bead to emit light based on the driving data.

[0499] In some embodiments, the power supply control circuit 60 can be integrated with the backlight driving circuit in the driver chip 202 in the controllable driver chip 204, that is, the controllable driver chip 204 includes the power supply control circuit 60 and the backlight driving circuit 203. The circuit structure of the controllable driver chip 204 is explained below using FIG. 34 as an example.

[0500] In some embodiments, the controllable driver chip 204 includes a power supply control circuit 60, and the first output end of the power supply control circuit 60 serves as the power supply end of the power supply control circuit 60, and is electrically connected to the power supply end VCC of at least one corresponding driver chip 202, and is also electrically connected to the power supply end VCC of the backlight driver circuit 203 in the controllable driver chip 204. Its first output end is configured to output the circuit power supply signal of the backlight driver circuit and the chip power supply signal of the driver chip 202, wherein the circuit power supply signal and the chip power supply signal are the same.

[0501] In some embodiments, the second output terminal of the power supply control circuit 60 is connected to the input terminal DI of the backlight driving circuit 203 of the controllable driving chip 204, and is configured to output driving data from its second output terminal after outputting the circuit power supply signal from its first output terminal.

[0502] In some embodiments, the circuit structure of the power supply control circuit 60 is shown in FIG. 29A or FIG. 29B .

[0503] In some embodiments, the address of the power supply control circuit 60 is an address burned into the control unit 602 .

[0504] In other embodiments, the address of the power supply control circuit 60 is set by a pin address. The control unit 602 in the power supply control circuit 60 is connected to the address pin of the controllable driver chip 204. The address pin is configured to set the physical address of the controllable driver chip 204, which is also the physical address of the power supply control circuit 60.

[0505] The control unit 602 is configured to, after obtaining the driving data, determine whether the address of the control unit 602 and the address in the driving data are the same based on the physical address set by the address pin. If they are the same, the control unit 602 generates a first control signal and a second control signal in sequence based on the driving data to control the DC voltage conversion unit 601 to output the circuit power supply signal and the chip power supply signal, and control the driving data transmission unit 603 to output the driving data.

[0506] In some embodiments, the address pin of the controllable driver chip 204 can be connected to other function pins of the chip. The other function pins correspond to their own physical addresses. Different function pins correspond to different physical addresses. When the address pin is connected to the function pin, the address of the address pin becomes the address of the function pin. The function pins include: power supply pins, data input pins, data output pins, and power supply pins.

[0507] In some embodiments, a level generating circuit may be provided in the controllable driving chip 204, and the address pin of the controllable driving chip 204 is electrically connected to the output end of the level generating circuit, and the voltage value or level state generated by the level generating circuit is set as the address of the controllable driving chip 204, wherein the level state includes a low level state or a high level state.

[0508] In other embodiments, the circuit structure of the power supply control circuit 60 is shown in FIG. 31 , and includes an address unit 604 , and a corresponding address can be set based on the address unit 604 .

[0509] In the above technical solution, after receiving the driving data, the driver chip of the power supply control circuit can regulate the power supply process of the current driver chip based on the driving data, so that the driver chip is powered on only when it receives its corresponding driving data, thereby reducing the leakage current generated by the driver chip during the standby process of the display device.

[0510] In some embodiments, the present application provides a driving group, which includes a controllable driving chip 204 and multiple driving chips 202. The address of the controllable driving chip 204 serves as the address of the driving group. The power supply end of the controllable driving chip 204 is electrically connected to the power supply circuit 13, the data input end is connected to the processor 250, the power supply end is electrically connected to the power supply end of the multiple driving chips 202, and the driving end is electrically connected to the corresponding lamp beads.

[0511] In some embodiments, the data output terminal of the controllable driver chip 204 is electrically connected to the data input terminals of the plurality of driver chips 202 ;

[0512] In other embodiments, the data output end of the controllable driver chip 204 is electrically connected to the data input end of the driver chip 202 located first among the multiple driver chips 202, and the data input ends of other driver chips 202 are electrically connected to the data output ends of the previous driver chip 202. The circuit structure is shown in Figure 34.

[0513] In some embodiments, the present application provides a driving group, which includes multiple controllable driving chips 204. As shown in Figure 35, the power end of each controllable driving chip 204 is electrically connected to the power supply circuit 13, and the driving end is electrically connected to the corresponding lamp bead.

[0514] In some embodiments, the data input terminal of the first controllable driver chip 204 is electrically connected to the processor 250 , and the data input terminals of other controllable driver chips 204 are electrically connected to the data output terminals of the previous controllable driver chip 204 .

[0515] In other embodiments, the data input terminals of each controllable driving chip 204 are electrically connected to the processor 250 .

[0516] In some embodiments, at least one driver chip 202 can be electrically connected between two adjacent controllable driver chips 204, and the power supply end of at least one driver chip 202 is electrically connected to the power supply end of the previous controllable driver chip 204, so as to divide the partitions in a row into multiple groups of partitions according to the number of controllable driver chips 204, and control each group of partitions separately and in a targeted manner, thereby improving the precision of the processor 204's control over the partitions without increasing the number of data line wiring on the backlight assembly.

[0517] In the above technical solution, each driving unit in the backlight assembly includes multiple driving groups, and each driving group includes at least one driving chip including a power supply control circuit to manage the power consumption process of the driving chip and related devices. When the driver receives a low-power command, the power supply circuit can be shut down in time to reduce the generation of leakage current. The power supply control circuit is integrated in the driving chip, which does not increase the number of chips used on the backlight assembly and reduces production costs. In addition, the multiple driving groups in the driving unit distinguish addresses based on the physical address of the driving chip, which improves the driving capability of the processor, reduces the use of data lines on the backlight assembly, and simplifies the circuit structure.

[0518] In some embodiments, the present application provides a processor 250 , as shown in FIG36 , the processor 250 includes a modulation unit 251 , and an output end of the modulation unit 251 is coupled to an output end of the processor 250 .

[0519] In some embodiments, the processor 250 is configured to obtain a frame of image data, acquire backlight data from the frame of image data, and generate driving data based on the backlight data.

[0520] In some embodiments, the processor 250 is configured to obtain a second power signal.

[0521] In some embodiments, the modulation unit 251 is configured to obtain the second power signal and driving data, and output modulated driving data, where the modulated driving data includes the driving data loaded on the second power signal.

[0522] In some embodiments, the waveform output by the modulation unit 251 is shown in FIG38 , wherein the second power signal is a high-level signal, and the driving data is a signal having a frequency higher than that of the second power signal. The level state corresponding to the driving data includes a high-level state or a low-level state.

[0523] The potential value of the second power supply signal loaded with high-level driving data remains unchanged, while the potential value of the second power supply signal loaded with low-level driving data decreases, but the level of the second power supply signal does not change. That is, after the high-level signal in the second power supply signal is loaded onto the low-level signal, the signal remains high. In the waveform diagram shown in FIG38 , period t1 represents the period during which the second power supply signal is loaded with driving data, and period t2 represents the low-level period during which neither driving data nor the second power supply signal is output.

[0524] This loading method has little impact on the change of the power supply signal and can simplify the modulation process of the modulation unit.

[0525] In other embodiments, the waveform output by the modulation unit 251 is shown in Figure 39, and the second power supply signal loaded with driving data fluctuates up and down according to the second power supply signal, wherein, during the t1 period, the second power supply signal that is not loaded with driving data is at the third level, as shown in the D2 period, the second power supply signal loaded with high-level driving data is at the first level, such as the level higher than the third level during the D1 period and the D2 period, and the second power supply signal loaded with low-level driving data is at the second level, such as the level lower than the third level during the D1 period and the D2 period.

[0526] The waveform shown in FIG39 can transmit multi-terminal driving data and helps to distinguish driving data from power signals.

[0527] In other embodiments, the waveform output by the modulation unit 251 is as shown in Figure 40, wherein the D1 period is address data, which can be used as the address by modulating the waveform of the second power supply signal; the D2 period is an invalid period, and the signal in this period is a signal at the third level and is not loaded with driving data. This period can pre-charge the subsequent power supply process to stabilize the high level of the second power supply signal, and can also provide processing time for the circuit structure that receives the address in the D1 period to process the address.

[0528] The power supply control circuit 60 is configured to separate the second power supply signal and the driving data in the driving data after obtaining the above-mentioned driving data, and convert the separated second power supply signal into voltage to power the driving chip, and transmit the separated original driving data to the driving chip to drive the light string to emit light.

[0529] In some embodiments, the backlight assembly 20 includes a demodulation unit 70, an input end of the demodulation unit 70 is coupled to the processor 250, a first output end is connected to the input end of the DC voltage conversion unit 601, and a second output end is connected to the input end of the control unit 602 and the driving data transmission unit 603. It is configured to obtain a second power supply signal loaded with driving data from the processor 250, output the second power supply signal from the first output end as the first power supply signal after signal decoupling, and output driving data from the second output end.

[0530] In some embodiments, the starting band of the original driving data includes address information, and the control unit 602 determines whether to output the first control signal based on the address information.

[0531] In some embodiments, the power supply control circuit 60 includes a demodulation unit 70, and an input terminal of the demodulation unit 70 is electrically connected to an input terminal of the power supply control circuit 60. A schematic diagram of the circuit structure of the power supply control circuit 60 is shown in FIG37.

[0532] In some other embodiments, the demodulation unit 70 is located outside the driver chip 202 , and the demodulation unit 70 is electrically connected to at least one power supply control circuit 60 .

[0533] Taking the demodulation unit 70 electrically connected to two power supply control circuits 60 as an example, the circuit connection relationship and control method of the demodulation unit 70 and the power supply control circuit 60 are explained. Among them, the circuit connection relationship of the demodulation unit 70 electrically connected to the two power supply control circuits 60 is shown in Figure 41.

[0534] In some embodiments, after the demodulation unit 70 decouples the second power supply signal loaded with driving data, it transmits the second power supply signal to the DC voltage conversion unit 601 in each corresponding power supply control circuit 60, and transmits the driving data to the control unit 602 and the driving data transmission unit 603 in each corresponding power supply control circuit 60.

[0535] The control unit 602 in each power supply control circuit 60 is configured to obtain address information from the driving data, and when the address information corresponds to its address information, control the corresponding DC voltage conversion unit 601 to supply power and control the corresponding driving data transmission unit 603 to output driving data.

[0536] In some embodiments, a gain amplifier is provided at the input end of the demodulation unit 70 , and is configured to perform gain amplification on the driving data to prevent attenuation of the decoupled signal and ensure the driving accuracy of the power supply control circuit 60 .

[0537] In the above technical solution, a modulation unit is set in the processor, and a corresponding demodulation unit is set in the backlight component, so that after the processor loads the driving data on the second power supply signal and outputs the modulated driving data, the modulated driving data is parsed to obtain the second power supply signal and driving data, so that the processor provides backlight for the driving chip on the backlight component, simplifying the structure of the circuit on the backlight component, and setting the power supply control circuit in the driving chip so that after the driving chip obtains the driving data, the power supply control circuit therein supplies power to the backlight driving circuit based on the driving data, and provides the driving data only after power-on, so that the backlight driving data generates a driving signal based on the driving data, drives the corresponding lamp beads to emit light, avoids the generation of leakage current when the driving chip obtains a low-power command, and reduces losses.

[0538] In other embodiments, the demodulation unit 70 is provided with address information, which is the address information of the drive groups corresponding to all the power supply control circuits 60 electrically connected to it. The demodulation unit 70 is configured to demodulate the signal of the start period after receiving the second power signal loaded with drive data from the processor 250. The duration of the start period is a preset duration, and the signal at the start end is the second power signal loaded with address information. If the address information is the same as the address information, demodulation continues; otherwise, demodulation stops. This circuit simplifies the operating loss of the demodulation unit.

[0539] In some embodiments, the demodulation unit 70 includes a demodulation circuit 701 , the input end of the demodulation circuit 701 is electrically connected to the output end of the processor 250 , and is configured to parse the modulated driving data and output a second power signal, driving data, and a target address.

[0540] In some embodiments, the demodulation unit 70 includes an address circuit 702, the input end of the address circuit 702 is electrically connected to the output end of the demodulation circuit 701, and the corresponding physical address is set in the address circuit 702, which is configured to control the demodulation circuit 701 to output a second power supply signal and drive data when the target address is the physical address corresponding to the address circuit.

[0541] The address circuit 702 is further configured to control the demodulation circuit 701 not to output the second power supply signal and driving data when the target address is not the physical address corresponding to the address circuit.

[0542] In some embodiments, the modulated driving data output by the processor 250 includes first modulated sub-data, and the first modulated sub-data includes a target address loaded on the second power signal.

[0543] In some embodiments, the demodulation circuit 701 is configured to parse the first modulated sub-data to obtain a target address;

[0544] In some embodiments, the address circuit 702 includes an address configuration circuit, which is electrically connected to the demodulation circuit and configured to obtain a target address. When the target address and the physical address corresponding to the address configuration circuit are the same, a parsing control signal is output; when the target address and the physical address corresponding to the address configuration circuit are different, no parsing control signal is output.

[0545] In some embodiments, the address configuration circuit in the address circuit 702 has the same structure as the address configuration circuit 6041 shown in FIG. 31 .

[0546] In some embodiments, a serial-to-parallel circuit is further provided between the demodulation circuit 701 and the address circuit 702 , and is configured to convert the address obtained by bit-by-bit analysis of the demodulation circuit 701 into an address for parallel transmission.

[0547] In some embodiments, the demodulation circuit 701 includes a reference circuit 703 , which is configured to output a reference electrical signal, wherein a voltage value of the reference electrical signal is the same as a voltage value of the second power signal.

[0548] In some embodiments, the reference circuit 703 may be a voltage divider circuit based on a resistor and a fixed voltage value, or may be a stable voltage value generated by a DA converter.

[0549] In some embodiments, the demodulation circuit 701 further includes a comparison circuit, wherein a first input terminal DIN of the comparison circuit is electrically connected to an output terminal of the processor 250, and a second input terminal of the comparison circuit is electrically connected to an output terminal of the reference circuit 703. The comparison circuit is configured to output a first level as the first data in the driving data when a voltage corresponding to the data input to the first terminal is greater than a voltage of a reference electrical signal obtained at the second terminal.

[0550] When the voltage corresponding to the data inputted at the first terminal is lower than the voltage of the reference electrical signal obtained at the second terminal, the second level is outputted as the second data in the driving data;

[0551] When the voltage corresponding to the data inputted at the first terminal is equal to the voltage of the reference electrical signal obtained at the second terminal, the third level is outputted as invalid data in the driving data.

[0552] In some embodiments, the circuit structure of the comparison circuit may be as shown in the example of FIG. 44 , including a comparator U1. The first input terminal CA+ of the comparator U1 is electrically connected to the output terminal of the processor 250, the second input terminal CA− is electrically connected to the output terminal of the reference circuit 703, and the power supply terminal of the comparator U1 is electrically connected to the power supply VLED. The comparator U1 is configured to obtain modulated driving data from its first input terminal and obtain a reference electrical signal Vref from its second input terminal, compare a voltage value corresponding to the modulated driving data with a voltage value of the reference electrical signal Vref, and output a high-level signal when the voltage value corresponding to the modulated driving data is greater than the voltage value of the reference electrical signal Vref.

[0553] When the voltage value corresponding to the modulated driving data is smaller than the voltage value of the reference electrical signal Vref, a low-level signal is output.

[0554] In some embodiments, the comparison circuit also includes a second capacitor C2, the first input terminal CA+ of the comparator U1 is electrically connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is electrically connected to the output end of the processor 250, and the second capacitor C2 is configured to adjust the voltage value of its first end based on its coupling effect and according to the change of the voltage value of its second end.

[0555] In some embodiments, the comparison circuit further includes a first capacitor C1 , a first end of which is electrically connected to the power supply terminal of the comparator U1 , a second end of which is grounded, and is configured to filter the power supply signal obtained by the comparator U1 .

[0556] In some embodiments, a controllable switch circuit is electrically connected in series between the first input terminal of the comparison circuit and the processor 250 , and the control terminal of the controllable switch circuit is electrically connected to the output terminal of the address circuit 702 . The controllable switch circuit is a normally closed switch circuit.

[0557] The controllable switch circuit is configured to remain in a closed state when the address circuit 702 outputs a parsing control signal, so as to continue receiving and parsing the drive data.

[0558] In some embodiments, the modulated driving data output by the processor 250 also includes invalid data, which is located after the first modulated sub-data. The data transmission duration of the invalid data is greater than the operating duration of the address circuit, so that the demodulation circuit 701 determines whether to parse the subsequently obtained data after the address circuit 702 completes the address analysis, thereby avoiding energy consumption caused by invalid analysis.

[0559] In some embodiments, the modulated driving data output by the processor 250 further includes second modulated sub-data, and the second modulated sub-data is located after the invalid data.

[0560] In the waveform diagram shown in FIG39 , the waveform in the D1 period corresponds to the first modulation sub-data, the waveform in the D2 period corresponds to the invalid data, and the waveform in the D3 period corresponds to the second modulation sub-data.

[0561] The second modulated sub-data includes driving data loaded on the second power signal;

[0562] The demodulation circuit 701 is further configured to parse the second modulated sub-data after obtaining the parsing control signal, and output a second power supply signal and driving data.

[0563] In some embodiments, the controllable switch circuit is further configured to turn off when the address circuit 702 outputs a parsing control signal at the second level, stop receiving the driving data, and not parse the driving data to reduce energy consumption generated by data parsing.

[0564] In some embodiments, the present application provides a backlight assembly, the circuit structure of which can be explained based on the structure illustrated in FIG. 42 .

[0565] The backlight assembly 20 includes at least one demodulation unit 701 , a plurality of driving chips and a lamp board. The lamp board includes lamp beads 301 distributed in an array.

[0566] One demodulation unit 701 and a plurality of driving chips form a driving group, and the address set in the demodulation unit 701 is the address of the driving group.

[0567] In some embodiments, the driving chip in the driving group is a controllable driving chip 204 including a backlight driving circuit 203 and a power supply control circuit 60 .

[0568] The demodulation unit 701 has an input terminal electrically connected to the processor 250 and an output terminal electrically connected to an input terminal of at least one corresponding driver chip, and is configured to parse the modulated drive data to obtain a second power supply signal and drive data;

[0569] The controllable driving chip 204 is configured to control the power supply control circuit 60 to supply power to the backlight driving circuit 203 based on the driving data, so that after the backlight driving circuit 203 is powered on, it generates a driving signal based on the driving data provided by the power supply control circuit 60 to drive the corresponding lamp beads to emit light.

[0570] In some embodiments, the above-mentioned driving group also includes at least one driving chip 202, the power supply end of at least one driving chip 202 is electrically connected to the power supply end of the corresponding controllable driving chip 204, the data input end of the driving chip 202 and the data output end of the controllable driving chip 204 can be electrically connected, and can also be electrically connected to the data output end of the previous driving chip 202.

[0571] In some embodiments, each driving group in the backlight assembly may include a power supply control circuit 60 and multiple driving chips 202 .

[0572] The structure of the above-mentioned driving group is explained below using the circuit structure shown in Figure 43.

[0573] The processor 250 includes a modulation unit 251, and the processor 250 is configured to obtain the second power signal and the driving data, and output the modulated driving data through the modulation unit, where the modulated driving data includes the driving data loaded on the second power signal;

[0574] The input end of the power supply control circuit 60 is electrically connected to the processor 250, its first output end is electrically connected to the power supply end of the corresponding driver chip 202, and its second output end is connected to the data input end of the corresponding driver chip 202. The power supply control circuit includes a demodulation unit 70. The power supply control circuit 60 is configured to demodulate the modulated drive data through the demodulation unit 60, and output the circuit power supply signal and drive data so that after the target driver chip is powered on, the corresponding lamp bead is driven to emit light based on the drive data.

[0575] In some embodiments, when the power supply control circuit 60 only includes the demodulation unit 70 , the voltage value of the second power supply signal is the same as the voltage value of the circuit power supply signal.

[0576] The processor 250 is further configured to send modulated driving data to the power supply control circuit of the corresponding driving group based on the address of the target driving chip; the driving data sequentially includes the target address and the driving data loaded on the second power signal;

[0577] The demodulation unit 70 is electrically connected to the processor 250. The demodulation unit 250 is provided with the address of the power supply control circuit 60 and is configured to parse the modulated drive data and output the second power signal and the drive data when the target address is consistent with the address of the power supply control circuit 60.

[0578] When the target address is inconsistent with the address of the power supply control circuit, the driving data loaded on the second power signal is not parsed, and the second power signal and the driving data are not output;

[0579] The output timing of the driving data is later than the output timing of the second power signal.

[0580] Figure 45 is a schematic diagram of the positional relationship between lamp beads and corresponding liquid crystal molecules according to some embodiments.

[0581] In some embodiments, the display panel 10 may include liquid crystal molecules distributed in an array.

[0582] In some embodiments, the liquid crystal molecules of the display panel 10 are scanned row by row, and a row of lamp beads 301 corresponds to a row of liquid crystal molecules 101 , and the lamp beads 301 are located below the liquid crystal molecules 101 , as shown in FIG. 45 .

[0583] In some embodiments, the liquid crystal molecules of the display panel 10 are scanned column by column, and one column of the lamp beads 301 corresponds to one column of the liquid crystal molecules 101 .

[0584] When the liquid crystal molecules are scanned line by line, the driving circuit in the backlight assembly drives the lamp beads in each row to emit light based on the driving data, and the processor controls the liquid crystal molecules in the corresponding row to deflect and display.

[0585] In some embodiments, when a display device continuously displays multiple frames of images, the liquid crystal molecules maintain a first deflection angle after the display panel is powered on or after displaying the previous frame of image data. After receiving a display trigger signal for the current frame of image data, the processor controls the liquid crystal molecules to adjust their deflection angles based on the display data corresponding to the pixel at which the liquid crystal molecules are located in the current frame, and also controls the corresponding light beads to adjust their brightness.

[0586] Since the response speed of liquid crystal molecules is lower than that of miniLED or microLED, there is a delay between the time when the deflection angle of the liquid crystal molecules is adjusted to within the preset angle range and the time when the lamp beads adjust the brightness to emit light. The schematic diagram of the delay characteristic waveform is shown in Figure 46.

[0587] In FIG46 , a0 is a first deflection angle, a1 is a second deflection angle corresponding to the current frame display data, a2 is a deflection angle that can normally display the current frame display data, and a2 to a3 are the aforementioned preset angle ranges, where a2 is determined based on the angle difference between the first deflection angle a0 and the second deflection angle a1 and a preset ratio. In some embodiments, the preset ratio is one-half.

[0588] Continuing with Figure 46, when the deflection angle of the liquid crystal molecules is between a0 and a2 (i.e., within the t0 to t1 period of each frame display) and the lamp beads provide backlight, the display device displays the transition image from the previous frame to the current frame. Only when the deflection angle of the liquid crystal molecules is between a2 and a1 (i.e., within the t1 to t2 period of each frame display) and the lamp beads provide backlight, can the display device correctly display the image data of the current frame. When multiple frames are played continuously, the human eye can observe the phenomenon of ghosting between t0 and t1 of each frame, affecting the user's viewing experience.

[0589] In some embodiments, the period t0 to t1 of each frame is determined as an unstable period of the liquid crystal molecules, and the period t1 to t2 of each frame is determined as a stable period of the liquid crystal molecules.

[0590] In related technologies, to address the streaking phenomenon caused by the slow response of liquid crystal molecules in the above-mentioned display panels, black frame insertion (BFI) is used to avoid displaying during the unstable periods of the liquid crystal molecules. That is, during the unstable period of the liquid crystal molecules during the display of each frame of image, the backlight is turned off to prevent the user from observing the streaking phenomenon caused by the deflection process of the liquid crystal molecules.

[0591] As shown in Figure 46, the angle range a0 to a2 is the unstable angle range of the liquid crystal molecules. When the angle of the liquid crystal molecule is within the period t0 to t1 corresponding to the period a0 to a2, the corresponding LED is controlled not to emit light, and the user cannot observe the image displayed during t0 to t1. This operation is called black insertion, and the period t0 to t1 when the image is not displayed is called the black insertion period. The length of this black insertion period is determined based on the response characteristics of the liquid crystal molecules. Generally, the same black insertion period is applied to the same liquid crystal molecule during the display of different frames.

[0592] In some embodiments, to improve the smoothness and clarity of the display device's images, some LCD display devices may use variable refresh rate (VRR) technology, which dynamically adjusts the display cycle of the display panel and backlight assembly in the display device according to the current frame rate effect to adjust the refresh rate of the image display.

[0593] Taking the display device continuously displaying three frames of images as an example, the BFI technology applied to VRR technology is explained.

[0594] Figure 47 is a waveform diagram of the BFI technology used in VRR technology. As shown in Figure 47, in response to three frame start trigger signals, the display device displays three consecutive frames of images, where the refresh rates applied to the three adjacent frames are different, namely 144Hz, 80Hz, and 100Hz. The larger the refresh rate, the shorter the corresponding frame display time, that is, T1 <T3<T2。

[0595] During each frame display period, since the black insertion time is the same, the light-emitting time is different and the black insertion ratio is different. When the driving data generated corresponding to three consecutive frames of image data is the same, the lower the refresh rate, the brighter the backlight brightness provided by the lamp beads.

[0596] When displaying the same image, the display device generally keeps the backlight brightness unchanged.

[0597] When displaying the same picture based on the three different refresh rates mentioned above, the display device generates the same driving data based on the same picture. Due to different black insertion ratios, the backlight brightness of the three frames displayed by the display device is different, resulting in flickering in the display device.

[0598] To this end, an embodiment of the present application provides a display device and a backlight control method thereof. After the processor in the display device completes the black insertion operation, it continues to provide driving data based on the backlight data. The backlight component can continuously provide backlight and adjust the average brightness of each frame of the picture display based on the backlight to keep it consistent, thereby reducing the flickering phenomenon in the picture display.

[0599] The following embodiments of the present application are described in detail in conjunction with specific examples. The following specific examples can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0600] In some embodiments, the processor may be configured to obtain image data of a frame and a frame start trigger signal.

[0601] In some embodiments, the processor obtains image data of the current frame based on the received video signal.

[0602] The image data may include display data and backlight data.

[0603] In some embodiments, the processor can be configured to obtain a frame start trigger signal and a line synchronization signal at the beginning of each frame, calculate the display duration of the current frame based on the line synchronization signal, and determine the display period of the current frame based on the frame start trigger signal and the display duration of the current frame.

[0604] In some embodiments, the frame start trigger signal may be a Vsync signal, or a time point represented by other forms, such as a software command, etc., which is not specifically limited here.

[0605] In some embodiments, the horizontal synchronization signal is an Hsync signal.

[0606] In some embodiments, the processor may be configured to calculate a refresh rate of the current frame based on the horizontal synchronization signal, and determine a display duration of the current frame based on the refresh rate of the current frame.

[0607] Calculating the refresh rate of the current frame based on the line synchronization signal may include: after obtaining the frame start trigger signal, determining to enter a new frame display, and in the process of line-by-line refresh, each time an Hsync signal is obtained, the image display of a scan line (or scan column) will start: the flip state of the liquid crystal molecules in the row is adjusted, and the luminous state of the lamp beads corresponding to the liquid crystal molecules in the row is adjusted.

[0608] Since the number of rows of liquid crystal molecules in the display panel is fixed, after obtaining two Hsync signals during the display period of the current frame, the frequency of the line synchronization signal in the current frame is determined based on the above two Hsync signals, and the refresh rate of the current frame is determined by dividing the frequency of the line synchronization signal by the number of rows.

[0609] In some embodiments, when calculating the display duration of a frame based on the refresh rate obtained by the aforementioned calculation, the quotient of 1 divided by the refresh rate is used as the display duration of the frame corresponding to the refresh rate. For example, the display period corresponding to 144 Hz is 1 / 144 seconds, and the display period corresponding to 80 Hz is 1 / 80 seconds.

[0610] In some embodiments, the processor obtains a frame start trigger signal at the start of each frame to determine the start time of the display period, and calculates the end time of the current frame based on the start time and the display duration of the current frame to determine the display period of the current frame.

[0611] In some embodiments, in the display panel, multiple liquid crystals displayed simultaneously are grouped into liquid crystal molecule groups based on a scanning method, and the division method of the light emitting unit groups in the backlight assembly is determined according to the division method of the liquid crystal molecule groups.

[0612] In some examples, in a display device based on row scanning display, the liquid crystal molecule groups and the light-emitting unit groups are divided by rows; in a display device based on column scanning, the liquid crystal molecule groups and the light-emitting unit groups are divided by columns.

[0613] In practice, the number of rows or columns of lamp beads in each light-emitting unit group can be the same. In this way, the corresponding number of rows and columns in each backlight data segment is the same. When the processor processes the data, it is not necessary to distinguish between the backlight data segments, thereby reducing the processing burden of the processor and improving the processing efficiency of the processor. Of course, the number of rows or columns of lamp beads in each light-emitting unit group can also be different. In contrast, this example does not impose any restrictions.

[0614] Taking the row-by-row scanning of the liquid crystal molecule group as an example, the liquid crystal molecule group of each row is flipped row by row according to the preset scanning order. The moment when the liquid crystal molecules in each row start to flip is the starting moment of the display period of the corresponding light-emitting display group in the current frame. When the display device displays a frame of picture, according to the preset scanning order, the delay time of the starting moment of the display period of each row of the light-emitting display group relative to the moment when the processor obtains the frame start trigger signal gradually increases.

[0615] In some embodiments, the processor may be configured to, in response to a frame start trigger signal, not output driving data during a black insertion period in a current frame display period.

[0616] The black insertion period may include an unstable period of liquid crystal molecules in the current frame.

[0617] In some embodiments, the backlight assembly 20 may be configured to not provide backlight when no driving data is obtained, and the display device does not display an image.

[0618] In some embodiments, the processor may be configured to determine the initial dimming data based on the backlight data within at most two light emitting periods in the current frame display period.

[0619] At most two light emitting periods are located within the stable periods of the liquid crystal molecules in the display panel.

[0620] In each frame display period, the non-black insertion period is the total lighting period.

[0621] The duration of each frame display period is determined based on the refresh rate of the current frame, which is less than or equal to the maximum refresh rate of the display panel.

[0622] In some embodiments, the maximum refresh rate of the display panel is generally 144 Hz.

[0623] In some embodiments, the initial dimming data is dimming data determined by the processor based on the backlight data after considering backlight black insertion when the refresh rate of the current frame display period is the maximum refresh rate of the display device.

[0624] In some embodiments, the processor may be configured to output driving data based on the initial dimming data, and the driving data may include a current value corresponding to each light-emitting period.

[0625] The average current value of the current values ​​corresponding to at most two light-emitting periods in the current frame display period is the product of the initial dimming data and the light-emitting ratio.

[0626] In some embodiments, the sum of the luminous ratio and the black insertion ratio is 1. The black insertion ratio is the ratio of the black insertion time determined for the maximum refresh rate of the display panel to the total display time period. The black insertion time is determined based on the deflection characteristics of the liquid crystal molecules on the display panel.

[0627] In some embodiments, backlight assembly 20 may be configured to provide backlight based on the driving data, and the greater the average current value, the brighter the backlight generated by backlight assembly 20 .

[0628] When the display device displays multiple frames of images continuously, when the refresh rates are different and the displayed images are the same, since the average current value obtained by the backlight component 20 is the same, the average brightness of the backlight provided by the backlight component 20 during each frame display period remains consistent, thereby reducing the flickering phenomenon in the display image.

[0629] Figure 48 is a flow chart of a backlight control method for a display device according to some embodiments, wherein in this embodiment, a processor executes the backlight control method provided in this embodiment. As shown in Figure 48, the backlight control method may include the following steps:

[0630] S401: The processor obtains image data of a frame and a frame start trigger signal; the image data may include backlight data;

[0631] S402: The processor does not output driving data during a black insertion period in a current frame display period in response to a frame start trigger signal.

[0632] S403: The processor determines initial dimming data based on backlight data within at most two light-emitting periods in the current frame display period.

[0633] S404: outputting driving data based on the initial dimming data, so that the backlight assembly provides backlight based on the driving data; the driving data may include current values ​​corresponding to each light-emitting period;

[0634] The average current value of the current values ​​corresponding to at most two light-emitting periods in the current frame display period is the product of the initial dimming data and the light-emitting ratio.

[0635] In the above embodiment, after obtaining the image data of a frame and the frame start trigger signal, the processor in the display device responds to the frame start trigger signal to control the backlight component to complete the black insertion operation, and then determines the initial dimming data based on the backlight data. Based on the initial dimming data, the drive data is output so that the average current value obtained by the backlight component in each frame of the picture display is the same, and the corresponding average brightness of the backlight provided is consistent, thereby reducing the flickering phenomenon in the picture display.

[0636] In some embodiments, when the processor generates driving data to regulate the light emission of the backlight assembly 20 , the light emission brightness of at most two light emission periods may be uniformly regulated.

[0637] That is, the processor determines the initial dimming data based on the backlight data, determines the stable current value based on the total luminous duration and black insertion duration of at most two luminous periods, and continuously outputs driving data with a current value of the stable current value within at most two luminous periods, so that the average brightness generated by the backlight component 20 within a frame display period based on the stable current value is the same.

[0638] The above embodiment is explained using the example of continuously displaying three frames of images at different refresh rates. A schematic diagram of the output of the stable current is shown in FIG49 . The display device continuously displays images for three time periods T1, T2, and T3, with refresh rates of 144 Hz, 72 Hz, and 100 Hz, respectively. The refresh rate corresponding to time period T1 is the maximum refresh rate.

[0639] In Figure 49, when the backlight assembly displays the same average brightness in three display periods, it outputs a first stable current in the luminous period within the T1 period, a second stable current in the luminous period within the T2 period, and a third stable current in the luminous period within the T3 period, wherein the luminous period of the T1 period may include the first luminous period, the luminous period of the T2 period may include the first luminous period and the second luminous period, and the luminous period of the T3 period may include the first luminous period and the second luminous period.

[0640] Taking the black insertion time into consideration, based on the above three stable currents and the corresponding light-emitting time, it is determined that the average brightness in the T1 period, the T2 period, and the T3 period is the same.

[0641] In one embodiment, the relationship between the stable current amplitude and the period length of the above three time periods is: (I1×(T1-tD)) / T1=(I2×(T2-tD)) / T2=(I3×(T3-tD)) / T3, wherein I1 represents the current value of the first stable current, I2 represents the current value of the second stable current, I3 represents the current value of the third stable current, T1 represents the duration of the T1 period, T2 represents the duration of the T2 period, T3 represents the duration of the T3 period, and tD represents the duration of the black insertion period.

[0642] In some embodiments, when determining the total luminous duration of at most two luminous periods, based on the refresh rate, the backlight duty cycle corresponding to the refresh rate of the current frame is determined from the locally stored mapping relationship between the refresh rate and the backlight duty cycle.

[0643] The backlight duty cycle represents the proportion of time that the backlight component can provide backlight during the current frame display period. Different refresh rates correspond to different backlight duty cycles.

[0644] In some embodiments, the processor may be configured to determine the duration that the backlight assembly 20 provides backlight in the current frame (the product of the backlight duty cycle and the length of the display period) based on the obtained backlight duty cycle and the length of the display period, which is the total duration of at most two light-emitting periods of the backlight assembly 20 in the display period of the current frame.

[0645] In some embodiments, when the refresh rate of the current frame is equal to the maximum refresh rate of the display panel, the current frame display period may include one light-emitting period; when the refresh rate of the current frame is less than the maximum refresh rate of the display panel, the current frame display period may include two light-emitting periods, and the current amplitudes of the two periods are the same.

[0646] In some embodiments, the processor may be configured to separately adjust the light emitting brightness of at most two light emitting periods based on the black insertion and light emitting operations corresponding to the maximum refresh rate.

[0647] In some embodiments, taking the maximum refresh rate of the display panel as a reference, when the refresh rate applied when the display device displays a frame of image data is equal to the maximum refresh rate, then at most two light-emitting periods only include the first light-emitting period.

[0648] During the first light-emitting period, the processor performs a black insertion operation according to a BFI-based Local Dimming operation strategy in the related art, and determines initial dimming data output during the light-emitting period. The initial dimming data may include an initial current value.

[0649] In some embodiments, the processor may be configured to obtain a maximum refresh rate of the display panel, determine an initial current value based on the maximum refresh rate and dimming data, and output the initial current value during the first light-emitting period.

[0650] In some embodiments, the processor can be configured to determine a first luminous duty cycle based on backlight data, output an initial current value in a first period within a first luminous period, and the duration of the first period is the product of the duration of the first luminous period and the first luminous duty cycle.

[0651] In some embodiments, the start time of the first light-emitting period is greater than or equal to a first preset time, and the first preset time is the sum of the start time of the current frame display period and the duration of the preset delay period. The preset delay period is determined based on the deflection angle change difference of the liquid crystal molecules and a preset ratio, wherein when the liquid crystal molecules adjust from the deflection angle a0 to the deflection angle a1, the deflection angle change difference is a1-a0, and the liquid crystal molecules are limited to enter a stable display state when the angle change is greater than or equal to the product of the deflection angle change difference and the preset ratio (such as a2), and the difference between the time t1 corresponding to a2 and the time t0 corresponding to a0 is determined as the preset delay period.

[0652] The black insertion period may include the above-mentioned preset delay period.

[0653] In some embodiments, the black insertion period may include an unstable period of liquid crystal molecules in the display panel; the black insertion period and the first light-emitting period constitute a reference display period;

[0654] When the refresh rate of the current frame is equal to the maximum refresh rate of the display panel, the duration of the current frame display period is the same as the duration of the reference display period.

[0655] In some embodiments, when the refresh rate applied when the display device displays a frame of image data is less than the maximum refresh rate, at most two light-emitting periods may include the first light-emitting period and the second light-emitting period in sequence.

[0656] The control strategy for the first light-emitting period remains unchanged.

[0657] In some embodiments, during the second light-emitting period, the processor may be configured to determine a current value corresponding to the second light-emitting period based on the initial current value and the light-emitting ratio, and output the corresponding current value during the second light-emitting period.

[0658] In some embodiments, the product of the initial current value and the light emission ratio is determined as the current value corresponding to the second light emission period.

[0659] The following is an example explanation of the processor's control strategy based on the waveform diagram shown in Figure 50.

[0660] Figure 50 shows a schematic waveform diagram of the drive data output by the processor when three frames of images are displayed continuously at different refresh rates. The refresh rate of 144 Hz corresponding to period T1 is the maximum refresh rate. Therefore, its display period only includes a non-luminous period D (i.e., a black insertion period) and a first luminous period. During non-luminous period D, the processor does not output drive data, and backlight assembly 20 does not emit light. During the first luminous period, the processor steadily outputs an initial current value, the amplitude of which is determined by the processor based on the backlight data.

[0661] In the T2 period adjacent to T1, the refresh rate 72Hz corresponding to this period is less than the maximum refresh rate, and the corresponding display duration is greater than the display duration of the T1 period. Then the T2 period is divided into two periods in sequence: the reference display period T21 and the second light-emitting period T22.

[0662] The reference display period T21 may include a non-luminous period D (ie, a black insertion period) and a first luminous period in sequence. The control strategy corresponding to the reference display period T21 is the same as the control strategy corresponding to the period T1.

[0663] During the second light-emitting period T22, the processor stably outputs a constant current. If the current value during period T22 is I0 and the current value during the first light-emitting period is Imax, then the relationship between the two currents is: Imax = I0 × light-emitting ratio. The light-emitting ratio is equal to the quotient of the duration of the first light-emitting period within the reference display period T21 divided by the duration of the reference display period T21.

[0664] That is to say, in the second light-emitting period T22, although the backlight continues to emit light, the brightness generated per unit time is the product of the brightness generated per unit time in the first light-emitting period and the light-emitting ratio. Therefore, during the entire T2 period, the brightness generated remains unchanged from the brightness in the T1 period.

[0665] In the above embodiment, the processor first outputs the initial current value in the first luminous period according to the black insertion strategy corresponding to the maximum refresh rate during each frame display period, and then determines the current value corresponding to the second luminous period according to the luminous ratio and the initial current value output in the first luminous period. Based on the second current value, the current is stably output in the remaining period, avoiding the display flicker phenomenon when applying VRR and BFI technology.

[0666] During the T3 period, the corresponding refresh rate of 100Hz is less than the maximum refresh rate, and the corresponding display duration is greater than the display duration of the T1 period. Similar to the T2 period, the T3 period is divided into two periods: the reference display period T31 and the second light-emitting period T32.

[0667] The manner of outputting the driving data during the T3 period is the same as the manner of outputting the driving data during the T2 period, and will not be described in detail here.

[0668] In some embodiments, the driving data may include pulse signal segments.

[0669] In some embodiments, the processor may be configured to continuously output the first pulse signal segment during the first light emitting period;

[0670] The amplitude of the first pulse signal segment is the initial current value, and the duty cycle of the first pulse signal segment is the first light-emitting duty cycle.

[0671] In some embodiments, the processor may be configured to continuously output the second pulse signal segment during the second light emitting period;

[0672] The amplitude of the second pulse signal segment is the current value corresponding to the second light-emitting period, and the duty cycle of the second pulse signal segment is the same as the duty cycle of the first pulse signal segment.

[0673] The current waveform diagram shown in FIG50 can be expressed as a PWM wave as shown in FIG52 .

[0674] In some embodiments, the processor can be configured to output the first pulse signal segment with the amplitude remaining unchanged during the first light-emitting period in each frame image display period, and to adjust the duty cycle of the first pulse signal segment based on the backlight data, wherein the larger the duty cycle, the brighter the backlight generated by the backlight assembly 20 based on the first pulse signal segment.

[0675] In other embodiments, the processor may be configured such that during the second luminous period, the amplitude of the output second pulse signal segment remains unchanged based on the unchanged amplitude of the first pulse signal segment, and the amplitude of the second pulse signal segment is the product of the amplitude of the first pulse signal segment and the luminous ratio, and the duty cycle is the same.

[0676] In this embodiment, the black insertion period corresponding to each backlight data can be guaranteed to remain unchanged, and the duration of the first light-emitting period is always fixed. For different backlight data, the light-emitting brightness can be adjusted by adjusting the duty cycle of the pulse signal segment in the first light-emitting period. Then, for each frame display period, it is only necessary to continuously output the pulse segment with the same duty cycle after the black insertion. It is only necessary to adjust the amplitude of the pulse segment, and there is no need to calculate the duration of the black insertion period, which further simplifies the calculation process.

[0677] Due to different black insertion strategies, in some processors, the processor inserts the black period D1, the first light-emitting period, and the black insertion period D2 in sequence within the display period corresponding to the maximum refresh rate. Only the position of the black insertion period is adjusted, as shown in Figures 51 and 53. Its control strategy is the same as that of the above embodiment and will not be repeated here.

[0678] The following explains the waveform of the driving data output by the processor for multiple rows of light-emitting display groups, wherein the liquid crystal molecule groups in the display panel are flipped and displayed row by row from top to bottom, and the corresponding light-emitting display groups in the backlight assembly also provide backlight row by row.

[0679] The waveform diagram of the driving data output by the processor for the backlight assembly is shown in FIG54 . FIG54 illustrates a backlight driving waveform diagram of the backlight assembly providing three consecutive frames of images.

[0680] For the first row of light-emitting display groups in the backlight assembly, the processor determines the first light-emitting delay D1 (0 in some embodiments) of the first row of light-emitting display groups in response to the frame start signal of the first frame, and determines the moment after the moment of obtaining the frame start signal is delayed by the first light-emitting delay D1 as the starting moment of the display period of the first row of light-emitting display groups. Since the refresh rate of the first frame is the maximum refresh rate, the display period of the first frame may include a black insertion period and a light-emitting period in sequence. During the light-emitting period, the current value and / or duty cycle of the driving data are adjusted based on the backlight data, and then transmitted to the corresponding first row of light-emitting display groups to drive them to emit light.

[0681] For the light-emitting display group of the i-th row in the backlight assembly, in response to the frame start signal of the first frame, the i-th light-emitting delay Di of the light-emitting display group of the i-th row is determined, and the moment after the moment of obtaining the frame start signal is delayed by the i-th light-emitting delay Di is determined as the starting moment of the display period of the light-emitting display group of the i-th row, which is the same as the emitting signal of the driving data of the light-emitting display group of the first row, and the black insertion and light-emitting operations are performed sequentially.

[0682] Similarly, after the processor obtains the frame start signal of the second frame, it delays the moment of obtaining the frame start signal of the second frame by the first light-emitting delay D1 and determines it as the start moment of the display period of the second frame of the first row light-emitting display group.

[0683] Because the refresh rate of the second frame (72Hz) is lower than the maximum refresh rate, during the first light-emitting period, black insertion and light-emitting operations are performed at the maximum refresh rate, and drive data, which may include an initial current value, is output based on the backlight data. During the second light-emitting period, a corresponding current value is determined based on the initial current value and light-emitting ratio determined during the first light-emitting period, and corresponding drive data is output.

[0684] When the current moment is the moment of the frame start signal of the second frame and the delay is the moment after the i-th light delay Di, the i-th row of light-emitting display groups starts to be controlled to display the second frame of the picture, and the same wave-emitting process of the first row of display light-emitting groups is performed to drive the i-th row of display light-emitting groups to provide backlight.

[0685] The display control process of the processor for the third frame is similar to that of the first two frames and will not be repeated here.

[0686] In some embodiments, the present application also provides a display device, as shown in Figure 2, wherein the display device may include a display panel; a processor coupled to the display panel may be configured to execute computer instructions so that the display device: obtains image data of a frame, a display period of the current frame and a black insertion ratio, and the image data may include backlight data; based on the black insertion ratio, divides the display period of the current frame into at least one black insertion period and at least one luminous period; the total duration of at least one black insertion period is the product of the duration of the display period of the current frame and the black insertion ratio; within at least one luminous period, based on the backlight data, outputs driving data; the backlight component coupled to the processor may be configured to provide backlight based on the driving data.

[0687] In some embodiments, to obtain a display period of a current frame, the processor may be configured to execute computer instructions to cause the display device to: obtain a frame start trigger signal and a line synchronization signal;

[0688] Calculate the refresh rate of the current frame based on the horizontal synchronization signal;

[0689] Based on the refresh rate of the current frame, determine the display duration of the current frame;

[0690] The display period of the current frame is determined based on the frame start trigger signal and the display duration of the current frame.

[0691] In some embodiments, based on the black insertion ratio, the display period of the current frame is divided into at least one black insertion period and at least one light-emitting period. The processor may be configured to:

[0692] Get the maximum refresh rate of the display panel;

[0693] Dividing the display period of the current frame into at least one display sub-period based on the maximum refresh rate;

[0694] Based on a preset black insertion sequence, each display sub-period is divided into at least one black insertion period and at least one light-emitting period;

[0695] In each display sub-period, the total duration of at least one black insertion period is the product of the duration of the display sub-period and the black insertion ratio.

[0696] In some embodiments, based on the maximum refresh rate, the display period of the current frame is divided into at least one display sub-period, and the processor may be configured to:

[0697] Determine a first display duration corresponding to the maximum refresh rate;

[0698] Dividing the display period of the current frame into at least one display sub-period based on the first display duration;

[0699] The at least one display sub-period may include at least one display sub-period having a first display duration.

[0700] In some embodiments, based on the first display duration, the display period of the current frame is divided into at least one display sub-period, and the processor may be configured to:

[0701] When the duration of the display period of the current frame is equal to N times the first display duration, the display period of the current frame is divided into N first display sub-periods; N is a positive integer;

[0702] When the duration of the display period of the current frame is not equal to N times the first display duration, the display period of the current frame is divided into at least one first display sub-period and one second display sub-period in sequence;

[0703] The duration of the first display sub-period is equal to the first display duration, and the duration of the second display sub-period is less than the first display duration.

[0704] In some embodiments, within each display sub-period, at least one black insertion period may include an unstable period of liquid crystal molecules in the display panel in the current frame.

[0705] In some embodiments, within each display sub-period, the stable period of the liquid crystal molecules in the display panel in the current frame may include a light-emitting period.

[0706] In some embodiments, during at least one light-emitting period, the processor may be configured to output driving data based on the backlight data:

[0707] Determining current data based on backlight data;

[0708] outputting current data during at least one light-emitting period;

[0709] The driving data may include current data.

[0710] In some embodiments, the current data may include pulse signal segments;

[0711] In at least one light emitting period, before continuously outputting the current data of the amplitude, the processor may be configured to:

[0712] Based on the backlight data, the duty cycle of the pulse signal segment is adjusted.

[0713] Taking into account the flicker problem of display devices, an embodiment of the present application also provides a display device and a backlight control method thereof. After obtaining the image data of a frame, the display period of the current frame and the black insertion ratio, the display device divides the display period of the current frame into at least one black insertion period and at least one luminous period based on the black insertion ratio. Since the ratio of the total duration of at least one black insertion period to the duration of the display period in which it is located is maintained at the black insertion ratio, after the processor outputs the driving data within the luminous period of each frame, the average brightness of the backlight component within the entire display period based on the driving data remains consistent, thereby reducing the flickering phenomenon of the display screen.

[0714] The implementation is described in detail below with reference to specific examples.

[0715] In some embodiments, the processor may be configured to obtain image data of a frame, a display period of the current frame, and a black insertion ratio.

[0716] In some embodiments, the processor may be configured to acquire image data of a current frame based on an input video signal. The image data may include backlight data and display data.

[0717] In some embodiments, the processor can be configured to obtain a frame start trigger signal and a line synchronization signal at the beginning of each frame, calculate the display duration of the current frame based on the line synchronization signal, and determine the display period of the current frame based on the frame start trigger signal and the display duration of the current frame.

[0718] In some embodiments, the frame start trigger signal may be a Vsync signal, or a time point represented by other forms, such as a software command, etc., which is not specifically limited here.

[0719] In some embodiments, the horizontal synchronization signal is an Hsync signal.

[0720] In some embodiments, the processor may be configured to calculate a refresh rate of the current frame based on the horizontal synchronization signal, and determine a display duration of the current frame based on the refresh rate of the current frame.

[0721] Calculating the refresh rate of the current frame based on the line synchronization signal may include: after obtaining the frame start trigger signal, determining to enter a new frame display, and in the process of line-by-line refresh, each time an Hsync signal is obtained, the image display of a scan line (or scan column) will start: the flip state of the liquid crystal molecules in the row is adjusted, and the luminous state of the lamp beads corresponding to the liquid crystal molecules in the row is adjusted.

[0722] Since the number of rows of liquid crystal molecules in the display panel is fixed, after obtaining two Hsync signals during the display period of the current frame, the frequency of the line synchronization signal in the current frame is determined based on the above two Hsync signals, and the refresh rate of the current frame is determined by dividing the frequency of the line synchronization signal by the number of rows.

[0723] In some embodiments, when calculating the display duration of a frame based on the refresh rate obtained by the aforementioned calculation, the quotient of 1 divided by the refresh rate is used as the display duration of the frame corresponding to the refresh rate. For example, the display period corresponding to 144 Hz is 1 / 144 seconds, and the display period corresponding to 80 Hz is 1 / 80 seconds.

[0724] In some embodiments, the processor obtains a frame start trigger signal at the start of each frame to determine the start time of the display period, and calculates the end time of the current frame based on the start time and the display duration of the current frame to determine the display period of the current frame.

[0725] In some embodiments, in the display panel, multiple liquid crystals displayed simultaneously are grouped into liquid crystal molecule groups based on a scanning method, and the division method of the light emitting unit groups in the backlight assembly is determined according to the division method of the liquid crystal molecule groups.

[0726] In some examples, in a display device based on row scanning display, the liquid crystal molecule groups and the light-emitting unit groups are divided by rows; in a display device based on column scanning, the liquid crystal molecule groups and the light-emitting unit groups are divided by columns.

[0727] In practice, the number of rows or columns of lamp beads in each light-emitting unit group can be the same. In this way, the corresponding number of rows and columns in each backlight data segment is the same. When the processor processes the data, it is not necessary to distinguish between the backlight data segments, thereby reducing the processing burden of the processor and improving the processing efficiency of the processor. Of course, the number of rows or columns of lamp beads in each light-emitting unit group can also be different. In contrast, this example does not impose any restrictions.

[0728] Taking the row-by-row scanning of the liquid crystal molecule group as an example, the liquid crystal molecule group of each row is flipped row by row according to the preset scanning order. The moment when the liquid crystal molecules in each row start to flip is the starting moment of the display period of the corresponding light-emitting display group in the current frame. When the display device displays a frame of picture, according to the preset scanning order, the delay time of the starting moment of the display period of each row of the light-emitting display group relative to the moment when the processor obtains the frame start trigger signal gradually increases.

[0729] In some embodiments, the processor may be configured to determine a black insertion ratio based on the display duration at the maximum refresh rate and the black insertion duration. The black insertion ratio is the quotient of the black insertion duration divided by the display duration at the maximum refresh rate.

[0730] In some embodiments, the processor may be configured to divide the display period of the current frame into at least one black insertion period and at least one light-emitting period based on the black insertion ratio.

[0731] When dividing the display period into various periods, it is necessary to ensure that the total duration of at least one black insertion period is the product of the duration of the display period of the current frame and the black insertion ratio, so that the light-emitting duration within the unit duration is the same and the backlight brightness is the same.

[0732] In some embodiments, the processor may be configured to output driving data based on the backlight data during at least one light emitting period.

[0733] In the backlight assembly, the driving circuit drives the corresponding luminous display group based on the driving data to not emit light during the black insertion period and to emit light during the luminous period, so that the average brightness of the backlight assembly based on the driving data remains consistent throughout the display period, thereby reducing the flickering phenomenon of the display screen.

[0734] Since the luminous period is shorter than that in the related art, resulting in brightness loss, the processor determines the corresponding light compensation coefficient based on different refresh rates and backlight data (for example: based on refresh rate, backlight data and light compensation coefficient) to increase the luminous brightness.

[0735] In some embodiments, the driving data may include current data, where the current data is determined based on the backlight data.

[0736] Since the luminous brightness of the luminous display group needs to be compensated during the luminous period, the amplitude of the current signal can be increased according to the light compensation coefficient. If a loss occurs during the compensation luminous period, the product of the light compensation coefficient and the amplitude of the current signal can be used as the amplitude of the compensated current signal.

[0737] In some embodiments, the current data may include a pulse signal segment, and the duty cycle of the pulse signal segment is regulated based on the backlight data. The product of the number of pulse signal segments in the luminous period and the duration of each pulse signal driving the luminescence is the luminous length of the luminous display group in the current display period. The luminous duration of the luminous display group can be increased by adjusting the duty cycle of the pulse signal segment based on the light compensation coefficient, thereby increasing the luminous brightness. For example: the luminous display group emits light when a high level in the pulse signal segment is obtained, and the duration of the high level in each pulse cycle is divided by the duration of the pulse cycle as the duty cycle. The product of the light compensation coefficient and the original duty cycle is determined as the duty cycle of the pulse signal after light compensation.

[0738] FIG55 is a flow chart of a backlight control method for a display device according to some embodiments. As shown in FIG55 , the backlight control method may include the following steps:

[0739] S405, obtaining image data of one frame, a display period of the current frame, and a black insertion ratio;

[0740] S406: Divide the display period of the current frame into at least one black insertion period and at least one light-emitting period based on the black insertion ratio;

[0741] S407 . Output driving data based on the backlight data in at least one light emitting period to drive the backlight assembly to provide backlight based on the driving data.

[0742] The following will explain the process of dividing at least one black insertion period and at least one light-emitting period within each frame display period.

[0743] In some embodiments, a maximum refresh rate of the display panel may be obtained.

[0744] In some embodiments, the maximum refresh rate of the display panel may be 144 Hz.

[0745] In some embodiments, the display period of the current frame may be divided into at least one display sub-period based on the maximum refresh rate.

[0746] When dividing the display sub-periods based on the maximum refresh rate, determine the first display duration corresponding to the maximum refresh rate, and divide the display period of the current frame into at least one display sub-period based on the first display duration, wherein it is necessary to ensure that within each display sub-period, the total duration of at least one black insertion period is the product of the duration of the display sub-period and the black insertion ratio.

[0747] In some embodiments, the at least one display sub-period may include at least one display sub-period with a first display duration, and the display sub-period with the first display duration is determined as the first display sub-period within the display period. Black insertion is performed within the first display sub-period according to the black insertion operation within the display period corresponding to the maximum refresh rate, thereby ensuring that the function of preventing smearing during the display process of liquid crystal molecules based on black insertion is properly implemented.

[0748] In some embodiments, each display sub-period is divided into at least one black insertion period and at least one light-emitting period based on a preset black insertion sequence.

[0749] In some embodiments, the display sub-period is divided into a black insertion period and a light-emitting period in sequence based on a preset black insertion order. As shown in the division of the T1 period in Figure 57, the T1 period may include the T1 black insertion period and the T1 light-emitting period in sequence, wherein the T1 black insertion period may include an unstable period in the liquid crystal molecule group, and the stable period of the liquid crystal molecule group may include the T1 light-emitting period and other periods in the display period except the first display sub-period (if any).

[0750] In some embodiments, the preset black insertion sequence of the display sub-periods may also be other black insertion sequences, for example: one black insertion period, one light-emitting period, and one black insertion period. No specific limitation is made here, and the description in this paragraph is just an example.

[0751] After the first display sub-period of the display period of the current frame is displayed, if the display process of the current frame has not yet ended, the remaining periods need to be divided.

[0752] In some embodiments, the remaining time period can be divided according to the black insertion ratio, as shown in the T2 time period in Figure 57. In this time period, the first display sub-period and the second display sub-period can be included in sequence. In the two display sub-periods, the black insertion period and the light-emitting period can be included in sequence, and the quotient of the duration of the black insertion period divided by the total duration of the corresponding display sub-period is the black insertion ratio.

[0753] The above embodiment is explained by taking the continuous display of three frames of images with different refresh rates as an example. As shown in Figure 57, the display device continuously displays three time periods T1, T2 and T3. The refresh rates of the three time periods are: 144Hz, 66Hz, and 100Hz, respectively. When the maximum refresh rate is 144Hz, the first time period T1 only needs to include one display sub-period.

[0754] In the second period T2, according to the maximum refresh rate, the display sub-period T21 and the display sub-period T22 may be included in sequence.

[0755] The duration of the display sub-period T11 is the same as the duration corresponding to the maximum refresh rate, and the corresponding black insertion duration and light-emitting duration are also the same.

[0756] In the display sub-period T22, according to the order of black insertion and then light emission and the black insertion ratio, it can include a compensation black insertion period T221 and a compensation light emission period T232 in sequence, and the duration of the period T221 is the product of the duration of the period T22 and the black insertion ratio.

[0757] Since the refresh rate of the third period T3 is less than the maximum refresh rate, the period division process of the second period T2 is referred to, and it is first divided into two display sub-periods, and then the black insertion order and black insertion ratio are preset to perform the corresponding black insertion operation, which will not be repeated here.

[0758] When the refresh rate is low, the compensation black insertion period and the compensation black insertion period being too long will still affect the display effect. Therefore, the display effect can be improved by adjusting the length of each display sub-period in the remaining period.

[0759] In some embodiments, the duration of the display sub-period can be set to be less than or equal to the first display duration corresponding to the maximum refresh rate.

[0760] In one case, the corresponding preset number of divisions can be determined based on the refresh rate of the current frame, and the remaining period can be divided into a preset number of display sub-periods of equal length. Within each display sub-period, the black insertion period and the display period are divided according to the preset black insertion order.

[0761] As shown in FIG58 , when the refresh rate of the second period T2 is 66 Hz, the remaining period is determined to be evenly divided into two display sub-periods T22 and T23 , and each display sub-period is divided according to the black insertion ratio and the preset black insertion order;

[0762] When the refresh rate of the third period T3 is 100 Hz, the remaining period is determined to be divided into a display sub-period T32 , and the display sub-period is divided according to the black insertion ratio and the black insertion sequence.

[0763] In some embodiments, in order to simplify the calculation process, the first display duration corresponding to the maximum refresh rate can be directly used as the duration of the divided time period. Then, when the duration of the display period of the current frame is equal to N times the first display duration, the display period of the current frame is divided into N first display sub-time periods.

[0764] When the length of the display period of the current frame is not equal to N times the first display period, the display period of the current frame is divided into at least one first display sub-period and one second display sub-period in sequence, N is a positive integer, the length of the first display sub-period is equal to the first display period, and the length of the second display sub-period is less than the first display period.

[0765] A waveform diagram of the driving data of the divided time periods is shown in Figure 59. In the second time period T2, if the duration of the remaining time period divided by the multiple of the first display time period is greater than 1 and less than 2, it is determined that the remaining time period can be divided into display sub-period T22 and display sub-period T23, wherein the duration of the display sub-period T22 is the same as the first display time period, and the duration of the display sub-period T23 is less than the first display time period. Within the display sub-period T22, the corresponding black insertion operation can still be performed using the black insertion process within the display period corresponding to the maximum refresh rate. Within the display sub-period T23, it can be divided according to the black insertion ratio and black insertion order.

[0766] In some embodiments, the current signal in the driving data during the light-emitting period may include a pulse signal segment, and the waveform diagram shown in FIG59 may be adjusted to the waveform diagram shown in FIG60. When adjusting the driving data based on the backlight data, the amplitude and / or duty cycle of each pulse in the pulse signal segment may be adjusted based on the backlight data.

[0767] Among them, when the refresh rates of two adjacent frames are different but the average brightness displayed by each light-emitting display group in the backlight component needs to be controlled to be the same, it is necessary to perform brightness compensation for the display period when the refresh rate is less than the maximum refresh rate. In response to the frame start signal, the light compensation coefficient is determined based on the refresh rate and backlight data, and the amplitude and duty cycle of the current signal are determined based on the light compensation coefficient and the backlight data.

[0768] FIG56 is a flowchart of a method for dividing a display time period according to some embodiments, which may include:

[0769] S4061. Obtain the maximum refresh rate of the display panel.

[0770] S4062: Divide the display period of the current frame into at least one display sub-period based on the maximum refresh rate.

[0771] S4063 : Based on a preset black insertion sequence, divide each display sub-period into at least one black insertion period and at least one light-emitting period.

[0772] The following explains the waveform of the driving data output for multiple rows of light-emitting display groups, wherein the liquid crystal molecule groups in the display panel are flipped and displayed row by row from top to bottom, and the corresponding light-emitting display groups in the backlight assembly also provide backlight row by row.

[0773] A waveform diagram of the driving data output by the backlight assembly is shown in FIG61 , which shows a backlight driving waveform diagram of the backlight assembly providing three consecutive frames of images.

[0774] For the first row of light-emitting display groups in the backlight assembly, in response to the frame start signal of the first frame, the first light-emitting delay D1 (0 in some embodiments) of the first row of light-emitting display groups is determined, and the moment after the moment of obtaining the frame start signal is delayed by the first light-emitting delay D1 is determined as the starting moment of the display period of the first row of light-emitting display groups. Since the refresh rate of the first frame is the maximum refresh rate, the display period of the first frame may include a black insertion period and a light-emitting period in sequence. During the light-emitting period, the amplitude and / or duty cycle of the driving data are adjusted based on the backlight data, and then transmitted to the corresponding first row of light-emitting display groups to drive them to emit light.

[0775] For the light-emitting display group of the i-th row in the backlight assembly, in response to the frame start signal of the first frame, the i-th light-emitting delay Di of the light-emitting display group of the i-th row is determined, and the moment after the moment of obtaining the frame start signal is delayed by the i-th light-emitting delay Di is determined as the starting moment of the display period of the light-emitting display group of the i-th row, which is the same as the transmitting signal of the driving data of the light-emitting display group of the first row, and the black insertion and light-emitting operations are performed sequentially, and the duration of the black insertion period and the duration of the light-emitting period are the same as the duration of the corresponding period of the light-emitting display group of the first row.

[0776] Similarly, after the processor obtains the frame start signal of the second frame, the moment of obtaining the frame start signal of the second frame is delayed by the first light-emitting delay D1 and determined as the start moment of the display period of the second frame of the first row light-emitting display group. Since the refresh rate of the second frame (66Hz) is less than the maximum refresh rate, the light compensation coefficient is determined based on the refresh rate of the current frame and the backlight data to adjust the amplitude of the current signal in the drive data, and the wave is emitted during the light-emitting period of the current display period based on the amplitude.

[0777] According to the maximum refresh rate, three display sub-periods are determined within the display period of the current frame, which may include two periods with a duration equal to the first display duration corresponding to the maximum refresh rate and one period less than the first display duration.

[0778] When the current moment is the moment of the frame start signal of the second frame and the delay is the moment after the i-th light delay Di, the i-th row of light-emitting display groups starts to be controlled to display the second frame of the picture, and the same wave-emitting process of the first row of display light-emitting groups is performed to drive the i-th row of display light-emitting groups to provide backlight.

[0779] The display control process of the processor for the third frame is similar to that of the first two frames and will not be repeated here.

[0780] In some embodiments, the present application further provides a display device, as shown in FIG2 , wherein the display device may include:

[0781] Display panel 10;

[0782] The processor coupled to the display panel 10 may be configured to:

[0783] Obtaining image data of a frame, a display period of the current frame, and a black insertion ratio, where the image data may include backlight data;

[0784] Based on the black insertion ratio, the display period of the current frame is divided into at least one black insertion period and at least one light-emitting period; the total duration of the at least one black insertion period is the product of the duration of the display period of the current frame and the black insertion ratio;

[0785] outputting driving data based on backlight data in at least one light emitting period;

[0786] A backlight assembly coupled to the processor may be configured to provide backlight based on the driving data.

[0787] In some embodiments, when obtaining the display period of the current frame, the processor may be specifically configured to:

[0788] Get the frame start trigger signal and line synchronization signal;

[0789] Calculate the refresh rate of the current frame based on the horizontal synchronization signal;

[0790] Based on the refresh rate of the current frame, determine the display duration of the current frame;

[0791] The display period of the current frame is determined based on the frame start trigger signal and the display duration of the current frame.

[0792] As another example, when the display period of the current frame is divided into at least one black insertion period and at least one light-emitting period based on the black insertion ratio, the processor may be specifically configured to: obtain a maximum refresh rate of the display panel;

[0793] Dividing the display period of the current frame into at least one display sub-period based on the maximum refresh rate;

[0794] Based on a preset black insertion sequence, each display sub-period is divided into at least one black insertion period and at least one light-emitting period;

[0795] In each display sub-period, the total duration of at least one black insertion period is the product of the duration of the display sub-period and the black insertion ratio.

[0796] Before dividing the display period of the current frame into at least one display sub-period based on the maximum refresh rate, the processor is further configured to:

[0797] Determine a first display duration corresponding to the maximum refresh rate;

[0798] Dividing the display period of the current frame into at least one display sub-period based on the first display duration;

[0799] The at least one display sub-period may include at least one display sub-period having a first display duration.

[0800] When dividing the display period of the current frame into at least one display sub-period based on the first display duration, the processor may be specifically configured to:

[0801] When the duration of the display period of the current frame is equal to N times the first display duration, the display period of the current frame is divided into N first display sub-periods; N is a positive integer;

[0802] When the duration of the display period of the current frame is not equal to N times the first display duration, the display period of the current frame is sequentially divided into at least one first display sub-period and one second display sub-period;

[0803] The duration of the first display sub-period is equal to the first display duration, and the duration of the second display sub-period is less than the first display duration.

[0804] Among them, in each display sub-period, at least one black insertion period may include an unstable period of liquid crystal molecules in the display panel in the current frame; in each display sub-period, the stable period of liquid crystal molecules in the display panel in the current frame may include a luminous period.

[0805] In some embodiments, the drive data may include current data;

[0806] When outputting driving data based on backlight data in at least one light-emitting period, the processor is specifically configured to:

[0807] determining an amplitude of the current data based on the backlight data;

[0808] During at least one light emitting period, current data is output.

[0809] The current data may include a pulse signal segment; and within at least one light-emitting period, before outputting the current data, the processor is further configured to:

[0810] Based on the backlight data, the duty cycle of the pulse signal segment is adjusted.

[0811] In the circuit structure shown in Figure 4, the driver chip 202 is provided with a data input terminal DIN and a data output terminal DOUT. The data input terminal DIN of the first driver chip 202 is electrically connected to the processor, and the data input terminals DIN of other driver chips 202 are electrically connected to the data output terminals DOUT of the previous driver chip 202.

[0812] Each driver chip 202 may be configured to obtain driving data from its data input terminal DIN, acquire a driving data segment of a preset length from the driving data, and transmit the driving data to the next driver chip 202 .

[0813] In some embodiments, a wire is electrically connected between the data output terminal DOUT of the last driver chip 202 and the processor, and the wire is configured to feed back the power supply status of the light-emitting unit groups driven by each driver chip 202 electrically connected in series to the processor.

[0814] In other embodiments, the last driver chip 202 may be configured to transmit the sampled power supply status from its data input terminal DIN to the data output terminal DOUT of the previous driver chip 202 after acquiring the driving data. Similarly, the first driver chip 202 feeds back the sampled power supply status of all driver chips connected in series with it to the processor, thereby simplifying the number of wirings on the backlight assembly and thus simplifying the circuit structure of the backlight assembly.

[0815] In some embodiments, the processor may be configured to generate a final feedback signal according to the feedback signals of each driver chip, and adjust the supply voltage output by the power supply circuit 13 based on the feedback signal so that each light-emitting unit group is not in an undervoltage state.

[0816] In the aforementioned scheme, which transmits the sampling state through the same channel that transmits drive data, the transmission of the sampling state affects the data line's transmission rate for drive data. This delays the driver chip's access to drive data, resulting in poor display quality. Therefore, ensuring the accuracy of supply voltage regulation while reducing the number of signals transmitted within the display device has become a key research priority.

[0817] In the present application, when the display device adjusts the power supply voltage of multiple light-emitting unit groups on the backlight assembly, it obtains the current-voltage relationship of the light-emitting unit group. When the display device obtains a frame of image data, the driving data of each light-emitting unit group is determined based on the backlight data in the image data. Since the display device adopts hybrid dimming, during the display of one frame of picture, the current value provided by each light-emitting unit group in the backlight assembly is always the same. Therefore, the power supply voltage can be determined based on the mapping relationship between the power supply voltage value and the current value determined in advance in the current value and the current-voltage relationship of the light-emitting unit group. It is no longer necessary to obtain feedback signals related to the light-emitting unit group from the driver chip, which reduces the number of transmission signals within the display device, reduces the demand for transmission signals to occupy the signal transmission lines within the display device, and reduces the computing power demand of the display device for signal processing. In addition, since the current-voltage relationship of the light-emitting unit group is pre-fitted, the consistency of the backlight circuit based on hybrid dimming ensures the accuracy of determining the power supply voltage, thereby ensuring the display accuracy.

[0818] The following describes the embodiments of the present application in detail with reference to specific examples. In the description of the present application, unless otherwise specified and limited, each term should be understood broadly in the art. The following describes the embodiments of the present application in conjunction with the accompanying drawings.

[0819] The execution subject of the power supply voltage adjustment method provided in this embodiment can be a power supply voltage adjustment device, which integrates a power supply module, a control module and a driver chip; it can also be an electronic device integrated with a power supply voltage adjustment device. This embodiment uses the execution subject as an example of the power supply voltage adjustment method to illustrate the power supply voltage adjustment method.

[0820] In one embodiment, the relationship between the image data of a frame and the current and voltage of the light emitting unit group can be obtained.

[0821] The image data may include backlight data and display data, wherein the backlight data is data for driving the backlight assembly to emit light, and the display data is data for driving the liquid crystal display panel to display.

[0822] The current-voltage relationship of a light-emitting unit group represents the mapping between the current flowing through the light-emitting unit group and the corresponding supply voltage values ​​when different supply voltage values ​​are applied to the light-emitting unit group. This current-voltage relationship is the mapping between the minimum supply voltage value provided by the power supply circuit and the preset current value when the driver chip is controlled to adjust the current value of the light-emitting unit group to the preset current value during the backlight assembly operation test, while ensuring that each light-emitting unit group does not suffer from undervoltage.

[0823] In some embodiments, the current-voltage relationship is determined by fitting when the display device leaves the factory;

[0824] In other embodiments, the current-voltage relationship is determined by fitting during a power-on initialization process of the display device.

[0825] In other embodiments, the current-voltage relationship is determined by sampling the supply voltage and current of the backlight sub-unit at preset time intervals during the operation of the display device and fitting the sampling information.

[0826] In one embodiment, driving data corresponding to each light-emitting unit group may be generated based on backlight data.

[0827] In some embodiments, the driving data may include a current value, which is data used to adjust the brightness of the light-emitting unit group per unit time. During the display device displaying each frame of an image, the backlight assembly provides backlight for the same duration in each frame. The driver chip may be configured to drive the light-emitting unit group to generate backlights of varying brightness based on the current value.

[0828] In some embodiments, the driving data may include a duty cycle, which is data that adjusts the duration of light emission by the light-emitting unit group during each frame display period. During the display device's display of each image frame, the backlight assembly provides the same backlight current value for each frame. The driver chip may be configured to drive the light-emitting unit group to generate backlights of varying brightness based on the duty cycle.

[0829] In some embodiments, the driving data may include a current value and a duty cycle, and the driving chip may be configured to jointly control the brightness of the light-emitting unit group based on the current value and the duty cycle.

[0830] In some embodiments, the display device uses hybrid dimming to adjust the backlight brightness of the backlight assembly in each frame.

[0831] When the display device displays a frame of image, the processor controls each light-emitting unit group to obtain the same current value but different duty cycles. When displaying brightness of different values, the brightness is distinguished by adjusting the size of the duty cycle.

[0832] When the display device displays different frames of images, the current values ​​obtained by the processor regulating each light-emitting unit group are not completely the same.

[0833] Figure 7 is a hybrid dimming schematic diagram provided by the present application, which may include driving data corresponding to four rows and five columns of light-emitting unit groups. The current value of each backlight sub-unit is the same, which is 70mA. The duty cycle of each backlight sub-unit is different, where the brighter the brightness, the greater the duty cycle, and the darker the brightness, the smaller the duty cycle.

[0834] In some embodiments, the corresponding supply voltage value may be determined based on the current-voltage relationship and the current value.

[0835] In some embodiments, the power supply circuit may be controlled to output a power supply voltage having a power supply voltage value to the light emitting unit group.

[0836] Since the current value of each backlight sub-unit is the same during the display of a frame of picture, ideally, the power supply voltage value corresponding to each backlight sub-unit is also the same. Therefore, when determining the power supply voltage of each backlight sub-unit, the current value is determined based on the backlight data generated by the component, and then based on the current value and the pre-fitted current-voltage relationship, the power supply voltage value that the power supply circuit needs to provide to the backlight sub-unit when the backlight sub-unit displays the image of the current frame is determined.

[0837] In one embodiment, a flow chart of a method for adjusting the supply voltage provided in the present application is shown in FIG62 , and may include:

[0838] S501: Obtaining a frame of image data and a current-voltage relationship of a light-emitting unit group;

[0839] S502: generating driving data corresponding to each light-emitting unit group based on the backlight data. The driving data may include a current value and a duty cycle. The current value corresponding to each light-emitting unit group is the same.

[0840] S503: Determine a corresponding supply voltage value based on the current-voltage relationship and the current value;

[0841] S504: Control the power supply circuit to output a power supply voltage having a power supply voltage value to the light emitting unit group.

[0842] In the above embodiment, when the display device adjusts the power supply voltage of multiple light-emitting unit groups on the backlight assembly, it obtains the current-voltage relationship of the light-emitting unit group. When the display device obtains a frame of image data, the drive data of each light-emitting unit group is determined based on the backlight data in the image data. Since the display device adopts hybrid dimming, during the display of one frame of picture, the current value provided by each light-emitting unit group in the backlight assembly is always the same. Therefore, the power supply voltage can be determined based on the mapping relationship between the power supply voltage value and the current value determined in advance in the current value and the current-voltage relationship of the light-emitting unit group. It is no longer necessary to obtain the feedback signal related to the light-emitting unit group from the driver chip, so the transmission path of the drive data is no longer occupied, thereby ensuring the transmission rate of the drive data. Moreover, since the current-voltage relationship of the light-emitting unit group is pre-fitted, the consistency of the backlight circuit based on hybrid dimming ensures the accuracy of determining the power supply voltage, thereby ensuring the display accuracy.

[0843] The fitting of the current-voltage relationship involved in the above embodiment is explained below.

[0844] In one embodiment, the processor obtains a supply voltage value of the light emitting unit group at a predetermined current and / or a current value of the light emitting unit group at the predetermined supply voltage value.

[0845] During the sampling of the voltage-current data group, since the power supply voltage value provided by the power supply circuit has a minimum value, when the current value of the light-emitting unit group is too small, the power supply voltage value required during the light-emitting process is also small. At this time, the minimum power supply voltage value provided by the power supply circuit is significantly greater than the power supply voltage required by the light-emitting unit group. When sampling the operating status of the light-emitting unit group, the power supply voltage value obtained when a small current flows through it is the minimum power supply voltage, and the sampling data may be inaccurate. Therefore, it is necessary to sample the minimum point within the effective light-emitting range of the light-emitting unit group (data corresponding to the minimum current and minimum supply voltage).

[0846] In one embodiment, when sampling the minimum point, the minimum supply voltage and the first preset current value that can be provided by the power supply circuit are obtained.

[0847] The first preset current is only a preset initial current, and its specific size is not specifically limited.

[0848] In one embodiment, the power supply circuit is controlled to output a minimum power supply voltage to the light emitting unit group, the driving chip is controlled to adjust the current value of the light emitting unit group to a first preset current value, and the state of each light emitting unit group on the backlight assembly is determined.

[0849] The state of the light emitting unit group may include an undervoltage state or an overvoltage state;

[0850] When the light emitting unit group is in an undervoltage state, it indicates that the actual current value flowing through the light emitting unit group is lower than the predetermined current value;

[0851] When the light emitting unit group is in an overvoltage state, it indicates that the actual current value flowing through the light emitting unit group is not lower than the predetermined current value.

[0852] It should be noted that in actual applications, the determination of undervoltage and overvoltage conditions is not limited to comparing the actual current value with the predetermined current value. In a voltage feedback circuit, it can also be a comparison between the actual voltage value of the light string and the predetermined voltage value. If the actual voltage value is less than the predetermined voltage value, it is an undervoltage condition; if the actual voltage value is not less than the predetermined voltage value, it is an overvoltage condition.

[0853] In one embodiment, the current value may be adjusted based on the state of each light emitting unit group to determine the current value corresponding to the minimum supply voltage.

[0854] During the current regulation process, if all light-emitting unit groups are in an overvoltage state, the current value of the light-emitting unit group is reduced according to the preset current step size until at least one light-emitting unit group is in an undervoltage state, and the current value of the light-emitting unit group when it was last in an overvoltage state is used to determine the current value of the light-emitting unit group under the minimum supply voltage;

[0855] If at least one light-emitting unit group is in an undervoltage state, the current value of the light-emitting unit group is increased according to a preset current step until all light-emitting unit groups are in an overvoltage state, and the current current value of the light-emitting unit group is determined as the current value of the light-emitting unit group under the minimum supply voltage value.

[0856] In the above embodiment, due to the differences in the driver chips, the driver chips are not always in an overvoltage state when the same current flows through them and the same supply voltage is obtained. Therefore, it is necessary to adjust the current value so that each driver chip is in an overvoltage state before determining that the current current value is the current value corresponding to the minimum supply voltage.

[0857] It should be noted that in actual applications, when it is detected that the light string changes from an overvoltage state to an undervoltage state, or from an undervoltage state to an overvoltage state, in addition to using the current current value as the current value under the predetermined supply voltage value as mentioned above, a current value can also be estimated between the current values ​​corresponding to the two states as the current value under the predetermined supply voltage value.

[0858] In some embodiments, when sampling other points, a preset supply voltage can be obtained, and the current value can be increased according to a preset current step until each light-emitting unit group is in an overvoltage state, and the current value is determined as the current value corresponding to the preset supply voltage.

[0859] In some embodiments, when the processor adjusts the current value corresponding to the preset supply voltage, the processor increases the current value according to the first preset current step until each light-emitting unit group is in an overvoltage state.

[0860] The current value is reduced according to the second preset current step until at least one light-emitting unit group is in an undervoltage state, and then the current value is increased according to the second preset current step until each light-emitting unit group is in an overvoltage state, until the number of cycles is greater than the preset cycle threshold, and the final determined current value is determined as the current value corresponding to the preset supply voltage.

[0861] The above embodiment is used to reduce the influence of the ripple voltage on the sampling state of the light emitting unit group during the current determination process.

[0862] In another embodiment, when sampling other points, a second preset current value may be obtained, where the second preset current value is greater than the current value of the light emitting unit group at the minimum supply voltage;

[0863] The supply voltage of the light emitting unit group is adjusted according to the first preset supply voltage step until all the light emitting unit groups are in an overvoltage state.

[0864] Among them, when the power supply voltage of the light-emitting unit group is adjusted from large to small, the power supply voltage of the light-emitting unit group is reduced according to the first preset power supply voltage step; when the power supply voltage of the light-emitting unit group is adjusted from small to large, the power supply voltage of the light-emitting unit group is increased according to the first preset power supply voltage step.

[0865] In one embodiment, after all the light-emitting unit groups are adjusted to an overvoltage state based on the first preset supply voltage step, a cycle is performed to reduce the supply voltage of the light-emitting unit group according to the second preset supply voltage step until at least one light-emitting unit group is in an undervoltage state, and then increase the supply voltage of the light-emitting unit group according to the second preset supply voltage step until all the light-emitting unit groups are in an overvoltage state, and the cycle is terminated when the number of cycles is greater than the preset number of cycles; the first preset supply voltage step is greater than the second preset supply voltage step to achieve coarse adjustment followed by fine adjustment.

[0866] The current supply voltage is determined as the supply voltage value of the light emitting unit group under the preset current value.

[0867] In the above embodiment, since there is ripple in the power supply voltage and the voltage fluctuation value of the ripple is much larger than the first preset power supply voltage step and the second preset power supply voltage step, when performing coarse adjustment based on the first preset power supply voltage step and fine adjustment based on the second preset power supply voltage step, it is necessary to determine multiple times whether the light-emitting unit group is in an overvoltage state before it can be determined that the obtained voltage-current data is not affected by the ripple.

[0868] In the above embodiment, when determining the supply voltage values ​​corresponding to at least two second preset current values, the preset current values ​​are arranged in ascending order, and then the voltage values ​​corresponding to the preset current values ​​are determined one by one according to the arrangement order.

[0869] When adjusting the supply voltage based on the first preset supply voltage step, the supply voltage can be increased according to the first preset supply voltage step based on the current supply voltage to roughly determine the supply voltage value corresponding to each preset current value. Then, for each preset current value, the supply voltage can be increased or decreased according to the second preset supply voltage step to determine the voltage value corresponding to the preset current value.

[0870] In some embodiments, when the current-voltage data sampling point is close to the minimum voltage value or the maximum voltage value that the power supply circuit can provide, the following operations may be performed during the aforementioned cycle of adjusting the supply voltage based on the second preset supply voltage compensation:

[0871] When the power supply voltage of the light-emitting unit group is reduced according to the second preset power supply voltage step, if the power supply voltage is reduced to the minimum power supply voltage, the first state value is accumulated; wherein, before the loop is performed, the processor initializes the first state value;

[0872] When the supply voltage of the light-emitting unit group is increased according to the second preset supply voltage step, if the supply voltage increases to a maximum supply voltage, accumulating the first state value;

[0873] When the first state value is greater than the preset state value, the loop ends.

[0874] The voltage-current sampling points determined above may be determined as edge points of the fitting curve.

[0875] In one embodiment, a voltage relationship mapping table is provided in the processor, which represents the mapping relationship between different power supply voltages and corresponding feedback voltages. The feedback voltage is the voltage generated based on the signal fed back by the driver chip to the processor when the power supply circuit provides the power supply voltage to the light-emitting unit group.

[0876] In some embodiments, the feedback voltage is inversely proportional to the supply voltage, so when the supply voltage is minimum, the feedback voltage is maximum, and vice versa.

[0877] The processor can sample the feedback voltage and the current value flowing through the light-emitting unit group to obtain multiple sets of feedback voltage-current data, and determine the supply voltage-current data based on at least two sets of feedback voltage-current data and the mapping relationship between the feedback voltage and the supply voltage to fit the current-voltage relationship.

[0878] In some embodiments, if the adjustment of the supply voltage is based on the feedback voltage, a preset range of the feedback voltage is set in the processor, and the processor outputs a maximum feedback voltage to the power supply circuit so that the power supply circuit outputs a minimum supply voltage based on the maximum feedback voltage, and based on this, regulates the current of each light-emitting unit group to determine the state of each light-emitting unit group.

[0879] When adjusting the supply voltage according to the first preset supply voltage step size, the current feedback voltage is reduced according to the first preset feedback voltage step size, and correspondingly, the power supply circuit increases the supply voltage according to the first preset supply voltage step size; wherein the first preset feedback voltage step size is the product of the first preset supply voltage step size and the preset ratio;

[0880] When adjusting the supply voltage according to the second preset supply voltage step, the current feedback voltage is reduced according to the second preset feedback voltage step, and correspondingly, the power supply circuit increases the supply voltage according to the second preset supply voltage step; wherein the second preset feedback voltage step is the product of the second preset supply voltage step and the preset ratio.

[0881] After the feedback voltage corresponding to the preset current value is determined, the power supply voltage that can be provided by the power supply circuit is determined based on the voltage relationship mapping table and the feedback voltage.

[0882] In some embodiments, during the process of determining the edge point based on the first state value, when the supply voltage of the light-emitting unit group is reduced according to the second preset supply voltage step size, if the feedback voltage corresponding to the supply voltage increases to the maximum feedback voltage, the first state value is accumulated; wherein, before the loop is performed, the processor initializes the first state value;

[0883] When the supply voltage of the light-emitting unit group is increased according to the second preset supply voltage step, if the feedback voltage corresponding to the supply voltage decreases to the minimum feedback voltage, the first state value is accumulated.

[0884] In one embodiment, the current-voltage relationship of the light-emitting unit group is fitted based on the predetermined current and the supply voltage value of the light-emitting unit group at the predetermined current, and / or the predetermined supply voltage and the current value of the light-emitting unit group at the predetermined supply voltage value.

[0885] When fitting the current-voltage relationship based on at least two sets of current-voltage data, linear fitting can be performed on the multiple sets of data, or fitting can be performed based on other fitting methods, such as least squares fitting, polynomial fitting, or non-parametric fitting.

[0886] After determining at least two sets of voltage-current data based on the above embodiment to fit the voltage-current relationship, the fitting accuracy of the current-voltage relationship is tested before application: at least one test current is determined within the current range in the current-voltage relationship, and the supply voltage value corresponding to each test current is determined based on the current-voltage relationship.

[0887] The processor controls the power supply circuit to provide the above-mentioned power supply voltage value to each light-emitting unit group, and controls the driver chip to provide the corresponding test current. Then, the driver chip samples the status of each light-emitting unit group.

[0888] In some embodiments, when the display tests the fitted current-voltage relationship, when it is determined that at least one light-emitting unit group is in an undervoltage state, the supply voltage value corresponding to each current value in the current-voltage relationship is compensated by a preset compensation voltage.

[0889] For example: after the current-voltage relationship fitting is completed, the processor determines that the current value in the driving data is 2A based on the backlight data, and determines that the corresponding supply voltage value is 5V in the current-voltage relationship. The processor controls the power supply circuit to output a supply voltage of 5V. When it is determined that at least one light-emitting unit group is in an undervoltage state based on the sampling state feedback from the driver chip, the power supply voltage output by the power supply circuit is controlled to increase the preset compensation voltage.

[0890] In one embodiment, the preset compensation voltage is 0.2V.

[0891] In other embodiments, the processor fits the current-voltage relationship at a preset temperature, and in the process of using the current-voltage relationship, measures the temperature of the display device. When it is determined that the temperature has been adjusted, the voltage adjustment coefficient is determined based on the current temperature and the preset temperature. When determining the supply voltage at the current temperature, the supply voltage corresponding to the current at the preset temperature is determined based on the current value and the current-voltage relationship, and the product of the supply voltage and the voltage adjustment coefficient is determined as the supply voltage at the current temperature.

[0892] In some embodiments, as the temperature of the display device decreases, the supply voltage value corresponding to the same current increases.

[0893] In some embodiments, the temperature measurement of the display device can be the temperature of the light board, the temperature of the driver chip, the temperature of the processor, or the temperature of the ambient temperature surrounding the display device. When determining the temperature, any of the above temperatures can be used, or a calculated value of at least two temperatures can be used, such as a weighted calculation.

[0894] To determine the minimum supply voltage-current, the present application provides a sampling process diagram, as shown in FIG63 , which may include:

[0895] S5001: Obtain a minimum supply voltage and a first preset current value that can be provided by the power supply circuit.

[0896] S5002: Control the power supply circuit to output a minimum power supply voltage to the light emitting unit group, and control the driving chip to adjust the current value of the light emitting unit group to a first preset current value.

[0897] S5003: Obtain the status of each light-emitting unit group on the display panel.

[0898] S5004: If all the light-emitting unit groups are in an overvoltage state, the current value of the light-emitting unit group is reduced according to a preset current step until at least one light-emitting unit group is in an undervoltage state, and the current value of the light-emitting unit group when it was last in an overvoltage state is determined as the current value of the light-emitting unit group under the minimum supply voltage.

[0899] S5005: If at least one light-emitting unit group is in an undervoltage state, the current value of the light-emitting unit group is increased according to a preset current step until all light-emitting unit groups are in an overvoltage state, and the current current value of the light-emitting unit group is determined as the current value of the light-emitting unit group under the minimum supply voltage value.

[0900] In order to determine the non-minimum supply voltage-current data, the present application provides a sampling process diagram, as shown in FIG64 , which may include:

[0901] S5006: Obtain a second preset current value.

[0902] S5007: Adjust the supply voltage of the light-emitting unit group according to the first preset supply voltage step until all the light-emitting unit groups are in an overvoltage state.

[0903] S5008: Initialize the first state value.

[0904] S5009: reducing the supply voltage of the light-emitting unit group according to a second preset supply voltage step size until at least one light-emitting unit group is in an undervoltage state, or until the feedback voltage corresponding to the supply voltage increases to a maximum feedback voltage.

[0905] S50010: If the feedback voltage corresponding to the power supply voltage increases to a maximum feedback voltage, the first state value is accumulated.

[0906] S50011: increasing the supply voltage of the light-emitting unit group according to the second preset supply voltage step until all the light-emitting unit groups are in an overvoltage state, or until the feedback voltage corresponding to the supply voltage drops to a minimum feedback voltage.

[0907] S50012: If the feedback voltage corresponding to the power supply voltage drops to a minimum feedback voltage, the first state value is accumulated.

[0908] S50013: Determine whether the first state value is greater than a preset state value, or whether the number of cycles is greater than a preset number of cycles.

[0909] If so, proceed to step S5009; otherwise, proceed to step S50014.

[0910] S50014: Determine the current supply voltage as the supply voltage value of the light-emitting unit group under the preset current value.

[0911] Based on the above example, in one embodiment, FIG65 is a schematic diagram of the structure of a driving circuit in an example, taking the example of each driving end of the driving chip being electrically connected to a light string to explain the circuit structure of the driving circuit.

[0912] As shown in FIG65 , the driving circuit may include multiple driver chips 202 and multiple open-drain modules 220. The multiple driver chips 202 correspond to the multiple open-drain modules 220. The multiple driver chips 202 are connected in series. Each driver chip 202 corresponds to at least one light string. The data input port of the first driver chip among the multiple driver chips 202 is connected to the control module 10. The data input port and / or data output port of each driver chip 202 is connected to the output end of the corresponding open-drain module 220. The open-drain module 220 is grounded. Determining the state of the light string based on the current state value may include:

[0913] For each driver chip, directly connect the data input port of the driver chip 202 to the data output port of the driver chip 202;

[0914] For each driver chip 202, if the current state value of the light string corresponding to the driver chip 202 is a first value, the output end of the open-drain module 220 is controlled to output a first level; if the current state value of the light string corresponding to the driver chip 202 is a second value, the output end of the open-drain module 220 is controlled to output a second level;

[0915] Obtain the output level of the data input port of the first driver chip 202. If the output level is the first level, it is determined that the light string is in an undervoltage state; if the output level is the second level, it is determined that the light string is in an overvoltage state. When the output ends of the open-drain modules 220 corresponding to the multiple driver chips 202 all output the second level, the data input port of the first driver chip 202 outputs the second level, otherwise it outputs the first level.

[0916] FIG65 is only an exemplary structure. In actual applications, the open-drain module 220 can be integrated into the driver chip 202 or connected to the outside of the driver chip 202. There is no limitation in this example.

[0917] As an example, FIG66 is a schematic diagram of a driving circuit in another example of the open-drain module 220. As shown in FIG66, the open-drain module 220 may include:

[0918] A first switch element V1, wherein a control terminal of the first switch element V1 is connected to the driver chip 202, one terminal of the first switch element V1 is connected to a data input port and / or a data output port of the driver chip 202, and the other terminal of the first switch element V1 is grounded;

[0919] a first pull-up resistor RT, one end of the first pull-up resistor RT being connected to one end of the first switch element V1 , and the other end of the first pull-up resistor RT receiving a fixed voltage V0 ;

[0920] The driving chip can be configured to output a first level to the control end of the first switching element V1 when the state value is a first value, so as to turn off the first switching element V1; and to output a second level to the control end of the first switching element V1 when the state value is a second value, so as to turn on the first switching element V1.

[0921] It should be noted that during normal operation, driving data is sent to the driver chip through the data input port Din of the driver chip. When executing S301, driving data is no longer input to the data input port of the driver chip 202, but the voltage of the data input port Din is detected to determine the current state of the light string.

[0922] It should also be noted that in actual applications, when the driver chip 202 is operating normally, multiple components are connected between the data input port Din and the data output port Dout. This makes it impossible to ensure that the voltage at the data input port Din is equal to the voltage at the data output port Dout. Therefore, in this example, the data input port Din is directly connected to the data output port Dout. A specific implementation method can be seen in Figures 65 and 66. That is, a second switch element V2 is provided in the driver chip 202. When S301 begins, a read instruction is sent to the driver chip 202. The driver chip 202 controls the conduction of the second switch element V2 to achieve a direct connection between the data input port Din and the data output port Dout. When S301 is completed, a completion instruction is sent to the driver chip 202. The driver chip 202 controls the disconnection of the second switch element V2 to achieve a disconnection between the data input port Din and the data output port Dout.

[0923] The following is an example of the present solution using the structure of the open-drain module in FIG66 as an example: As shown in FIG66 , the first switch element V1 is a PMOS tube, and the first level is a low level. The processor sends a read instruction to each driver chip 202; for each driver chip 202, the second switch element V2 is controlled to be turned on, and the data input port Din is directly connected to the data output port Dout; when the state value is the first value (0), the driver chip 202 outputs a low level F1 to the corresponding first switch element V1, the first switch element V1 is turned on, and the output level of the data input port Din of the driver chip 202 is a low level.

[0924] When the state value is the second value (1), the driver chip 202 outputs a high level F1 to the corresponding first switch element V1, the first switch element V1 is disconnected, and the output level of the data input port Din of the driver chip is a high level.

[0925] It can be understood that the output level of the data input port Din connected to the processor (the data input port of the first driver chip) is high only when the output level of each driver chip 202 is high; otherwise, it is low. In other words, if the light string corresponding to any driver chip is undervoltage, it is considered to be in an undervoltage state. Therefore, when the control module detects that the output level of the data input port Din of the first driver chip is high, it is considered that the light string is in an overvoltage state; otherwise, it is in an undervoltage state.

[0926] In this example, by directly connecting the data input port Din and the data output port Dout of the driver chip 202, the output levels of all serially connected driver chips 202 can be obtained by simply obtaining the data input port of the first driver chip 202, thereby determining the status of the light strings corresponding to all driver chips 202.

[0927] In another embodiment, FIG67 is a schematic structural diagram of a driving circuit in another example. As shown in FIG67 , there is only one driving chip 202 in the driving circuit. The data input port Din of the driving chip 202 is connected to the processor, one end of a first switching element V1, and one end of a first pull-up resistor RT. The other end of the first switching element V1 is grounded. The control end of the first switching element V1 is connected to the driving chip 202. The other end of the first pull-up resistor RT receives a fixed voltage V0. Determining the state of the light string based on the current state value may include:

[0928] Obtaining a current state value, and if the current state value is a first value, outputting a first level to a control terminal of a first switching element; if the current state value is a second value, outputting a second level to the first switching element; the first switching element is turned on when the control terminal receives the first level, and is turned off when the control terminal receives the second level;

[0929] The output level of the data input port of the driver chip 202 is obtained; if the output level is a first level, the light string is determined to be in an undervoltage state; if the output level is a second level, the light string is determined to be in an overvoltage state.

[0930] The driver chip 202 in this example outputs a corresponding output level based on the state value, so that the output end (DIN) of the open drain circuit composed of the first switching element and the pull-up resistor outputs a corresponding level, so that the control module can know the current state of the light string by detecting the level of the data input port Din of the driver chip, thereby achieving the purpose of obtaining the power supply voltage of the light string under the target current.

[0931] In actual applications, to save costs, backlight integration is becoming increasingly high, and the spacing between the driver chip and the lamp beads 301 is decreasing. When the driver chip outputs the same current to the lamp beads 301, the temperature of the driver chip and the lamp beads 301 in a backlight with a higher degree of integration will be higher. Excessive temperatures can affect the lifespan of the driver chip. Similarly, when the operating temperature of the lamp beads 301 is too high, it can cause problems such as changes in the emission wavelength of the lamp beads 301, a decrease in luminous efficiency, and a shortened lifespan. In actual applications, the greater the current output by the driver chip to the lamp beads 301, the higher the temperature of the driver chip and the lamp beads 301.

[0932] FIG68 is a schematic diagram of a temperature threshold control method according to some embodiments. As shown in FIG68 , before time t1, as the current increases, the temperature of the driver chip and the lamp beads gradually rises. At times t1 and t2, the temperature of the driver chip reaches the temperature threshold T1, immediately shutting down the driver chip or reducing the output current of the driver chip to a lower value. This large current change causes noticeable flickering in the displayed image. After times t1 and t2, the current decreases, and the temperature of the driver chip decreases. When the temperature of the driver chip drops to T2, the driver chip can output the driving current to the lamp beads according to the current display requirements of the display device.

[0933] It is understandable that setting a temperature threshold corresponding to the driver chip and immediately shutting down the driver chip or reducing the output current of the driver chip to a lower value when the temperature of the driver chip reaches the temperature threshold will cause the image displayed by the display device to flicker, and the accuracy and reliability of the backlight control will be low.

[0934] To this end, some embodiments of the present application provide a display device and a backlight control method thereof, wherein, if the temperature value of the current driver chip reaches the upper limit of the temperature range of the driver chip, the current reduction rate is determined according to the temperature value of the current driver chip, and the target output current value of the current driver chip is determined acco...

Claims

1. A display device, comprising: Display panel; a power supply circuit electrically connected to the display panel; at least one processor electrically connected to the display panel and the power supply circuit; a backlight assembly electrically connected to the at least one processor and the power supply circuit, the backlight assembly comprising a driving circuit and a light board; The light board includes lamp beads distributed in an array, at least one lamp bead is electrically connected to form a light-emitting unit group; The driving circuit includes at least one driving chip, each of which is provided with a power supply end, at least one driving end and a plurality of power supply ends, the power supply end is electrically connected to the power supply circuit, each of the driving ends is electrically connected to a plurality of light-emitting unit groups, and the plurality of light-emitting unit groups are electrically connected to the plurality of power supply ends respectively; Wherein, different driving ends are electrically connected to different light emitting unit groups.

2. The display device according to claim 1, wherein the display panel comprises liquid crystal molecules distributed in an array, and at least one liquid crystal molecule displayed simultaneously constitutes a liquid crystal molecule group; The plurality of light-emitting unit groups electrically connected to the driving chip correspond to a plurality of liquid crystal molecule groups; The plurality of light emitting unit groups electrically connected to each driving chip are distributed based on the first scanning direction and the second scanning direction of the plurality of liquid crystal molecule groups; A plurality of liquid crystal molecule groups arranged along the first scanning direction are displayed based on the same phase; A plurality of liquid crystal molecule groups arranged along the second scanning direction are displayed based on different phases. 3 . The display device according to claim 2 , wherein the plurality of light emitting unit groups electrically connected to each driving chip are arranged in the first scanning direction in the plurality of light emitting unit groups, and in the second scanning direction in the plurality of light emitting unit groups.

4. The display device according to claim 2, wherein the number of the plurality of light-emitting unit groups electrically connected to each driving chip arranged in the second scanning direction is at least two; The number of the at least two arranged terminals is less than or equal to the number of the power supply terminals; The number of the plurality of light emitting unit groups electrically connected to each driving end arranged in the second scanning direction is one.

5. The display device according to claim 2, wherein the number of the plurality of light emitting unit groups electrically connected to each driving end arranged in the second scanning direction is at least two; The number of the at least two arranged terminals is less than or equal to the number of the power supply terminals.

6. The display device according to claim 1, wherein the driver chip is provided with a plurality of power switches and a control unit; The input terminals of the plurality of power switches are coupled to the power terminal of the driving chip; The output ends of the multiple power switches are correspondingly connected to the multiple power supply ends; The control unit is electrically connected to control ends of the plurality of power switches.

7. The display device according to any one of claims 1 to 6, when at least two wires connected between the plurality of light-emitting unit groups and the driving chip are bridged, in the bridged region, an insulating layer is coated on the upper side of the bridged wire, and a conductive layer is coated on the upper side of the insulating layer; The conductive layer conducts electricity through the jumper wire.

8. The display device according to claim 7, In the bridging area, the insulating layer is coated on the upper side of the jumpered wire along the routing of the jumpered wire; The width of the insulating layer is greater than the width of the jumpered wire.

9. The display device according to claim 7, wherein a conductive layer is coated on the upper side of the insulating layer, comprising: Along the vertical direction of the routing direction of the jumpered routing, a first jumper wire and a second jumper wire are respectively provided on both sides of the insulating layer, the first jumper wire is connected to the first pad in the jumping area, and the second jumper wire is connected to the second pad in the jumping area, and the conductive layer is coated on the first pad, the second pad and the insulating layer between the first pad and the second pad. 10 . The display device according to claim 9 , wherein in the jumper region, the wires with narrower width are jumpered wires, and the wires with wider width are jumper wires.

11. A method for controlling a display device, the display device further comprising: a display panel, a power supply circuit, at least one processor and a light board; The light board includes lamp beads distributed in an array, at least one lamp bead is electrically connected to form a light-emitting unit group; The driving circuit is provided with an input end, at least one driving end and a plurality of power supply ends, the input end is electrically connected to the at least one processor, each of the driving ends corresponds to a plurality of light emitting unit groups, and the plurality of light emitting unit groups respectively correspond to the plurality of power supply ends; wherein different driving ends correspond to different light emitting unit groups; The method comprises: Obtaining a power signal provided by the power supply circuit and driving data provided by the at least one processor; Based on the driving data, the power supply signal is sequentially output from the power supply end, and the corresponding driving signal is output from the driving end to drive the light-emitting unit group corresponding to the power supply end and the driving end to emit light.

12. The method according to claim 11, wherein within a frame display period, the driving data comprises a plurality of pulse signal segments, and the plurality of pulse signal segments correspond to the plurality of power supply terminals; Based on the driving data, the power supply signal is sequentially output from the power supply end, and the corresponding driving signal is output from the driving end to drive the light-emitting unit group corresponding to the power supply end and the driving end to emit light, including: Based on the multiple pulse signal segments, the power signal is output from the corresponding power supply end in the power supply period corresponding to the pulse signal segment; the display cycle includes multiple power supply periods, and the multiple power supply periods do not intersect with each other; the multiple pulse signal segments correspond to the multiple power supply periods, and the multiple power supply periods correspond to the multiple power supply ends; In each of the power supply time periods, a driving signal is output based on the pulse signal segment to drive the light-emitting unit group electrically connected to the driving end to emit light.

13. The method according to claim 12, wherein the pulse signal segment comprises at least one first level signal and / or at least one second level signal; In each of the power supply periods, a driving signal is output based on the pulse signal segment to drive the light-emitting unit group electrically connected to the driving end to emit light, including: In each of the power supply periods, based on the first level signal in the pulse signal segment, a current is output from the driving end to drive the light emitting unit group electrically connected to the driving end to emit light; and / or In each of the power supply time periods, based on the second level signal in the pulse signal segment, no current is output from the driving end, and the light-emitting unit group electrically connected to the driving end is driven not to emit light.

14. The method according to claim 12 or 13, before outputting the power signal from the corresponding power supply end, the method may further include: Based on the multiple pulse signal segments, the power supply end that supplies power last in a display cycle is controlled to be the same as the power supply end that supplies power first in a next display cycle.

15. A method for controlling a display device, the display device comprising: Display panel, power supply circuit, light board and driving circuit; The light board includes lamp beads distributed in an array, at least one lamp bead is electrically connected in series to form a light-emitting unit group; The driving circuit is provided with an input end, at least one driving end and a plurality of power supply ends, the input end is electrically connected to the at least one processor, each of the driving ends corresponds to a plurality of light emitting unit groups, the plurality of light emitting unit groups respectively correspond to the plurality of power supply ends, wherein different driving ends correspond to different light emitting unit groups; The method comprises: After outputting driving data so that the driving circuit obtains the driving data and the power signal output by the power supply circuit, based on the driving data, the power signal is sequentially output from the power supply end, and the corresponding driving signal is output from the driving end to drive the light-emitting unit group corresponding to the power supply end and the driving end to emit light.

16. The method according to claim 15, further comprising: Obtaining display data, wherein the display data includes backlight data; Based on the backlight data, multiple pulse signal segments are provided in multiple power supply periods of each display cycle, so that the driving circuit drives the corresponding light-emitting unit group to emit light based on the pulse signal segments; The pulse signal segments correspond to the multiple power supply time periods, and each pulse signal segment corresponds to a plurality of light-emitting unit groups connected to each power supply end.

17. The method according to claim 16, providing a plurality of pulse signal segments in a plurality of power supply periods of each frame display cycle based on the backlight data, comprising: Obtaining a plurality of power supply time periods corresponding to the driving end of the driving circuit in each display cycle; The power supply period is a period during which each light-emitting unit group electrically connected to the driving end obtains power from the corresponding power supply end, and the arrangement order of each power supply period in the display cycle is the same as the power supply order of each power supply end of the driving circuit; Based on the backlight data, determining the light emission duty ratio and amplitude of the pulse signal segment within the power supply period; During the power supply period, a pulse signal segment is output based on the light emission duty ratio and the amplitude.

18. The method according to claim 17, wherein the display panel comprises liquid crystal molecules distributed in an array, and at least one liquid crystal molecule displayed simultaneously constitutes a liquid crystal molecule group; Obtaining a plurality of power supply time periods corresponding to each driving end of the driving circuit in each display cycle, comprising: Obtaining display periods of a plurality of light-emitting unit groups electrically connected to the driving end, wherein the scanning periods of the liquid crystal molecule groups corresponding to the plurality of light-emitting unit groups are the same; Based on the power-on sequence of the plurality of light emitting unit groups, the display cycle is sequentially divided into a plurality of power supply time periods, and each light emitting unit group corresponds to at least one power supply time period.

19. The method according to claim 17 or 18, before obtaining a plurality of power supply time periods corresponding to each driving end of the driving circuit, further comprising: Obtaining a frame start signal and a delay time of a liquid crystal molecule group corresponding to a light-emitting unit group; A display period corresponding to the light emitting unit group is determined based on the frame start signal and the delay time.

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