Imaging element and imaging device

Abstract

An imaging element according to one embodiment of the present disclosure includes: a first semiconductor substrate having a first surface and a second surface facing each other and including a plurality of pixels arranged in an array in an in-plane direction, a plurality of protrusions being provided on the first surface for each of the plurality of pixels; a plurality of photoelectric converters which are formed so as to be embedded in the first semiconductor substrate for each pixel and which generate electric charges in accordance with the amount of received light; a plurality of charge holding units provided on upper surfaces of the plurality of protrusions, respectively, and holding charges generated in the plurality of photoelectric converters; a second semiconductor substrate laminated on a first surface side of the first semiconductor substrate and provided with one or more pixel circuits that generate pixel signals based on charges generated by each of the plurality of photoelectric converters; and a gate of a transfer transistor disposed around the plurality of protrusions and transferring the charge held in the charge holding unit to the pixel circuit.

Description

Technical Field

[0001] The present disclosure relates to, for example, an imaging element and an imaging device having a three-dimensional structure. Background Art

[0002] In recent years, three-dimensional structure imaging elements have been developed to make imaging devices smaller and achieve high pixel density. For example, Patent Document 1 discloses an imaging element in which a first substrate including sensor pixels that perform photoelectric conversion and a second substrate including a readout circuit are stacked one above the other.

[0003] Citation list

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. WO 2019 / 131965 Summary of the invention

[0006] In view of this, it is expected that an imaging element having a three-dimensional structure as described above can reduce the generation of dark current.

[0007] It is desirable to provide an imaging element and an imaging device that can reduce the generation of dark current.

[0008] An imaging element of an embodiment of the present disclosure includes: a first semiconductor substrate, the first semiconductor substrate having a first surface and a second surface opposite to each other, and including a plurality of pixels arranged in an array in an in-plane direction, a plurality of protrusions being arranged on the first surface according to each of the plurality of pixels; a plurality of photoelectric converters, the plurality of photoelectric converters being formed in a manner embedded in the first semiconductor substrate according to each of the pixels, and generating charges according to the amount of received light; a plurality of charge holding units, the plurality of charge holding units being respectively arranged on the upper surfaces of the plurality of protrusions, and holding the charges generated in the plurality of photoelectric converters; a second semiconductor substrate, the second semiconductor substrate being stacked on the first surface side of the first semiconductor substrate, and being provided with one or more pixel circuits, the pixel circuits generating pixel signals based on the charges generated by each of the plurality of photoelectric converters; and a gate of a transfer transistor, the gate being arranged around the plurality of protrusions, and transferring the charges held in the charge holding units to the pixel circuits.

[0009] An imaging device according to one embodiment of the present disclosure includes the imaging element according to the above-described embodiment.

[0010] In an imaging element and an imaging device of an embodiment of the present disclosure, in a first semiconductor substrate having a first surface and a second surface opposite to each other and including a plurality of pixels arranged in an array in an in-plane direction, a plurality of protrusions are provided on the first surface in accordance with each of the plurality of pixels, a plurality of charge holding units for holding charges generated in a plurality of photoelectric converters are provided on upper surfaces of the plurality of protrusions, each charge holding unit is formed to be embedded in each pixel, and a gate of a transfer transistor for transferring the charges held in the charge holding unit to a pixel circuit is provided around the plurality of protrusions. Therefore, a distance in a height direction between the charge holding unit and the transfer gate is ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram illustrating a functional configuration example of an imaging device according to the first embodiment of the present disclosure.

[0012] Figure 2 It is shown Figure 1 A schematic plan view of the schematic configuration of the imaging device shown.

[0013] Figure 3 is a diagram showing the imaging device along Figure 2 A schematic diagram of the cross-sectional configuration along line II' is shown.

[0014] Figure 4 yes Figure 1 The equivalent circuit diagram of the pixel sharing unit is shown.

[0015] Figure 5 It is shown Figure 1 A schematic diagram of an example of a cross-sectional configuration of an imaging device shown.

[0016] Figure 6 It is shown Figure 5 A schematic diagram of an example of a planar layout of the first substrate is shown.

[0017] Fig. 7A It is shown Figure 5 A schematic cross-sectional view of the manufacturing process of the first substrate is shown.

[0018] Figure 7B It is shown Fig. 7A Schematic cross-sectional view of the process continuation.

[0019] Figure 7C It is shown Figure 7B Schematic cross-sectional view of the process continuation.

[0020] Fig.7D It is shown Figure 7C Schematic cross-sectional view of the process continuation.

[0021] Fig. 7EIt is shown Fig.7D Schematic cross-sectional view of the process continuation.

[0022] Figure 7F It is shown Fig. 7E Schematic cross-sectional view of the process continuation.

[0023] Figure 7G It is shown Figure 7F Schematic cross-sectional view of the process continuation.

[0024] Figure 7H It is shown Figure 7G Schematic cross-sectional view of the process continuation.

[0025] Fig.7I It is shown Figure 7H Schematic cross-sectional view of the process continuation.

[0026] Figure 7J It is shown Fig.7I Schematic cross-sectional view of the process continuation.

[0027] Figure 7K It is shown Figure 7J Schematic cross-sectional view of the process continuation.

[0028] Figure 7L It is shown Figure 7K Schematic cross-sectional view of the process continuation.

[0029] Figure 8 It is used to explain Figure 3 A schematic diagram of the signal path of an input signal of an imaging device is shown.

[0030] Fig. 9 It is used to explain Figure 3 Schematic diagram of the signal path of the pixel signal of the imaging device shown.

[0031] Fig. 10A is a schematic diagram showing an example of a planar layout of pixels of a general imaging device.

[0032] Fig. 10B is shown along Fig. 10A A schematic diagram of the cross-sectional configuration along line II-II' is shown.

[0033] Fig.11 : is a schematic diagram illustrating a cross-sectional configuration example of an imaging device according to Modification 1 of the present disclosure.

[0034] Fig.12 It is shown Fig.11 FIG. 1 is a schematic diagram of an example of a planar layout of a first substrate and a second substrate of an imaging device shown in FIG.

[0035] Fig.13A: is a schematic plan view showing an example of a pixel array of an imaging device according to Modification 2 of the present disclosure.

[0036] Fig. 13B : is a schematic plan view showing another pixel array example of the imaging device according to Modification 2 of the present disclosure.

[0037] Fig.14 : is a schematic diagram illustrating a cross-sectional configuration example of an imaging device according to a second embodiment of the present disclosure.

[0038] Fig.15 is a schematic diagram showing a cross-sectional configuration example of an imaging device according to a second embodiment of the present disclosure, and its position is Fig.14 The location is different.

[0039] Fig.16 It is shown Fig.14 and 15 A schematic diagram of an example of a planar layout of an imaging device is shown.

[0040] Fig.17A It is shown Fig.14 and 15 A cross-sectional view of the manufacturing process of the first substrate is shown.

[0041] Fig. 17B It is shown Fig.17A Schematic cross-sectional view of the process continuation.

[0042] Fig. 17C It is shown Fig. 17B Schematic cross-sectional view of the process continuation.

[0043] Fig.17D It is shown Fig. 17C Schematic cross-sectional view of the process continuation.

[0044] Fig.17E It is shown Fig.17D Schematic cross-sectional view of the process continuation.

[0045] Fig.17F It is shown Fig.17E Schematic cross-sectional view of the process continuation.

[0046] Figure 17G It is shown Fig.17F Schematic cross-sectional view of the process continuation.

[0047] Fig.18 : is a schematic diagram illustrating a cross-sectional configuration example of an imaging device according to Modification 3 of the present disclosure.

[0048] Fig.19 is a schematic diagram showing a cross-sectional configuration example of an imaging device according to Modification 3 of the present disclosure, and its position is Fig.18 The location is different.

[0049] Fig. 20 : is a schematic diagram illustrating a cross-sectional configuration example of an imaging device according to Modification 4 of the present disclosure.

[0050] Fig.21 is a schematic diagram showing a cross-sectional configuration example of an imaging device according to Modification 4 of the present disclosure, and its position is Fig. 20 The location is different.

[0051] Fig. 22 : is a schematic diagram showing a planar layout example of an imaging device according to Modification 5 of the present disclosure.

[0052] Fig.23 : is a schematic diagram showing a planar configuration example of a pixel of an imaging device according to a third embodiment of the present disclosure.

[0053] Fig.24 is shown with Fig.23 The schematic diagram of the cross-sectional configuration example corresponding to the line VV' shown is shown.

[0054] Fig.25 It is shown Fig.23 Schematic plan view of an example of the configuration of a pixel array section of an imaging device shown.

[0055] Fig.26 is shown with Fig.23 The line VV' shown is a schematic diagram of another cross-sectional configuration example.

[0056] Fig. 27 : is a schematic diagram showing a planar configuration example of a pixel of an imaging device according to Modification Example 6 of the present disclosure.

[0057] Fig.28 is shown with Fig. 27 Schematic diagram of a cross-sectional configuration example corresponding to line VI-VI' shown.

[0058] Fig.29 is shown with Fig. 27 The line VI-VI' shown is a schematic diagram of another cross-sectional configuration example.

[0059] Fig.30 : is a schematic diagram showing a planar configuration example of a pixel of an imaging device according to Modification 7 of the present disclosure.

[0060] Fig.31 is shown with Fig.30 The schematic diagram of the cross-sectional configuration example corresponding to the line VII-VII' shown is shown.

[0061] Fig.32 is shown with Fig.30 The line VII-VII' shown is a schematic diagram of another cross-sectional configuration example.

[0062] Fig.33 : is a schematic diagram showing an example of a planar configuration of a pixel of an imaging device according to Modification Example 8 of the present disclosure.

[0063] Fig.34 is shown with Fig.33 A schematic diagram of a cross-sectional configuration example corresponding to line VIII-VIII' is shown.

[0064] Fig.35 is shown with Fig.33 The line VIII-VIII' shown is a schematic diagram of another cross-sectional configuration example.

[0065] Fig.36 : is a schematic diagram showing a planar configuration example of a pixel of an imaging device according to Modification Example 9 of the present disclosure.

[0066] Fig.37 : is a schematic diagram showing another planar configuration example of a pixel of an imaging device according to Modification Example 9 of the present disclosure.

[0067] Fig.38 : is a schematic diagram showing a planar configuration example of a pixel of an imaging device according to Modification Example 9 of the present disclosure.

[0068] Fig.39 : is a schematic diagram showing another planar configuration example of a pixel of an imaging device according to Modification 10 of the present disclosure.

[0069] Fig.40 : is a schematic diagram showing a planar configuration example of a pixel of an imaging device according to Modification 11 of the present disclosure.

[0070] Fig.41 : is a schematic diagram showing another planar configuration example of a pixel of an imaging device according to Modification 11 of the present disclosure.

[0071] Fig.42 : is a schematic diagram showing still another planar configuration example of a pixel of an imaging device according to Modification 11 of the present disclosure.

[0072] Fig.43 : is a schematic diagram showing still another planar configuration example of a pixel of an imaging device according to Modification 11 of the present disclosure.

[0073] Fig.44 : is a schematic diagram showing an example of a cross-sectional configuration of a semiconductor layer of a first substrate of an imaging device according to a fourth embodiment of the present disclosure.

[0074] Fig.45A It is shown Fig.44A schematic diagram of an example of a planar layout of the semiconductor layer of the first substrate is shown.

[0075] Fig.45B It is shown Fig.44 FIG. 1 is a schematic diagram of another planar layout example of the semiconductor layer of the first substrate shown.

[0076] Fig.46 : is a schematic diagram showing an example of a cross-sectional configuration of a semiconductor layer of a first substrate of an imaging device according to Modification 12 of the present disclosure.

[0077] Fig.47A It is shown Fig.46 A schematic diagram of an example of a planar layout of the semiconductor layer of the first substrate is shown.

[0078] Fig.47B It is shown Fig.46 FIG. 1 is a schematic diagram of another planar layout example of the semiconductor layer of the first substrate shown.

[0079] Fig.48 : is a schematic diagram showing a planar configuration example of a pixel of an imaging device according to Modification 13 of the present disclosure.

[0080] Fig.49 : is a schematic diagram showing another planar configuration example of a pixel of an imaging device according to Modification 13 of the present disclosure.

[0081] Fig.50 : is a schematic diagram showing still another planar configuration of a pixel of an imaging device according to Modification 13 of the present disclosure.

[0082] Fig.51 : is a schematic diagram showing still another planar configuration of a pixel of an imaging device according to Modification 13 of the present disclosure.

[0083] Fig.52 : is a schematic diagram showing still another planar configuration of a pixel of an imaging device according to Modification 13 of the present disclosure.

[0084] Fig.53 : is a schematic diagram showing still another planar configuration of a pixel of an imaging device according to Modification 13 of the present disclosure.

[0085] Fig.54 : is a schematic diagram showing still another planar configuration of a pixel of an imaging device according to Modification 13 of the present disclosure.

[0086] Fig.55 : is a schematic diagram showing still another planar configuration of a pixel of an imaging device according to Modification 13 of the present disclosure.

[0087] Fig.56 : is a schematic diagram showing still another planar configuration of a pixel of an imaging device according to Modification 13 of the present disclosure.

[0088] Fig.57 : is a schematic diagram showing still another planar configuration of a pixel of an imaging device according to Modification 13 of the present disclosure.

[0089] Fig.58 : is a plan view showing a configuration example of a pixel array section of an imaging device according to a fifth embodiment of the present disclosure.

[0090] Fig.59 is shown with Fig.58 Schematic diagram of a cross-sectional configuration example corresponding to line XI-XI' shown.

[0091] Fig.60 is shown with Fig.58 The line XI-XI' shown is a schematic diagram of another cross-sectional structure example.

[0092] Fig.61 : is a schematic diagram showing a planar configuration example of a pixel of an imaging device according to Modification 14 of the present disclosure.

[0093] Fig.62 : is a schematic diagram showing another planar configuration example of a pixel of an imaging device according to Modification 14 of the present disclosure.

[0094] Fig.63 : is a diagram showing a schematic configuration example of an imaging system 6 including the imaging device according to the above-described embodiment and its modified example.

[0095] Fig.64 It is shown Fig.63 A diagram of an example of an imaging process in an imaging system shown.

[0096] Fig.65 is a view showing a schematic configuration example of an endoscopic surgery system.

[0097] Fig.66 is a block diagram showing an example of the functional configuration of a camera head and a camera control unit (CCU).

[0098] Fig.67 is a block diagram showing a schematic configuration example of a vehicle control system.

[0099] Fig.68 It is a diagram to assist in explaining an example of the installation positions of the vehicle exterior information detection section and the imaging section. DETAILED DESCRIPTION

[0100] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the following aspects. In addition, for the layout, size, size ratio, etc. of each component shown in each figure, the present disclosure is not limited to these layouts, sizes, size ratios, etc. It should be noted that the description order is as follows.

[0101] 1. First Embodiment (Example of an Imaging Device in Which an FD is Provided in a Protrusion of a Semiconductor Substrate and a Transfer Gate is Provided Around the Protrusion at a Position Lower than the FD)

[0102] 2. Modifications

[0103] 2-1. Modification 1 (Another Configuration Example of Imaging Device)

[0104] 2-2. Modification 2 (Another Configuration Example of Imaging Device)

[0105] 3. Second Embodiment (Example of an Imaging Device in Which an FD is Provided in a Protrusion of a Semiconductor Substrate and a Transfer Gate is Provided Around the Protrusion at a Position Higher Than the FD)

[0106] 4. Modifications

[0107] 4-1. Modification 3 (Another Configuration Example of Imaging Device)

[0108] 4-2. Modification 4 (Another Configuration Example of Imaging Device)

[0109] 4-3. Modification 5 (Another Configuration Example of Imaging Device)

[0110] 5. Third Embodiment (Example of an Imaging Device in Which an FD is Provided in a Protrusion of a Semiconductor Substrate and a Transfer Gate is Provided Around the Protrusion in a Phase Difference Pixel)

[0111] 6. Modifications

[0112] 6-1. Modification 6 (Another Configuration Example of Imaging Device)

[0113] 6-2. Modification 7 (Another Configuration Example of Imaging Device)

[0114] 6-3. Modification 8 (Another Configuration Example of Imaging Device)

[0115] 6-4. Modification 9 (Another Configuration Example of Imaging Device)

[0116] 6-5. Modification 10 (Another Configuration Example of Imaging Device)

[0117] 6-6. Modification 11 (Another Configuration Example of Imaging Device)

[0118] 7. Fourth Embodiment (Example of Imaging Device with FD Provided Between Upper and Lower Surfaces of Transfer Gate)

[0119] 8. Modifications

[0120] 8-1. Modification 12 (Another Configuration Example of Imaging Device)

[0121] 8-2. Modification 13 (Another Configuration Example of Imaging Device)

[0122] 9. Fifth Embodiment (Example of an imaging device in which FD is shared between adjacent pixels and a transfer gate of each pixel is provided around FD in an overall phase difference pixel)

[0123] 10. Modification 14 (Another Configuration Example of Imaging Device)

[0124] 11. Application Examples (Imaging Systems)

[0125] 12. Practical application examples

[0126] <1. First Embodiment>

[0127] [Functional Configuration of Imaging Device]

[0128] Figure 1 : is a block diagram showing a functional configuration example of an imaging device (imaging device 1 ) according to the first embodiment of the present disclosure.

[0129] Figure 1 The imaging device 1 in , for example, includes an input section 510A, a row drive section 520 , a timing control section 530 , a pixel array section 540 , a column signal processing section 550 , an image signal processing section 560 , and an output section 510B.

[0130] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, a unit cell 539 including a group of pixels is used as a repeating unit, and the unit cells 539 are repeatedly arranged in an array having rows and columns, that is, arranged in the row direction and the column direction. It should be noted that in this specification, for convenience, the row direction may be referred to as the H direction, and the column direction perpendicular to the row direction may be referred to as the V direction. Figure 1 In the example of FIG. 5 , one unit cell 539 includes, for example, four pixels (pixels 541A, 541B, 541C, and 541D).

[0131] In addition to the pixels 541A, 541B, 541C, and 541D, the pixel array section 540 is provided with a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column readout lines) 543. The row drive signal lines 542 drive the pixels 541 included in each of the plurality of unit cells 539 arranged side by side in the row direction in the pixel array section 540. The row drive signal lines 542 drive each pixel arranged side by side in the row direction in the unit cells 539. As will be described later, Figure 4 In detail, a plurality of transistors are provided in the unit cell 539. In order to drive each of these plurality of transistors, a plurality of row drive signal lines 542 are connected to one unit cell 539. The unit cell 539 is connected to a vertical signal line (column readout line) 543. A pixel signal is read out from each of the pixels 541A, 541B, 541C, and 541D included in the unit cell 539 through the vertical signal line (column readout line) 543.

[0132] The row driving section 520 includes, for example, a row address controller (ie, a row decoder section) that determines row positions for driving pixels and a row driving circuit section that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0133] The column signal processing section 550 includes, for example, a load circuit section that is connected to the vertical signal line 543 and forms a source follower circuit with the pixels 541A, 541B, 541C, and 541D (unit cell 539). The column signal processing section 550 may include an amplifier circuit section that amplifies the signal read out from the unit cell 539 through the vertical signal line 543. The column signal processing section 550 may include a noise processor. The noise processor removes, for example, a system noise level caused by photoelectric conversion in the signal read out from the unit cell 539.

[0134] The column signal processing unit 550 includes, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read out from the unit cell 539 or the analog signal subjected to the above-mentioned noise processing is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted is compared with a reference signal for comparing with the analog signal. In the counter unit, the time when the comparison result in the comparator unit is reversed is measured. The column signal processing unit 550 may include a horizontal scanning circuit unit that performs scanning control of the column to be read.

[0135] The timing control section 530 provides a signal for controlling timing to the row driving section 520 and the column signal processing section 550 based on a reference clock signal or a timing control signal input to the device.

[0136] The image signal processing section 560 is a circuit that performs various signal processing on data obtained by photoelectric conversion (i.e., data obtained by imaging operation in the imaging device 1). The image signal processing section 560 includes, for example, an image signal processing circuit section and a data holding section. The image signal processing section 560 may include a processor section.

[0137] An example of the signal processing performed in the image signal processing section 560 is a tone curve correction process that causes the A / D-converted image data to have more tones when it is captured image data of a dark subject, and to have less tones when it is captured image data of a bright subject. In this case, it is desirable to store the characteristic data of the tone curve in the data holding section of the image signal processing section 560 in advance to determine whether to determine the tone of the image data according to which type of tone curve.

[0138] The input section 510A is used to input, for example, the above-mentioned reference clock signal, timing control signal, characteristic data, etc. from outside the device to the imaging device 1. Examples of the timing control signal include a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is used to be stored in, for example, a data holding section of the image signal processing section 560. The input section 510A includes, for example, an input terminal 511, an input circuit section 512, an input amplitude changing section 513, an input data conversion circuit section 514, and a power supply unit (not shown).

[0139] The input terminal 511 is an external terminal for inputting data. The input circuit section 512 is used to extract the signal input to the input terminal 511 to the inside of the imaging device 1. In the input amplitude changing section 513, the amplitude of the signal extracted by the input circuit section 512 is changed to an amplitude that allows the signal to be used inside the imaging device 1. In the input data conversion circuit section 514, the order of the data string of the input data is changed. The input data conversion circuit section 514 includes, for example, a serial-to-parallel conversion circuit. In the serial-to-parallel conversion circuit, a serial signal received as input data is converted into a parallel signal. It should be noted that the input amplitude changing section 513 and the input data conversion circuit section 514 can be omitted from the input section 510A. The power supply unit provides power having various voltages required inside the imaging device 1 according to the power supplied from the outside to the imaging device 1.

[0140] The input section 510A may be provided with a memory interface circuit that receives data from an external memory device when the imaging device 1 is connected to the external memory device. Examples of the external memory device include flash memory, SRAM, and DRAM.

[0141] The output section 510B outputs the image data to the outside of the device. Examples of the image data include image data of an image captured by the imaging device 1 and image data that has been signal-processed by the image signal processing section 560. The output section 510B includes, for example, an output data conversion circuit section 515, an output amplitude change section 516, an output circuit section 517, and an output terminal 518.

[0142] The output data conversion circuit section 515 includes, for example, a parallel-to-serial conversion circuit; in the output data conversion circuit section 515, a parallel signal used inside the imaging device 1 is converted into a serial signal. The output amplitude change section 516 changes the amplitude of the signal used inside the imaging device 1. The signal with the changed amplitude becomes available to an external device externally connected to the outside of the imaging device 1. The output circuit section 517 is a circuit that outputs data from the inside of the imaging device 1 to the outside of the device, and the wiring connected to the output terminal 518 outside the imaging device 1 is driven by the output circuit section 517. In the output terminal 518, data is output from the output imaging device 1 to the outside of the device. The output data conversion circuit section 515 and the output amplitude change section 516 can be omitted from the output section 510B.

[0143] The output section 510B may be provided with a memory interface circuit that outputs data to an external memory device when the imaging device 1 is connected to the external memory device. Examples of the external memory device include a flash memory, an SRAM, and a DRAM.

[0144] [Schematic Configuration of Imaging Device]

[0145] Figure 2 and 3 There is shown a schematic configuration example of the imaging device 1. The imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). Figure 2 The planar structures of the first substrate 100, the second substrate 200 and the third substrate 300 are schematically shown, and Figure 3 The cross-sectional configuration of the first substrate 100 , the second substrate 200 , and the third substrate 300 stacked up and down is schematically shown. Figure 3 Corresponding to the imaging device 1 along Figure 2The cross-sectional structure of the line II' shown. The imaging device 1 is a three-dimensional structure imaging device, which includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300) bonded together. The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film around it is referred to as a wiring layer (100T, 200T, 300T) provided in each substrate (each of the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100, the second substrate 200 and the third substrate 300 are stacked up and down in sequence, and the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the semiconductor layer 300S and the wiring layer 300T are arranged in sequence along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200 and the third substrate 300 will be described later. Figure 3 The arrow shown indicates the incident direction of the light L on the imaging device 1. In this specification, in the subsequent cross-sectional views, for the sake of convenience, the light incident side of the imaging device 1 may be referred to as the "lower part", "lower side" or "below", and the side opposite to the light incident side may be referred to as the "upper part", "upper side" or "above". In addition, in this specification, for a substrate including a semiconductor layer and a wiring layer, for the sake of convenience, the wiring layer side may be referred to as the front side, and the semiconductor layer side may be referred to as the back side. It should be noted that the description in the specification is not limited to the above terms. The imaging device 1 is, for example, a back-illuminated imaging device in which light enters from the back side of the first substrate 100 including a photodiode.

[0146] The pixel array section 540 and the unit cell 539 included in the pixel array section 540 are both included in the first substrate 100 and the second substrate 200. The first substrate 100 is provided with groups of pixels 541A, 541B, 541C and 541D included in the unit cell 539. Each of these pixels 541 includes a photodiode (photodiode PD to be described later) and a transfer transistor (transfer transistor TR to be described later). The second substrate 200 is provided with a pixel circuit (pixel circuit 210 to be described later) included in the unit cell 539. The pixel circuit reads out the pixel signal transmitted from the photodiode of each pixel 541A, 541B, 541C and 541D through the transfer transistor, or resets the photodiode. In addition to the above-mentioned pixel circuit, the second substrate 200 also includes a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 also includes a power supply line 544 extending in the row direction. The third substrate 300 includes, for example, an input section 510A, a row driving section 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. The row driving section 520 is, for example, disposed in a region in which a portion of the row driving section overlaps with the pixel array section 540 in the direction in which the first substrate 100, the second substrate 200, and the third substrate 300 are stacked (hereinafter referred to as the "stacking direction"). More specifically, the row driving section 520 is disposed in a region in which the row driving section overlaps with a portion of the end portion of the pixel array section 540 in the H direction in the stacking direction ( Figure 2 ). The column signal processing section 550 is, for example, disposed in a region in which a portion of the column signal processing section overlaps with the pixel array section 540 in the stacking direction. More specifically, the column signal processing section 550 is disposed in a region in which a portion of the column signal processing section overlaps with a portion of an end portion of the pixel array section 540 in the V direction in the stacking direction ( Figure 2 ). Although not shown, the input section 510A and the output section 510B may be provided in a portion different from the third substrate 300; for example, they may be arranged in the second substrate 200. Alternatively, the input section 510A and the output section 510B may be provided on the back side (light incident side) of the first substrate 100. It should be noted that the pixel circuit provided in the second substrate 200 may sometimes be represented by different names, such as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit. In this specification, the name of the pixel circuit is used.

[0147] The first substrate 100 and the second substrate 200 are connected to each other by, for example, a contact portion (eg, Figure 5 The contact electrodes 122 and 222 in the embodiment of the present invention) or the through-electrodes (for example, Fig.11 The through electrodes 223, 224 and 225 in the second substrate 200 are electrically connected. For example, the second substrate 200 and the third substrate 300 are electrically connected through the contact portions 201, 202, 301 and 302. The second substrate 200 is provided with the contact portions 201 and 202, and the third substrate 300 is provided with the contact portions 301 and 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact portion region 201R provided with a plurality of contact portions 201 and a contact portion region 202R provided with a plurality of contact portions 202. The third substrate 300 has a contact portion region 301R provided with a plurality of contact portions 301 and a contact portion region 302R provided with a plurality of contact portions 302. The contact regions 201R and 301R are provided between the pixel array section 540 and the row drive section 520 in the stacking direction ( Figure 3 ). In other words, the contact regions 201R and 301R are provided in, for example, the overlapping region of the row drive section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) in the stacking direction or in the adjacent region thereof. For example, the contact regions 201R and 301R are arranged in the ends of each of these regions in the H direction ( Figure 2 In the third substrate 300, for example, the contact region 301R is disposed at a position where the contact region 301R overlaps a portion of the row drive unit 520, specifically, overlaps an end portion of the row drive unit 520 in the H direction ( Figure 2 and 3 ). The contact portions 201 and 301 connect, for example, the row driving portion 520 provided in the third substrate 300 to the row driving signal line 542 provided in the second substrate 200. For example, the contact portions 201 and 301 can connect the input portion 510A provided in the third substrate 300 to the power supply line 544 and the reference potential line (reference potential line VSS described later). The contact portion regions 202R and 302R are provided between the pixel array portion 540 and the column signal processing portion 550 in the stacking direction ( Figure 3 ). In other words, the contact regions 202R and 302R are provided in, for example, the overlapping region of the column signal processing section 550 (third substrate 300) and the pixel array section 540 (second substrate 200) in the stacking direction or in the adjacent region thereof. For example, the contact regions 202R and 302R are provided in the ends of each of these regions in the V direction ( Figure 2 In the third substrate 300, for example, the contact region 301R is provided at a position where the contact region 301R overlaps a portion of the column signal processing section 550, specifically, overlaps an end portion of the column signal processing section 550 in the V direction ( Figure 2 and3 ). The contact portions 202 and 302 connect a pixel signal (a signal corresponding to the amount of charge generated by photoelectric conversion of a photodiode) output from each of the plurality of unit cells 539 included in the pixel array portion 540 to a column signal processing portion 550 provided in the third substrate 300. The pixel signal is configured to be transmitted from the second substrate 200 to the third substrate 300.

[0148] Figure 3 is an example of a cross-sectional view of the imaging device 1. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected through wiring layers 100T, 200T, and 300T. For example, the imaging device 1 includes an electrical connector that electrically connects the second substrate 200 to the third substrate 300. Specifically, the contact portions 201, 202, 301, and 302 are respectively formed using electrodes including a conductive material. The conductive material, for example, includes a metal material such as copper (Cu), aluminum (Al), or gold (Au). The contact portion regions 201R, 202R, 301R, and 302R electrically connect the second substrate 200 to the third substrate 300, for example, by directly connecting the wiring formed as the electrode, thereby realizing signal input and / or output between the second substrate 200 and the third substrate 300.

[0149] An electrical connector for electrically connecting the second substrate 200 to the third substrate 300 may be provided at a desired position. Figure 3 In the contact portion regions 201R, 202R, 301R, and 302R described in the figure, the electrical connector may be provided in a region that allows it to overlap with the pixel array portion 540 in the stacking direction. In addition, the electrical connector may be provided in a region that allows it not to overlap with the pixel array portion 540 in the stacking direction. Specifically, the electrical connector may be provided in a region that allows it to overlap with the peripheral portion provided outside the pixel array portion 540 in the stacking direction.

[0150] The first substrate 100 and the second substrate 200 are provided with connection holes H1 and H2, for example. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 ( Figure 3 The connection holes H1 and H2 are provided outside the pixel array section 540 (or in a portion overlapping with the pixel array section 540) ( Figure 2). For example, the connection hole H1 is arranged on the outside of the pixel array section 540 in the H direction, and the connection hole H2 is arranged on the outside of the pixel array section 540 in the V direction. For example, the connection hole H1 reaches the input section 510A provided in the third substrate 300, and the connection hole H2 reaches the output section 510B provided in the third substrate 300. The connection holes H1 and H2 may be hollow, and at least a portion thereof may include a conductive material. For example, there is a structure in which a bonding wire is connected to an electrode formed as the input section 510A and / or the output section 510B. Alternatively, there is a structure in which an electrode formed as the input section 510A and / or the output section 510B is connected to a conductive material provided in the connection holes H1 and H2. The conductive material provided in the connection holes H1 and H2 may be embedded in all or part of the connection holes H1 and H2, or the conductive material may be formed on the side walls of each of the connection holes H1 and H2.

[0151] It should be noted that Figure 3 The structure in which the input portion 510A and the output portion 510B are provided in the third substrate 300 is shown; however, the present disclosure is not limited thereto. For example, by configuring the signal of the third substrate 300 to be transmitted to the second substrate 200 through the wiring layers 200T and 300T, the input portion 510A and / or the output portion 510B may be provided in the second substrate 200. Similarly, by configuring the signal of the second substrate 200 to be transmitted to the first substrate 1000 through the wiring layers 100T and 200T, the input portion 510A and / or the output portion 510B may be provided in the first substrate 100.

[0152] Pixels 541A, 541B, 541C, and 541D have common components. Hereinafter, in order to distinguish the respective components of pixels 541A, 541B, 541C, and 541D, a distinguishing number "1" is added after the reference numeral of the corresponding component of pixel 541A, a distinguishing number "2" is added after the reference numeral of the corresponding component of pixel 541B, a distinguishing number "3" is added after the reference numeral of the corresponding component of pixel 541C, and a distinguishing number "4" is added after the reference numeral of the corresponding component of pixel 541D. In the case where it is not necessary to distinguish the respective components of pixels 541A, 541B, 541C, and 541D, the distinguishing numbers added after the reference numerals of the respective components of pixels 541A, 541B, 541C, and 541D are omitted.

[0153] Figure 4 539 is an equivalent circuit diagram showing a configuration example of a unit cell 539. The unit cell 539 includes a plurality of pixels 541 (in Figure 4, namely, pixels 541A, 541B, 541C, and 541D), a pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, which are specifically an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, by operating the one pixel circuit 210 in a time-division manner, the unit cell 539 sequentially outputs the pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) arranged in two adjacent pixels. The situation in which a pixel circuit 210 is connected to a plurality of pixels 541 and the pixel signals of the plurality of pixels 541 are output by the one pixel circuit 210 in a time-division manner means that "a plurality of pixels 541 share one pixel circuit 210".

[0154] Pixels 541A, 541B, 541C, and 541D have common components.

[0155] Pixels 541A, 541B, 541C, and 541D include, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. In the photodiode PD, the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD performs photoelectric conversion on incoming light and generates charges according to the amount of light received. The transfer transistor TR is, for example, an N-type complementary metal oxide semiconductor (CMOS) transistor. In the transfer transistor TR, the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to a drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to one unit cell 539 (see Figure 1 ). The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD. The floating diffusion FD is an n-type diffusion region formed in the p-type semiconductor layer. The floating diffusion FD is a charge holding member that temporarily holds the charge transferred from the photodiode PD, and is a charge-voltage conversion member that generates a voltage according to the amount of charge.

[0156] The four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in one unit cell 539 are electrically connected to each other, and are electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to the drive signal line. The drive signal line is a part of the multiple row drive signal lines 542 connected to one unit cell 539. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. The drive signal line is a part of the multiple row drive signal lines 542 connected to one unit cell 539. The gate of the amplifier transistor AMP is connected to the floating diffusion FD, the drain of the amplifier transistor AMP is connected to the power supply line VDD, and the source of the amplifier transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. The driving signal line is a part of a plurality of row driving signal lines 542 connected to one unit cell 539 .

[0157] If the transfer transistor TR enters the on state, the transfer transistor TR transfers the charge in the photodiode PD to the floating diffusion FD. As will be described in detail later, the gate (transfer gate TG) of the transfer transistor TR is, for example, arranged around a columnar protrusion 100X, and a floating diffusion FD (FD 114) is formed on the upper surface of the protrusion; the protrusion 100X is arranged on the front side (surface 100S1) of the semiconductor layer 100S. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. If the reset transistor RST enters the on state, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The selection transistor SEL controls the timing of outputting a pixel signal from the pixel circuit 210. The amplifier transistor AMP generates a voltage signal as a pixel signal according to the level of the charge held in the floating diffusion FD. The amplifier transistor AMP is connected to the vertical signal line 543 through the selection transistor SEL. In the column signal processing unit 550, the amplifier transistor AMP is connected to the load circuit unit (see Figure 1 ) together constitute a source follower. If the selection transistor SEL enters the on state, the amplifier transistor AMP outputs the voltage of the floating diffusion portion FD to the column signal processing portion 550 through the vertical signal line 543. The reset transistor RST, the amplifier transistor AMP and the selection transistor SEL are, for example, N-type CMOS transistors.

[0158] When changing the charge-voltage conversion gain in the floating diffusion FD, the FD conversion gain switching transistor FDG is used. Generally, when taking an image in a dark place, the pixel signal is small. Based on Q=CV, when performing charge-voltage conversion, if the capacitance of the floating diffusion FD (FD capacitance C) is high, the voltage V converted in the amplifier transistor AMP becomes smaller. At the same time, the pixel signal becomes larger in a bright place; therefore, if the FD capacitance C is not high, the floating diffusion FD cannot receive the charge of the photodiode PD. In addition, the FD capacitance C must be high so that the voltage V converted in the amplifier transistor AMP is not too high (ie, low). In view of this, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance FD increases the capacitance of the conversion gain switching transistor FDG, so the entire FD capacitance C becomes higher. At the same time, when the FD conversion gain switching transistor FDG is turned off, the entire FD capacitance C becomes lower. In this way, by turning on and off the FD conversion gain switching transistor FDG, the FD capacitance C can be changed, and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0159] It should be noted that a configuration in which the FD conversion gain switching transistor FDG is not provided is also possible. In this case, for example, the pixel circuit 210 includes three transistors: an amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 includes at least one of the pixel transistors such as the amplifier transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0160] The selection transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (see Figure 1 ). The source of the amplifier transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. It should be noted that, although not shown, the number of pixels 541 that share one pixel circuit 210 may not be 4. For example, two or eight pixels 541 may share one pixel circuit 210.

[0161] [Cross-sectional structure of imaging device]

[0162] Figure 5 1 shows a cross-sectional configuration example of the imaging device 1 in a direction perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300. In order to simplify the positional relationship of the components, Figure 5A schematic cross-sectional configuration is shown, and it may be different from the actual cross-sectional configuration. In the imaging device 1, a first substrate 100, a second substrate 200, and a third substrate 300 are stacked up and down in this order. The imaging device 1 also includes a light receiving lens 414 located on the back side (light incident side) of the first substrate 100. Between the light receiving lens 414 and the first substrate 100, for example, a light shielding film 411, a protective layer 412, and a color filter layer 413 are provided. For example, a light receiving lens 414 is provided in each of pixels 541A, 541B, 541C, and 541D. The imaging device 1 is, for example, a back-illuminated imaging device. The imaging device 1 includes a pixel array portion 540 arranged in the middle and a peripheral portion (not shown) arranged outside the pixel array portion 540.

[0163] The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The semiconductor layer 100S includes, for example, a silicon substrate. The semiconductor layer 100S has a pair of surfaces opposite to each other (a surface 100S1 as a front surface and a surface 100S2 as a back surface). The semiconductor layer 100S includes a p-well layer 112 in a portion of the surface 100S1 and its adjacent region, and includes an n-type semiconductor region 111 in another region (a region deeper than the p-well layer 112). For example, the n-type semiconductor region 111 and the p-well layer 112 constitute a pn junction photodiode PD. The p-well layer 112 is a p-type semiconductor region.

[0164] The FD 114 and the contact layer 117 are disposed adjacent to the front surface of the semiconductor layer 100S. The FD 114 includes an n-type semiconductor region disposed in the p-well layer 112. The FD 114 is disposed for each pixel 541. For example, Figure 6 As shown, the FD 114 provided for each pixel 541 is provided approximately in the middle of the pixel 541. As will be described in detail later, each of the FDs 114 (FD1, FD2, FD3, and FD4) provided in the four pixels 541A, 541B, 541C, and 541D constituting the unit cell 539 is electrically connected to each other through an electrical connection member (wiring in the wiring layer 100T) within the first substrate 100 (more specifically, within the wiring layer 100T). In addition, the FD 114 is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) through an electrical member (for example, contact portions 122, 222, etc.). In the second substrate 200 (more specifically, within the wiring layer 200T), the FD 114 is electrically connected to the gate of the amplifier transistor AMP constituting the pixel circuit 210 and the source of the FD conversion gain switching transistor FDG through the electrical member.

[0165] The contact layer 117 is a region electrically connected to the reference potential line VSS, and is arranged away from the FD 114. The contact layer 117 is, for example, provided between adjacent unit cells 539 along the V direction (Z-axis direction). The contact layer 117 is, for example, connected to a ground potential or a fixed potential. Thus, the semiconductor layer 100S is provided with a reference potential. The contact layer 117 includes, for example, polycrystalline silicon (poly-Si), more specifically, doped polycrystalline silicon doped with impurities.

[0166] In addition to the photodiode PD, the FD 114, and the contact layer 117, the first substrate 100 is also provided with a transfer transistor TR. The transfer transistor TR is provided, for example, for each pixel 541. The transfer transistor TR has a transfer gate TG. As will be described in detail later, for example, for each pixel 541, the transfer gate TG may be provided around the FD 114, or, for example, as Figure 6 As shown, it can be disposed between unit cells 539 adjacent to each other in the X-axis direction and continuous in two pixels 541 adjacent to each other in the X-axis direction. Thus, the number of wirings can be reduced.

[0167] The semiconductor layer 100S is provided with a separation portion 115 that separates adjacent pixels 541 from each other. The separation portion 115 is formed to extend along the normal direction (Y-axis direction) of the semiconductor layer 100S. The separation portion 115 is used to separate adjacent unit cells 539 and separate the four pixels 541 (pixels 541A, 541B, 541C and 541D) constituting the unit cell 539 from each other, and has, for example, a grid-like planar shape. For example, the separation portion 115 electrically separates adjacent pixels 541 from each other. The separation portion 115, for example, has a full trench isolation (FTI: Full Trench Isolation) structure, and passes through between the surfaces 100S1 and 100S2 of the semiconductor layer 100S. In addition, the separation portion 115 may, for example, have a deep trench isolation (DTI: Deep Trench Isolation) structure, in which the separation portion 115 does not pass through the semiconductor layer 100S. The separation portion 115 is formed by embedding an insulating film such as silicon oxide (SiO) in a groove (eg, an opening H1 (see FIG. 1 )) provided on the semiconductor layer 100S. Figure 7B It should be noted that a metal material having a light shielding effect, such as tungsten (W), may be embedded inside the insulating film of the separation portion 115. Thus, adjacent pixels 541 can be electrically and optically separated from each other.

[0168] In the present embodiment, the semiconductor layer 100S has a structure in which the surface 100S1 is uneven. Specifically, the semiconductor layer 100S has a plurality of protrusions 100X for each pixel 541 on the surface 100S1, and Figure 5As shown, FD 114 is formed on the upper part of each of the plurality of protrusions 100X. In the lower part of the plurality of protrusions 100X, for example, a p-type semiconductor layer 113 having a higher impurity concentration than the p-well layer 112 is formed; the p-type semiconductor layer 113 serves as an overflow path. That is, in the plurality of protrusions 100X, the p-type semiconductor layer 113, the p-well layer 112, and the FD 114 are stacked in sequence from the n-type semiconductor region 111 side. The transmission gate TG is provided around the plurality of protrusions 100X, and is formed so that the position of its upper surface is lower than the FD 114. Specifically, it is formed so that the upper surface of the transmission gate TG is positioned on the side surface of the p-well layer 112 among the p-type semiconductor layer 113, the p-well layer 112, and the FD 114 stacked in the Y-axis direction. Therefore, the distance between the FD 114 and the transmission gate TG in the height direction (Y-axis direction) can be ensured.

[0169] The contact layer 117 is embedded in the surface 100S1 of the semiconductor layer 100S and is located above the separation portion 115, and is electrically connected to the semiconductor layer 100S on its side surface. More specifically, the portion of the surface 100S1 of the semiconductor layer 100S in which the contact layer 117 is embedded is a recess 100Y. Therefore, the distance between the FD 114 and the contact layer 117 in the height direction (Y-axis direction) can be ensured.

[0170] On the surface 100S1 of the semiconductor layer 100S and the side surface of the semiconductor layer 100S provided with the separation portion 115, for example, a pinning region 116 including a p-type semiconductor region is formed. In addition, although not shown, the pinning region may also be provided on the surface 100S2 of the semiconductor layer 100S. Thus, the generation of dark current caused by the interface state of the semiconductor layer 100S can be reduced.

[0171] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 includes an interlayer insulating layer 121, the above-mentioned transmission gate TG, and a plurality of contact portions 122. The interlayer insulating layer 121 is provided on the entire surface of the semiconductor layer 100S, and buries the protrusions and depressions on the front side (surface 100S1) of the semiconductor layer 100S. Further, one or more wirings are formed in the interlayer insulating layer 121, and a plurality of contact portions 122 are embedded in the front side of the interlayer insulating layer opposite to the second substrate 200. The interlayer insulating layer 121 includes, for example, a silicon oxide film. It should be noted that the configuration of the wiring layer 100T is not limited to the above-mentioned configuration, and it only needs to include wirings and an insulating film.

[0172] A plurality of contacts 122 are exposed on the surface of the wiring layer 100T. Some of the contacts 122 are connected to, for example, the FD 114 provided for each pixel 541, and are connected to the pixel circuit 210 (for example, the gate of the amplifier transistor AMP) through the contact 222 provided on the second substrate 200 side. In addition, some of the contacts 122 are connected to the contact layer 117, and are connected to, for example, a reference potential line VSS provided in the third substrate 300 through the contact 222 provided on the second substrate 200 side, etc. The plurality of contacts 122 are used to be bonded to the second substrate 200. The plurality of contacts 122 include, for example, a metal such as copper (Cu) or aluminum (Al).

[0173] The second substrate 200 includes a semiconductor layer 200S, a wiring layer 200T-1 disposed on the front side (surface 200S1) of the semiconductor layer 200S, and a wiring layer 200T-2 disposed on the back side (surface 200S2) of the semiconductor layer 200S. The semiconductor layer 200S includes a silicon substrate. The semiconductor layer 200S is provided with a well region 211 in the entire thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 200 is provided with a pixel circuit 210. For example, in the unit cell 539, one pixel circuit 210 is provided for each of two pixels adjacent in the V direction. The pixel circuit 210 is, for example, disposed on the front side (surface 200S1) of the semiconductor layer 200S, that is, on the wiring layer 200T-1 side. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 so that the front side (surface 200S1 side of the semiconductor layer 200S) of the second substrate 200 is opposite to the front side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is bonded to the first substrate 100 in a front-to-front manner.

[0174] The second substrate 200 further includes an insulating region 212 for dividing the semiconductor layer 200S. The insulating region 212 has substantially the same thickness as that of the semiconductor layer 200S, and the semiconductor layer 200S is divided by the insulating region 212. The insulating region 212 includes, for example, silicon oxide.

[0175] The wiring layer 200T-1 includes an interlayer insulating layer 221, gates of various transistors (selection transistor SEL, amplifier transistor AMP, reset transistor RST, FD conversion gain switching transistor FDG) constituting the pixel circuit 210, and a plurality of contact portions 222. The insulating layer 221 is provided on the entire surface of the semiconductor layer 200S. Further, one or more wirings are formed in the interlayer insulating layer 221. A plurality of contact portions 222 are exposed on the surface of the wiring layer 200T-1 opposite to the first substrate 100. The plurality of contact portions 222 are used to bond with the first substrate 100. The interlayer insulating layer 221 includes, for example, a silicon oxide film. The plurality of contact portions 222 include, for example, a metal such as copper (Cu) or aluminum (Al). It should be noted that the configuration of the wiring layer 200T-1 is not limited to the above configuration, and it only needs to include wiring and an insulating film.

[0176] The wiring layer 200T-2 includes an interlayer insulating layer 231 and a plurality of contact portions 232. The interlayer insulating layer 231 is provided on the entire surface of the semiconductor layer 200S. Further, one or more wirings are formed in the interlayer insulating layer 231. The plurality of contact portions 232 are exposed on the surface of the wiring layer 200T-2 opposite to the third substrate 300. The plurality of contact portions 232 are used to bond with the third substrate 300. The interlayer insulating layer 231 includes, for example, a silicon oxide film. The plurality of contact portions 232 include, for example, a metal such as copper (Cu) or aluminum (Al). It should be noted that the configuration of the wiring layer 200T-2 is not limited to the above configuration, and it only needs to include wiring and an insulating film.

[0177] The third substrate 300 includes, for example, a wiring layer 300T and a semiconductor layer 300S in sequence starting from the second substrate 200 side. For example, the front side of the semiconductor layer 300S is arranged on the second substrate 200 side. The semiconductor layer 300S includes a silicon substrate. A circuit is arranged in a part of the front side of the semiconductor layer 300S. Specifically, in the part of the front side of the semiconductor layer 300S, for example, at least some of the input part 510A, the row drive part 520, the timing control part 530, the column signal processing part 550, the image signal processing part 560 and the output part 510B are arranged. The wiring layer 300T arranged between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating layer 321 and a plurality of contact parts 332. The plurality of contact portions 322 are exposed on the surface of the wiring layer 200T, and the plurality of contact portions 322 are electrically connected to the circuit formed in the semiconductor layer 300S (for example, at least one of the input portion 510A, the row driving portion 520, the timing control portion 530, the column signal processing portion 550, the image signal processing portion 560, and the output portion 510B). The plurality of contact portions 322 are used to be bonded to the second substrate 200. The plurality of contact portions 322 include, for example, a metal such as copper (Cu) or aluminum (Al).

[0178] [Manufacturing method of imaging device]

[0179] Figures 7A to 7L Show Figure 1 An example of a method for manufacturing the imaging device 1 (particularly the first substrate 100) is shown.

[0180] First, if Fig. 7A As shown in FIG. 1 , an n-type semiconductor region serving as a p-type semiconductor layer 113, a p-well layer 112, and an FD 114 is formed on the surface 100S1 side of the semiconductor layer 100S. Then, as shown in FIG. Figure 7B As shown, a mask 601 is formed on a surface 100S1 of the semiconductor layer 100S, and an opening H1 penetrating the semiconductor layer 100S is formed by, for example, photolithography and etching.

[0181] Next, if Figure 7C As shown, for example, a p-type pinning region 116 is formed on the side surface of the opening H1 by conformal doping, and then, for example, a SiO film serving as the separation portion 115 is formed inside the opening H1 by chemical vapor deposition (CVD). Thereafter, the SiO film formed on the surface 100S1 of the semiconductor layer 100S is polished by chemical mechanical polishing (CMP), for example. Thus, the separation portion 115 is formed.

[0182] Then, if Fig.7D As shown, an opening H2 serving as a groove 100Y is formed by etching back the separation portion 115, and then, using, for example, an atomic layer deposition (ALD) method, insulating films 602 and 603 having different etching rates from each other are sequentially formed on the surface 100S1 of the semiconductor layer 100S and the exposed side surface of the semiconductor layer 100S.

[0183] Next, if Fig. 7E As shown, the insulating film 602 formed on the separation portion 115 is removed by isotropic etching, and then, as shown in Figure 7F As shown in FIG. 1 , a polysilicon film serving as a contact layer 117 is formed. Then, as shown in FIG. Figure 7G As shown, the contact portion layer 117 is formed on the separation portion 115 by etching back the insulating films 602 and 603 to remove them.

[0184] Next, if Figure 7H As shown in FIG. 1 , for example, a SiO film serving as the interlayer insulating layer 112 is formed on the contact layer 117 by CVD so as to embed the opening H2. Then, as shown in FIG. Fig.7I As shown, a mask 640 is formed at a predetermined position on the semiconductor layer 100S, and then a protrusion 100X is formed by photolithography and etching. Then, a p-type pinning region 116 is formed on a surface 100S1 of the semiconductor layer 100S exposed from the mask 604 by conformal doping.

[0185] Next, if Figure 7J As shown, mask 604 is removed, and then, as shown Figure 7K As shown in FIG. 1 , a polysilicon film serving as a transfer gate TG is formed to cover a surface 100S1 of the semiconductor layer 100S including the protrusion 100X. Then, as shown in FIG. Figure 7L As shown, the transfer gate TG is formed by processing the polysilicon film (for example, by photolithography and etching and CMP). After that, for example, a SiO film serving as an interlayer insulating layer 121, wiring and a contact portion 122 are formed, thereby forming a wiring layer 100T. Through the above process, the Figure 5 The first substrate 100 is shown.

[0186] [Operation of imaging device]

[0187] Then, use Figure 8 and 9 The operation of the imaging device 1 will be described. Figure 8 and 9 exist Figure 3 Arrows representing each signal path are added to the . Figure 8 Paths of input signals input from the outside to the imaging device 1 , power supply potentials, and reference potentials are shown indicated by arrows. Fig. 9 The signal path of the pixel signal output from the imaging device 1 to the outside is shown. For example, the input signal (for example, the pixel clock and the synchronization signal) input to the imaging device 1 through the input section 510A is transmitted to the row driving section 520 of the third substrate 300, and a row driving signal is created in the row driving section 520. The row driving signal is transmitted to the second substrate 200 through the contact sections 301 and 201. In addition, the row driving signal reaches each unit cell 539 of the pixel array section 540 through the row driving signal line 542 within the wiring layer 200T. Among the row driving signals reaching the unit cells 539 in the second substrate 200, driving signals other than the driving signal for the transmission gate TG are input to the pixel circuit 210, and drive the respective transistors included in the pixel circuit 210. The driving signal for the transmission gate TG is input to the transmission gate TG in the first substrate 100, and drives the pixel 541 ( Figure 8). In addition, the power supply potential and the reference potential provided from the outside to the input portion 510A (input terminal 511) in the third substrate 300 are transmitted to the second substrate 200 through the contacts 301 and 201, and are provided to the pixel circuit 210 of each unit cell 539 through the wiring in the wiring layer 200T. The reference potential is also provided to the pixel 541 in the first substrate 100. At the same time, for each unit cell 539, the pixel signal photoelectrically converted by the pixel 541 in the first substrate 100 is transmitted to the pixel circuit 210 in the second substrate 200. Pixel signals based on these pixel signals are transmitted from the pixel circuit 210 to the third substrate 300 through the vertical signal line 543 and the contacts 202 and 302. These pixel signals are processed by the column signal processing portion 550 and the image signal processing portion 560 in the third substrate 300, and then output to the outside through the output portion 510B.

[0188] [Effect]

[0189] In the imaging device 1 of the present embodiment, in the semiconductor layer 100S having a pair of surfaces (surfaces 100S1 and 100S2) opposing each other, a plurality of protrusions 100X are provided on the surface 100S1, an FD 114 is provided on the upper portion of each protrusion 100X, and a transfer gate TG is provided around the plurality of protrusions 100X and below the FD 114. Therefore, the distance between the FD 114 and the transfer gate TG in the height direction is ensured.

[0190] As described above, in recent years, three-dimensional structure imaging elements have been developed to make imaging devices smaller and achieve high pixel density. In the three-dimensional structure imaging element, for example, a first substrate is provided with sensor pixels that perform photoelectric conversion, and a second substrate stacked on the first substrate is provided with a readout circuit. Fig. 10A As shown, in the first substrate, as a sensor pixel, an FD 1014, a transfer transistor (transfer gate TG), and a well contact (contact layer 1017) are arranged.

[0191] However, in a fine pixel structure having a pixel pitch of 0.5 μm or less, for example, the effective pixel area is narrow; for example, Fig. 10B Shown with Fig. 10A The cross section corresponding to the line II-II' in FIG. 10 is a cross section in which the distances between the FD 1014, the transfer gate TG and the contact layer 1017 become closer and the electric field intensity becomes higher. Therefore, the three-dimensional structure imaging element has a disadvantage in that the dark current component caused by the electric field increases.

[0192] Meanwhile, in the present embodiment, as described above, in the semiconductor layer 100S having a pair of surfaces (surfaces 100S1 and 100S2) opposing each other, a plurality of protrusions 100X are provided on the surface 100S1, the FD 114 is provided on the upper portion of each protrusion 100X, and the transfer gate TG is provided around the plurality of protrusions 100X and below the FD 114. Therefore, the distance between the FD 114 and the transfer gate TG in the height direction is ensured, and the electric field between the FD 114 and the transfer gate TG is relaxed.

[0193] As described above, in the imaging device 1 of the present embodiment, it is possible to realize an imaging device having a three-dimensional structure that can reduce the generation of dark current. In addition, it is possible to improve the charge transfer efficiency.

[0194] Furthermore, in the present embodiment, the contact layer 117 is formed in the recess 100Y of the semiconductor layer 100S; therefore, in addition to the distance between the FD 114 and the transfer gate TG, the distance in the height direction from the contact layer 117 is also ensured. Therefore, the electric field between the transfer gate TG and the contact layer 117 is relaxed, thereby being able to further reduce the generation of dark current.

[0195] The second embodiment and modified examples 1 to 5, application examples, and actual application examples will be described below. In the following description, the same components as those of the first embodiment are denoted by the same reference numerals, and their description is omitted.

[0196] <2. Modifications>

[0197] (2-1. Modification 1)

[0198] Fig.11 A cross-sectional configuration example of an imaging device (imaging device 1A) according to Modification 1 of the present disclosure is shown. Fig.12 Schematically shows Fig.11 2A and 2B show an example of a planar layout of a first substrate 100 and a second substrate 200 of an imaging device 1A.

[0199] The first embodiment described above provides an example in which the second substrate 200 is bonded to the first substrate 100 in a front-to-front manner, so that the front side (surface 200S1) of the semiconductor layer 200S on which various transistors (select transistor SEL, amplifier transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) constituting the pixel circuit 210 are disposed is opposite to the first substrate 100; however, the present disclosure is not limited thereto. For example, as Fig.11In the imaging device 1A shown, when various transistors (select transistor SEL, amplifier transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) constituting the pixel circuit 210 are three-dimensional structures such as Fin-FETs, the second substrate 200 can be bonded to the first substrate 100 in such a manner that the back side (surface 200S2 of the semiconductor layer 200S) of the second substrate 200 faces the front side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 can be bonded to the first substrate 100 in a front-to-back manner.

[0200] In this way, in the imaging device 1A in which the first substrate 100 and the second substrate 200 are joined in a front-to-back manner, for example, the FD 114 provided in the first substrate 100 and the gate of the amplifier transistor AMP provided in the second substrate 200 and the transfer gate TG provided in the first substrate and the reference potential line VSS provided in the third substrate 300 can be electrically connected, for example, through the through electrodes 223 and 224.

[0201] In this configuration, effects similar to those of the above-described first embodiment can be obtained.

[0202] (2-2. Modification 2)

[0203] Fig.13A An example of a pixel array of an imaging device according to Modification 2 of the present disclosure is schematically shown. Fig. 13B Another example of a pixel array of an imaging device according to a second variation of the present disclosure is schematically shown. The device structure described in the first embodiment and variation 1 above is also applicable to a device having, for example, Fig.13A The Bayer array shown in FIG. Fig. 13B The imaging device of the Quad Bayer array shown in FIG. 1 is a Quad Bayer array. Note that, in the case of the Quad Bayer array, the FDs 114 for the same color pixels are connected to each other by, for example, Cu wires or the like.

[0204] <3. Second embodiment>

[0205] Fig.14 A cross-sectional configuration example of an imaging device (imaging device 2 ) according to a second embodiment of the present disclosure in a direction perpendicular to the main surfaces of the first substrate 100 , the second substrate 200 , and the third substrate 300 is shown. Fig.15 An example of a cross-sectional structure of an imaging device 2 according to a second embodiment of the present disclosure in a direction perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300 is shown, but the position is different from Fig.14 location. Fig.16Schematically shows a planar layout example of an imaging device 2 according to a second embodiment of the present disclosure; Fig.14 and 15 Corresponding to the Fig.16 Cross sections along line III-III' and line IV-IV' are shown.

[0206] [Cross-sectional structure of imaging device]

[0207] In the imaging device 2, as in the above-mentioned first embodiment, the first substrate 100, the second substrate 200 and the third substrate 300 are stacked up and down in this order. The imaging device 2 also includes a light receiving lens 414 located on the back side (light incident side) of the first substrate 100. Between the light receiving lens 414 and the first substrate 100, for example, a light shielding film 411, a protective layer 412 and a color filter layer 413 are provided. The light receiving lens 414 is provided, for example, in each of the pixels 541A, 541B, 541C and 541D. The imaging device 2 is, for example, a back-illuminated imaging device. The imaging device 2 includes a pixel array portion 540 provided in the middle and a peripheral portion (not shown) provided outside the pixel array portion 540.

[0208] The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The semiconductor layer 100S includes, for example, a silicon substrate. The semiconductor layer 100S has a pair of surfaces opposite to each other (a surface 100S1 as a front surface and a surface 100S2 as a back surface). The semiconductor layer 100S includes a p-well layer 112 in a portion of the surface 100S1 and its adjacent region, and includes an n-type semiconductor region 111 in another region (a region deeper than the p-well layer 112). For example, the n-type semiconductor region 111 and the p-well layer 112 constitute a pn junction photodiode PD. The p-well layer 112 is a p-type semiconductor region.

[0209] The FD 114 and the contact region 118 are disposed adjacent to the front surface of the semiconductor layer 100S. The FD 114 includes an n-type semiconductor region disposed in the p-well layer 112. The FD 114 is disposed for each pixel 541. For example, Fig.16As shown, the FD 114 provided for each pixel 541 is provided approximately in the middle of the pixel 541. As will be described in detail later, each of the FDs 114 (FD1, FD2, FD3, and FD4) provided in the four pixels 541A, 541B, 541C, and 541D constituting the unit cell 539 is electrically connected to each other through an electrical connection member (wiring in the wiring layer 100T) within the first substrate 100 (more specifically, within the wiring layer 100T). In addition, the FD 114 is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) through an electrical member (for example, contact portions 122, 222, etc.). In the second substrate 200 (more specifically, within the wiring layer 200T), the FD 114 is electrically connected to the gate of the amplifier transistor AMP constituting the pixel circuit 210 and the source of the FD conversion gain switching transistor FDG through the electrical member.

[0210] The contact region 118 is a region electrically connected to the reference potential line VSS, and is arranged away from the FD 114. The contact region 118 is provided, for example, between the unit cells 539 adjacent in the V direction (Z-axis direction). The contact region 118 includes, for example, a p-type semiconductor region. The contact region 118 is connected to, for example, a ground potential or a fixed potential. Thus, the semiconductor layer 100S is provided with a reference potential. The contact region 118 includes, for example, a p-type semiconductor region.

[0211] In addition to the photodiode PD, FD 114 and the contact region 118, the first substrate 100 is also provided with a transfer transistor TR. The transfer transistor TR is provided for each pixel 541. The transfer transistor TR has a transfer gate TG. As will be described in detail later, the transfer gate TG may be, for example, Fig.16 Each pixel 541 is arranged around the FD 114 as shown, or it may be arranged around the FD 114 as shown, for example. Fig. 22 As shown, it is disposed between the unit cells 539 adjacent in the X-axis direction and is continuous in two pixels 541 adjacent in the X-axis direction. Thus, the number of wirings extending in the stacking direction (Y-axis direction) (for example, the number of through electrodes 224) can be reduced.

[0212] The semiconductor layer 100S is provided with a separation portion 115 that separates adjacent pixels 541 from each other. The separation portion 115 is formed to extend along the normal direction (Y-axis direction) of the semiconductor layer 100S. The separation portion 115 is used to separate adjacent unit cells 539 and separate the four pixels 541 (pixels 541A, 541B, 541C, and 541D) constituting the unit cell 539 from each other, and has, for example, a grid-like planar shape. For example, the separation portion 115 electrically separates adjacent pixels 541 from each other. The separation portion 115 may have, for example, the same FTI structure as in the first embodiment described above, or may have, for example, Fig.14 and 15 The structure shown in the figure, wherein it passes through between the surfaces 100S1 and 100S2 of the semiconductor layer 100S by a combination of a shallow trench isolation (STI) structure and a DTI structure that does not penetrate the semiconductor layer 100S. The separation portion 115 is formed, for example, by embedding an insulating film such as silicon oxide (SiO) into a groove provided on the semiconductor layer 100S. It should be noted that a metal material having a light-shielding effect, such as tungsten (W), can be embedded inside the insulating film of the separation portion 115. Thus, adjacent pixels 541 can be separated from each other electrically and optically. The semiconductor layer 100S is also provided with a p-type diffusion region 119 on the side surface of the separation portion 115.

[0213] In the present embodiment, the semiconductor layer 100S has the following structure: the surface 100S1 is uneven. Specifically, the semiconductor layer 100S has a plurality of protrusions 100X on the surface 100S1, and Fig.14 and 15 As shown, FD 114 is formed on the upper surface of each of the plurality of protrusions 100X. In the lower portion of each of the plurality of protrusions 100X, for example, a p-type semiconductor layer 113 having a higher impurity concentration than the p-well layer 112 is formed; the p-type semiconductor layer 113 serves as an overflow path. That is, in the plurality of protrusions 100X, the p-type semiconductor layer 113, the p-well layer 112, and the FD 114 are stacked in sequence starting from the n-type semiconductor region 111 side. The transfer gate TG is disposed around the plurality of protrusions 100X and is formed so that the position of its upper surface is higher than that of the FD 114. The side wall 123 is disposed on the side surface of the transfer gate TG protruding more upward than the protrusion 100X. Thus, the distance between the FD 114 and the transfer gate TG in the height direction (Z-axis direction) can be ensured.

[0214] The contact region 118 is formed in the surface 100S1 of the semiconductor layer 100S and over the separation portion 115 , and is electrically connected to the semiconductor layer 100S.

[0215] The wiring layer 100T disposed between the semiconductor layer 100S and the second substrate 200 includes an interlayer insulating layer 121, the above-mentioned transmission gate TG, a plurality of contacts 122, and a contact region 118. The interlayer insulating layer 121 is disposed on the entire surface of the semiconductor layer 100S and buries the protrusions and depressions on the front side (surface 100S1) of the semiconductor layer 100S. Further, one or more wirings are formed in the interlayer insulating layer 121, and a plurality of contacts 122 are embedded in the front side of the interlayer insulating layer relative to the second substrate 200. The interlayer insulating layer 121 includes, for example, a silicon oxide film. The contact layer 124 includes, for example, polycrystalline silicon (poly-Si), more specifically, doped polycrystalline silicon doped with impurities. It should be noted that the configuration of the wiring layer 100T is not limited to the above configuration, and it only needs to include wiring and an insulating film.

[0216] A plurality of contacts 122 are exposed on the surface of the wiring layer 100T. Some of the contacts 122 are connected to, for example, the FD 114 provided for each pixel 541, and are connected to the pixel circuit 210 (for example, the gate of the amplifier transistor AMP) through the contact 222 provided on the second substrate 200 side. In addition, some of the contacts 122 are connected to the contact region 118, and are connected to, for example, a reference potential line VSS provided in the third substrate 300 through the contact 222 provided on the second substrate 200 side, etc. The plurality of contacts 122 are used to bond with the second substrate 200. The plurality of contacts 122 include, for example, a metal such as copper (Cu) or aluminum (Al).

[0217] The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T disposed on the front side (surface 200S1) of the semiconductor layer 200S. The semiconductor layer 200S includes a silicon substrate. The semiconductor layer 200S is provided with a well region 211 in the entire thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 200 is provided with a pixel circuit 210, for example, in the unit cell 539, one pixel circuit 210 is provided for two pixels adjacent in the V direction. The pixel circuit 210 is, for example, disposed on the front side (surface 200S1) of the semiconductor layer 200S, that is, the wiring layer 200T side. In the imaging device 2, the second substrate 200 is bonded to the first substrate 100 so that the back side of the second substrate 200 (surface 200S2 side of the semiconductor layer 200S) is opposite to the front side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is bonded to the first substrate 100 in a front-to-back manner.

[0218] The second substrate 200 further includes an insulating region 212 for dividing the semiconductor layer 200S. The insulating region 212 has substantially the same thickness as that of the semiconductor layer 200S, and the semiconductor layer 200S is divided by the insulating region 212. The insulating region 212 includes, for example, silicon oxide.

[0219] The wiring layer 200T includes an interlayer insulating layer 221, gates of the various transistors (selection transistor SEL, amplifier transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) constituting the pixel circuit 210, and a plurality of contact portions 222. The interlayer insulating layer 221 is disposed on the entire surface of the semiconductor layer 200S. Further, one or more wirings are formed in the interlayer insulating layer 221. A plurality of contact portions 222 are exposed on the surface of the wiring layer 200T opposite to the first substrate 100. The plurality of contact portions 222 are used to bond with the third substrate 300. The interlayer insulating layer 221 includes, for example, a silicon oxide film. The plurality of contact portions 222 include, for example, a metal such as copper (Cu) or aluminum (Al). It should be noted that the configuration of the wiring layer 200T is not limited to the above configuration, and it only needs to include wiring and an insulating film.

[0220] For example, through electrodes 223, 224, and 225 are provided in the insulating region 212. The through electrodes 223, 224, and 225 are provided to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 223, 224, and 225 are connected to the wiring of the wiring layer 200T. These through electrodes 223, 224, and 225 are provided to penetrate the insulating region 212 and the interlayer insulating layer 121, and their lower ends are connected to the transfer gate TG, FD 114, and the contact layer 124, respectively.

[0221] The through electrode 223 electrically connects the transfer gate TG to the wiring of the wiring layer 200T (a part of the row drive signal line 542). That is, the transfer gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 through the through electrode 223, and the drive signal is transmitted to each transfer transistor TR. The through electrode 2224 electrically connects the FD 114 to the pixel circuit 210. That is, the FD 114 of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 through the through electrode 224. The through electrode 225 electrically connects the contact layer 124 to the reference potential line VSS of the third substrate 300. That is, the contact layer 124 of the first substrate 100 is electrically connected to the reference potential line VSS of the third substrate 300 through the through electrode 225.

[0222] The third substrate 300 includes, for example, a wiring layer 300T and a semiconductor layer 300S in sequence from the second substrate 200 side. For example, the front side of the semiconductor layer 300S is arranged on the second substrate 200 side. The semiconductor layer 300S includes a silicon substrate. A circuit is arranged in a part of the front side of the semiconductor layer 300S. Specifically, in the part of the front side of the semiconductor layer 300S, for example, at least some of the input part 510A, the row drive part 520, the timing control part 530, the column signal processing part 550, the image signal processing part 560 and the output part 510B are arranged. The wiring layer 300T arranged between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating layer 321 and a plurality of contact parts 332. The plurality of contact portions 322 are exposed on the surface of the wiring layer 200T, and the plurality of contact portions 322 are electrically connected to the circuit formed in the semiconductor layer 300S (for example, at least one of the input portion 510A, the row driving portion 520, the timing control portion 530, the column signal processing portion 550, the image signal processing portion 560, and the output portion 510B). The plurality of contact portions 322 are used to be bonded to the second substrate 200. The plurality of contact portions 322 include, for example, a metal such as copper (Cu) or aluminum (Al).

[0223] [Manufacturing method of imaging device]

[0224] Figures 17A to 17G Show Fig.14 An example of a method for manufacturing the imaging device 2 (particularly the first substrate 100) is shown in FIG.

[0225] First, if Fig.17A As shown, for example, a separation portion 115A having an STI structure is formed on the surface 100S1 side of the semiconductor layer 100S, and then a separation portion 115B having a DTI structure is formed from the surface 100S2 side of the semiconductor layer 100S, and a p-type diffusion region 119 is formed on its side surface.

[0226] Next, if Fig. 17B As shown, a mask 605 is formed on the surface 100S1 of the semiconductor layer 100S, and then, as shown in FIG. Fig. 17C As shown, the protrusion 100X is formed by processing the semiconductor layer 100S by, for example, photolithography and etching. Thereafter, a polysilicon film serving as a transfer gate TG is formed to cover a surface 100S1 of the protrusion 100X including the semiconductor layer 100S.

[0227] Then, if Fig.17D As shown in FIG. 6 , a mask 606 is formed on the polysilicon film. Next, as shown in FIG. Fig.17E As shown in FIG. 1 , the polysilicon film is processed by photolithography and etching, and then a derivatization process is performed. Next, as shown in FIG. Fig.17FAs shown, a p-type semiconductor layer 113 is formed at the lower portion of the protrusion 100C.

[0228] Then, if Figure 17G As shown in FIG. 1 , a side wall 123 is provided on the side surface of the transfer gate TG protruding from the protrusion 100X, and then, an n-type semiconductor region serving as the FD 114 is formed on the upper surface of the protrusion 100X by self-alignment. Then, a SiO film serving as an interlayer insulating layer 121, wiring, and a contact portion 122 are formed to form a wiring layer 100T. Through the above-mentioned process, the wiring layer 100T is completed. Fig.14 The first substrate 100 is shown in the figure.

[0229] [Effect]

[0230] In the imaging device 2 of the present embodiment, in the semiconductor layer 100S having a pair of surfaces (surfaces 100S1 and 100S2) opposing each other, a plurality of protrusions 100X are provided on the surface 100S1, an FD 114 is provided on the upper surface of each protrusion 100X, and a transfer gate TG is provided around the plurality of protrusions 100X with its upper surface protruding more upward than the protrusion 100X provided with the FD 114. Therefore, the distance between the FD 114 and the transfer gate TG in the height direction is ensured, and the electric field between the FD 114 and the transfer gate TG is relaxed.

[0231] As described above, in the imaging device 2 of the present embodiment, an imaging device having a three-dimensional structure in which generation of dark current is reduced can be realized. In addition, the charge transfer efficiency can be improved.

[0232] <4. Modifications>

[0233] (4-1. Modification 3)

[0234] Fig.18 A cross-sectional configuration example of an imaging device (imaging device 2A) according to Modification 3 of the present disclosure in a direction perpendicular to the main surfaces of the first substrate 100 , the second substrate 200 , and the third substrate 300 is shown. Fig.19 1 shows a cross-sectional configuration example of an imaging device 2A according to a second embodiment of the present disclosure in a direction perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300, but the position is different from Fig.18 location. Fig.18 and 19 Corresponding to the Fig.16 Cross sections along line III-III' and line IV-IV' are shown.

[0235] like Fig.18 and 19As shown, the sidewall 123 provided on the side surface of the transfer gate TG protruding more upward than the protrusion 100X may be embedded in the transfer gate TG along the side surface of the protrusion 100X.

[0236] Therefore, in addition to the effects of the second embodiment described above, an effect of being able to achieve reduction in pixel size while maintaining electric field relaxation is obtained.

[0237] (4-2. Modification 4)

[0238] Fig. 20 An example of a cross-sectional configuration of an imaging device (imaging device 2B) according to Modification 4 of the present disclosure in a direction perpendicular to the main surfaces of the first substrate 100 , the second substrate 200 , and the third substrate 300 is shown. Fig.21 1 shows a cross-sectional configuration example of an imaging device 2B according to a second embodiment of the present disclosure in a direction perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300, but the position is different from Fig. 20 location. Fig. 20 and 21 Corresponding to the Fig.16 Cross sections along line III-III' and line IV-IV' are shown.

[0239] like Fig. 20 and 21 As shown, the transmission gate TG formed around the protrusion 100X may be partially embedded in the semiconductor layer 100S. In other words, the transmission gate TG may be a vertical gate. In addition, an n-type semiconductor region 111X may be provided between the transmission gates TG embedded in the semiconductor layer 100S.

[0240] Therefore, in addition to the effect of the second embodiment described above, an effect of being able to achieve pixel size reduction while maintaining electric field relaxation is obtained.

[0241] (4-3. Modification 5)

[0242] Fig. 22 An example of a planar layout of an imaging device 2 according to a fifth modification of the present disclosure is schematically shown. For example, between unit cells 539 adjacent in the X-axis direction, the transfer gate TG may be continuously provided in two pixels 541 adjacent in the X-axis direction. Thus, the number of through electrodes 2254 may be reduced, thereby improving area efficiency.

[0243] <5. Third embodiment>

[0244] Fig.23 A planar configuration example of a pixel 541 of an imaging device (imaging device 3) according to a third embodiment of the present disclosure is schematically shown. Fig.24 Schematically showing the Fig.23 An example of a cross-sectional configuration corresponding to line VV' is shown.

[0245] [Configuration of Imaging Device]

[0246] As in the first embodiment described above, in the imaging device 3, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked up and down in this order. The imaging device 3 also includes a light receiving lens 414 located on the back side (light incident side) of the first substrate 100. Between the light receiving lens 414 and the first substrate 100, for example, a light shielding film 411, a protective layer 412, and a color filter layer 413 are provided. The light receiving lens 414 is provided, for example, for each pixel 541. The imaging device 3 is, for example, a back-illuminated imaging device. The imaging device 3 includes a pixel array portion 540 provided in the middle and a peripheral portion provided outside the pixel array portion 540.

[0247] Fig.25 An example of a planar configuration of a pixel array section 540 in an imaging device 3 is schematically shown. As in the imaging device 1 of the first embodiment described above, in the pixel array section 540, pixels 541 are repeatedly arranged in an array. In the imaging device 3 of the present embodiment, all pixels 541 constituting the pixel array section 540 are image plane phase difference pixels (image plane phase difference detection pixels). The image plane phase difference pixels divide the pupil area of ​​the imaging lens, and perform photoelectric conversion on the subject image from the divided pupil area, thereby generating a signal for phase difference detection.

[0248] like Fig.25 As shown, each pixel 541 constituting the pixel array section 540 is provided with a light receiving lens 414 (A) and, for example, any one of a color filter 413R that selectively allows wavelengths in the red band to be transmitted, a color filter 413G that selectively allows wavelengths in the green band to be transmitted, and a color filter 413B that selectively allows wavelengths in the blue band to be transmitted (B). It should be noted that the color filters 413R, 413G, and 413B are not limited to the following. Fig.25 The Bayer array shown in part (B) may be in various forms, such as a quad Bayer array, etc.

[0249] For example, Fig.25 As shown in part (A) of FIG. 5 , each pixel 541 includes left and right pixels 541R and 541L arranged in parallel along the X-axis direction. Fig.23 and 24As shown, the left and right pixels 541R and 541L are each provided with an n-type semiconductor region 111 constituting a photodiode PD, FD 114 and a transfer transistor TR. The left and right pixels 541R and 541L are also each provided with a contact region 117X connected to a contact layer 117.

[0250] On the front side (surface 100S1) of the semiconductor layer 100S, a columnar protrusion 100X is formed in each of the left and right pixels 541R and 541L. FD 114 is provided on the upper surface of the protrusion 100X. In addition, a gate (transfer gate TG) of a transfer transistor is formed around the protrusion 100X. The transfer gate TG is provided, for example, below the protrusion 100X provided with FD 114. Fig.23 As shown, the protrusion 100X formed in each of the left and right pixels 541R and 541L is preferably formed at the approximate center of the n-type semiconductor region 111 constituting the photodiode PD in a plan view. Thus, the charge generated by the photoelectric conversion can be efficiently transferred to the FD 114.

[0251] [Function and Effect]

[0252] In the pixel for phase difference detection (image plane phase difference pixel), phase difference information is acquired by reading out the charge photoelectrically converted by the right pixel and the left pixel respectively. Therefore, the transfer gates of the left and right pixels need to be driven independently of each other.

[0253] By the way, in the fine pixel structure as described above, for example, when the pixel pitch is less than 0.5 μm, the layout freedom in one pixel is limited. If a general planar transistor is used in the fine pixel structure, the formation area of ​​the transistor cannot be sufficiently ensured, so the transmission efficiency deteriorates, which leads to a decrease in image quality, for example, under low light conditions.

[0254] In order to improve the transfer efficiency, the introduction of an embedded gate that three-dimensionally extends the transfer gate has been promoted. However, in the embedded gate of a planar transistor, the channel for transferring charges may be affected by impurities, etc. used to separate the photodiode or element, and as it becomes finer, this influence becomes stronger, so the design difficulty increases and it is difficult to ensure the characteristics of the transistor.

[0255] Meanwhile, in the present embodiment, in the imaging device 3 in which all pixels 541 constituting the pixel array section 540 are image plane phase difference pixels, in each of the left and right pixels 541R and 541L, the protrusion 100X is provided on the surface 100S1 of the semiconductor layer 100S, the FD 114 is provided on the upper surface of each protrusion 100X, and the transfer gate TG is provided around the plurality of protrusions 100X and below the protrusion 100X provided with the FD 114. Therefore, the distance between the FD 114 and the transfer gate TG in the height direction is ensured, and the electric field between the FD 114 and the transfer gate TG is relaxed. In addition, the transfer channel can be protected from the influence of external impurities.

[0256] As described above, in the imaging device 3 of this embodiment, an imaging device having a three-dimensional structure that can reduce the generation of dark current can be realized. In addition, the charge transfer efficiency in the imaging device (imaging device 3) in which all pixels 541 constituting the pixel array section 540 are image plane phase difference pixels can be improved.

[0257] Furthermore, in the present embodiment, the protrusion 100X formed in each of the left and right pixels 541R and 541L is formed substantially at the center of the n-type semiconductor region 111 constituting the photodiode PD in a plan view. Therefore, the charge transfer efficiency can be further improved.

[0258] Note that, in the present embodiment, an example has been described in which the FD 114 is provided on the upper surface of the protrusion 100X formed on the surface 100S1 of the semiconductor layer 100S and is surrounded by the transfer gate TG; however, Fig.26 As shown, in an imaging device in which the FD 114 is disposed on the flat surface 100S1 without providing the protrusion 100X and a part of the transfer gate TG is embedded around the FD 114, the charge transfer efficiency can also be improved.

[0259] <6. Modifications>

[0260] (6-1. Modification 6)

[0261] Fig. 27 A planar configuration example of pixels of an imaging device (imaging device 3A) according to Modification 6 of the present disclosure is shown. Fig.28 Schematically showing the Fig. 27 An example of a cross-sectional configuration corresponding to line VI-VI' is shown.

[0262] In the third embodiment described above, an example has been described in which, in a plan view, the protrusion 100X is formed at approximately the center of the n-type semiconductor region 111 constituting the photodiode PD; however, the present disclosure is not limited thereto. In the imaging device 3A of the present modification, the protrusion 100X is formed near the end of the n-type semiconductor region 111 extending in the Z-axis direction.

[0263] In this way, in the present modification, the protrusion 100X is formed near the end of the n-type semiconductor region 111 extending in the Z-axis direction. Therefore, for example, when a plurality of pixels 541 share the FD 114, the FD wiring used can be shortened, and thus the conversion efficiency can be improved. Therefore, the S / N ratio is improved, and thus the image quality can be improved.

[0264] It should be noted that in this modification, the impurity concentration is adjusted so that the potential center of gravity of the photodiode PD is formed below the protrusion 100X, thereby improving the conversion efficiency and the transmission efficiency.

[0265] In addition, if Fig.29 As shown, in the imaging device in which the FD 114 is provided on the flat surface 100S1 without providing the protrusion 100X and a part of the transfer gate TG is embedded in the vicinity of the FD 114, the present configuration can also similarly improve the conversion efficiency.

[0266] (6-2. Modification 7)

[0267] Fig.30 A planar configuration example of pixels of an imaging device (imaging device 3B) according to Modification 7 of the present disclosure is shown. Fig.31 Schematically showing the Fig.30 An example of a cross-sectional structure corresponding to line VII-VII' is shown.

[0268] In the third embodiment described above, the example in which the contact portion CS is provided on the annular transmission gate TG surrounding the protrusion 100X has been described; however, the present disclosure is not limited thereto. In the imaging device 3B of this modified example, the annular transmission gate TG is provided with an overhang portion X, and the contact portion CS is provided on the overhang portion X.

[0269] In this way, in the present modification, the ring-shaped transmission gate TG is provided with the overhang portion X, and the contact portion CS is provided on the overhang portion X, so that the distance between the contact portion CS and the contact portion of the FD 114 can be ensured. Therefore, in addition to the effects of the third embodiment described above, the FD capacitance can be reduced. In addition, the occurrence of a short circuit can also be avoided.

[0270] In addition, if Fig.32As shown, in the imaging device in which the FD 114 is provided on the flat surface 100S1 without providing the protrusion 100X and a part of the transfer gate TG is embedded in the vicinity of the FD 114, the present configuration can also reduce the FD capacitance. In addition, the occurrence of a short circuit can be avoided.

[0271] (6-3. Modification 8)

[0272] Fig.33 An example of a planar configuration of pixels of an imaging device (imaging device 3C) according to Modification 8 of the present disclosure is shown. Fig.34 Schematically showing the Fig.33 The cross-sectional configuration example corresponding to the line VIII-VIII' shown.

[0273] In the above-described modification 7, an example has been described in which, in a plan view, the protrusion 100X is formed at approximately the center of the n-type semiconductor region 111 constituting the photodiode PD, the ring-shaped transfer gate TG having the overhang X is provided around the protrusion 100X, and the contact portion CS is provided on the overhang X; however, the present disclosure is not limited thereto. In the imaging device 3C of the present modification, the protrusion 100X is formed near the end of the n-type semiconductor region 111, and the overhang X is provided in the center direction of each of the left and right pixels 541R and 541L.

[0274] In this way, in the present modification, the protrusion 100X is formed near the end of the n-type semiconductor region 111, the ring-shaped transmission gate TG has an overhang X extending in the center direction of each of the left and right pixels 541R and 541L, and the contact portion CS is provided on the overhang X. Therefore, in addition to the effects of the third embodiment described above, the FD capacitance can be reduced while the conversion efficiency is improved. Furthermore, the occurrence of a short circuit can also be avoided.

[0275] In addition, if Fig.35 As shown, in the imaging device, the FD 114 is provided on the flat surface 100S1 without providing the protrusion 100X and a part of the transfer gate TG is embedded in the vicinity of the FD 114. This configuration can also reduce the FD capacitance and improve the conversion efficiency at the same time. In addition, short circuits can be avoided.

[0276] (6-4. Modification 9)

[0277] Fig.36 A planar configuration example of pixels of an imaging device (imaging device 3D) according to Modification 9 of the present disclosure is shown. Fig.37 Another planar configuration example of pixels of the imaging device (imaging device 3D) according to Modification 9 of the present disclosure is shown.

[0278] In the third embodiment described above, an example has been described in which a protrusion having a substantially perfect circular shape in a plan view and a ring-shaped transfer gate TG are provided; however, the present disclosure is not limited thereto. In the imaging device 3D of the present modification, a protrusion having a substantially elliptical shape in a plan view and a ring-shaped transfer gate TG surrounding the protrusion are provided at the substantially center or end of the n-type semiconductor region 111 constituting the photodiode PD in a plan view, and the contact portion CS is provided in the long axis direction.

[0279] In this way, in the present modification, a protrusion having a substantially elliptical shape in a plan view and a ring-shaped transfer gate TG surrounding the protrusion are provided, and the contact portion CS is provided in the long axis direction. Therefore, the contact portion of the FD 114 can be physically separated from the contact portion CS of the transfer gate TG. Therefore, in addition to the effects of the third embodiment described above, the S / N ratio can be improved.

[0280] (6-5. Modification 10)

[0281] Fig.38 A planar configuration example of an imaging device (imaging device 3E) according to Modification 10 of the present disclosure is shown. Fig.39 Another planar configuration example of the imaging device (imaging device 3E) according to Modification 10 of the present disclosure is shown.

[0282] In two pixels 541 adjacent to each other in a direction intersecting the parallel arrangement direction of the left and right pixels 541R and 541L, the respective annular transfer gates TG provided in the left and right pixels 541R and 541L can be connected to each other and shared. Fig.38 As shown, among the pixels 541-1, 541-2, 541-3 and 541-4 arranged in two rows and two columns, between the pixels 541-1 and 541-3 adjacent to each other along the Z-axis direction and between the pixels 541-2 and 541-4 adjacent to each other along the Z-axis direction, the respective annular transfer gates TG may be connected to each other and shared between the respective right pixels (between the right pixels 541R-1 and 541R-3 and between the right pixels 541R-2 and 541R-4) and between the respective left pixels (between the left pixels 541L-1 and 541L-3 and between the left pixels 541L-2 and 541L-4).

[0283] The shared transfer gate TG between the right pixel 541R-1 and 541R-3 and the shared transfer gate TG between the right pixel 541R-2 and 541R-4 are respectively connected to the wiring TRGL1. The shared transfer gate TG between the left pixel 541L-1 and 541L-3 and the shared transfer gate TG between the left pixel 541L-2 and 541L-4 are respectively connected to the wiring TRGL2. The respective FDs 114 arranged in the right pixel 541R-1 and the left pixel 541L-1 of the pixel 541-1 are electrically connected to each other through the wiring FDL1. The respective FDs 114 arranged in the right pixel 541R-2 and the left pixel 541L-2 of the pixel 541-2 are electrically connected to each other through the wiring FDL2. The respective FDs 114 arranged in the right pixel 541R-3 and the left pixel 541L-3 of the pixel 541-3 are electrically connected to each other through the wiring FDL3. The respective FDs 114 provided in the right pixel 541R- 4 and the left pixel 541L- 4 of the pixel 541 - 4 are electrically connected to each other through a wiring FDL4 .

[0284] Therefore, each transistor TR in the left and right pixels 541R and 541L of each pixel 541-1, 541-2, 541-3, and 541-4 can be controlled separately. In addition, the charge generated in the pixels 541-1, 541-2, 541-3, and 541-4 can be read out without mixing with the charge of another pixel. In addition, two pixels 541 adjacent to each other in the Z-axis direction can be read at the same time, thereby improving the frame rate.

[0285] It should be noted that Fig.39 As shown, the respective protrusions 100X provided in the left and right pixels 541R and 541L of each pixel 541-1, 541-2, 541-3, and 541-4 can be provided close to each other between pixels adjacent in the Z-axis direction. Thus, the area of ​​the electrode connected to the corresponding transfer gate TG is reduced, and thus the capacitance of the entire transfer gate TG is reduced. Therefore, the time required for the readout cycle can be reduced, and thus the frame rate can be increased.

[0286] In this way, in this modification, between two pixels 541 adjacent to each other in the direction intersecting the parallel arrangement direction of the left and right pixels 541R and 541L, the respective annular transfer gates TG provided in the left and right pixels 541R and 541L are connected to each other. Therefore, the number of contact portions CS is reduced compared to the third embodiment and the like described above. Therefore, the degree of freedom of layout can be improved.

[0287] (6-6. Modification 11)

[0288] Figures 40 to 43 A planar configuration example of pixels of an imaging device (imaging device 3F) according to Modification 11 of the present disclosure is shown.

[0289] In the third embodiment described above, an example has been described in which the separator 115 extends from opposite sides of the separator 115 in the Z-axis direction toward the center of the pixel 541 between the left and right pixels 541R and 541L in order to prevent the colors of the adjacent right pixel 541R and the left pixel 541L from being electrically mixed; however, the present disclosure is not limited thereto. For example, Fig.40 and 41 As shown, the separation portion 115 that separates the adjacent right pixel 541R and the left pixel 541L may extend from one side toward the other side of the separation portion 115 on both sides opposite to each other in the Z-axis direction.

[0290] In addition, if Fig.42 As shown, the separation portion (separation portion 115X) separating the adjacent left and right pixels 541R and 541L can be separated from the separation portion 115 surrounding the pixel 541. In this case, the separation portion 115X can have, for example, a reverse deep trench isolation (RDTI: Reverse Deep Trench Isolation) structure formed from the back side (surface 100S2) of the semiconductor layer 100S (such as Fig.43 as shown), or may be formed as, for example, a p-type impurity layer.

[0291] <7. Fourth embodiment>

[0292] Fig.44 A cross-sectional configuration example of a semiconductor layer 100S of an imaging device (imaging device 4 ) according to a fourth embodiment of the present disclosure is schematically shown. Fig.45A Schematically shows Fig.44 An example of a planar layout of a semiconductor layer 100S is shown. Fig.45B Schematically shows Fig.44 Another planar layout example of the semiconductor layer 100S is shown. It should be noted that Fig.44 Shown corresponding to Fig.45A and 45B A cross section along line IX-IX' is shown.

[0293] [Configuration of Imaging Device]

[0294] As in the first embodiment described above, in the imaging device 4, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked up and down in this order. The imaging device 4 also includes a light receiving lens 414 located on the back side (light incident side) of the first substrate 100. Between the light receiving lens 414 and the first substrate 100, for example, a light shielding film 411, a protective layer 412, and a color filter layer 413 are provided. The light receiving lens 414 is provided for each pixel 541. The imaging device 4 is, for example, a back-illuminated imaging device. The imaging device 4 includes a pixel array portion 540 arranged in the middle and a peripheral portion provided outside the pixel array portion 540.

[0295] The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The semiconductor layer 100S has a pair of surfaces opposite to each other (a surface 100S1 as a front surface and a surface 100S2 as a back surface), and a pn junction photodiode PD is formed in the layer. The semiconductor layer 100S includes, for example, a plurality of columnar protrusions 100X arranged for each pixel 541 on the surface 100S1, and FD 114 is formed on the upper surface of each of the plurality of protrusions 100X. The annular transmission gate TG is arranged around the protrusion 100X, and is formed so that its upper surface is located above the FD 114. In other words, the FD 114 is arranged at a height between the upper surface and the lower surface of the transmission gate TG.

[0296] The above structure is also applicable to the Fig.45B The left and right pixels 541R and 541L of the image plane phase difference pixel shown. Specifically, in each of the left and right pixels 541R and 541L, a columnar protrusion 100X is formed, and the FD 114 is set on the upper surface of the protrusion 100X. The annular transmission gate TG is set around each protrusion 100X and is formed so that the position of its upper surface is higher than the FD 114.

[0297] [Function and Effect]

[0298] In the imaging device 4 of the present embodiment, in the semiconductor layer 100S having a pair of surfaces (surfaces 100S1 and 100S2) opposing each other, a plurality of protrusions 100X are provided on the surface 100S1, an FD 114 is provided on the upper surface of each protrusion 100X, and a transfer gate TG is provided around the plurality of protrusions 100X with its upper surface protruding more upward than the protrusion 100X provided with the FD 114. Therefore, the pixel becomes finer, thereby reducing the occurrence of crosstalk between the FD 114 provided on the upper surfaces of adjacent protrusions 100X in adjacent pixels.

[0299] As described above, in the imaging device 4 of the present embodiment, an imaging device having a three-dimensional structure capable of reducing the generation of dark current can be realized. In addition, color mixing between adjacent pixels can be suppressed.

[0300] <8. Modifications>

[0301] (8-1. Modification 12)

[0302] Fig.46 A cross-sectional configuration example of a semiconductor layer 100S of an imaging device (imaging device 4A) according to Modification 12 of the present disclosure is schematically shown. Fig.47A Schematically shows Fig.46 An example of a planar layout of a semiconductor layer 100S is shown. Fig.47B Schematically shows Fig.46 Another planar layout example of the semiconductor layer 100S is shown. It should be noted that Fig.46 Shown corresponding to Fig.47A and 47B A cross section along line XX' is shown.

[0303] In the fourth embodiment described above, an example is described in which a continuous ring-shaped transfer gate TG is provided around the protrusion 100X; however, the present disclosure is not limited thereto. In the imaging device 4A of the present modification, the transfer gate TG is selectively formed only in the direction where FD connection between adjacent pixels is concerned.

[0304] In this way, in the present modification, the transfer gate TG is selectively formed only in the direction where there is a concern about FD connection between adjacent pixels. Therefore, an effect similar to that of the fourth embodiment described above can be obtained.

[0305] (8-2. Modification 13)

[0306] Fig.48 A planar configuration example of pixels of an imaging device (imaging device 4B) according to Modification 13 of the present disclosure is schematically shown.

[0307] In the above-mentioned modification 12, the following example is described: in the pixel 541 as an imaging pixel having a square shape, the transfer gate TG is selectively formed only in the direction in which FD connection between adjacent pixels is concerned; however, the present disclosure is not limited to this. In the imaging device 4B of this modification, in the left and right pixels 541R and 541L having a substantially rectangular shape constituting the image plane phase difference pixel, the transfer gate TG is selectively formed only in the direction in which FD connection is concerned.

[0308] also, Fig.48An example is shown in which the protrusion 100X is formed at approximately the center of the n-type semiconductor region 111 constituting the photodiode PD in a plan view; however, the present disclosure is not limited thereto. Fig.49 As shown, the present structure is also applicable to an imaging device 3A in which the protrusion 100X in the above-mentioned modification example 6 is formed near the end of the n-type semiconductor region 111 .

[0309] In addition, if Fig.50 and 51 As shown, the present structure can also be applied to imaging devices 3B and 3C in which the transfer gate TG in the above-mentioned modified examples 7 and 8 is provided with an overhang X, and the contact portion CS is provided on the overhang X. Fig.52 and 53 As shown, the present structure can also be applied to an imaging device 3D in which the transfer gate TG in the above-mentioned modification 9 is provided with a protrusion that is substantially elliptical in a plan view, and the contact portion CS is provided in the long axis direction. Fig.54 and 55 As shown, the present structure can also be applied to an imaging device 3E, in which, in two adjacent pixels 541 in the above-mentioned variant example 10 along a direction intersecting with the parallel arrangement direction of the left and right pixels 541R and 541L, the respective transfer gates TG arranged in the left and right pixels 541R and 541L are interconnected and shared.

[0310] also, Figures 48 to 55 An example is shown in which the transfer gate TG is selectively formed on the adjacent pixel 541 side; however, the present disclosure is not limited thereto. In the case where there is a concern about FD connection between the adjacent right pixel 541R and the left pixel 541L in the pixel 541, as shown in FIG. Fig.56 and 57 As shown, the transfer gate TG is selectively formed on the adjacent left and right pixel 541R and pixel 541L sides.

[0311] In this manner, in the present modification, the transfer gate TG is selectively formed only in the direction where there is a concern about FD connection between adjacent image plane phase difference pixels. Therefore, it is possible to obtain an effect similar to that of the fourth embodiment described above.

[0312] <9. Fifth embodiment>

[0313] Fig.58 A planar configuration example of a pixel array section 540 in an imaging device (imaging device 5 ) according to a fifth embodiment of the present disclosure is schematically shown. Fig.59 The semiconductor layer 100S is schematically shown along Fig.58 The cross-sectional configuration example of the line XI-XI' is shown. Fig.60The semiconductor layer 100S is schematically shown along Fig.58 Another cross-sectional structure example along line XI-XI' is shown.

[0314] [Configuration of Imaging Device]

[0315] As in the first embodiment described above, in the imaging device 5, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked up and down in this order. The imaging device 5 also includes a light receiving lens 414 located on the back side (light incident side) of the first substrate 100. Between the light receiving lens 414 and the first substrate 100, for example, a light shielding film 411, a protective layer 412, and a color filter layer 413 are provided. The light receiving lens 414 is provided for each pixel 541. The imaging device 5 is, for example, a back-illuminated imaging device. The imaging device 2 includes a pixel array portion 540 provided in the middle and a peripheral portion provided outside the pixel array portion 540.

[0316] All pixels 541 constituting the pixel array section 540 are image plane phase difference pixels. In each pixel 541 constituting the pixel array section 540, one light receiving lens 414 is provided, and, for example, any one of a color filter 413R that selectively allows wavelengths in the red band to be transmitted, a color filter 413G that selectively allows wavelengths in the green band to be transmitted, and a color filter 413B that selectively allows wavelengths in the blue band to be transmitted is provided in four pixels 541 arranged in two rows and two columns.

[0317] In the imaging device 5, among the four pixels 541 arranged in two rows and two columns and provided with any of the color filters 413R, 413G, and 413B, each FD 114 is formed near the intersection of each of the left and right pixels 541R and 541L between two pixels 541 adjacent in the direction (Y-axis direction) intersecting the parallel arrangement direction (X-axis direction) of the left and right pixels 541R and 541L. The four FDs 114 provided in each of the left and right pixels 541R, 541L of the two pixels 541 adjacent in the Z-axis direction are electrically connected to each other through the contact portion layer 114X formed on the separation portion 115, and therefore, the four FDs 114 are shared in each of the left and right pixels 541R, 541L of the two adjacent pixels 541. In the present embodiment, a substantially annular transfer gate TG is formed to surround the shared four FDs 114.

[0318] It should be noted that in the imaging device 5, the separation portion 115 may have an FTI structure in which the separation portion is formed from the front side (surface 100S1) of the semiconductor layer 100S, or a DTI structure in which the separation portion is formed from the back side (surface 100S2). By adopting the DTI structure and adjusting the depth of the separation portion 115, the contact layer 114X can be formed more deeply. In addition, in the case where the separation portion 115 is configured as a DTI structure, a continuous annular transmission gate TG can be formed around the common four FDs 114.

[0319] It should be noted that Fig.59 For example, an example is shown in which the FD 114 is provided on the upper surface of the protrusion 100X formed on the surface 100S1 of the semiconductor layer 100S; however, Fig.60 As shown, the FD 114 may be disposed on the flat surface 100S1 without providing the protrusion 100X, and a portion of the transfer gate TG may be embedded around the FD 114 .

[0320] [Function and Effect]

[0321] In the imaging device 5 of the present embodiment, among the plurality of pixels 541 that share the same color filters 413R, 413G, and 413B, between two pixels 541 that are adjacent in a direction (Y-axis direction) that intersects the parallel arrangement direction (X-axis direction) of the left and right pixels 541R and 541L, four FDs 114 are formed near the intersection of the respective left and right pixels 541R and 541L, and a substantially annular transfer gate TG is formed to surround the four FDs 114. Thus, the occurrence of electrical crosstalk between pixels having different detection wavelengths is reduced.

[0322] As described above, in the imaging device 5 of the present embodiment, it is possible to realize an imaging device having a three-dimensional structure capable of reducing the generation of dark current. In addition, adjacent pixels can be suppressed.

[0323] Furthermore, in the present embodiment, the contact layer 114X is formed between the four FDs 114, and the contact CS is provided on the contact layer 114X. Therefore, the number of the contact CS can be reduced.

[0324] <10. Modification 14>

[0325] Fig.61 A planar configuration example of pixels of an imaging device (imaging device 5A) according to Modification 14 of the present disclosure is schematically shown. Fig.62 Another planar configuration example of pixels of the imaging device (imaging device 5A) according to Modification 14 of the present disclosure is schematically shown.

[0326] In the fifth embodiment described above, an example has been described in which four FDs 114 are formed near the intersection of each of the left and right pixels 541R and 541L between two pixels adjacent in the Y-axis direction, and the four FDs 114 are shared with each other; however, the present disclosure is not limited thereto. In the imaging device 5A of the present modification, the FDs 114 are shared only between the left and right pixels 541R and 541L.

[0327] It should be noted that in the case where the FD 114 is shared between the left and right pixels 541R and 541L, as shown in FIG. Fig.61 As shown, FD 114 may be formed at the end of pixel 541, or as Fig.62 As shown, a separation portion 115X independent of the separation portion 115 may be provided, and the FD 114 may be formed at a substantial center of the pixel 541 .

[0328] <11. Application Examples>

[0329] Fig.63 A schematic configuration example of an imaging system 6 including the imaging apparatus (eg, the imaging apparatus 1 ) according to the above-described first to fifth embodiments and Modifications 1 to 14 thereof is shown.

[0330] The imaging system 6 is an electronic device, for example, an imaging device such as a digital still camera or a video camera, a portable terminal device such as a smartphone or a tablet terminal, etc. The imaging system 6 includes, for example, the imaging device 1 according to the above-described embodiment and its modified example, a DPS circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the imaging system 6, the imaging device 1 according to the above-described embodiment and its modified example, the DPS circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are connected to each other via a bus 249.

[0331] The imaging device (e.g., the imaging device 1) according to the above-described embodiments and the like outputs image data according to incident light. The DPS circuit 243 is a signal processing circuit that processes a signal (image data) output from the imaging device 1 according to the above-described embodiments and their modified examples. The frame memory 244 temporarily stores the image data processed by the DPS circuit 243 frame by frame. The display unit 245 includes, for example, a panel-type display device (e.g., a liquid crystal panel or an organic electroluminescent (EL) panel), and displays thereon a moving image or a still image captured by the imaging device 1 according to the above-described embodiments and their modified examples. The storage unit 246 records the image data of the moving image or the still image captured by the imaging device 1 according to the above-described embodiments and their modified examples on a recording medium (e.g., a semiconductor memory or a hard disk). The operation unit 247 issues operation commands related to various functions possessed by the imaging system 6 according to the user's operation. The power supply unit 248 appropriately supplies various electric powers that become the operation power of these power supply targets to the imaging device 1 according to the above-described embodiments and their modified examples, the DPS circuit 243, the frame memory 244, the display unit 245, the storage unit 246, and the operation unit 247.

[0332] Subsequently, the imaging process in the imaging system 6 will be described.

[0333] Fig.64 An example of the flow of the imaging process in the imaging system 6 is shown. The user operates the operation unit 247 and thereby issues an instruction to start imaging (step S101). Then, the operation unit 247 sends an imaging command to the imaging device 1 (step S102). When the imaging command is received, the imaging device 1 (specifically, the system control circuit 36) performs imaging by a predetermined imaging method (step S103).

[0334] The imaging device 1 outputs the image data obtained by imaging to the DPS circuit 243. The image data here refers to the data of the pixel signals generated in all pixels based on the charge temporarily stored in the floating diffusion FD. The DPS circuit 243 performs predetermined signal processing such as noise reduction processing according to the image data input from the imaging device 1 (step S104). The DPS circuit 243 causes the frame memory 244 to store the image data subjected to the predetermined signal processing, and the frame memory 244 causes the storage unit 246 to store the image data (step S105). In this way, imaging is performed in the imaging system 6.

[0335] In this application example, the imaging device 1 according to the above-described embodiment and its modified example is applied to an imaging system 6. Thus, the imaging device 1 can be made smaller or have higher definition, so that a small-sized or high-definition imaging system 6 can be provided.

[0336] <12. Practical application examples>

[0337] [Actual application example 1]

[0338] Fig.65 : is a diagram showing a schematic configuration example of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (the present technology) can be applied.

[0339] exist Fig.65 , a state is shown in which a surgical operator (doctor) 11131 is using an endoscopic surgical system 11000 to perform surgery on a patient 11132 on a bed 11133. As shown in the figure, the endoscopic surgical system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 for supporting the endoscope 11100 thereon, and a cart 11200 on which various endoscopic surgical devices are mounted.

[0340] The endoscope 11100 includes a lens barrel 11101 and a camera head 11102 connected to the proximal end of the lens barrel 11101, and a region of the lens barrel 11101 having a predetermined length starting from the distal end thereof is inserted into a body cavity of a patient 11132. In the illustrated example, the endoscope 11100 is shown as including a rigid endoscope including the rigid lens barrel 11101. However, the endoscope 11100 may also be a flexible endoscope including the flexible lens barrel 11101.

[0341] The lens barrel 11101 has an opening at its distal end, and the objective lens is fitted into the opening. The light source device 11203 is connected to the endoscope 11100, so that the light generated by the light source device 11203 is introduced into the distal end of the lens barrel 11101 through the light guide extending inside the lens barrel 11101, and irradiated toward the observation target in the body cavity of the patient 11132 through the objective lens. It should be noted that the endoscope 11100 can be a forward-looking endoscope, or can be an oblique-looking endoscope or a side-looking endoscope.

[0342] An optical system and an image capturing element are provided inside the camera 11102, so that the reflected light (observation light) from the observation target is focused on the image capturing element through the optical system. The observation light is photoelectrically converted by the image capturing element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the CCU 11201 as raw data.

[0343] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102, and performs various image processing such as development processing (demosaic processing) on ​​the image signal to display an image based on the image signal.

[0344] Under the control of the CCU 11201 , the display device 11202 displays an image thereon based on the image signal on which the CCU 11201 has performed image processing.

[0345] The light source device 11203 includes, for example, a light source such as a light emitting diode (LED), and provides illumination light to the endoscope 11100 when imaging a surgical field.

[0346] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various types of information or instructions in the endoscopic surgery system 11000 through the input device 11204. For example, the user can input instructions for changing the image capturing conditions (type of irradiation light, magnification factor, focal length, etc.) of the endoscope 11100.

[0347] The treatment tool control device 11205 controls the driving of the energy device 11112 for cauterizing tissue, cutting tissue, sealing blood vessels, etc. The pneumoperitoneum device 11206 feeds gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity, thereby ensuring the field of view of the endoscope 11100 and ensuring the working space for the treatment operation. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of printing various information related to the operation in various forms such as text, images, and charts.

[0348] It should be noted that, for example, the light source device 11203 that provides irradiation light to the endoscope 11100 when imaging the surgical area may include a white light source, such as an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted by the light source device 11203. In addition, in this case, if the laser beam from the RGB laser light source is irradiated to the observation target in a time-division manner and the drive of the image capturing element of the camera 11102 is controlled in synchronization with the emission timing, images corresponding to RGB respectively can be captured in a time-division manner. According to this method, a color image can be acquired even if a color filter is not provided for the image capturing element.

[0349] In addition, the light source device 11203 can be controlled so that the intensity of the output light is changed at each predetermined time. By controlling the drive of the image capturing element of the camera 11102 in synchronization with the timing of the change in light intensity so as to acquire images in a time-division manner and synthesize the images, a high dynamic range image without underexposed shadows and overexposed highlights can be generated.

[0350] In addition, the light source device 11203 can be configured to provide light having a predetermined wavelength region domain prepared for specific light observation. In specific light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue to irradiate light having a narrower band than the irradiation light (i.e., white light) during normal observation, imaging (narrow-band imaging) for predetermined tissues such as blood vessels in the surface part of the mucosal layer with high contrast is performed. Alternatively, in specific light observation, fluorescence observation for obtaining an image based on fluorescence generated by irradiation of excitation light can be performed. In fluorescence observation, observation of fluorescence from body tissue (autofluorescence observation) can be performed by irradiating body tissue, or a fluorescent image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to provide narrow-band light and / or excitation light suitable for specific light observation as described above.

[0351] Fig.66 It is shown Fig.65 A block diagram of an example of the functional configuration of the camera 11102 and the CCU 11201 shown.

[0352] The camera 11102 includes a lens unit 11401, an image capturing unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 to communicate with each other.

[0353] The lens unit 11401 is an optical system provided at a position connected to the lens barrel 11101. Observation light acquired from the distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0354] The number of image capturing elements included in the image capturing unit 11402 may be one (single-board type) or multiple (multi-board type). In the case where the image capturing unit 11402 is configured as a multi-board type, for example, image signals corresponding to R, G, and B, respectively, are generated by the image capturing elements, and a color image can be obtained by synthesizing these image signals. The image capturing unit 11402 may also be configured to have a pair of image capturing elements for acquiring a right-eye image signal and a left-eye image signal for three-dimensional (3D) display. If a 3D display is performed, the surgical operator 11131 is able to more accurately perceive the depth of body tissue at the surgical site. It should be noted that in the case where the image capturing unit 11402 is configured as a multi-board type, a plurality of systems of lens units 11401 may be arranged in a manner corresponding to the respective image capturing elements.

[0355] In addition, the image capturing unit 11402 may not necessarily be disposed in the camera head 11102. For example, the image capturing unit 11402 may be disposed immediately after the objective lens inside the lens barrel 11101.

[0356] The driving unit 11403 includes an actuator, and under the control of the camera control unit 11405, the driving unit 11403 moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis. Therefore, the magnification and focus of the image captured by the image capturing unit 11402 can be appropriately adjusted.

[0357] The communication unit 11404 includes a communication device for transmitting / receiving various information to / from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the image capturing unit 11402 to the CCU 11201 through the transmission cable 11400 as raw data.

[0358] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and provides the control signal to the camera control unit 11405. For example, the control signal includes information related to imaging conditions, such as information for specifying a frame rate for capturing an image and information for specifying an exposure value when capturing an image and / or information for specifying a magnification and a focus of a captured image.

[0359] It should be noted that image capturing conditions such as frame rate, exposure value, magnification, and focus may be appropriately specified by the user or automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are combined in the endoscope 11100.

[0360] The camera control unit 11405 controls the driving of the camera 11102 based on a control signal received from the CCU 11201 through the communication unit 11404 .

[0361] The communication unit 11411 includes a communication device for transmitting / receiving various types of information to / from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 through the transmission cable 11400.

[0362] In addition, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal may be transmitted through electrical communication, optical communication, or the like.

[0363] The image processing unit 11412 performs various image processing on the image signal transmitted from the camera 11102 in the form of raw data.

[0364] The control unit 11413 performs various types of control related to image capture of the operation area, etc. performed by the endoscope 11100 and display of captured images obtained by the image capture of the operation area, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0365] In addition, the control unit 11413 controls the display device 11202 to display a captured image depicting the surgical area, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 can identify various objects in the captured image by using various image recognition technologies. For example, the control unit 11413 can identify surgical tools such as forceps, specific living parts, bleeding, fog when using the energy device 11112, etc. by detecting the shape, color, etc. of the edge of the object included in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can display various surgical auxiliary information in a manner superimposed with the image of the surgical area by using the recognition result. By displaying and presenting the surgical auxiliary information to the surgical operator 11131 in a superimposed manner, the burden on the surgical operator 11131 can be reduced, or the surgeon 11131 can be enabled to perform surgery more reliably.

[0366] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electric signal cable for electric signal communication, an optical fiber for optical communication, or a composite cable for both electric communication and optical communication.

[0367] Here, in the example shown, although communication is performed by wired communication using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 may be performed by wireless communication.

[0368] As described above, an example of an endoscopic surgical system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be appropriately applied to the image capturing unit 11402 in the above-mentioned components, which is provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the image capturing unit 11402, the image capturing unit 11402 can be made smaller or have higher definition; therefore, a small-sized or high-definition endoscope 11100 can be provided.

[0369] [Actual application example 2]

[0370] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented in the form of a device installed on any type of mobile body, such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, and a robot.

[0371] Fig.67 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0372] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.67 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and an in-vehicle network interface (I / F) 12053 are shown as a functional configuration of the integrated control unit 12050.

[0373] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 acts as a control device for the following devices: a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a vehicle drive force, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a vehicle braking force, etc.

[0374] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a portable device as a key substitute or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0375] The vehicle exterior information detection unit 12030 detects external information about the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform processing for detecting objects such as people, vehicles, obstacles, signs, characters on the road surface, or processing for detecting their distances.

[0376] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may also output an electrical signal as an image, or may output an electrical signal as measured distance information. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0377] The in-vehicle information detection unit 12040 detects interior information about the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting a driver state. The driver state detection unit 12041 includes, for example, a camera for capturing an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0378] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside and outside of the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and output the control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control of functions aimed at realizing an advanced driver assistance system (ADAS), including collision avoidance or shock absorption of the vehicle, following driving based on vehicle spacing, speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0379] In addition, based on the environmental information about the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc., which enables the vehicle to drive automatically without relying on the driver's operation, etc.

[0380] In addition, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the external information about the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control for preventing glare by, for example, controlling the headlights to change from high beam to low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0381] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig.67 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are used as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0382] Fig.68 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0383] exist Fig.68 In the embodiment, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0384] The imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, arranged at the front nose, rearview mirror, rear bumper, rear door, and upper portion of the windshield of the vehicle 12100. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper portion of the windshield of the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged at the rearview mirror mainly acquire images on both sides of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or rear door mainly acquires images behind the vehicle 12100. The imaging unit 12105 arranged at the upper portion of the windshield of the vehicle is mainly used to detect vehicles in front, pedestrians, obstacles, signal lights, traffic signs, lanes, etc.

[0385] Notice, Fig.68An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0386] At least one of the imaging units 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0387] For example, the microcomputer 12051 can determine the distance of each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and extract the nearest three-dimensional object as the preceding vehicle, which is particularly present on the driving path of the vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in the substantially same direction as the vehicle 12100. In addition, the microcomputer 12051 is capable of presetting the following distance to be maintained in front of the preceding vehicle, and performing automatic braking control (including following stop control), automatic acceleration control (including following start control), etc. Therefore, it is possible to perform coordinated control for automatic driving so that the vehicle can travel automatically without relying on the operation of the driver, etc.

[0388] For example, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult to be visually identified by the driver of the vehicle 12100. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0389] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. This pedestrian recognition is performed, for example, by the following process: a process of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras; and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a square contour line for emphasis superimposed on the identified pedestrian. In addition, the sound / image output unit 12052 may control the display unit 12062 so as to display an icon or the like for indicating a pedestrian at a desired position.

[0390] As described above, an example of a mobile body control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to the imaging unit 12031 among the components of the above-mentioned structure. Specifically, the imaging device according to any one of the aforementioned embodiments and their modified examples can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a high-definition captured image with less noise can be obtained, so that high-precision control can be performed using the captured image in the mobile body control system.

[0391] The present disclosure has been described using the first to fifth embodiments and their Modifications 1 to 14, application examples, and actual application examples; however, the present disclosure is not limited to the above-described embodiments and the like, and various modifications may be made.

[0392] It should be noted that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have other effects than those described in this specification.

[0393] It should be noted that the present disclosure has the following construction. According to the following construction, in a first semiconductor substrate having first and second surfaces opposite to each other and including a plurality of pixels arranged in an array in an in-plane direction, a plurality of protrusions are arranged on the first surface according to each of the plurality of pixels, a plurality of charge holding units are arranged on each upper surface of the plurality of protrusions, the plurality of charge holding units hold charges generated in a plurality of photoelectric converters, a photoelectric converter is embedded in each pixel, and a gate of a transfer transistor is arranged around the plurality of protrusions, the transfer transistor transfers the charge held in the charge holding unit to the pixel circuit. Therefore, the distance in the height direction between the charge holding unit and the transfer gate is ensured. Therefore, the generation of dark current can be reduced.

[0394] (1) An imaging element comprising:

[0395] a first semiconductor substrate having a first surface and a second surface opposite to each other and including a plurality of pixels arranged in an array in an in-plane direction, a plurality of protrusions being provided on the first surface in accordance with each of the plurality of pixels;

[0396] a plurality of photoelectric converters, the plurality of photoelectric converters being formed in a manner embedded in the first semiconductor substrate for each of the pixels and generating charges according to an amount of received light;

[0397] a plurality of charge holding units which are respectively disposed on upper surfaces of the plurality of protrusions and hold charges generated in the plurality of photoelectric converters;

[0398] a second semiconductor substrate which is stacked on the first surface side of the first semiconductor substrate and is provided with one or more pixel circuits which generate pixel signals based on the charges generated by each of the plurality of photoelectric converters; and

[0399] A gate of a transfer transistor is provided around the plurality of protrusions and transfers the charge held in the charge holding unit to the pixel circuit.

[0400] (2) The imaging element according to (1), wherein the gate electrode is provided below the plurality of charge holding units respectively provided on the plurality of protrusions.

[0401] (3) The imaging element according to (1) or (2), wherein the gate electrode is provided to protrude upward more than upper surfaces of the plurality of protrusions, and a side wall is formed on a side surface of a protruding portion of the gate electrode.

[0402] (4) The imaging element according to (3), wherein a portion of the side wall is embedded between a side surface of the gate electrode and a side surface of the plurality of protrusions.

[0403] (5) The imaging element according to (3) or (4), wherein a portion of the gate electrode is embedded in the first semiconductor substrate.

[0404] (6) The imaging element according to any one of (1) to (5), wherein the first semiconductor substrate further includes a separation portion provided between the plurality of adjacent pixels and extending between the first surface and the second surface.

[0405] (7) The imaging element according to (6), further comprising a contact layer for applying a reference potential to the first semiconductor substrate.

[0406] The contact layer is embedded in the first surface of the first semiconductor substrate and is located above the separation portion.

[0407] (8) The imaging element according to (7), wherein the first surface of the first semiconductor substrate on which the contact layer is formed is a recess.

[0408] (9) The imaging element according to (7), wherein the contact portion layer is provided at the same height as the charge holding unit.

[0409] (10) The imaging element according to any one of (1) to (9), wherein the gate is provided for each of the plurality of pixels.

[0410] (11) The imaging element according to any one of (1) to (10), wherein the gate electrode is continuously provided in the plurality of adjacent pixels.

[0411] (12) The imaging element according to any one of (1) to (11), wherein one pixel circuit is provided for one pixel or each of the plurality of pixels.

[0412] (13) The imaging element according to any one of (1) to (12), wherein

[0413] Each of the first semiconductor substrate and the second semiconductor substrate further includes a multilayer wiring layer on the opposite surface side,

[0414] One or more pad electrodes are provided on the surface of each of the multilayer wiring layers, and

[0415] By bonding the one or more pad electrodes together, the first semiconductor substrate and the second semiconductor substrate are electrically connected to each other.

[0416] (14) The imaging element according to any one of (1) to (13), wherein the first semiconductor substrate and the second semiconductor substrate are electrically connected to each other via a through electrode penetrating between the first semiconductor substrate and the second semiconductor substrate.

[0417] (15) The imaging element according to any one of (1) to (14), wherein

[0418] The second semiconductor substrate has a third surface and a fourth surface facing each other,

[0419] The pixel circuit includes: a reset transistor that resets the potential of the charge holding unit to a predetermined position; an amplifying transistor that generates a signal having a voltage consistent with the level of the charge held in the charge holding unit as a pixel signal; and a selecting transistor that controls the timing of outputting the pixel signal from the amplifying transistor.

[0420] The reset transistor, the amplifying transistor, and the selecting transistor are provided on the third surface of the second semiconductor substrate, and

[0421] The first semiconductor substrate and the second semiconductor substrate are stacked, and the first surface and the third surface are opposite to each other.

[0422] (16) The imaging element according to any one of (1) to (15), wherein

[0423] The second semiconductor substrate has a third surface and a fourth surface facing each other,

[0424] The pixel circuit includes: a reset transistor that resets the potential of the charge holding unit to a predetermined position; an amplifying transistor that generates a signal having a voltage consistent with the level of the charge held in the charge holding unit as a pixel signal; and a selecting transistor that controls the timing of outputting the pixel signal from the amplifying transistor.

[0425] The reset transistor, the amplifying transistor, and the selecting transistor are provided on the third surface of the second semiconductor substrate, and

[0426] The first semiconductor substrate and the second semiconductor substrate are stacked, and the first surface and the third surface are opposite to each other.

[0427] (17) The imaging element according to (16), wherein the reset transistor, the amplification transistor, and the selection transistor are transistors having a three-dimensional structure.

[0428] (18) The imaging element according to any one of (1) to (17), further comprising, on the second surface side of the first semiconductor substrate, a color filter layer that selectively allows light of a predetermined wavelength to be transmitted, and a plurality of light receiving lenses arranged for each of the pixels.

[0429] (19) An imaging element according to (18), wherein, for one light receiving lens, each of the plurality of pixels includes two of the photoelectric converters, two of the protrusions, two of the charge holding units respectively arranged on the upper surfaces of the two protrusions, and two of the gates of the transfer transistors respectively arranged around the two protrusions.

[0430] (20) The imaging element according to (19), wherein

[0431] The plurality of pixels include a first pixel and a second pixel adjacent to each other in a second direction intersecting the first direction, the two photoelectric converters are arranged in parallel in the first direction, and

[0432] The gates of the two transfer transistors are each continuous between the first pixel and the second pixel.

[0433] (21) The imaging element according to any one of (1) to (20), wherein the plurality of charge holding units are provided at a height between an upper surface and a lower surface of the gate electrode.

[0434] (22) The imaging element according to any one of (1) to (21), wherein the gate electrode is continuously provided around the plurality of protrusions.

[0435] (23) The imaging element according to any one of (1) to (21), wherein the gate electrode is provided to surround a portion of the plurality of protrusions.

[0436] (24) The imaging element according to (23), wherein the gate electrode is provided between adjacent ones of the plurality of charge holding units.

[0437] (25) The imaging element according to any one of (19) to (24), wherein

[0438] The color filter layer includes a first color filter, a second color filter, and a third color filter for selectively allowing light of different wavelengths to be transmitted, and

[0439] The first color filter, the second color filter, and the third color filter are disposed throughout the plurality of pixels adjacent in at least one of a first direction and a second direction intersecting the first direction, and the two photoelectric converters are arranged in parallel in the first direction.

[0440] (26) The imaging element according to (25), wherein

[0441] In the plurality of pixels sharing any one of the first color filter, the second color filter, and the third color filter, the plurality of charge holding units are shared between two pixels adjacent in the second direction, and

[0442] The gate is provided to surround the plurality of charge holding units shared between two pixels adjacent in the second direction.

[0443] (27) An imaging device comprising an imaging element, wherein the imaging element comprises:

[0444] a first semiconductor substrate having a first surface and a second surface opposite to each other and including a plurality of pixels arranged in an array in an in-plane direction, a plurality of protrusions being provided on the first surface in accordance with each of the plurality of pixels;

[0445] a plurality of photoelectric converters, the plurality of photoelectric converters being formed in a manner embedded in the first semiconductor substrate for each of the pixels and generating charges according to an amount of received light;

[0446] a plurality of charge holding units which are respectively disposed on upper surfaces of the plurality of protrusions and hold charges generated in the plurality of photoelectric converters;

[0447] a second semiconductor substrate which is stacked on the first surface side of the first semiconductor substrate and is provided with one or more pixel circuits which generate pixel signals based on the charges generated by each of the plurality of photoelectric converters; and

[0448] A gate of a transfer transistor is provided around the plurality of protrusions and transfers the charge held in the charge holding unit to the pixel circuit.

[0449] This application claims the benefit of Japanese Priority Patent Application JP2022-102157 filed on Jun. 24, 2022, and Japanese Priority Patent Application JP2023-051956 filed with the Japan Patent Office on Mar. 28, 2023, the entire contents of which are incorporated herein by reference.

[0450] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. An imaging element, include: a first semiconductor substrate having a first surface and a second surface opposite to each other and including a plurality of pixels arranged in an array in an in-plane direction, a plurality of protrusions being provided on the first surface in accordance with each of the plurality of pixels; a plurality of photoelectric converters, the plurality of photoelectric converters being formed in a manner embedded in the first semiconductor substrate for each of the pixels and generating charges according to an amount of received light; a plurality of charge holding units which are respectively disposed on upper surfaces of the plurality of protrusions and hold charges generated in the plurality of photoelectric converters; a second semiconductor substrate which is stacked on the first surface side of the first semiconductor substrate and is provided with one or more pixel circuits which generate pixel signals based on the charges generated by each of the plurality of photoelectric converters; as well as A gate of a transfer transistor is provided around the plurality of protrusions and transfers the charge held in the charge holding unit to the pixel circuit.

2. The imaging element according to claim 1, in, The gate is disposed below the plurality of charge holding units respectively disposed on the plurality of protrusions.

3. The imaging element according to claim 1, in, The gate is disposed to protrude upward more than upper surfaces of the plurality of protrusions, and a side wall is formed on a side surface of a protruding portion of the gate.

4. The imaging element according to claim 3, in, A portion of the side wall is embedded between a side surface of the gate and side surfaces of the plurality of protrusions.

5. The imaging element according to claim 3, in, A portion of the gate is embedded in the first semiconductor substrate.

6. The imaging element according to claim 1, in, The first semiconductor substrate further includes a separation portion disposed between adjacent ones of the plurality of pixels and extending between the first surface and the second surface.

7. The imaging element according to claim 6, further comprising a contact layer for applying a reference potential to the first semiconductor substrate, in, The contact layer is embedded in the first surface of the first semiconductor substrate and is located above the separation portion.

8. The imaging element according to claim 7, in, The first surface of the first semiconductor substrate on which the contact layer is formed is recessed.

9. The imaging element according to claim 7, in, The contact layer is provided at the same height as the charge retention unit.

10. The imaging element according to claim 1, in, The gate is provided for each of the plurality of pixels.

11. The imaging element according to claim 1, in, The gate electrodes are continuously disposed in adjacent ones of the plurality of pixels.

12. The imaging element according to claim 1, in, One pixel circuit is provided for one pixel or each of the plurality of pixels.

13. The imaging element according to claim 1, in, Each of the first semiconductor substrate and the second semiconductor substrate further includes a multilayer wiring layer on the opposite surface side, One or more pad electrodes are provided on the surface of each of the multilayer wiring layers, and By bonding the one or more pad electrodes together, the first semiconductor substrate and the second semiconductor substrate are electrically connected to each other.

14. The imaging element according to claim 1, in, The first semiconductor substrate and the second semiconductor substrate are electrically connected to each other through a through electrode penetrating between the first semiconductor substrate and the second semiconductor substrate.

15. The imaging element according to claim 1, in, The second semiconductor substrate has a third surface and a fourth surface facing each other, The pixel circuit includes: a reset transistor that resets the potential of the charge holding unit to a predetermined position; an amplifying transistor that generates a signal having a voltage consistent with the level of the charge held in the charge holding unit as the pixel signal; and a selecting transistor that controls the timing of outputting the pixel signal from the amplifying transistor. The reset transistor, the amplifying transistor, and the selecting transistor are provided on the third surface of the second semiconductor substrate, and The first semiconductor substrate and the second semiconductor substrate are stacked, and the first surface and the third surface are opposite to each other.

16. The imaging element according to claim 1, in, The second semiconductor substrate has a third surface and a fourth surface facing each other, The pixel circuit includes: a reset transistor that resets the potential of the charge holding unit to a predetermined position; an amplifying transistor that generates a signal having a voltage consistent with the level of the charge held in the charge holding unit as the pixel signal; and a selecting transistor that controls the timing of outputting the pixel signal from the amplifying transistor. The reset transistor, the amplifying transistor, and the selecting transistor are provided on the third surface of the second semiconductor substrate, and The first semiconductor substrate and the second semiconductor substrate are stacked, and the first surface and the third surface are opposite to each other.

17. The imaging element according to claim 16, in, The reset transistor, the amplification transistor, and the selection transistor are transistors having a three-dimensional structure. 18 . The imaging element according to claim 1 , further comprising, on the second surface side of the first semiconductor substrate, a color filter layer that selectively allows light of a predetermined wavelength to be transmitted, and a plurality of light receiving lenses provided for each of the pixels.

19. The imaging element according to claim 18, in, For one light receiving lens, each of the plurality of pixels includes two of the photoelectric converters, two of the protrusions, two of the charge holding units respectively arranged on the upper surfaces of the two protrusions, and the gates of the two transfer transistors respectively arranged around the two protrusions.

20. The imaging element according to claim 19, in, The plurality of pixels include a first pixel and a second pixel adjacent to each other in a second direction intersecting the first direction, the two photoelectric converters are arranged in parallel in the first direction, and The gates of the two transfer transistors are each continuous between the first pixel and the second pixel.

21. The imaging element according to claim 1, in, The plurality of charge holding units are disposed at a height between an upper surface and a lower surface of the gate.

22. The imaging element according to claim 1, in, The gate is continuously disposed around the plurality of protrusions.

23. The imaging element according to claim 1, in, The gate is disposed to surround a portion of the plurality of protrusions.

24. The imaging element according to claim 23, in, The gate is disposed between adjacent ones of the plurality of charge holding units.

25. The imaging element according to claim 19, in, The color filter layer includes a first color filter, a second color filter, and a third color filter for selectively allowing light of different wavelengths to be transmitted, and The first color filter, the second color filter, and the third color filter are disposed throughout the plurality of pixels adjacent in at least one of a first direction and a second direction intersecting the first direction, and the two photoelectric converters are arranged in parallel in the first direction.

26. The imaging element according to claim 25, in, In the plurality of pixels sharing any one of the first color filter, the second color filter, and the third color filter, the plurality of charge holding units are shared between two pixels adjacent in the second direction, and The gate is provided to surround the plurality of charge holding units shared between two pixels adjacent in the second direction.

27. An imaging device comprising an imaging element, wherein the imaging element include: a first semiconductor substrate having a first surface and a second surface opposite to each other and including a plurality of pixels arranged in an array in an in-plane direction, a plurality of protrusions being provided on the first surface in accordance with each of the plurality of pixels; a plurality of photoelectric converters, the plurality of photoelectric converters being formed in a manner embedded in the first semiconductor substrate for each of the pixels and generating charges according to an amount of received light; a plurality of charge holding units which are respectively disposed on upper surfaces of the plurality of protrusions and hold charges generated in the plurality of photoelectric converters; a second semiconductor substrate which is stacked on the first surface side of the first semiconductor substrate and is provided with one or more pixel circuits which generate pixel signals based on the charges generated by each of the plurality of photoelectric converters; as well as A gate of a transfer transistor is provided around the plurality of protrusions and transfers the charge held in the charge holding unit to the pixel circuit.

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