Self-aligned vertical bit lines for three-dimensional (3D) dynamic random access memory (DRAM) devices

Abstract

A semiconductor structure includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer, a word line metal layer, and an interface on a cross-section of the semiconductor layer; a spacer between adjacent ones of the plurality of memory levels in the first direction; and a bit line in contact with an interface of each of the plurality of memory tiers, the bit line extending in a first direction. The bit line includes a metal material, and the interface includes silicide.

Description

[0001] background

[0002] field

[0003] Embodiments described herein relate generally to semiconductor device fabrication, and more particularly to systems and methods for forming vertical bit lines in three-dimensional dynamic random access memory devices.

[0004] Description of Related Technology

[0005] Three-dimensional (3D) dynamic random-access memory (DRAM) devices present challenges for manufacturability due to their three-dimensional (3D) design and small size. Individual memory cells, each of which includes a field-effect transistor (FET) device, need to be connected to a bit line at the source / drain region of the FET device. The fabrication of such a bit line typically requires direct-view processing and multiple process steps including a high-aspect-ratio (HAR) etching process to form a slot for the bit line. For example, a 3D DRAM device may include alternating layers of silicon (Si) and silicon germanium (SiGe), wherein the silicon germanium (SiGe) layer is selectively recessed. A vertical bit line may be formed by filling the HAR slot through a silicon (Si) layer with polycrystalline silicon (poly-Si). This conventional method for forming a vertical bit line in a 3D DRAM device results in a void in the resulting vertical bit line, resulting in a relatively high parasitic resistance.

[0006] Therefore, there is a need for a system and method that can fabricate vertical bit lines in 3D DRAM devices with minimized parasitic resistance through reduced processing steps.

[0007] Overview

[0008] Embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer, a word line metal layer, and an interface on a cross section of the semiconductor layer; spacers between adjacent memory levels in the plurality of memory levels in the first direction; and a bit line in contact with the interface of each of the plurality of memory levels, the bit line extending in the first direction. The bit line includes a metal material, and the interface includes silicide.

[0009] Embodiments of the present disclosure also provide a method for forming a metal bit line in a semiconductor device. The method includes performing a first selective deposition process to selectively form a metal silicide layer on a sidewall of a trench, the sidewall of the trench including a first cross-section of each of a plurality of semiconductor layers stacked in a first direction, and a second cross-section of a spacer disposed between adjacent semiconductor layers in the plurality of semiconductor layers; performing a second selective deposition process to selectively form a metal layer on the sidewall of the trench; and performing a filling process, the filling process including depositing a dielectric material in the trench. The metal layer on the sidewall of the trench is continuous above the plurality of semiconductor layers, thereby forming a metal bit line.

[0010] Embodiments of the present disclosure further provide a three-dimensional (3D) dynamic random access memory (DRAM) device. The 3D DRAM device includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer having a first end and a second end in a second direction orthogonal to the first direction, a word line metal layer, and an interface on a cross section at the first end of the semiconductor layer; spacers between adjacent memory levels in the plurality of memory levels in the first direction; and a bit line in contact with the interface of each of the plurality of memory levels, the bit line extending in the first direction. The bit line includes a metal material, and the interface includes silicide.

[0011] Brief description of the attached figure

[0012] Thus, the manner in which the above-described features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and, therefore, should not be considered limiting of the scope of the present disclosure, as the disclosure may admit to other equally effective embodiments.

[0013] Figure 1 is a schematic top view of an example multi-chamber processing system according to one embodiment.

[0014] Figure 2A A schematic diagram of a portion of a three-dimensional (3D) memory cell array of a dynamic random access memory (DRAM) cell according to one embodiment. Figure 2B A schematic diagram of a DRAM unit.

[0015] Figure 3A is an isometric view of a semiconductor structure according to one embodiment. Figure 3B , Figure 3C , Figure 3D and Figure 3E for Figure 3AA cross-sectional view of the semiconductor structure shown in FIG.

[0016] Figure 4 A process flow diagram depicts a method of forming a contact trench structure in a semiconductor structure according to one embodiment.

[0017] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E is a cross-sectional view of a portion of a semiconductor structure according to one embodiment.

[0018] For ease of understanding, the same reference numerals have been used, where possible, to represent the same elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated into other embodiments without further description. In the figures and the following description, an orthogonal coordinate system including an X-axis, a Y-axis, and a Z-axis is used. For convenience, the direction indicated by an arrow in the drawings is assumed to be a positive direction.

[0019] Specific description

[0020] Embodiments described herein provide systems and methods for forming transistor devices for very large process nodes, such as 3D DRAM devices, having vertical metal bit lines and interfaces between the vertical bit lines and FET devices forming memory cells. The vertical bit lines are formed of metal, such as molybdenum (Mo), which reduces the resistance of the bit lines compared to polysilicon bit lines. The interface is formed by a selective self-aligned deposition process with a metal silicide, such as molybdenum silicide (MoSi 2 、MoSi、Mo 2 Si)) is formed and provides an ohmic contact between the FET device and the vertical bit line, thereby reducing the contact parasitic resistance.

[0021] Figure 11 is a schematic top view of an example of a multi-chamber processing system 100 according to some examples of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with corresponding transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, wafers in the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the wafers to an ambient environment external to the processing system 100 (e.g., such as an atmospheric ambient environment that may exist in a wafer fab). For example, wafers can be processed in various chambers under low pressure (e.g., less than or equal to about 300 Torr) or vacuum environments and transferred between various chambers without breaking the low pressure or vacuum environment between various processes performed on the wafers in the processing system 100. Thus, the processing system 100 can provide an integrated solution for some wafer processing.

[0022] Examples of processing systems that may be appropriately modified in accordance with the teachings provided herein include the APPLICATION®, commercially available from Applied Materials, Inc., located in Santa Clara, California. or Integrated processing system or other suitable processing system. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the aspects described herein.

[0023] exist Figure 1 In the illustrated example of FIG. 1 , the factory interface 102 includes a docking station 140 and a factory interface robot 142 to facilitate the transfer of wafers. The docking station 140 is configured to receive one or more front opening unified pods (FOUPs) 144. In some examples, each factory interface robot 142 generally includes a blade 148 disposed on one end of the respective factory interface robot 142, which is configured to transfer wafers from the factory interface 102 to the load lock chambers 104, 106.

[0024] The load lock chambers 104, 106 have respective ports 150, 152 coupled to the factory interface 102 and respective ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 158, 160 coupled to the holding chambers 116, 118 and respective ports 162, 164 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 166, 168 coupled to the holding chambers 116, 118 and respective ports 170, 172, 174, 176 coupled to the processing chambers 124, 126, 128, 130. Ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 may be, for example, slit valve openings with slit valves for allowing wafers to pass therethrough by the transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas from passing therethrough. In general, any port is opened to transfer a wafer therethrough. Otherwise, the port is closed.

[0025] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 142 transfers a wafer from the FOUP 144 to the load lock chamber 104 or 106 via port 150 or 152. The gas and pressure control system then evacuates the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 with an internal low pressure or vacuum environment (which may include an inert gas). Thus, evacuating the load lock chamber 104 or 106 facilitates transferring wafers between the atmospheric pressure environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108 , for example.

[0026] With the wafer in the evacuated load lock chamber 104 or 106, the transfer robot 112 transfers the wafer from the load lock chamber 104 or 106 into the transfer chamber 108 via the port 154 or 156. The transfer robot 112 can then transfer the wafer to either of the processing chambers 120, 122 via the respective ports 162, 164 and / or transfer the substrate between either of the processing chambers 120, 122 for processing and to the holding chambers 116, 118 via the respective ports 158, 160 for holding to await further transfer. Similarly, the transfer robot 114 is capable of accessing a wafer in a holding chamber 116 or 118 via port 166 or 168 and is capable of transferring the wafer to any of the processing chambers 124, 126, 128, 130 via respective ports 170, 172, 174, 176 and / or transferring the substrate between any of the processing chambers 124, 126, 128, 130 for processing and transferring to the holding chambers 116, 118 via respective ports 166, 168 for holding to await further transfer. Transferring and holding the wafers within and between the various chambers may be in a low pressure or vacuum environment provided by a gas and pressure control system.

[0027] The processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chamber for processing wafers. In some examples, the processing chamber 122 may be capable of performing a cleaning process, the processing chamber 120 may be capable of performing an etching process, and the processing chambers 124, 126, 128, 130 may be capable of performing a corresponding epitaxial growth process. The processing chamber 122 may be a SiCoNi 1000 wafer available from Applied Materials of Santa Clara, California. TM Pre-clean chamber. The processing chamber 120 may be a Selectra available from Applied Materials of Santa Clara, California. TM Etching chamber.

[0028] The system controller 190 is coupled to the processing system 100 to control the processing system 100 or components thereof. For example, the system controller 190 may control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130. In operation, the system controller 190 enables data collection and feedback from the respective chambers to coordinate the performance of the processing system 100.

[0029] The system controller 190 generally includes a central processing unit (CPU) 192, a memory 194, and support circuits 196. The CPU 192 may be one of any form of general purpose processor that may be used in an industrial environment. The memory 194 or non-transitory computer readable medium may be accessed by the CPU 192 and may be one or more of memories such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 196 are coupled to the CPU 192 and may include caches, clock circuits, input / output subsystems, power supplies, and the like. Computer instruction codes stored in the memory 194 (or in the memory of a particular process chamber) may be executed by the CPU 192 generally under the control of the CPU 192 as, for example, a software routine to implement the various methods disclosed herein. When the computer instruction codes are executed by the CPU 192, the CPU 192 controls the chamber to perform processes according to the various methods.

[0030] Other processing systems may have other configurations. For example, more or fewer processing chambers may be coupled to the transfer apparatus. In the illustrated example, the transfer apparatus includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer apparatus in a processing system.

[0031] Figure 2A Schematic diagram of a portion of a three-dimensional (3D) memory cell array 200 of dynamic random access memory (DRAM) cells (also referred to as "memory cells") M according to one or more embodiments of the present disclosure.

[0032] like Figure 2B As shown in FIG, a single memory cell M includes an access transistor Q and a storage capacitor C. The memory cell M stores a data bit by storing a charge packet (i.e., binary one) or no charge (i.e., binary zero) on the storage capacitor C. The data bit is input and output by a bit line BL connected to the source / drain of the access transistor Q, and the input is controlled by a word line WL connected to the gate of the access transistor Q.

[0033] The memory cell array 200 includes memory levels L stacked in the Z direction. n (n=1, 2, 3, ...) (showing the first memory level L 1 and the second memory level L 2 Each memory level Ln A two-dimensional (2-D) array of memory cells M is included. Although Figure 2A Only two memory levels are shown in FIG. 2 , but the memory cell array 200 may include memory cells stacked in the second memory level L in the Z direction. 2 More memory levels L above n (n=3,4,...).

[0034] In the memory cell array 200, the bit lines BL extend vertically in the Z direction, and the word lines WL extend horizontally in the Y direction. Each of the bit lines BL is linked to the source / drain of the access transistor Q vertically aligned in the Z direction. Each of the word lines WL is linked to the gate of the access transistor Q horizontally aligned in the Y direction.

[0035] Figure 3A is an isometric view of a portion of a semiconductor structure 300 that may form a portion of a 3D memory cell array, such as memory cell array 200 , according to one or more embodiments of the present disclosure. Figure 3B For along Figure 3A FIG. 4 is a cross-sectional view of a portion of the semiconductor structure 300 taken along line BB′ shown in FIG. Figure 3C For along Figure 3A FIG. 4 is a cross-sectional view of a portion of the semiconductor structure 300 taken along line CC′ shown in FIG. Figure 3D For along Figure 3A FIG. 4 is a cross-sectional view of a portion of the semiconductor structure 300 taken along line DD′ shown in FIG. Figure 3E For along Figure 3A 1 is a cross-sectional view of a portion of the semiconductor structure 300 along the line EE' shown in FIG. As shown, two memory levels L 1 and L 2 The semiconductor structure 300 may include a second memory level L stacked in the Z direction on the substrate 302. 2 More memory levels L above n (n=3, 4, ...) (not shown).

[0036] The semiconductor structure 300 includes a left field effect transistor (FET) module TR L , in the X direction through the trench 304 and the left FET module TR L Separate right FET module TR R The semiconductor structure 300 further includes a left FET module TR L The adjacent left capacitor module C L , and in the X direction with the right FET module TR R The adjacent right capacitor module C R . Left FET module TRL And left capacitor module C L Divided into multiple parts S in the Y direction Lm (m=1,2,3,...)(in Figure 3A S L1 , S L2 and S L3 ). Right FET module TR R And right capacitor module C R Divided into multiple parts S in the Y direction Rm (m=1,2,3,...)(in Figure 3A , Figure 3C and Figure 3D S R1 , S R2 and S R3 ). Each portion S of the access FET transistor Q and the storage capacitor C is formed respectively Lm Each memory level L in (m=1,2,3) n Left FET module TR in (n=1,2,...) L The left capacitor module CL and the left capacitor module CL together form a memory cell M. Similarly, each portion S of the access FET transistor Q and the storage capacitor C are formed separately. Rm Each memory level L in (m=1,2,3) n Right FET module TR in (n=1,2,...) R And right capacitor module C R Together they form a memory cell M. Although only three parts S are shown Lm (m=1,2,3) and S Rm (m=1, 2, 3), but more parts can be set along the Y direction.

[0037] As used herein, the term "substrate" refers to a material layer that serves as a base for subsequent processing operations and includes a surface to be cleaned. Substrate 302 may be a silicon-based material or any suitable insulating or conductive material, as desired. Substrate 302 may include materials such as: crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass or sapphire.

[0038] Memory Level L n ( n =1,2,...) in the FET module TR L and TRR Each includes a semiconductor layer 306 and a word line metal layer 308a. In some embodiments, the memory level L n ( n =1,2,...) in the FET module TR L and TR R Each further includes a word line metal layer 308b. The cross-section 306S of the semiconductor layer 306 each serves as a source / drain of a corresponding access transistor Q. Memory level L n ( n =1, 2, ...) in the word line metal layer 308a and the word line metal layer 308b extend in the Y direction and can be n The semiconductor layer 306 has a gate oxide 310 above and below in the Z direction. Each of the word line metal layers 308a and 308b has a gate oxide 310 around the word line metal layers 308a, 308b and buried in spacers 312. n ( n =1,2,...) in the FET module TR L and TR R The spacer 312 and the adjacent memory level L n+1 FET module TR in L and TR R Spacers 312 are also provided to separate the memory levels L n ( n =1,2,...) within the adjacent part (for example, Figure 3C The S shown in R1 , S R2 and S R3 ) between the semiconductor layer 306. FET module TR in the memory level L and TR RThe semiconductor layers 306 may be separated from the substrate 302 by spacers 312. The semiconductor layers 306 may each have a width between about 20 nm and about 60 nm (e.g., about 40 nm) in the Y direction, and a thickness between about 10 nm and about 30 nm (e.g., about 20 nm) in the Z direction. The horizontal spacing between adjacent semiconductor layers 306 in the Y direction may be between about 140 nm and about 180 nm (e.g., about 160 nm), and the vertical spacing between adjacent semiconductor layers 306 in the Z direction may be between about 50 nm and about 100 nm (e.g., about 80 nm). The bit line BL may have a width between about 40 nm and about 120 nm (e.g., about 80 nm) in the Y direction, and a thickness between about 40 nm and about 120 nm (e.g., about 80 nm) in the X direction. In some memory array designs, the BL crosses the trench 304 for the left FET module TR L And right FET module TR R 304, and thus the width of the bit line BL in the X direction is the width of the trench 304. In these designs, the left FET module TR L Upper and right FET module TR R The word line WL on the left FE can address two logical word line addresses and is controlled independently. In some other memory array designs, two separate bit lines BL are formed, one on the left FE T Module TR L On the right FET module TR R These bit lines BL are isolated from each other and can be individually connected to different global bit lines. Allowing a single word line connection to be used for both the left and right word lines WL greatly reduces the number and therefore the area required for deep word line "staircase" contacts.

[0039] The semiconductor layer 306 may be formed of silicon (Si) or silicon germanium (SiGe). The word line metal layers 308a and 308b may be formed of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt), or conductive oxides or nitrides thereof, or any combination thereof. The gate oxide 310 may be formed of silicon oxide (SiO 2 ), silicon oxynitride (SiON), high dielectric constant dielectric materials such as hafnium oxide (HfO 2 )、ZrO 2 ), vanadium oxide (VO 2 ), titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO), niobium oxide (Nb 2 O5 ), Tantalum pentoxide (Ta 2 O 5 ) or any combination thereof. The spacer 312 may be formed of a dielectric material, such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), silicon oxycarbide (SiOCN), boron-doped silicon oxycarbon nitride (SiOCBN), or any combination thereof.

[0040] Memory Level L n ( n =1,2,...) in the left capacitor module C L And right capacitor module C R Each includes a memory level L electrically connected to n The semiconductor layer 306 of the semiconductor layer 306 is formed of a first plate metal layer 314, a second plate metal layer 316 connected to ground (not shown), and a dielectric layer 318 between the first plate metal layer 314 and the second plate metal layer 316. The first plate metal layer 314 is surrounded by a dielectric layer 320. The dielectric layer 320 is also configured to separate adjacent portions (e.g., S R1 , S R2 and S R3 ,like Figure 3D 314, a second plate metal layer 316, and a dielectric layer 320 are formed between the first plate metal layer 314 and the semiconductor layer 306. A diffusion barrier layer (not shown) may be inserted between the first plate metal layer 314 and the semiconductor layer 306. The first plate metal layer 314 and the second plate metal layer 316 may serve as two plates of the capacitor C. The first plate metal layer 314 and the second plate metal layer 316 may be formed of cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), rhodium (Rh), or a conductive metal nitride, or any combination thereof. The dielectric layer 318 may be formed of a high dielectric constant dielectric material, such as hafnium oxide (HfO 2 )、ZrO 2 ), vanadium oxide (VO 2 ), titanium oxide (TiO 2 ), tin oxide (SnO 2 ), aluminum oxide (Al 2 O 3 ), zinc oxide (ZnO), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO), niobium oxide (Nb 2 O 5 ), Tantalum pentoxide (Ta 2 O 5 ) or any combination thereof.

[0041] The semiconductor structure 300 further includes a bit line BL extending in the Z direction within a trench 304 between the left FET module TR L And right FET module TR R The adjacent part S Lm (m=1,2,3,...) and S Rm (m=1,2,3,...) (for example, in part S L1 and S R1 Between, in part S L2 and S R2 Between, and in part S L3 and S R3 Between, such as Figure 3A and Figure 3E Part S Lm and S Rm The bit lines BL between (m=1, 2, 3, . . . ) are in direct contact with the interface 322 on the cross section 306S of the semiconductor layer 306 and are connected to the memory level L via all memory levels L. n Part S in (n=1,2,...) Lm The left FET module TR L The interface 322 in the portion S is electrically connected to the semiconductor layer 306. Lm and S Rm The bit lines BL between (m=1, 2, 3, . . . ) further directly contact the interface 322 on the cross section 306S of the silicon layer 306 and pass through all memory levels L n Part S in (n=1,2,...) Rm Right FET module TR R The interface 322 in is electrically connected to the semiconductor layer 306 .

[0042] The bit lines BL are conventionally formed by filling the trenches 304 with doped polysilicon or other conductive material and etching away the vertical isolation gaps between the bit lines BL to leave the conductive material as the finished bit lines BL, or by depositing a dielectric material in the trenches 304 and etching vertical contact holes that will connect to each of the source-drain regions below them. In both cases, the bit lines BL for the left FET module TR are formed. L And right FET module TR R The common bit line BL.

[0043] In the embodiments described herein, the bit line BL is formed using selective deposition, which may also allow two separate bit lines BL to be formed in the left FET module TR. L And right FET module TR RFirst, doped source / drain regions are formed on the exposed cross-section 306S of the semiconductor layer 306 using an appropriate doping method. These doped source / drain regions may or may not bridge to vertically connect the bit lines BL. Subsequently, another selective metal deposition is performed to form a metal silicide interface 322, followed by the same deposition or even deposition of a different metal to form a metal interconnect layer (such as Figure 5C The metal silicide may be molybdenum silicide (Mo x Si y ), titanium silicide (Ti x Si y ), cobalt silicide (Co x Si y ), nickel (Ni x Si y ), Tantalum silicide (Ta x Si y ) or any combination thereof. Interface 322 provides an ohmic contact between semiconductor layer 306 and bit line BL. Bit line BL may be formed of a metal, such as molybdenum (Mo), titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta) or any combination thereof. The selectively deposited material may be a silicon layer, a silicide layer or a metal layer, or any combination thereof, as long as it bridges and forms a continuous vertical connection to form the bit line BL. A dielectric layer 324 is finally provided to trench 304 and bit line BL to isolate the bit line BL, which may also partially or completely fill trench 304. Trench 304 may leave an air gap buried below the surface to reduce the parasitic capacitance of the bit line BL, but be sealed at the top surface to allow processing of top interconnects for individual vertical bit lines BL. Dielectric layer 324 is formed of a dielectric material, such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), boron nitride (BN), silicon oxycarbide (SiOCN), boron-doped silicon oxycarbide nitride (SiOCBN), aluminum oxide (Al 2 O 3 ), or hafnium oxide (HfO 2 ), or any combination thereof.

[0044] Figure 4 A FET module TR in a semiconductor structure 300 is depicted according to one or more implementations of the present disclosure. L and TR R 4 is a process flow chart of a method 400 for forming a bit line BL between the two. Corresponding to various states of the method 400, Figure 5A and Figure 5C For along Figure 3A A cross-sectional view of a portion of the semiconductor structure 300 taken along line BB′ in FIG. Figure 5B, Figure 5D and Figure 5E For along Figure 3A FIG. 3 is a cross-sectional view of a portion of the semiconductor structure 300 along line EE′ in FIG. 3 . It should be understood that Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E Only a partial schematic diagram of the semiconductor structure 300 is shown, and the semiconductor structure 300 may contain any number of transistor portions and additional materials having aspects as shown in the figures. It should also be noted that although the sequential description Figure 4 Other process sequences that are consistent with the methods depicted in , but include one or more operations that have been omitted and / or added, and / or have been rearranged in another desired order are within the scope of embodiments of the present disclosure provided herein.

[0045] Before forming the bit line BL by the method 400, the FET module TR in the semiconductor structure 300 may be formed using any suitable deposition technique (such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD)) and patterning technique (such as photolithography and etching process). L and TR R , the semiconductor structure 300 includes a semiconductor layer 306, a word line metal layer 308a, a word line metal layer 308b, a gate oxide 310, a spacer 312, a first plate metal layer 314, a second plate metal layer 316, a dielectric layer 318, a dielectric layer 320, and a dielectric layer 324. The semiconductor layers 306 may each have a width between about 20 nm and about 60 nm (e.g., about 40 nm) in the Y direction, and a thickness between about 10 nm and about 30 nm (e.g., about 20 nm) in the Z direction. The horizontal spacing between adjacent semiconductor layers 306 in the Y direction may be between about 140 nm and about 180 nm (e.g., about 160 nm), and the vertical spacing between adjacent semiconductor layers 306 in the Z direction may be between about 50 nm and about 100 nm (e.g., about 80 nm). The bit line BL may have a width between about 40 nm and about 120 nm (eg, about 80 nm) in the Y direction, and a thickness between about 40 nm and about 120 nm (eg, about 80 nm) in the X direction.

[0046] The method 400 begins at block 410 where a first selective deposition process is performed to form a self-aligned interface 322 on the exposed cross-section 306S of the semiconductor layer 306 on the sidewalls of the trench 304 (including the cross-section 306S of the semiconductor layer 306, the cross-section 310S of the gate oxide 310, and the cross-section 312S of the spacer 312). Figure 5A and Figure 5B The first selective deposition begins with a suitable doping method to form a doped source / drain region at the cross section 306S of the semiconductor layer 306. The first selective deposition selectively deposits a metal silicide (such as molybdenum silicide (Mo x Si y ), titanium silicide (Ti x Si y ), cobalt silicide (Co x Si y ), nickel (Ni x Si y ), Tantalum silicide (Ta x Si y ) or any combination thereof) to form an interface 322 at the exposed cross section 306S of the semiconductor layer 306. The interface 322 provides an ohmic contact between the semiconductor layer 306 and the bit line BL to be formed.

[0047] In some embodiments, the metal source may include molybdenum (Mo), titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), or any combination thereof. The etching gas includes an etchant gas and a carrier gas, wherein the etchant gas may be a byproduct of the deposition gas itself. The etchant gas may include a chlorine-containing gas, such as hydrogen chloride (HCl), chlorine (Cl 2 ), carbon tetrachloride (CCl 4 ), chloroform (CHCl 3 ), dichloromethane (CH 2 Cl 2 ) or methyl chloride (CH 3 The carrier gas may include nitrogen (N 2 ), argon (Ar), helium (He), or hydrogen (H 2 ).

[0048] The deposition process may include any suitable deposition process, such as epitaxial deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), spin coating, physical vapor deposition (PVD), or the like. The deposition process and the etching process at block 410 may each be performed at a temperature between about 300° C. and about 800° C. and a pressure between 1 Torr and 50 Torr in a processing chamber such as, Figure 1 The process is performed in a processing chamber 120, 122, 124, 126, 128 or 130 as shown in FIG.

[0049] At block 420, a second selective deposition process is performed to form a self-aligned metal interconnect layer 502 on the exposed surface of the interface 322 on the sidewalls of the trench 304 (including the interface 322, the cross section 310S of the gate oxide 310, and the cross section 312S of the spacer 312), such as Figure 5C and Figure 5D . The second selective deposition process is a continuation of the first selective deposition process in block 410, such that there is a net deposition of material on the interface 322 and there is zero deposition or net etching of material on the surrounding surfaces of the sidewalls of the trench 304 (including the cross section 310S of the gate oxide 310 and the cross section 312S of the spacer 312). In the deposition process, the exposed surface of the trench 304 is exposed to a deposition gas containing a metal source. The metal source may be the same as the metal source used in block 410 or different from the metal source used in block 410. The interface 322 reacts with the metal source to form a metal interconnect layer 502. The metal interconnect layer 502 grows isotropically in the X direction and in the YZ plane from each of the interfaces 322 toward the middle of the trench 304, and merges with the portion grown from the adjacent interface 322. With the FET module TR L The adjacent merged metal interconnect layer 502 is further connected to the FET module TR R Adjacent merged metal interconnect layers 502 are merged and form a continuous bit line BL, such as Figure 3B and Figure 3E In some other embodiments, the FET module TR L The adjacent merged metal interconnect layer 502 forms a bit line BL separately and is connected to the FET module TR R Adjacent merged metal interconnect layers 502 form individual bit lines BL.

[0050] In some embodiments, the metal source may include molybdenum (Mo), titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), or any combination thereof.

[0051] At block 430, a filling process is performed to fill the trench 304 with a dielectric material to form a dielectric layer 324, such as Figure 5E as shown in .

[0052] The dielectric layer 324 is formed of a dielectric material, such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), boron nitride (BN), silicon oxycarbide (SiOCN), boron-doped silicon oxycarbide nitride (SiOCBN), aluminum oxide (Al 2 O 3 ), or hafnium oxide (HfO 2), or any combination thereof.

[0053] The filling process in block 430 may include filling a processing chamber (such as Figure 1 The process chambers 120, 122, 124, 126, 128, or 130 shown in FIG. 1 may be any suitable deposition process, such as a chemical vapor deposition (CVD) process.

[0054] Embodiments described herein provide systems and methods for forming vertical bit lines in a 3D DRAM device having an interface between the vertical bit lines and a FET device forming a memory cell. The vertical bit lines are formed from a metal such as molybdenum (Mo) by a self-aligned deposition process without requiring a HAR etching process to form a slot for the vertical bit lines. Thus, the resistance of the bit lines is reduced compared to a conventional polycrystalline phase used as a bit line that may include a void. The interface is formed by a selective self-aligned deposition process with a metal silicide (such as molybdenum silicide (MoSi 2 )) is formed and provides an ohmic contact between the FET device and the vertical bit line, thereby reducing the contact parasitic resistance.

[0055] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, the scope of which is determined by the claims that follow.

Claims

1. A semiconductor structure comprising: A plurality of memory levels are stacked in a first direction, each of the plurality of memory levels comprising: Semiconductor layer; a word line metal layer over the semiconductor layer in the first direction; and an interface, in a cross section of the semiconductor layer; spacers between adjacent memory levels of the plurality of memory levels in the first direction; and A bit line contacts the interface of each of the plurality of memory levels, the bit line extending in the first direction, wherein The bit line includes a metal material, and The interface includes silicide.

2. The semiconductor structure of claim 1, wherein The semiconductor layer includes silicon.

3. The semiconductor structure of claim 1, wherein the metal material comprises molybdenum (Mo) and the interface comprises molybdenum silicide.

4. The semiconductor structure of claim 1, wherein the metal material comprises titanium (Ti) and the interface comprises titanium silicide.

5. The semiconductor structure of claim 1, wherein the spacer comprises silicon nitride.

6. The semiconductor structure of claim 1, wherein the semiconductor layer comprises: a width between 20 nm and 60 nm in a second direction orthogonal to said first direction, a thickness in said first direction between 10 nm and 30 nm, and A vertical spacing of between 140 nm and 180 nm between the semiconductor layer of an adjacent memory level in the plurality of memory levels.

7. The semiconductor structure of claim 6, wherein the bit line has: a width in said second direction between 40 nm and 120 nm, and A thickness between 40 nm and 120 nm in a third direction orthogonal to the first direction and the second direction.

8. A method for forming a metal bit line in a semiconductor device, the method comprising the following steps: performing a first selective deposition process to selectively form a metal silicide layer on a sidewall of a trench, the sidewall of the trench including a first cross-section of each of a plurality of semiconductor layers stacked in a first direction and a second cross-section of a spacer disposed between adjacent semiconductor layers of the plurality of semiconductor layers; performing a second selective deposition process to selectively form a metal layer on the sidewalls of the trench; and performing a filling process, the filling process comprising depositing a dielectric material in the trench, wherein The metal layer on the sidewalls of the trench is continuous over the plurality of semiconductor layers, thereby forming a metal bit line.

9. The method of claim 8, wherein The semiconductor layers each include silicon.

10. The method of claim 8, wherein the metal layer comprises molybdenum (Mo) and the metal layer comprises molybdenum silicide.

11. The method of claim 8, wherein the metal layer comprises titanium (Ti) and the metal layer comprises titanium silicide.

12. The method of claim 9, wherein the spacer comprises silicon nitride.

13. The method of claim 8, wherein each of the semiconductor layers has: a width between 20 nm and 60 nm in a second direction orthogonal to said first direction, a thickness in said first direction between 10 nm and 30 nm, and The vertical spacing to the adjacent semiconductor layer is between 140 nm and 180 nm.

14. The method of claim 13, wherein the metal bit line has: a width in said second direction between 40 nm and 120 nm, and A thickness between 40 nm and 120 nm in a third direction orthogonal to the first direction and the second direction.

15. A three-dimensional (3D) dynamic random access memory (DRAM) device comprising: A plurality of memory levels are stacked in a first direction, each of the plurality of memory levels comprising: A semiconductor layer having a first end and a second end in a second direction orthogonal to the first direction; word line metal layer; and an interface, in a cross section at the first end of the semiconductor layer; spacers between adjacent memory levels of the plurality of memory levels in the first direction; and A bit line contacts the interface of each of the plurality of memory levels, the bit line extending in the first direction, wherein The bit line includes a metal material, and The interface includes silicide.

16. The 3D DRAM device of claim 15, wherein The semiconductor layer includes silicon. 17 . The 3D DRAM device of claim 15 , wherein the metal material comprises molybdenum (Mo) and the interface comprises molybdenum silicide.

18. The 3D DRAM device of claim 15, wherein the metal material comprises titanium (Ti) and the interface comprises titanium silicide.

19. The 3D DRAM device of claim 15, wherein the spacer comprises silicon nitride.

20. The 3D DRAM device of claim 15, wherein The semiconductor layer has: a width in said second direction between 20 nm and 60 nm, a thickness in said first direction between 10 nm and 30 nm, and The semiconductor layer of an adjacent memory level in the plurality of memory levels is vertical spacing between 140nm and 180nm, and The bit line has: a width in said second direction between 40 nm and 120 nm, and A thickness between 40 nm and 120 nm in a third direction orthogonal to the first direction and the second direction.

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