Storage array and manufacturing method thereof, memory and electronic equipment

Abstract

A storage array (1) and a manufacturing method thereof, a memory (01), and an electronic device, relating to the technical field of storage and capable of improving the storage capacity of the storage array (1). The memory array (1) may include a substrate and at least one bit line (BL) disposed on the substrate, a plurality of memory groups connected to each bit line (BL). Wherein at least one bit line (BL) is perpendicular to the substrate; the plurality of storage groups connected with each bit line (BL) are stacked along the direction vertical to the substrate, each storage group comprises at least one storage unit (M), and each storage unit (M) comprises a first transistor (10) and a storage capacitor (11) connected with the first transistor (10). The first transistor (10) includes a source (S), a drain (D), at least one gate (G), and a channel (C). In each memory group, all the first transistors (10) share a source electrode (S), and the source electrode (S) is arranged around the bit line (BL) and is connected with the bit line (BL). In each first transistor (10), a channel (C) is arranged between a source electrode (S) and a drain electrode (D) in the direction parallel to the substrate; at least one gate (G) is disposed stacked with the channel (C) in a direction perpendicular to the substrate.

Description

Storage array and manufacturing method thereof, memory, and electronic device Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage array and a manufacturing method thereof, a memory, and an electronic device. Background Art

[0002] With the continuous advancement of storage and computing integration in the world of the Internet of Things, various fields have put forward higher requirements for memory. For example, applications such as smart cars, cloud computing, big data, artificial intelligence and the Internet of Things require large amounts of data to be processed, which in turn places higher requirements on the storage capacity of memory.

[0003] Figure 1 is a schematic diagram of a 1T1C (one transistor and one capacitor) memory cell in a conventional memory. This 1T1C memory cell includes an access transistor T and a storage capacitor C, wherein the storage capacitor C is directly integrated with the source terminal S of the access transistor T. In this prior art, the access transistor T is a planar front-end transistor, and the source and drain regions of the access transistor T are formed by direct doping on the substrate. In this case, the source terminal S, drain terminal D, and gate terminal G of the access transistor T all occupy the surface integration area of ​​the substrate, thereby limiting the scalability of the entire memory cell and resulting in low storage density.

[0004] In the above-mentioned prior art, on the one hand, because the access transistor T uses a planar front-end transistor, the memory array is integrated in a planar manner, which limits the improvement of storage capacity. On the other hand, the requirement of the access transistor T for a substrate makes it difficult to stack the memory array in three dimensions. In order to increase storage capacity, it is necessary to rely on device miniaturization. However, with the continuous reduction of process dimensions, affected by factors such as lithography technology and device performance, the scaling of memory cells has shown a trend of slowing down and saturation. Therefore, the industry needs a memory that can achieve three-dimensional stacking to meet the demand for high storage capacity.

[0005] Summary of the Invention

[0006] The present application provides a storage array and a manufacturing method thereof, a memory, and an electronic device, which can increase the storage capacity of the storage array.

[0007] The present application provides a memory array, which may include a substrate and at least one bit line arranged on the substrate, and multiple memory groups connected to each bit line. At least one bit line is perpendicular to the substrate; the multiple memory groups connected to each bit line are stacked in a direction perpendicular to the substrate, each memory group includes at least one memory cell, and each memory cell includes a first transistor and a storage capacitor connected to the first transistor. The first transistor includes a source, a drain, at least one gate, and a channel. In each memory group, all first transistors share a source, and the source is arranged around the bit line and connected to the bit line. In each first transistor, a channel is arranged between the source and the drain in a direction parallel to the substrate; at least one gate is stacked with the channel in a direction perpendicular to the substrate.

[0008] The embodiments of the present application employ a transistor with a novel structure (i.e., a first transistor) as an access transistor in a memory cell. The drain, channel, and source of the transistor are distributed parallel to the substrate, and the gate and channel are stacked. Since the transistor and the substrate are independent structures, the substrate only serves as a support carrier for the transistor, that is, the transistor itself does not rely on the substrate. Therefore, when the transistor is used as an access transistor in a memory cell, the transistor can be placed in the back end of line (BEOL), thereby enabling the stacking of multiple transistors in a direction perpendicular to the substrate (i.e., the Z direction). This allows multiple memory cells in a memory array to be stacked in the Z direction and connected to bit lines extending along the Z direction, thereby improving the storage density and capacity of the memory array.

[0009] In some possible implementations, the storage group includes a storage unit; in the first transistor, the channel is arranged around the source, the drain is arranged around the channel, and the gate is arranged around the bit line; that is, the source, the channel, and the drain are arranged in sequence from the inside to the outside, so that the channel has a larger width, thereby ensuring that the first transistor has sufficient on-state current.

[0010] In some possible implementations, the storage group includes a first storage unit and a second storage unit. The first transistor in the first storage unit includes a first drain, a first gate, and a first channel. The first transistor in the second storage unit includes a second drain, a second gate, and a second channel. The storage group is also provided with a first gap and a second gap, the first gap and the second gap are filled with insulating dielectric material, and the first gap and the second gap are symmetrically arranged with respect to the bit line. The first drain and the second drain are symmetrically arranged with respect to the first gap and the second gap; the first gate and the second gate are symmetrically arranged with respect to the first gap and the second gap; and the first channel and the second channel are symmetrically arranged with respect to the first gap and the second gap. In this case, the storage density of the storage array can be further improved.

[0011] In some possible implementations, the storage capacitor includes: a dielectric layer and a first electrode layer; the dielectric layer and the first electrode layer are stacked with the drain of the first transistor in a direction parallel to the substrate, and the dielectric layer is located between the drain and the first electrode layer; thereby further improving the storage density, simplifying the manufacturing process, and reducing the manufacturing cost.

[0012] In some possible implementations, the storage capacitor may be a ferroelectric capacitor.

[0013] In some possible implementations, the storage capacitor may be a dielectric capacitor.

[0014] In some possible implementations, the first transistor may include two gates, and the two gates are located on both sides of the channel in a direction perpendicular to the substrate; that is, the first transistor has a dual-gate structure, thereby ensuring that the first transistor has sufficient gate control capability and reducing leakage current.

[0015] In some possible implementations, the first transistor includes an intermediate insulating layer, and the channel covers a surface of the intermediate insulating layer.

[0016] In some possible implementations, the first transistor includes a gate insulating layer, which covers a surface of the gate, thereby reducing leakage current of the first transistor.

[0017] In some possible implementations, a memory array is provided with a plurality of bit lines distributed in an array, and the plurality of bit lines are manufactured through a same manufacturing process.

[0018] In some possible implementations, gates of a plurality of first transistors located in the same layer and connected to a plurality of bit lines in the same row are connected to form a word line; thereby simplifying the process and reducing the manufacturing cost.

[0019] In some possible implementations, among a plurality of first transistors located in the same layer and connected to a plurality of bit lines in the same row, gates of two adjacent first transistors contact each other to form a word line.

[0020] In some possible implementations, among a plurality of first transistors located in the same layer and connected to a plurality of bit lines in the same row, gates of two adjacent first transistors are connected via an intermediate connecting portion to form a word line.

[0021] In some possible implementations, the storage array further includes: a plurality of plate lines; and the first electrode layers of the plurality of storage capacitors disposed in the same layer are connected to the same plate line.

[0022] In some possible implementations, the memory array further includes: a plurality of second transistors disposed between the plurality of bit lines and the substrate, at least one first control line, and at least one second control line. The second transistors include a source, a drain, a gate, and a channel. The drains of the plurality of second transistors are respectively connected to the plurality of bit lines. The gates of the plurality of second transistors connected to the plurality of bit lines in the same row are connected to the same first control line. The sources of the plurality of second transistors connected to the plurality of bit lines in the same column are connected to the same second control line.

[0023] In some possible implementations, the source, channel, and drain of the second transistor are stacked in a direction perpendicular to the substrate, and the source of the second transistor is close to the substrate relative to the drain of the second transistor; the gate of the second transistor is arranged around the channel of the second transistor.

[0024] An embodiment of the present application also provides a method for manufacturing a storage array, which may include: forming a plurality of initial stacking units stacked on a substrate, and forming at least one first through-hole penetrating the plurality of initial stacking units by etching; wherein the initial stacking unit includes a sacrificial layer and a first insulating layer provided on the upper surface and / or lower surface of the sacrificial layer. A portion of the first insulating layer is removed along the sidewall of the first through-hole to form a first groove structure, and a gate of a first transistor and a gate insulating layer wrapping the gate are formed in the first groove structure. The sacrificial layer is removed, and a drain and a channel of the first transistor are formed at the location where the sacrificial layer is removed; wherein the channel is located on the side of the drain close to the first through-hole. The source and bit line of the first transistor are formed in the first through-hole.

[0025] The method for manufacturing a memory array provided in an embodiment of the present application is based on the arrangement of transistors of a novel structure. A multi-layer stacked arrangement of first transistors can be formed through a single manufacturing process without relying on a substrate. This saves mask costs and simplifies the manufacturing process. Furthermore, in this manufacturing method, the formed bit lines extend along the Z direction to connect to the multiple stacked memory cells, thereby enabling three-dimensional stacking of the memory cells, thereby increasing storage density and reducing the cost per bit per unit area.

[0026] In some possible implementations, the sacrificial layer is removed, and the drain and channel of the first transistor are formed at the location where the sacrificial layer is removed, including: removing part of the sacrificial layer along the side wall of the first through hole to form a second groove structure, and forming the channel of the first transistor in the second groove structure; removing the remaining sacrificial layer along the side of the initial stacked unit to form a third groove structure to expose the channel, and forming a drain on the side of the channel.

[0027] In some possible implementations, the manufacturing method further includes: sequentially forming a dielectric layer and a first electrode layer on the side of the drain electrode in the third groove structure.

[0028] In some possible implementations, the sacrificial layer is removed, and the drain and channel of the first transistor are formed at the location where the sacrificial layer is removed, including: removing part of the sacrificial layer along the side wall of the first through hole to form a second groove structure, and sequentially forming the drain and channel of the first transistor in the second groove structure.

[0029] In some possible implementations, the manufacturing method further includes: removing the remaining sacrificial layer along the side of the initial stacked unit to form a third groove structure and expose the drain, and sequentially forming a dielectric layer and a first electrode layer on the side of the exposed drain.

[0030] An embodiment of the present application further provides an electronic device comprising a substrate and a transistor disposed on the substrate; the transistor comprising a source, a drain, at least one gate, and a channel. The channel surrounds the source, and the drain surrounds the channel, in a direction parallel to the substrate. The at least one gate and the channel are stacked perpendicular to the substrate, and the at least one gate surrounds the source.

[0031] An embodiment of the present application also provides an electronic device, comprising a substrate and a first transistor and a second transistor disposed on the substrate. The first transistor and the second transistor share a first source; the first transistor further comprises a first channel, a first drain, and at least one first gate; the second transistor further comprises a second channel, a second drain, and at least one second gate. In a direction parallel to the substrate, the first channel is located between the first drain and the first source, and the second channel is located between the second drain and the first source. In a direction perpendicular to the substrate, at least one first gate is stacked with the first channel, and at least one second gate is stacked with the second channel. The electronic device also comprises a first gap and a second gap, each filled with an insulating dielectric material, and symmetrically disposed about the first source. The first drain and the second drain are symmetrical about the first gap and the second gap; the first gate and the second gate are symmetrical about the first gap and the second gap; and the first channel and the second channel are symmetrical about the first gap and the second gap.

[0032] An embodiment of the present application further provides a memory, which includes a controller and a storage array provided in any of the aforementioned possible implementation methods, wherein the storage array is connected to the controller.

[0033] An embodiment of the present application also provides an electronic device, including a circuit board and the aforementioned memory, wherein the memory is connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a schematic structural diagram of a storage unit provided in the prior art;

[0035] FIG2 is a schematic diagram of the structure of a transistor provided in an embodiment of the present application;

[0036] FIG3 is a cross-sectional schematic diagram of a transistor provided in an embodiment of the present application;

[0037] FIG4 is a schematic cross-sectional view of a transistor provided in an embodiment of the present application;

[0038] FIG5 is a cross-sectional schematic diagram of a transistor provided in an embodiment of the present application;

[0039] FIG6 is a schematic diagram of a memory provided in an embodiment of the present application;

[0040] FIG7 is a schematic diagram of a storage array provided in an embodiment of the present application;

[0041] FIG8 is a schematic structural diagram of a plurality of memory cells stacked in a memory array provided in an embodiment of the present application;

[0042] FIG9 is a schematic structural diagram of a storage unit provided in an embodiment of the present application;

[0043] FIG10 is a schematic diagram of a word line in a memory array provided in an embodiment of the present application;

[0044] FIG11 is a schematic diagram of a word line in a memory array provided by an embodiment of the present application;

[0045] FIG12 is a schematic diagram of a storage circuit provided in an embodiment of the present application;

[0046] FIG13 is a waveform diagram of a method for controlling a storage array provided in an embodiment of the present application;

[0047] FIG14 is a waveform diagram of a storage array control method provided by an embodiment of the present application;

[0048] FIG15 is a flow chart of a method for manufacturing a memory array according to an embodiment of the present application;

[0049] FIG16 is a schematic diagram of a manufacturing process of a storage array provided in an embodiment of the present application;

[0050] FIG17 is a flow chart of a method for manufacturing a memory array according to an embodiment of the present application;

[0051] FIG18 is a schematic diagram of a manufacturing process of a storage array provided in an embodiment of the present application;

[0052] FIG19 is a schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0053] FIG20 is a cross-sectional view of a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0055] The terms "first", "second", etc. in the specification, embodiments, claims and drawings of this application are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between the two elements. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products, or devices are not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to the processes, methods, products, or devices. "Up," "down," "left," "right," etc. are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. They may change accordingly depending on the orientation of the components in the drawings.

[0056] An embodiment of the present application provides an electronic device, which includes a printed circuit board (PCB; also called a circuit board) and an electronic device arranged on the printed circuit board. The electronic device is electrically connected to the printed circuit board, and the electronic device adopts a field-effect transistor (also referred to as a transistor) with a new structure, which can meet a wider range of needs of electronic devices.

[0057] This application does not limit the configuration of the above-mentioned electronic device. For example, the electronic device can be a mobile phone, tablet computer, notebook, car computer, smart watch, smart bracelet and other electronic products.

[0058] This application does not limit the configuration of the above-mentioned electronic device. For example, the electronic device can be a chip, such as a processor, a memory, a sensor, etc.

[0059] The following uses the above-mentioned electronic device as an example of a memory to specifically describe the transistor with a novel structure and the memory using the transistor provided in the embodiments of the present application.

[0060] 2 is a schematic structural diagram of a transistor provided in an embodiment of the present application, FIG. 3 is a partial cross-sectional view of FIG. 2 , and FIG. 4 is a schematic cross-sectional diagram along position OO′ of FIG. 2 .

[0061] With reference to Figures 2, 3, and 4, an embodiment of the present application provides a transistor (also referred to as a first transistor), wherein the first transistor 10 includes a source S, a drain D, a gate G, and a channel C. In a direction parallel to the substrate (not shown in the figure), the channel C is arranged around the source S, and the drain D is arranged around the channel C; that is, the source S, the channel C, and the drain D are arranged in sequence from the inside to the outside. The gate G is stacked with the channel C in a direction perpendicular to the substrate (i.e., the Z direction); of course, the gate G can also be arranged around the source S. It should be noted here that the substrate, as a supporting carrier of the first transistor 10, can be located below the first transistor 10. The substrate is not illustrated in the drawings of this application.

[0062] In the first transistor 10 , by arranging the source S, the channel C, and the drain D in sequence from the inside out, the channel can have a larger width, thereby ensuring that the first transistor has sufficient on-state current.

[0063] Schematically, in the first transistor 10, the drain D, gate G, and channel C may be roughly annular in structure, and the source S may be located in the middle of the annular structure. Of course, it should be understood that, for the first transistor 10, in some embodiments, the source S and the drain D may be interchangeable, that is, the source S and the drain D may not be clearly distinguished.

[0064] In addition, the present application does not limit the structure and material of the source S. For example, in some possible implementations, the source S may be a cylindrical structure. For another example, in other possible implementations, as shown in FIG4 , the source S may include a hollow circular tube structure. Of course, according to actual needs, a conductive material (such as a metal) or an insulating dielectric material may be filled in the hollow circular hole. The source S itself may be a metal material (such as copper) or a doped semiconductor material (such as a doped polysilicon material). In practice, it can be selected and set as needed.

[0065] In the embodiment of the present application, there is no limitation on the number of gates G in the first transistor 10 and the number can be set as needed in practice.

[0066] For example, in some possible implementations, as shown in Figures 3 and 4, two gates G can be set in the above-mentioned first transistor 10, that is, the first transistor 10 has a dual-gate structure; in this case, the two gates G are respectively located on both sides of the channel C in the direction perpendicular to the substrate, that is, the two gates G are respectively arranged above and below the channel C, thereby ensuring that the first transistor has sufficient gate control capability and reducing leakage current.

[0067] For another example, in some other possible implementations, as shown in FIG5 , only one gate G may be provided in the first transistor 10, that is, the first transistor 10 is a single-gate structure; the gate G may be provided above or below the channel C in a direction perpendicular to the substrate.

[0068] In addition, referring to Figure 4, a gate insulating layer 101 is provided in the first transistor 10 to ensure electrical insulation between the gate G and the channel C and the source S. The gate insulating layer 101 at least covers the surface of the gate G facing the channel C and the source S. Of course, according to the actual manufacturing process and the actual application scenario of the first transistor, part of the surface of the gate G can be set not to be covered by the gate insulating layer 101.

[0069] Schematically, as shown in FIG4 , in some possible implementations, the gate insulating layer 101 may include a first insulating layer 101a and a second insulating layer 101b ; wherein the first insulating layer 101a is located outside the gate G (i.e., away from the source S) and extends to cover the upper and lower surfaces of the gate G; the second insulating layer 101b is located inside the gate G (i.e., closer to the source S). In other words, the first insulating layer 101a and the second insulating layer 101b can be manufactured using two different manufacturing processes.

[0070] In addition, to reduce leakage current of the first transistor 10, as shown in FIG4 , in some possible implementations, in the first transistor 10, an intermediate insulating layer 102 may be disposed within the channel C. The intermediate insulating layer 102 is disposed around the source S, and the channel C covers the surface of the intermediate insulating layer 102. Schematically, as shown in FIG4 , in some embodiments, the cross-section of the channel C may be a groove structure with an opening toward the source S, and the intermediate insulating layer 102 fills the groove structure.

[0071] In summary, the source S and drain D of the first transistor 10 provided in the embodiment of the present application are not doped regions on the substrate. The first transistor 10 and the substrate are independent structures, and the substrate only serves as a supporting carrier for the first transistor 10. That is, the production of the first transistor 10 does not depend on the substrate.

[0072] The memory provided in the embodiment of the present application is described in detail below with reference to the aforementioned first transistor 10 .

[0073] First, this application does not limit the type of memory. For example, the memory can be dynamic random access memory (DRAM), ferroelectric random access memory (FeRAM), resistive random access memory (ReRAM), or magnetic random access memory (MRAM). The following embodiments are all illustrated using FeRAM as an example.

[0074] Schematically, as shown in FIG6 , an embodiment of the present application provides a memory 01, which includes at least one memory array 1 and a controller 2, wherein the controller 2 is electrically connected to the memory array 1. Each memory array 1 is provided with a plurality of memory cells M ( FIG7 ). The controller 2 controls the memory array 1, thereby enabling storage and reading of data in the memory cells M. Each memory cell M includes the aforementioned first transistor 10 (also referred to as an access transistor) and a storage capacitor, and the storage capacitor is electrically connected to the first transistor 10.

[0075] It can be understood that, with reference to Figure 7, in the embodiment of the present application, the fabrication of the first transistor 10 does not depend on the substrate. Therefore, when the first transistor 10 is used in the memory as an access transistor in the memory cell M, the first transistor 10 can be set in the back end of line (BEOL), thereby enabling the memory cell M to be stacked in the Z direction (i.e., the direction perpendicular to the substrate), thereby improving the storage density of the memory.

[0076] Schematically, as shown in FIG. 7 , an embodiment of the present application provides a memory array 1, comprising a plurality of bit lines BL (bit lines) disposed on a substrate and extending along the Z direction. In other words, the plurality of bit lines BL are perpendicular to the substrate. Each bit line BL is connected to a plurality of memory cells M stacked along the Z direction. In this memory array 1, the plurality of bit lines BL may be distributed in an array. In this case, the plurality of memory cells M of the memory array 1 are distributed across multiple layers, with each layer including the plurality of memory cells M distributed in an array.

[0077] With reference to FIG7 , for ease of description and understanding, multiple stacked memory cells M connected to the same bit line BL are defined in this application as a memory unit 100. Of course, other components may also be provided in the memory unit 100 based on actual needs. With reference to FIG7 and FIG8 , in a memory unit 100, multiple first transistors (10_1, 1_2) are stacked, that is, the projections of the multiple first transistors (10_1, 10_2) on the substrate may overlap. In this case, the sources S of the multiple first transistors (10_1, 10_2) may be connected to form a hollow circular tube structure, and the interior of the hollow circular tube structure is filled with a conductive material (e.g., a metal material) to form a bit line BL extending along the Z direction. That is, in the memory unit 100, the multiple first transistors (10_1, 10_2) share the same source S, and the source S surrounds the bit line BL to form an electrical connection.

[0078] It should be noted that in the memory component 100, the source S and the bit line BL may be fabricated in two separate processes, that is, the source S and the bit line BL may be two components. Of course, in other embodiments, the source S and the bit line BL may be fabricated in a single process, forming a single component, without explicitly distinguishing between the two. This application does not impose any limitation on this, and this configuration may be implemented as needed in practice.

[0079] In addition, in the present application, the storage density is further improved, the manufacturing process is simplified, and the manufacturing cost is reduced, and the storage capacitor can be integrated with the first transistor 10. Schematically, referring to FIG9 , in some embodiments, a dielectric layer a1 and a first electrode layer a2 can be sequentially stacked on the side of the drain electrode D, that is, in a direction parallel to the substrate, the dielectric layer a1 is located between the drain electrode D and the first electrode layer a2, and the drain electrode D and the first electrode layer a2 respectively serve as the two electrodes of the storage capacitor 11.

[0080] As shown, the storage capacitor 11 may be a ferroelectric capacitor or a dielectric capacitor, and this application does not impose any limitation thereto. In practice, the storage capacitor 11 may be configured as required.

[0081] In addition, as shown in FIG. 7 , other components are also provided in the memory array 1, such as a word line WL (word line), a plate line PL (plate line), a second transistor 20 (also referred to as a selection transistor), a first control line CNTL, a second control line GBL (global bit line), etc. Other related components in the memory array 1 are schematically described below.

[0082] Schematically, as shown in FIG7 , in the memory array 1, a plurality of word lines WL may be respectively provided for the plurality of memory cells M in each layer; in this case, in the plurality of memory cells M in the same layer, along the xx' direction, the gates G of the plurality of first transistors 10 in the plurality of memory cells M located in the same row are connected to form the word line WL, that is, in the plurality of memory cells M located in the same layer, the gates G of the plurality of first transistors connected to the plurality of bit lines BL in the same row are connected to form the word line WL.

[0083] The present application does not impose any limitation on the connection method of the gates G of the plurality of first transistors 10 forming the word line WL. In practice, the connection method of the gates G may be set according to the structure of the gates G.

[0084] For example, as shown in FIG10 , in some possible implementations, the outer edge of the gate G may be set to protrude beyond the outer edge of the drain D. In this case, the gates G of a plurality of first transistors 10 in the same row may be set to be in direct contact, thereby forming a word line WL.

[0085] For another example, as shown in FIG11 , in some possible implementations, the outer edge of the drain D may be configured to protrude beyond the outer edge of the gate G. In this case, due to the size of the drain D, the gates G of two adjacent first transistors 10 in the same row do not directly contact each other. Therefore, an intermediate connector 103 may be provided between the gates G of the two adjacent first transistors 10. The gates G of the two adjacent first transistors 10 are connected via the intermediate connector 103, thereby forming a word line WL. For the fabrication of the intermediate connector 103, please refer to the corresponding description in the fabrication method below.

[0086] Schematically, referring to Figures 7 and 9, for the first electrode layer a2 in the storage capacitor 11, in some possible implementation methods, the first electrode layers a2 of multiple storage capacitors 11 located on the same layer can be connected to the same plate line PL, that is, a fixed potential is provided to the first electrode layers a2 of multiple storage capacitors 11 located on the same layer through a plate line PL, without the need for an additional driving circuit, which has the advantage of low power consumption.

[0087] The present application does not impose any restrictions on the structure of the plate line PL, and in practice, it can be determined according to the specific setting form of the manufacturing process. For example, in some possible implementations, as shown in Figure 7, a planar plate line PL can be formed on the side of the first electrode layer a2 of multiple storage capacitors 11 located in the same layer. For another example, in some possible implementations, multiple strip-shaped plate lines PL can be formed on the side of the first electrode layer a2 of multiple storage capacitors 11 located in the same column (yy' direction) or the same row (xx' direction), and the multiple strip-shaped plate lines PL located in the same layer are connected at the edge area.

[0088] It should be noted here that the "rows" and "columns" involved in this application are only a set of relative positions and do not refer to a fixed position. In some cases, the positions of "rows" and "columns" can be interchanged.

[0089] Schematically, referring to FIG. 7 and FIG. 12 , to control each memory cell M, the memory array 1 further includes: a plurality of second transistors 20, and a plurality of first control lines CNTL and a plurality of second control lines GBL connected to the plurality of second transistors 20. The plurality of second transistors 20 serve as selection transistors and are located in a plurality of different memory units 100. The plurality of second transistors 20 are controlled by the first control lines CNTL and the second control lines GBL to selectively turn each memory cell M on or off.

[0090] Schematically, in some possible implementations, with reference to FIG7 and FIG12 , in the storage unit 100, the second transistor 20 can be located below the plurality of first transistors 10 (memory cells M) that are stacked, that is, the second transistor 20 is located between the plurality of first transistors 10 that are stacked and the substrate. In this case, the second transistor 20 does not need to occupy the area of ​​the substrate alone. In each storage unit 100, the drain of the second transistor 20 is connected to the bit line BL, the gates of the plurality of second transistors 20 located in the same row (xx' direction) are connected to the same first control line CNTL, and the sources of the plurality of second transistors 20 located in the same column (yy' direction) are connected to the same second control line GBL. In other words, the stacked memory cells M can be directly connected to the second transistor 20 through the bit line BL, thereby reducing the overlap (overhead) area between the memory cell M and the second transistor 20.

[0091] This application does not limit the specific structure of the second transistor 20. For example, in some possible implementations, the source, channel, and drain of the second transistor 20 can be stacked along the Z direction, with the source of the second transistor 20 closer to the substrate than the drain, and the drain of the second transistor 20 directly connected to the bit line BL located above it; the gate of the second transistor 20 can be arranged around the channel, that is, the second transistor 20 adopts a ring-gate structure.

[0092] Of course, as shown in FIG12 , in some possible implementations, a third transistor 30 may be further provided in the storage circuit of the storage array 1. The drain of the third transistor 30 is connected to the second control line GBL, and the source of the third transistor 30 is connected to the voltage terminal. By controlling the on or off state of the third transistor 30, the voltage on the second control line GBL is controlled.

[0093] Furthermore, referring to FIG12 , for the entire memory 01, in some possible implementations, the second control line GBL of one memory array 1_1 can be connected to the second control line GBLN of another memory array 1_N via a sense amplifier 2. This allows a reference voltage to be provided to the memory array 1_1 via the memory array 1_N, thereby amplifying the signal. The specific circuit structure of the sense amplifier 2 can be seen in FIG12 , but the present application is not limited thereto. Amplifiers with other circuit structures may also be selected based on actual needs, as long as they meet the amplification requirements of the memory circuit.

[0094] In conjunction with the storage circuit of FIG12 , the control method of the storage array 1 in the embodiment of the present application is described below. Schematically, the embodiment of the present application provides two different control methods, as follows:

[0095] Control method 1

[0096] Figure 13 is a waveform diagram of a control method for a storage array 1 provided in an embodiment of the present application. Referring to Figures 7, 12, and 13, this control method includes: a read precharge phase, a destruction phase, an amplification phase, a read / write phase, a write-back phase, a standby precharge phase, and a standby phase. These seven distinct phases are described in detail below.

[0097] Read pre-charge phase: The read pre-charge operation provides an initial potential for the bit line BL to ensure that the stored charge in the storage capacitor 11 (ferroelectric capacitor) is subsequently destroyed. In this process, the voltage on the first control line CNTL is set to Vpp, so that the second transistor 20 is turned on, and the voltage V0 on the second control line GBL is transferred to the bit line BL. In addition, the voltage on the second control line GBLN and the bit line BLN in the memory array 1_N will be pre-charged to Vref. In this phase, the voltage on the word line WL remains at V0, and the first transistor 10 remains in the off state. Since it is not desired to change the polarization state of any storage capacitor 11 at this stage, the plate line PL and the floating gate node FG (floating gate) both maintain a voltage of Vw. At this time, the voltage difference across the storage capacitor 11 is 0.

[0098] Destruction phase: The voltage of the selected word line WL is set to Vpp, turning on the first transistor 10. Since the voltages on the second control line GBL and the bit line BL are V0, the voltage on the floating gate node FG gradually decreases as charge is shared. At this time, since the voltage of the plate line PL remains at Vw, the voltage difference across the storage capacitor 11 gradually increases. If the selected storage capacitor 11 is in a negative polarization state (i.e., storing information "1"), the polarization state of the storage capacitor 11 will change from negative to positive because the voltage difference between the plate line PL and the floating gate node FG is in the positive polarization direction. During this process, the charge on the storage capacitor 11 will enter the floating gate node FG, the bit line BL, and the second control line GBL, causing its voltage to rise to Vrd1. If the selected storage capacitor 11 is in a positive polarization state (i.e., storing information "0"), the polarization state of the storage capacitor 11 will not change and will remain at voltage Vrd0.

[0099] Amplification stage: In this stage, the sense amplifier 2 starts working, and its two ends are respectively connected to the second control lines (GBL, GBLN) in the two storage arrays (1_1, 1_N). Since the voltage of the second control line GBL becomes Vrd0 or Vrd1 after ferroelectric flipping and charge sharing, and the voltage of the second control line GBLN is Vref, when the information "1" is read, the voltage on the second control line GBL is Vrd1, and the voltage of the second control line GBLN is Vref. Vrd1 is greater than Vref. At this time, the potentials of the second control line GBL and the second control line GBLN are pulled to Vcore and V0 respectively by the sense amplifier; when the information "0" is read, the voltage on the second control line GBL is Vrd0, and the voltage of the second control line GBLN is Vref. Vrd0 is less than Vref. At this time, the voltages of the second control line GBL and the second control line GBLN are pulled to V0 and Vcore respectively by the sense amplifier 2.

[0100] Read / Write Phase: After sense amplifier 2 completes amplification, the information stored in storage capacitor 11 is stored on second control line GBL. At this point, when a read command is received, the information on second control line GBL is read out through the output path to the final output port. When a write command is received, the information on second control line GBL is rewritten with the desired information, and the voltage of second control line GBL connected to sense amplifier 2 changes. If a "1" is written, the voltage on second control line GBL is Vcore after the write command completes. If a "0" is written, the voltage on second control line GBL is V0 after the write command completes.

[0101] Write-back phase: The voltage on the word line WL is Vpp, the first transistor 10 is always in the open state, and the storage capacitor 11 is written back. A voltage difference of Vw needs to be established across the storage capacitor 11 to change the polarization state of the storage capacitor 11. Since the voltage of the second control line GBL is V0 or Vcore in the read and write phase, the voltage on the plate line PL is still maintained at Vw at this time. If the voltage on the second control line GBL is V0, and the voltage difference between the plate line PL and the floating gate node FG is Vw, the storage capacitor 11 will be written back to "0". If the voltage on the second control line GBL is Vcore, and the voltage difference between the plate line PL and the floating gate node FG is -Vw, the storage capacitor 11 will be written back to "1", and the write-back is completed.

[0102] Standby precharge stage: In this stage, the word line WL remains open, the sense amplifier 2 is turned off, and the selected floating gate node FG, the second control line GBL, the bit line LBL, the second control line GBLN and the bit line BLN are precharged back to Vw through the equalizer.

[0103] In the standby phase, the word line WL maintains the voltage V0, and the second control line GBL, the bit line BL, the bit line BLN, the second control line GBLN and the plate line PL maintain the voltage Vw. At this time, the first transistor 10 is turned off, the second transistor 20 is turned off, the voltage of each floating gate node FG is Vw, the voltage difference across the storage capacitor 11 is 0, and the polarization state remains unchanged.

[0104] Control method 2

[0105] Figure 14 is a waveform diagram of a control method for a storage array 1 provided in an embodiment of the present application. Referring to Figures 7, 12, and 14, this control method includes a destruction phase, an amplification phase, a read / write phase, a write-back phase, a standby precharge phase, and a standby phase. These six distinct phases are described in detail below.

[0106] Destruction stage: The voltage of WL is kept at V0, the first transistor 10 is turned off, the voltage of the floating gate node FG is kept at V0, and the voltage of the first control line CNTL is set to V pp , turn on the second transistor 20, and precharge the voltages on the second control line GBL, the bit line BL, the second control line GBLN and the bit line BLN to V ref . Raise the voltage of the plate line PL to V w Since the voltage of the floating gate node FG is V0, the voltage difference between the two ends of the storage capacitor 11 is V wIf the selected storage capacitor 11 is in a negative polarization state (i.e., storing information "1"), since the voltage difference between the plate line PL and the floating gate node FG is in the positive polarization direction, the polarization state of the storage capacitor 11 will change from negative polarization to positive polarization. In this process, the charge on the storage capacitor 11 will enter the floating gate node FG, the bit line BL and the second control line GBL, causing their voltage to rise to V fg1 If the selected storage capacitor 11 is in a positive polarization state (ie, the storage information is "0"), the polarization state of the storage capacitor 11 will not change, and the voltage will remain at V fg0 .

[0107] Amplification stage: Raise the voltage of the selected word line WL to V pp , turn on the first transistor 10, the floating gate node FG and the bit line BL start to share charge, and the capacitance and voltage on the floating gate node FG before charge sharing start are C fg and V fg , the capacitance and voltage on the bit line BL are C BL and V ref After charge sharing is completed, the voltage on the floating gate node FG and the bit line BL becomes V rd According to the law of conservation of charge, it satisfies the following relationship:

[0108] C fg *V fg1 +C BL *V ref =(C fg +C BL )*V rd1

[0109] C fg *V fg0 +C BL *V ref =(C fg +C BL )*V rd0

[0110] In this amplification phase, after charge sharing is completed, the sense amplifier 2 starts to work, and its two ends are respectively connected to the second control lines (GBL, GBLN) in the two storage arrays (1_1, 1_N). Since the voltage of the second control line GBL becomes V after ferroelectric flipping and charge sharing, rd0 or V rd1 , and the second control line GBLN is V ref When the information "1" is read, the voltage on GBL is V rd1 , GBLN is V ref , V rd1 Greater than V refAt this time, the second control line GBL and the second control line GBLN are pulled to V by the sense amplifier respectively. core and V0; when reading information "0", the voltage on the second control line GBL is V rd0 , the second control line GBLN is V ref , V rd0 Less than V ref At this time, the second control line GBL and the second control line GBLN are pulled to V0 and V1 respectively by the sense amplifier 2. w .

[0111] Read and write phase: After the sense amplifier 2 completes amplification, the information stored in the storage capacitor 11 is stored on the second control line GBL. At this time, when a read command is received, the information on the second control line GBL will be read out to the final output port through the output path. When a write command is received, the information on the second control line GBL will be rewritten with the information to be written, and the voltage of the second control line GBL connected to the sense amplifier 2 will change. If "1" is written, after the write command is completed, the voltage on GBL will be V w If "0" is written, after the write command is completed, the voltage on the second control line GBL is V0.

[0112] Write-back phase: The voltage on the word line WL is V pp , the first transistor 10 is always open, and the storage capacitor 11 is written back. It is necessary to establish V across the storage capacitor 11. w The voltage difference between the first and second control lines GBL can change the polarization state of the storage capacitor 11. w , at this time the plate line PL is still maintained at V0. If the voltage on the second control line GBL is V0, the voltage difference between the plate line PL and the floating gate node FG is 0, then the ferroelectric cell will not flip, "0" does not need to be written back, if the voltage on the second control line GBL is V w , the voltage difference between the plate line PL and the floating gate node FG is -V w , the storage capacitor 11 will be written back to "1", and the write-back is completed.

[0113] Standby precharge stage: In this stage, the word line WL remains open, the sense amplifier 2 is turned off, and the selected floating gate node FG, the second control line GBL, the bit line BL, the second control line GBLN and the bit line BLN are precharged back to V0 through the equalizer.

[0114] In the standby phase, the word line WL maintains the voltage V0, and the second control line GBL, the bit line BL, the bit line BLN, the second control line GBLN and the plate line PL maintain the voltage V0. At this time, the first transistor 10 is turned off, the second transistor 20 is turned off, the voltage of each floating gate node FG is V0, the voltage difference across the storage capacitor 11 is 0, and the polarization state remains unchanged.

[0115] The following describes a method for manufacturing the memory array 1 in an embodiment of the present application. Schematically, the embodiment of the present application provides two different control methods, as follows:

[0116] Preparation method 1

[0117] As shown in FIG15 , an embodiment of the present application provides a method for manufacturing a memory array 1, which may include:

[0118] Step 11, referring to (a) and (b) in FIG16 , a plurality of initial stacking units E are stacked on a substrate (not shown in the figure), and at least one first through hole 201 penetrating the plurality of initial stacking units E is formed by etching; wherein the initial stacking unit E includes a first insulating layer b1, a sacrificial layer b2, and a first insulating layer b1 stacked in sequence.

[0119] It should be noted here that the substrate is located below the initial stacking unit E, and other devices, such as the second transistor 20 mentioned above, may be provided on the substrate.

[0120] By stacking a plurality of initial stacked units E, a plurality of stacked first transistors 10 can be subsequently formed, thereby realizing a stacked arrangement of the memory cell M. In the subsequent fabrication process of the initial stacked unit E, the sacrificial layer b2 is used to form the channel C, drain D, etc. of the first transistor 10, and the first insulating layer b1 is used to form the gate G of the first transistor 10. Of course, depending on actual needs, insulating layers can generally be provided on both the upper and lower surfaces of the initial stacked unit E to meet process requirements and electrical insulation between devices.

[0121] Figure 16 is only a schematic illustration of the case where the first insulating layer b1 is provided on both the upper and lower surfaces of the sacrificial layer b2 (corresponding to the formation of the first transistor with a dual-gate structure). In other possible implementation methods, the first insulating layer b1 can be provided only on the upper or lower surface of the sacrificial layer b2 in the initial stacking unit E (corresponding to the formation of the first transistor with a single-gate structure).

[0122] In addition, the shape of the initial stacking unit E can be determined according to actual manufacturing requirements. Schematically, in some possible implementations, the initial stacking unit E can be a strip structure, and one initial stacking unit E corresponds to the production of a row (or column) of first transistors 10 in the memory array 1. Multiple initial stacking units E stacked together can form a stacked multilayer first transistor 10. Therefore, for a memory array with a multilayer structure, initial stacking unit groups (i.e., including multiple stacked initial stacking units E) are formed for multiple rows of memory cells through step 11, and each initial stacking unit group is etched to form multiple first through holes 201; a bit line BL is formed at a position corresponding to the first through hole 201 through a subsequent manufacturing process; in this case, a bit line BL is connected to multiple first transistors 10 stacked along the Z direction in a memory unit 100; for details, please refer to the manufacturing process below.

[0123] Step 12, referring to (c) and (d) in Figure 16, a portion of the first insulating layer b1 is removed along the side wall of the first through hole 201 to form a first groove structure 31, and the gate G of the first transistor 10 and the gate insulating layer 101 wrapping the gate G are formed in the first groove structure 301.

[0124] Schematically, the above-mentioned step 12 may include: referring to (c) in FIG16 , selectively etching along the side wall of the first through hole 201 to remove part of the first insulating layer b1 to form a first groove structure 31; then, referring to (d) in FIG16 , depositing a gate insulating layer 101a on the side wall and bottom of the first groove structure 31, then depositing the gate G, and finally depositing the gate insulating layer 101b again at the notch position of the first groove structure, so that the upper, lower, left and right sides of the gate G are all covered with the gate insulating layer.

[0125] In some possible implementations, while the gate G is formed in step 12 , the gates G of the first transistors 10 in the same row in the corresponding memory array 1 may be connected to form a word line WL.

[0126] Schematically, in some possible implementations, the first groove structure 31 formed at the position of the first transistor 10 in the same row in the memory array 1 in step 12 is a connected groove structure, so that while the gate G is deposited to form, the gate G of the first transistor 10 in the same row is connected to form a word line WL. For details, please refer to Figure 10 and the relevant description above.

[0127] Schematically, in some possible implementations, the two adjacent first groove structures 31 formed at the positions of the first transistors 10 in the same row in the memory array 1 in step 12 are connected through an intermediate groove structure. In this case, in combination with reference to Figure 11, it is necessary to form an intermediate through hole 104 between the corresponding two adjacent first through holes 201 in step 11. In this way, in step 12, an intermediate groove can be formed along the side wall of the intermediate through hole 104 to connect the two adjacent first groove structures 31, so that while depositing and forming the gate G, an intermediate connecting portion 103 is formed between the two adjacent gates G, and the two gates G are connected to form a word line WL. For details, please refer to Figure 11 and the relevant description above.

[0128] Of course, the filling material in the middle through hole 104 can be a conductive material or a non-conductive material. In order to simplify the manufacturing process and reduce the manufacturing cost, the middle through hole 104 can be manufactured with the bit line BL through the same manufacturing process.

[0129] Step 13, referring to (e) and (f) in FIG. 16 , a portion of the sacrificial layer b2 is removed along the sidewall of the first through hole 201 to form a second groove structure 32 , and a channel C of the first transistor is formed in the second groove structure 32 .

[0130] Schematically, the above-mentioned step 12 may include: referring to (c) in FIG16 , the above-mentioned step 13 may include: referring to (e) in FIG16 , selectively etching along the side wall of the first through hole 201 to remove part of the sacrificial layer b2 to form a second groove structure 32; then, referring to (f) in FIG16 , polysilicon is deposited in the second groove structure 32 to form a channel C.

[0131] It should be noted that, when the channel C can be formed by depositing polysilicon, in some possible implementations, the polysilicon material can fill the entire second groove structure 32. Of course, in order to reduce the leakage current of the first transistor 10, in other possible implementations, a polysilicon film layer can be deposited only on the sidewalls and bottom of the second groove structure 32 to form the channel C, and then the second groove structure 32 can be filled with an insulating dielectric material, thereby forming an intermediate insulating layer 102 inside the channel C.

[0132] Step 14: Referring to FIG. 16 (g), the source S of the first transistor 10 and the bit line BL are formed in the first through hole 201 .

[0133] It can be understood that the source S formed in step 14 serves as a common source S for the plurality of first transistors 10 stacked in the Z direction.

[0134] Illustratively, in some possible implementations, the above step 14 may include: depositing a polysilicon film layer on the inner side wall of the first through hole 201 to form a common source S of multiple first transistors 10 stacked in the Z direction; and then filling metal material in the polysilicon film layer to form a bit line BL.

[0135] Of course, in some possible implementations, the source S and the bit line BL may not be clearly distinguished, and the first through hole 201 may be directly filled with a conductive material to form the source S, which also serves as the bit line BL.

[0136] Step 15, referring to (h) and (i) in FIG16 , the remaining sacrificial layer b2 is removed along the side of the initial stacked unit E to form a third groove structure 33 to expose the channel C, and a drain D is formed on the side of the exposed channel C.

[0137] Schematically, the above-mentioned step 15 may include: referring to (h) in FIG16 , removing the remaining sacrificial layer b2 by selective etching along the side of the initial stacking unit E to form a third groove structure 33 and expose the channel C; then, referring to (i) in FIG16 , forming a drain D on the side of the exposed channel C.

[0138] Of course, in some possible implementations, in order to further improve the storage density of the memory array 1, referring to FIG16(i), after the drain D of the first transistor 10 is formed in step 15, a dielectric layer a1 and a first electrode layer a2 stacked with the drain D may be sequentially formed on the side of the drain D to form a storage capacitor 11. In this case, the drain D and the first electrode layer a2 serve as the two plates of the storage capacitor 11.

[0139] In addition, after the first electrode layer a2 is formed, a plate line PL may be formed on a side of the first electrode layer a2 to provide a voltage to the storage capacitor 11 in the same layer through the plate line PL.

[0140] Preparation method 2

[0141] As shown in FIG17 , an embodiment of the present application provides a method for manufacturing a memory array 1, which may include:

[0142] Step 21, referring to (a) and (b) in FIG18 , a plurality of initial stacking units E are stacked on a substrate (not shown in the figure), and at least one first through hole 201 penetrating the plurality of initial stacking units E is formed by etching; wherein the initial stacking unit 201 includes a first insulating layer b1, a sacrificial layer b2, and a first insulating layer b1 stacked in sequence.

[0143] The shape of the initial stacking unit E can be determined based on actual manufacturing requirements. For example, in some possible implementations, the initial stacking unit E can be a block structure, and one initial stacking unit E can correspond to a layer of memory cells in the memory array 1. In other words, a plurality of stacked initial stacking units E can form a memory array 1 through subsequent manufacturing steps.

[0144] For other related instructions about step 21, please refer to the corresponding part in the aforementioned step 11, which will not be repeated here.

[0145] Step 22, referring to (c) and (d) in Figure 18, a portion of the first insulating layer a1 is removed along the side wall of the first through hole 201 to form a first groove structure 31, and the gate G of the first transistor and the gate insulating layer 101 wrapping the gate G are formed in the first groove structure 31.

[0146] For the relevant instructions about step 22, please refer to the corresponding part in the aforementioned step 12, which will not be repeated here.

[0147] Step 23, referring to (e) and (f) in FIG18 , a portion of the sacrificial layer b2 is removed along the sidewall of the first through hole to form a second groove structure 32, and the drain D and the channel C of the first transistor 10 are sequentially formed in the second groove structure 32.

[0148] Schematically, in some possible implementation methods, the above-mentioned step 23 may include: referring to (e) in FIG18 , selectively etching along the side wall of the first through hole 201 to remove part of the sacrificial layer b2 to form a second groove structure 32; then, referring to (f) in FIG18 , first depositing metal in the second groove structure 32 to form a drain D, and then depositing polysilicon to form a channel C.

[0149] For other related settings of the above-mentioned channel C, please refer to the relevant instructions in the aforementioned step 13, which will not be repeated here.

[0150] Step 24 , referring to FIG. 18 ( g ), the source S of the first transistor 10 and the bit line BL are formed in the first through hole 201 .

[0151] For the relevant instructions about step 24, please refer to the corresponding part in the aforementioned step 14, which will not be repeated here.

[0152] Of course, in order to further improve the storage density of the storage array 1, after the drain D is formed through step 23, in some possible implementation methods, referring to (h) and (i) in Figure 18, the remaining sacrificial layer b2 can be removed along the side of the initial stacked unit E to form a third groove structure 33 to expose the drain D, and a dielectric layer a1 and a first electrode layer a2 are sequentially formed on the side of the exposed drain D to form a storage capacitor 11.

[0153] In addition, after the first electrode layer a2 is formed, a plate line PL may be formed on a side of the first electrode layer a2 to provide a voltage to the storage capacitor 11 in the same layer through the plate line PL.

[0154] In summary, the method for manufacturing a memory array provided in an embodiment of the present application, based on a transistor of a novel structure, can form a first transistor in a multi-layer stacked arrangement through a single manufacturing process without relying on a substrate; the cost of a mask is saved and the manufacturing process is simplified; and in this manufacturing method, the formed bit line extends along the Z direction to connect with multiple stacked memory cells, thereby enabling three-dimensional stacking of memory cells, thereby improving the storage density and reducing the cost per bit per unit area.

[0155] Based on the setting of the first transistor 10 provided in the aforementioned embodiment of the present application, the embodiment of the present application also provides another semiconductor device (including two transistors). The structure of this semiconductor device is similar to that of the aforementioned first transistor 10. The differences between this semiconductor device and the aforementioned first transistor 10 are schematically explained below.

[0156] FIG19 is a schematic three-dimensional diagram of a semiconductor device provided in an embodiment of the present application, and FIG20 is a cross-sectional view of FIG19 .

[0157] Referring to Figures 19 and 20, an embodiment of the present application provides a semiconductor device, which has a structure similar to that of the first transistor 10 provided in the aforementioned embodiment, but differs in that, based on the structure of the first transistor 10, the semiconductor device is further provided with a first gap r1 and a second gap r2 symmetrically arranged about the source S, and the first gap r1 and the second gap r2 are filled with an insulating dielectric material. By setting the first gap r1 and the second gap r2, the first transistor 10 can be divided into two transistors (T1, T2).

[0158] Referring to Figures 19 and 20, the gate G, channel C, and drain D of the above-mentioned first transistor 10 are divided by the first gap r1 and the second gap r2, corresponding to the gate, channel, and drain of the two transistors (T1, T2) respectively; for example, the gate G, channel C, and drain D of the first transistor 10 are a circular ring structure, which is called two semi-circular ring structures after being divided by the first gap r1 and the second gap r2, serving as the gate, channel, and drain of the two transistors (T1, T2) respectively.

[0159] That is, the first gap r1 and the second gap r2 divide the gate G structure of the first transistor 10 to form the gate G1 of the transistor T1 and the gate G2 of the transistor T2, and the gate G1 and the gate G2 are symmetrically arranged with respect to the first gap r1 and the second gap r2. The first gap r1 and the second gap r2 divide the channel C of the first transistor 10 to form the channel C1 of the transistor T1 and the channel C2 of the transistor T2, and the channels C1 and C2 are symmetrically arranged with respect to the first gap r1 and the second gap r2. The first gap r1 and the second gap r2 divide the drain D of the first transistor 10 to form the drain D1 of the transistor T1 and the drain D2 of the transistor T2, and the drain D1 and the drain D2 are symmetrically arranged with respect to the first gap r1 and the second gap r2.

[0160] The sources S of the two transistors (T1, T2) are not divided, that is, the structure of the sources S of the two transistors (T1, T2) is the same as the source S of the first transistor 10, that is, the two transistors (T1, T2) in the semiconductor device are connected through the source S.

[0161] Regarding other configurations of the two transistors (T1, T2), reference may be made to the corresponding description of the first transistor 10 in the aforementioned embodiment, and will not be repeated here. For example, the two transistors (T1, T2) may be single-gate structures or dual-gate structures. Figures 19 and 20 are merely schematic illustrations using a single-gate structure as an example, and for details, reference may be made to the corresponding descriptions in the aforementioned embodiments.

[0162] In addition, the two transistors (T1, T2) can be applied to a memory array. Similar to the configuration of the first transistor 10, the two transistors (T1, T2) serve as a memory group and are connected to a bit line BL via a source S. In this case, the two transistors (T1, T2) can be located in two different memory cells (a first memory cell and a second memory cell). That is, one bit line BL is connected to two memory cells in a layer, while in the aforementioned embodiment, one bit line BL is connected to only one memory cell in a layer. In this way, one bit line BL is equivalent to connecting two memory units 200, further improving the storage density of the memory array.

[0163] Regarding other settings in the memory array in which the two memory cells formed by the two transistors (T1, T2) can be used as a memory group, such as the bit line BL, the word line WL, the plate line PL, the second transistor 20, etc., it is similar to the setting in which the memory cell formed by the aforementioned first transistor 10 is used as a memory group in the memory array. For details, please refer to the relevant description in the previous text and will not be repeated here.

[0164] In addition, the fabrication of the two transistors (T1, T2) described above is similar to the fabrication process of the first transistor 10 described above. Before forming the first through-hole 201 in the fabrication method provided in the aforementioned embodiment, the stacked plurality of initial laminate units E may be etched to form a gap, and the gap may be filled with an insulating dielectric material. The first through-hole 201 may then be formed at the center of the gap, thereby forming two gaps (r1, r2) symmetrical about the first through-hole 201. Subsequent fabrication processes may refer to the aforementioned fabrication method and will not be described in detail here.

[0165] It should be noted that the above-mentioned semiconductor device including two transistors (T1, T2) can be applied not only to memories, but also to other electronic devices, and this application does not impose any limitation on this.

[0166] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that: include: substrate; at least one bit line, the at least one bit line being disposed on the surface of the substrate and perpendicular to the substrate; a plurality of memory groups connected to each of the bit lines, the plurality of memory groups being stacked in a direction perpendicular to the substrate, each of the memory groups including at least one memory cell, each of the memory cells including a first transistor and a storage capacitor connected to the first transistor; Wherein, the first transistor includes a source, a drain, at least one gate, and a channel; In each of the memory groups, all the first transistors share a source, and the source is disposed around the bit line and connected to the bit line; In each of the first transistors, the channel is disposed between the source and the drain along a direction parallel to the substrate; and the at least one gate is disposed stacked with the channel along a direction perpendicular to the substrate.

2. The storage array according to claim 1, wherein: The storage group includes one storage unit; The channel is arranged around the source, the drain is arranged around the channel, and the gate is arranged around the bit line.

3. The storage array according to claim 1, wherein: The storage group includes a first storage unit and a second storage unit; The first transistor in the first storage unit includes a first drain, a first gate, and a first channel; The first transistor in the second storage unit includes a second drain, a second gate, and a second channel; The memory group is further provided with a first gap and a second gap, the first gap and the second gap are filled with an insulating dielectric material, and the first gap and the second gap are symmetrically arranged with respect to the bit line; The first drain electrode and the second drain electrode are symmetrically arranged with respect to the first gap and the second gap; The first gate and the second gate are symmetrically arranged with respect to the first gap and the second gap; The first channel and the second channel are symmetrically arranged with respect to the first gap and the second gap.

4. The storage array according to any one of claims 1 to 3, wherein: The storage capacitor includes: a dielectric layer and a first electrode layer; the dielectric layer and the first electrode layer are stacked with the drain of the first transistor in a direction parallel to the substrate, and the dielectric layer is located between the drain and the first electrode layer.

5. The storage array according to any one of claims 1 to 4, wherein: The storage capacitor is a ferroelectric capacitor or a dielectric capacitor.

6. The storage array according to any one of claims 1 to 5, wherein: The first transistor includes two gates, and the two gates are respectively located on both sides of the channel in a direction perpendicular to the substrate.

7. The storage array according to any one of claims 1 to 6, wherein: The first transistor includes an intermediate insulating layer, and the channel covers a surface of the intermediate insulating layer.

8. The storage array according to any one of claims 1 to 7, wherein: The first transistor includes a gate insulating layer, and the gate insulating layer covers a surface of the gate.

9. The storage array according to any one of claims 1 to 8, wherein: The memory array is provided with a plurality of bit lines distributed in an array, and the plurality of bit lines are manufactured through a same manufacturing process.

10. The storage array according to claim 9, wherein: The gates of the plurality of first transistors located in the same layer and connected to the plurality of bit lines in the same row are connected to form a word line.

11. The storage array according to claim 10, wherein: Among the plurality of first transistors located in the same layer and connected to the plurality of bit lines in the same row, gates of two adjacent first transistors contact each other to form the word line.

12. The storage array according to claim 10, wherein: Among the plurality of first transistors located in the same layer and connected to the plurality of bit lines in the same row, gates of two adjacent first transistors are connected via an intermediate connecting portion to form the word line.

13. The storage array according to any one of claims 9 to 12, wherein: The storage array further includes: a plurality of plate lines; The first electrode layers of a plurality of the storage capacitors arranged in the same layer are connected to the same plate line.

14. The storage array according to any one of claims 9 to 13, wherein: The memory array further includes: a plurality of second transistors, at least one first control line, and at least one second control line disposed between the plurality of bit lines and the substrate; The second transistor includes a source, a drain, a gate, and a channel; The drains of the plurality of second transistors are respectively connected to the plurality of bit lines; The gates of the plurality of second transistors connected to the plurality of bit lines in the same row are connected to the same first control line; Sources of the plurality of second transistors connected to the plurality of bit lines in the same column are connected to the same second control line.

15. The storage array according to claim 14, wherein: The source, channel, and drain of the second transistor are stacked in a direction perpendicular to the substrate, and the source of the second transistor is closer to the substrate than the drain of the second transistor; The gate of the second transistor is arranged around the channel of the second transistor.

16. A method for manufacturing a storage array, characterized in that: include: Forming a plurality of initial stacking units stacked on a substrate, and forming at least one first through-hole penetrating the plurality of initial stacking units by etching; wherein the initial stacking unit includes a sacrificial layer and a first insulating layer disposed on the upper surface and / or the lower surface of the sacrificial layer; removing a portion of the first insulating layer along a sidewall of the first through hole to form a first groove structure, and forming a gate of the first transistor and a gate insulating layer wrapping the gate in the first groove structure; removing the sacrificial layer, and forming a drain and a channel of the first transistor at the location where the sacrificial layer is removed; wherein the channel is located on a side of the drain close to the first through hole; A source and a bit line of the first transistor are formed in the first through-hole.

17. The method for manufacturing a memory array according to claim 16, wherein: The removing of the sacrificial layer and forming the drain and the channel of the first transistor at the location where the sacrificial layer is removed comprises: removing a portion of the sacrificial layer along a sidewall of the first through hole to form a second groove structure, and forming a channel of the first transistor in the second groove structure; The sacrificial layer is removed along the side of the initial stacked unit to form a third groove structure to expose the channel, and a drain is formed on the side of the channel.

18. The method for manufacturing a memory array according to claim 17, wherein: The production method further comprises: A dielectric layer and a first electrode layer are sequentially formed on the side of the drain electrode in the third groove structure.

19. The method for manufacturing a memory array according to claim 16, wherein: The removing of the sacrificial layer and forming the drain and the channel of the first transistor at the location where the sacrificial layer is removed comprises: A portion of the sacrificial layer is removed along the sidewall of the first through hole to form a second groove structure, and a drain and a channel of the first transistor are sequentially formed in the second groove structure.

20. The method for manufacturing a memory array according to claim 19, wherein: The production method further comprises: The sacrificial layer is removed along the side surface of the initial stacked unit to form a third groove structure and expose the drain electrode, and a dielectric layer and a first electrode layer are sequentially formed on the side surface where the drain electrode is exposed.

21. An electronic device, characterized in that: The invention comprises a substrate and a transistor provided on the substrate; the transistor comprises a source, a drain, at least one gate, and a channel; In a direction parallel to the substrate, the channel is arranged around the source, and the drain is arranged around the channel; The at least one gate is stacked along the channel in a direction perpendicular to the substrate, and the at least one gate is disposed around the source.

22. An electronic device, characterized in that: comprising a substrate and a first transistor and a second transistor disposed on the substrate; The first transistor and the second transistor share a first source; The first transistor further includes a first channel, a first drain, and at least one first gate; the second transistor further includes a second channel, a second drain, and at least one second gate; In a direction parallel to the substrate, the first channel is located between the first drain and the first source, and the second channel is located between the second drain and the first source; In a direction perpendicular to the substrate, the at least one first gate is stacked with the first channel, and the at least one second gate is stacked with the second channel; The electronic device is further provided with a first gap and a second gap, the first gap and the second gap are filled with an insulating dielectric material, and the first gap and the second gap are symmetrically arranged with respect to the first source; The first drain electrode and the second drain electrode are symmetrical with respect to the first gap and the second gap; The first gate and the second gate are symmetrical about the first gap and the second gap; The first channel and the second channel are symmetrical with respect to the first gap and the second gap.

23. A memory, characterized in that: The device comprises a controller and a storage array according to any one of claims 1 to 15, wherein the storage array is connected to the controller.

24. An electronic device, characterized in that: The device comprises a circuit board and the memory according to claim 23, wherein the memory is connected to the circuit board.

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