Case management controller test circuit, test system, test method and device

Abstract

The invention provides a case management controller test circuit, test system, test method and device, and relates to the technical field of computers.The method comprises the steps that a local area network IP address of a to-be-tested case management controller is obtained through a CMC management network port of the to-be-tested case management controller; executing the network test instruction through a first node BMC management network port of the case management controller test circuit to obtain a first test result; and under the condition that the first test result indicates that the first high-speed connector can receive a Serdes signal sent by the to-be-tested chassis management controller, sending an I2C test instruction to the to-be-tested chassis management controller through a CMC management network port of the to-be-tested chassis management controller, and testing whether the to-be-tested chassis management controller can receive target data. The case management controller test circuit, test system, test method and device provided by the invention are used for reducing the test complexity and test cost of the case management controller.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a chassis management controller test circuit, test system, test method and device. Background Art

[0002] The Chassis Management Controller (CMC) is a system management hardware and software solution for managing multiple blade servers. The CMC allows IT administrators to perform the following tasks: inventory resources, perform configuration and monitoring tasks, remotely turn blade servers on and off, and support alerts for server and component events in the blade chassis. The CMC can also manage chassis fans, power supplies, and other resources.

[0003] In the related art, for the production test of the chassis management controller, a multi-node blade server environment is usually established to meet the test coverage requirements of the board.

[0004] However, this testing method requires multiple blade node motherboards, which not only makes the testing environment architecture complex, but also makes the testing process complicated. Summary of the invention

[0005] The purpose of the present application is to provide a chassis management controller test circuit, test system, test method and device, which are used to reduce the test complexity and test cost of the chassis management controller.

[0006] The present application provides a chassis management controller test circuit, comprising: A first test sub-circuit and a second test sub-circuit; the first test sub-circuit is used to test the network function of the chassis management controller under test; the second test sub-circuit is used to test the I2C communication function of the chassis management controller under test; the first test sub-circuit includes: a first high-speed connector connected to the network path of the chassis management controller under test, and a first node BMC management network port connected to the test equipment through a network cable; the second test sub-circuit includes: a second high-speed connector connected to the I2C path of the chassis management controller under test, and an I2C interaction unit connected to the second high-speed connector through the integrated circuit bus I2C.

[0007] Optionally, the first test subcircuit further includes: a port physical layer chip; the port physical layer chip is used to convert the Serdes signal received by the first high-speed connector into a medium-dependent interface MDI signal, and forward the MDI signal to the test device through the first node BMC management network port.

[0008] Optionally, the I2C interaction unit includes: a first electrically erasable programmable read-only memory EEPROM storing node BMC signal data, a second EEPROM storing Siwtch interaction signal data, a third EEPROM storing Fan interaction signal data, and an I2C main register; the I2C main register is used to forward the node BMC signal data, the Siwtch interaction signal data and the Fan interaction signal data to the chassis management controller to be tested through the second high-speed connector.

[0009] Optionally, the chassis management controller test also includes: a power supply electronic circuit; the power supply electronic circuit is used to test the PSU interaction signal of the chassis management controller to be tested; the power supply electronic circuit includes: a power supply control switch, a power supply connector, and a power supply PSU power supply module; the power supply connector is respectively communicated with the power supply control switch and the PSU power supply module; the power supply connector is used to use the power provided by the PSU power supply module to power the first high-speed connector and the second high-speed connector; the power supply control switch is used to control the conduction and closing of the power supply circuit between the power supply connector and the first high-speed connector, and control the conduction and closing of the power supply circuit between the power supply connector and the second high-speed connector.

[0010] The present application provides a chassis management controller testing method, which is applied to a testing device, and the method includes: The LAN IP address of the chassis management controller to be tested is obtained through the CMC management network port of the chassis management controller to be tested, and a network test instruction is executed through the first node BMC management network port of the chassis management controller test circuit to obtain a first test result; the network test instruction is used to test whether the first high-speed connector of the chassis management controller test circuit can receive the Serdes signal sent by the chassis management controller to be tested; when the first test result indicates that the first high-speed connector can receive the Serdes signal sent by the chassis management controller to be tested, an I2C test instruction is sent to the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and a second test result is obtained; the I2C test instruction is used to test whether the chassis management controller to be tested can receive target data; the target data includes: node BMC signal data, selected Siwtch interaction signal data and fan Fan interaction signal data; based on the second test result, it is judged whether the test of the chassis management controller to be tested is completed.

[0011] Optionally, judging whether the test of the chassis management controller under test is completed based on the second test result includes: when the second test result indicates that the chassis management controller under test can receive the target data, sending a PSU test instruction to the chassis management controller under test through the CMC management network port of the chassis management controller under test, and obtaining a third test result; the PSU test instruction is used to test whether the chassis management controller under test can receive PSU interaction signal data; when the third test result indicates that the chassis management controller under test can receive the PSU interaction signal data, determining that the chassis management controller under test passes the test, and completing the test of the chassis management controller under test.

[0012] Optionally, the method also includes: determining that the chassis management controller under test fails the test when the first test result indicates that the first high-speed connector fails to receive the Serdes signal sent by the chassis management controller under test, or the second test result indicates that the chassis management controller under test fails to receive the target data, or the third test result indicates that the chassis management controller under test fails to receive the PSU interaction signal data.

[0013] The present application also provides a chassis management controller testing device, comprising: An information acquisition module is used to obtain the LAN IP address of the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested; a functional test module is used to execute a network test instruction through the first node BMC management network port of the chassis management controller test circuit to obtain a first test result; the network test instruction is used to test whether the first high-speed connector of the chassis management controller test circuit can receive the Serdes signal sent by the chassis management controller to be tested; the functional test module is also used to send an I2C test instruction to the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested when the first test result indicates that the first high-speed connector can receive the Serdes signal sent by the chassis management controller to be tested, and obtain a second test result; the I2C test instruction is used to test whether the chassis management controller to be tested can receive target data; the target data includes: node BMC signal data, selected Siwtch interaction signal data and fan Fan interaction signal data; the functional test module is also used to determine whether the test of the chassis management controller to be tested is completed based on the second test result.

[0014] Optionally, the functional testing module is specifically used to send a PSU test instruction to the chassis management controller under test through the CMC management network port of the chassis management controller under test and obtain a third test result when the second test result indicates that the chassis management controller under test can receive the target data; the PSU test instruction is used to test whether the chassis management controller under test can receive PSU interaction signal data; the functional testing module is also specifically used to determine that the chassis management controller under test has passed the test and complete the test of the chassis management controller under test when the third test result indicates that the chassis management controller under test can receive the PSU interaction signal data.

[0015] Optionally, the functional testing module is further used to determine that the chassis management controller under test fails the test when the first test result indicates that the first high-speed connector fails to receive the Serdes signal sent by the chassis management controller under test, or the second test result indicates that the chassis management controller under test fails to receive the target data, or the third test result indicates that the chassis management controller under test fails to receive the PSU interaction signal data.

[0016] The present application also provides a chassis management controller testing system, comprising: a chassis management controller testing circuit and a testing device as described in any one of the above items; the testing device is used to execute the chassis management controller testing method as described in any one of the above items.

[0017] The present application also provides a computer program product, comprising a computer program / instruction, which implements the steps of any of the above-mentioned chassis management controller testing methods when executed by a processor.

[0018] The present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of any of the above-mentioned chassis management controller testing methods are implemented.

[0019] The present application also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of any of the above-mentioned chassis management controller testing methods are implemented.

[0020] The chassis management controller test circuit, test system, test method and device provided by the present application first obtain the LAN IP address of the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and execute the network test instruction through the first node BMC management network port of the chassis management controller test circuit to obtain a first test result; the network test instruction is used to test whether the first high-speed connector of the chassis management controller test circuit can receive the Serdes signal sent by the chassis management controller to be tested; then, when the first test result indicates that the first high-speed connector can receive the Serdes signal sent by the chassis management controller to be tested, send an I2C test instruction to the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and obtain a second test result; the I2C test instruction is used to test whether the chassis management controller to be tested can receive target data; the target data includes: node BMC signal data, selected Siwtch interaction signal data and fan Fan interaction signal data; finally, based on the second test result, determine whether the test of the chassis management controller to be tested is completed. In this way, the testing complexity and testing cost of the chassis management controller can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 It is a schematic diagram of the architecture of a chassis management controller test system in the related art provided by the present application; Figure 2 is a schematic diagram of the architecture of the chassis management controller test system provided by the present application; Figure 3 This is a schematic diagram of the I2C channel detection process provided by this application; Figure 4 It is one of the flow charts of the chassis management controller testing method provided by this application; Figure 5 This is the second flow chart of the chassis management controller testing method provided by this application; Figure 6 is a structural schematic diagram of a chassis management controller test device provided by the present application; Figure 7 It is a structural schematic diagram of the electronic device provided by this application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0024] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0025] With the development of computer server information technology, blade servers have been widely used in enterprise-level applications, cloud computing, high-performance computing and other fields, and have become an important part of data center infrastructure. Blade servers use a high-density, modular server architecture. They are composed of multiple card-type server units inserted in a standard height rack chassis. Each such unit is called a "blade". Each blade usually contains an independent processor, memory, storage and network interface. They can work independently like traditional servers, or they can work together by sharing resources.

[0026] Since blade servers are composed of multiple blade motherboards and have a very complex architecture, if the test environment is built completely according to the blade server architecture during the production test of the printed circuit board assembly (PCBA), the test hardware environment will be very large for the test board. Figure 1 As shown in the figure, when testing the CMC of a blade server, a multi-node blade server environment is usually used to meet the test coverage requirements of the board. This test method requires multiple blade node motherboards, which are connected to the chassis management controller to be tested through a high-speed interconnect backplane. The environment architecture is complex and the test cost is very high.

[0027] In response to the above-mentioned technical problems existing in the related technology, the embodiment of the present application provides a chassis management controller test circuit, and a chassis management controller test method based on the chassis management controller test circuit. By bringing out the CMC test signal link and replacing the high-speed interconnection backplane and node mainboard of the existing blade server, the problems of complex blade server testing environment and high testing cost are solved, a simple testing environment is constructed, and the CMC is tested, which greatly reduces the testing cost.

[0028] The chassis management controller test circuit provided in the embodiment of the present application is described in detail below through specific embodiments and application scenarios in conjunction with the accompanying drawings.

[0029] Exemplarily, the chassis management controller test circuit provided in the embodiment of the present application includes: A first test sub-circuit and a second test sub-circuit; the first test sub-circuit is used to test the network function of the chassis management controller under test; the second test sub-circuit is used to test the I2C communication function of the chassis management controller under test.

[0030] Exemplarily, the first test sub-circuit includes: a first high-speed connector connected to the network path of the chassis management controller under test, and a first node BMC management network port connected to the test equipment through a network cable; the second test sub-circuit includes: a second high-speed connector connected to the I2C path of the chassis management controller under test, and an I2C interaction unit connected to the second high-speed connector through the integrated circuit bus I2C.

[0031] Exemplarily, the first high-speed connector is used to receive the deserializer Serdes signal of the chassis management controller under test; the I2C interaction unit is used to receive the I2C test instruction forwarded by the chassis management controller under test through the second high-speed connector; the I2C interaction unit is also used to respond to the I2C test instruction and send the target data stored in the I2C interaction unit to the chassis management controller under test through the second high-speed connector; the I2C test instruction is sent by the chassis management controller under test based on the I2C scanning device instruction; the target data includes: node baseboard management controller (Board Management Controller, BMC) signal data, selected Siwtch interaction signal data and fan Fan interaction signal data.

[0032] Among them, the test device is connected to the chassis management controller CMC management network port of the chassis management controller under test through a network cable; the test device tests whether the first high-speed connector can receive the Serdes signal through the first node BMC management network port; the test device tests whether the chassis management controller under test can receive the target data through the CMC management network port; the I2C test instruction is sent by the test device to control the chassis management controller under test.

[0033] For example, Figure 2 As shown, it is a structural schematic diagram of the chassis management controller test system provided by an embodiment of the present application, and the system includes: a test device, a chassis management controller test circuit; the chassis management controller test circuit includes: a high-speed connector 1 (i.e., the first high-speed connector mentioned above) and a high-speed connector 2 (i.e., the second high-speed connector mentioned above). The chassis management controller test circuit is connected to the two high-speed connectors of the chassis management controller to be tested through the above two high-speed connectors respectively. In this way, after the chassis management controller test circuit is connected to the chassis management controller to be tested through the high-speed connector, the I2C signal of the chassis management controller to be tested can be introduced into the chassis management controller test circuit, such as the node I2C interaction signal, the PSU interaction signal, the Siwtch interaction signal, the Fan interaction signal, and the like. Based on the above interaction signals, the corresponding node BMC signal data, the Siwtch interaction signal data, the Fan interaction signal data, and the PSU interaction signal data can be obtained, and the chassis management controller to be tested can be tested accordingly.

[0034] Exemplarily, the first test subcircuit also includes: a port physical layer chip; the port physical layer chip is used to convert the Serdes signal received by the first high-speed connector into a medium-dependent interface MDI signal, and forward the MDI signal to the test device through the first node BMC management network port.

[0035] For example, Figure 2As shown, the chassis management controller test circuit provided by the embodiment of the present application has a built-in port physical layer (Physical, PHY) chip and an RJ45 network port (i.e., the first node BMC management network port mentioned above), and the Serdes signal led out by the chassis management controller to be tested is connected to the PHY chip of the chassis management controller test circuit, converted into an MDI signal through the PHY chip, and communicated with the test equipment through the RJ45 network port of the chassis management controller test circuit. When testing, the ping command is used to ping the IP address obtained from the test LAN by the node BMC management network port of the chassis management controller to be tested, and whether the Serdes signal led out by the chassis management controller to be tested is normal is determined by whether the IP address can be pinged through.

[0036] Exemplarily, the I2C interaction unit includes: a first electrically erasable programmable read-only memory EEPROM storing the node BMC signal data, a second EEPROM storing the Siwtch interaction signal data, a third EEPROM storing the Fan interaction signal data, and an I2C master register. The I2C master register is used to forward the node BMC signal data, the Siwtch interaction signal data, and the Fan interaction signal data to the chassis management controller to be tested through the second high-speed connector after receiving the I2C test instruction.

[0037] For example, Figure 2 As shown, the chassis management controller test circuit provided in the embodiment of the present application links the node I2C signal, Siwtch interaction signal, and Fan interaction signal derived from the chassis management controller to be tested through a built-in electrically erasable programmable read only memory (EEPROM) chip.

[0038] For example, Figure 3 As shown, it is a schematic diagram of the I2C channel detection process provided by the embodiment of the present application. During the test, the serial port header of the chassis management controller to be tested is used to execute the I2C device scan command, which is: i2c-test -b$index–scan. Whether the I2C interaction channel with the chassis management controller is normal is determined by whether the EEPROM (including EEPROM1, EEPROM2, and EEPROM3) corresponding to the I2C (including: node I2C, Switch I2C, and fan Fan I2C) of the chassis management controller test circuit can be scanned.

[0039] Exemplarily, the chassis management controller test also includes: a power supply circuit; the power supply circuit is used to test the PSU interaction signal of the chassis management controller to be tested; the power supply circuit includes: a power supply control switch, a power supply connector, and a power supply module of a power supply unit (PSU); the power supply connector is respectively communicated with the power supply control switch and the PSU power supply module; the power supply connector is used to use the power provided by the PSU power supply module to power the first high-speed connector and the second high-speed connector; the power supply control switch is used to control the conduction and closing of the power supply circuit between the power supply connector and the first high-speed connector, and control the conduction and closing of the power supply circuit between the power supply connector and the second high-speed connector; the power supply connector is also used to respond to the PUS information acquisition instruction sent by the chassis management controller to be tested, and obtain the PSU interaction signal data to be obtained by the PUS information acquisition instruction from the PSU power supply module; the power supply connector is also used to send the PSU interaction signal data to the I2C main register, and the I2C The Header master register forwards the PSU interaction signal data to the chassis management controller under test through the second high-speed connector. The chassis management controller test circuit provided in the embodiment of the present application provides 12v_STBY power supply to the chassis management controller under test through a high-speed connector plugged into the chassis management controller under test.

[0040] For example, Figure 2 As shown, the chassis management controller test circuit provided in the embodiment of the present application provides an independently controllable PSU power supply. The chassis management controller test circuit links the PSU interaction signal led out by the chassis management controller provided in the embodiment of the present application to be tested with the PSU power supply module plugged into the chassis management controller test circuit. The test equipment can read the PSU presence and PSU information through the chassis management controller to be tested to realize PSU interaction signal detection. At the same time, the PSU power supply switch in the chassis management controller test circuit provided in the embodiment of the present application can control the power on and off of the chassis management controller test circuit and the chassis management controller.

[0041] For example, Figure 2 As shown, the chassis management controller test circuit provided in the embodiment of the present application also provides an independent fan interface to support an external fan for heat dissipation during testing.

[0042] The chassis management controller testing method provided in the embodiment of the present application is described in detail below through specific embodiments and application scenarios in conjunction with the accompanying drawings.

[0043] like Figure 4As shown, a chassis management controller testing method provided in an embodiment of the present application is applied to a testing device. The method may include the following steps 401 to 403: Step 401: obtain the LAN IP address of the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and execute a network test instruction through the first node BMC management network port of the chassis management controller test circuit to obtain a first test result.

[0044] The network test instruction is used to test whether the first high-speed connector of the chassis management controller test circuit can receive a Serdes signal sent by the chassis management controller to be tested.

[0045] Exemplarily, the test equipment is connected to the CMC management network port of the chassis management controller to be tested through a network cable, and the node BMC management network port of the chassis management controller to be tested is connected to the factory test local area network through the network cable. When the chassis management controller to be tested is tested using the test equipment, the test equipment logs into the CMC management system of the chassis management controller to be tested through the Secure Shell (lSSH) protocol, executes the ipmitool lan print 8 command, and obtains the IP address of the node BMC management network port.

[0046] Afterwards, the RJ45 network port of the chassis management controller test circuit is connected to the designated test equipment and the ping command (the above network test instruction) is used to ping the IP address obtained from the test LAN by the node BMC management network port of the chassis management controller to be tested. Whether the Serdes signal led out by the chassis management controller to be tested is normal is determined by whether the IP address can be pinged through.

[0047] For example, Figure 5 As shown, after starting the test, first determine whether the IP address of the node BMC management interface of the chassis management controller to be tested can be obtained. If so, continue to the next step of the test, otherwise, the test fails and the test ends; after obtaining the IP address of the node BMC management interface, check whether the IP address of the node BMC management interface obtained in the above steps can be pinged. If so, proceed to the next step of the test, otherwise, the test fails and the test ends.

[0048] Step 402: When the first test result indicates that the first high-speed connector can receive the Serdes signal sent by the chassis management controller under test, an I2C test instruction is sent to the chassis management controller under test through the CMC management network port of the chassis management controller under test, and a second test result is obtained.

[0049] The I2C test instruction is used to test whether the chassis management controller to be tested can receive target data; the target data includes: node BMC signal data, selected Siwtch interaction signal data and fan Fan interaction signal data.

[0050] For example, when testing the I2C channel, the test device executes an I2C device scan command in the CMC management system of the chassis management controller to be tested to check whether the I2C interaction signal is normal. Figure 5 As shown, if the I2C interactive signal data is obtained after executing the I2C device scan instruction, the next step of testing can be performed, otherwise, the test fails and ends.

[0051] Step 403: Based on the second test result, determine whether the test of the chassis management controller to be tested is completed.

[0052] Exemplarily, the above step 403 may further include the following steps 403a1 and 403a2: Step 403a1: When the second test result indicates that the chassis management controller under test can receive the target data, a PSU test instruction is sent to the chassis management controller under test through the CMC management network port of the chassis management controller under test, and a third test result is obtained.

[0053] The PSU test instruction is used to test whether the chassis management controller to be tested can receive PSU interaction signal data.

[0054] Step 403a2: When the third test result indicates that the chassis management controller under test can receive the PSU interaction signal data, determine that the chassis management controller under test passes the test, and complete the test of the chassis management controller under test.

[0055] For example, in the embodiment of the present application, it is also necessary to check whether the acquisition of the PSU interaction signal data of the chassis management controller to be tested is normal. Figure 5 As shown, the test equipment executes the PSU in place and PSU information reading instructions out of band to check whether the PSU interaction information is normal. If so, it is determined that the chassis management controller to be tested has passed the test, and the test of the chassis management controller to be tested is completed. Otherwise, the test fails and the test ends.

[0056] In a possible implementation, the chassis management controller testing method provided in the embodiment of the present application may further include the following step 404: Step 404: When the first test result indicates that the first high-speed connector fails to receive the Serdes signal sent by the chassis management controller under test, or the second test result indicates that the chassis management controller under test fails to receive the target data, or the third test result indicates that the chassis management controller under test fails to receive the PSU interaction signal data, it is determined that the chassis management controller under test fails to pass the test.

[0057] Exemplarily, in the embodiment of the present application, the chassis management controller to be tested is tested by accessing the chassis management controller to be tested out of band (OOB). The chassis management controller test circuit provided in the embodiment of the present application can independently control the power on and off of the device, and control the power on and off of the chassis management controller to be tested. The power on and off does not affect the power on and off of the test equipment, so that after the chassis management controller to be tested is tested, the test of the next chassis management controller to be tested can be changed without repeatedly starting the operating system, thereby improving the test efficiency.

[0058] The chassis management controller test method provided in the embodiment of the present application comprises the following steps: first, obtaining the LAN IP address of the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and executing a network test instruction through the first node BMC management network port of the chassis management controller test circuit to obtain a first test result; the network test instruction is used to test whether the first high-speed connector of the chassis management controller test circuit can receive the Serdes signal sent by the chassis management controller to be tested; then, when the first test result indicates that the first high-speed connector can receive the Serdes signal sent by the chassis management controller to be tested, sending an I2C test instruction to the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and obtaining a second test result; the I2C test instruction is used to test whether the chassis management controller to be tested can receive target data; the target data includes: node BMC signal data, Siwtch interaction signal data and fan Fan interaction signal data; finally, judging whether the test of the chassis management controller to be tested is completed based on the second test result. In this way, the test complexity and test cost of the chassis management controller can be reduced.

[0059] It should be noted that the chassis management controller test method provided in the embodiment of the present application can be executed by a test device or a control module in the chassis management controller test device for executing the chassis management controller test method. In the embodiment of the present application, the chassis management controller test device provided in the embodiment of the present application is described by taking the chassis management controller test device executing the chassis management controller test method as an example.

[0060] It should be noted that, in the embodiments of the present application, the chassis management controller test methods shown in the above-mentioned method drawings are all illustrated by taking one of the drawings in the embodiments of the present application as an example. In specific implementation, the chassis management controller test methods shown in the above-mentioned method drawings can also be implemented in combination with any other drawings that can be combined as shown in the above-mentioned embodiments, which will not be repeated here.

[0061] The chassis management controller testing device provided in the present application is described below, and the chassis management controller testing method described below and described above can correspond to each other.

[0062] Figure 6 A schematic diagram of the structure of the chassis management controller test device provided in an embodiment of the present application, such as Figure 6 As shown, specifically including: The information acquisition module 601 is used to obtain the LAN IP address of the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested; the function test module 602 is used to execute a network test instruction through the first node BMC management network port of the chassis management controller test circuit to obtain a first test result; the network test instruction is used to test whether the first high-speed connector of the chassis management controller test circuit can receive the Serdes signal sent by the chassis management controller to be tested; the function test module 602 is also ... In the case of a Serdes signal sent by the chassis management controller to be tested, an I2C test instruction is sent to the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and a second test result is obtained; the I2C test instruction is used to test whether the chassis management controller to be tested can receive target data; the target data includes: node BMC signal data, selected Siwtch interaction signal data and fan Fan interaction signal data; the functional test module 602 is also used to determine whether the test of the chassis management controller to be tested is completed based on the second test result.

[0063] Optionally, the functional testing module 602 is specifically used to send a PSU test instruction to the chassis management controller under test through the CMC management network port of the chassis management controller under test and obtain a third test result when the second test result indicates that the chassis management controller under test can receive the target data; the PSU test instruction is used to test whether the chassis management controller under test can receive PSU interaction signal data; the functional testing module 602 is also specifically used to determine that the chassis management controller under test has passed the test and complete the test of the chassis management controller under test when the third test result indicates that the chassis management controller under test can receive the PSU interaction signal data.

[0064] Optionally, the functional testing module 602 is further used to determine that the chassis management controller under test fails the test when the first test result indicates that the first high-speed connector fails to receive the Serdes signal sent by the chassis management controller under test, or the second test result indicates that the chassis management controller under test fails to receive the target data, or the third test result indicates that the chassis management controller under test fails to receive the PSU interaction signal data.

[0065] The chassis management controller test device provided by the present application first obtains the LAN IP address of the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and executes the network test instruction through the first node BMC management network port of the chassis management controller test circuit to obtain the first test result; the network test instruction is used to test whether the first high-speed connector of the chassis management controller test circuit can receive the Serdes signal sent by the chassis management controller to be tested; then, when the first test result indicates that the first high-speed connector can receive the Serdes signal sent by the chassis management controller to be tested, the I2C test instruction is sent to the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and a second test result is obtained; the I2C test instruction is used to test whether the chassis management controller to be tested can receive the target data; the target data includes: node BMC signal data, selected Siwtch interaction signal data and fan Fan interaction signal data; finally, based on the second test result, it is judged whether the test of the chassis management controller to be tested is completed. In this way, the test complexity and test cost of the chassis management controller can be reduced.

[0066] Figure 7 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 7As shown, the electronic device may include: a processor (processor) 710 , a communication interface (Communications Interface) 720 , a memory (memory) 730 and a communication bus 740 , wherein the processor 710 , the communication interface 720 , and the memory 730 communicate with each other through the communication bus 740 . The processor 710 can call the logic instructions in the memory 730 to execute the chassis management controller test method, which includes: obtaining the local area network IP address of the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and executing the network test instruction through the first node BMC management network port of the chassis management controller test circuit to obtain a first test result; the network test instruction is used to test whether the first high-speed connector of the chassis management controller test circuit can receive the Serdes signal sent by the chassis management controller to be tested; when the first test result indicates that the first high-speed connector can receive the Serdes signal sent by the chassis management controller to be tested, sending an I2C test instruction to the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and obtaining a second test result; the I2C test instruction is used to test whether the chassis management controller to be tested can receive target data; the target data includes: node BMC signal data, selected Siwtch interaction signal data and fan Fan interaction signal data; based on the second test result, judging whether the test of the chassis management controller to be tested is completed.

[0067] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0068] On the other hand, the present application also provides a computer program product, which includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the chassis management controller test method provided by the above methods, and the method includes: obtaining the local area network IP address of the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and executing a network test instruction through the first node BMC management network port of the chassis management controller test circuit to obtain a first test result; the network test instruction is used to test whether the first high-speed connector of the chassis management controller test circuit can receive the a Serdes signal sent by the chassis management controller under test; when the first test result indicates that the first high-speed connector can receive the Serdes signal sent by the chassis management controller under test, sending an I2C test instruction to the chassis management controller under test through the CMC management network port of the chassis management controller under test, and obtaining a second test result; the I2C test instruction is used to test whether the chassis management controller under test can receive target data; the target data includes: node BMC signal data, selected Siwtch interaction signal data and fan Fan interaction signal data; based on the second test result, judging whether the test of the chassis management controller under test is completed.

[0069] On the other hand, the present application also provides a computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to execute the chassis management controller test method provided above, the method comprising: obtaining the local area network IP address of the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and executing a network test instruction through the first node BMC management network port of the chassis management controller test circuit to obtain a first test result; the network test instruction is used to test whether the first high-speed connector of the chassis management controller test circuit can receive the Serdes signal sent by the chassis management controller to be tested. signal; when the first test result indicates that the first high-speed connector can receive the Serdes signal sent by the chassis management controller to be tested, an I2C test instruction is sent to the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and a second test result is obtained; the I2C test instruction is used to test whether the chassis management controller to be tested can receive target data; the target data includes: node BMC signal data, selected Siwtch interaction signal data and fan Fan interaction signal data; based on the second test result, it is determined whether the test of the chassis management controller to be tested is completed.

[0070] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0071] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A chassis management controller test circuit, characterized in that: include: a first test subcircuit and a second test subcircuit; The first test subcircuit is used to test the network function of the chassis management controller to be tested; The second test sub-circuit is used to test the I2C communication function of the chassis management controller to be tested; The first test subcircuit comprises: a first high-speed connector connected to the network path of the chassis management controller to be tested, and a first node BMC management network port connected to the test equipment via a network cable; The second test subcircuit includes: a second high-speed connector connected to the I2C path of the chassis management controller to be tested, and an I2C interaction unit connected to the second high-speed connector via an integrated circuit bus I2C.

2. The test circuit according to claim 1, characterized in that: The first test subcircuit further includes: a port physical layer chip; The port physical layer chip is used to convert the Serdes signal received by the first high-speed connector into a medium-dependent interface MDI signal, and forward the MDI signal to the test equipment through the first node BMC management network port.

3. The test circuit according to claim 1, characterized in that: The I2C interaction unit includes: a first electrically erasable programmable read-only memory EEPROM storing node BMC signal data, a second EEPROM storing Siwtch interaction signal data, a third EEPROM storing Fan interaction signal data, and an I2C master register; The I2C master register is used to forward the node BMC signal data, the Siwtch interaction signal data and the Fan interaction signal data to the chassis management controller to be tested through the second high-speed connector.

4. The test circuit according to claim 3, characterized in that: The chassis management controller test further includes: a power supply circuit; the power supply circuit is used to test the PSU interaction signal of the chassis management controller to be tested; The power supply circuit includes: a power supply control switch, a power supply connector, and a power supply module of a power supply (PSU); the power supply connector is respectively connected to the power supply control switch and the PSU power supply module for communication; The power supply connector is used to use the power provided by the PSU power supply module to supply power to the first high-speed connector and the second high-speed connector; The power supply control switch is used to control the on / off of the power supply circuit between the power supply connector and the first high-speed connector, and to control the on / off of the power supply circuit between the power supply connector and the second high-speed connector.

5. A chassis management controller testing method, characterized in that: Applied to testing equipment, the method comprises: Acquire the LAN IP address of the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and execute a network test instruction through the first node BMC management network port of the chassis management controller test circuit to obtain a first test result; the network test instruction is used to test whether the first high-speed connector of the chassis management controller test circuit can receive the Serdes signal sent by the chassis management controller to be tested; In the case where the first test result indicates that the first high-speed connector can receive the Serdes signal sent by the chassis management controller to be tested, an I2C test instruction is sent to the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and a second test result is obtained; the I2C test instruction is used to test whether the chassis management controller to be tested can receive target data; the target data includes: node BMC signal data, selected Siwtch interaction signal data and fan Fan interaction signal data; Based on the second test result, it is determined whether the test of the chassis management controller to be tested is completed.

6. The method according to claim 5, characterized in that The determining, based on the second test result, whether the test of the chassis management controller to be tested is completed includes: When the second test result indicates that the chassis management controller under test can receive the target data, a PSU test instruction is sent to the chassis management controller under test through the CMC management network port of the chassis management controller under test, and a third test result is obtained; the PSU test instruction is used to test whether the chassis management controller under test can receive the PSU interaction signal data; When the third test result indicates that the chassis management controller under test can receive the PSU interaction signal data, it is determined that the chassis management controller under test passes the test, and the test on the chassis management controller under test is completed.

7. The method according to claim 6, characterized in that The method further comprises: When the first test result indicates that the first high-speed connector fails to receive the Serdes signal sent by the chassis management controller under test, or the second test result indicates that the chassis management controller under test fails to receive the target data, or the third test result indicates that the chassis management controller under test fails to receive the PSU interaction signal data, it is determined that the chassis management controller under test fails to pass the test.

8. A chassis management controller testing device, characterized in that: The device comprises: An information acquisition module, used to acquire the LAN IP address of the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested; A functional test module, configured to execute a network test instruction through a first node BMC management network port of a chassis management controller test circuit to obtain a first test result; the network test instruction is configured to test whether a first high-speed connector of the chassis management controller test circuit can receive a Serdes signal sent by the chassis management controller to be tested; The functional test module is further used to send an I2C test instruction to the chassis management controller to be tested through the CMC management network port of the chassis management controller to be tested, and obtain a second test result when the first test result indicates that the first high-speed connector can receive the Serdes signal sent by the chassis management controller to be tested; the I2C test instruction is used to test whether the chassis management controller to be tested can receive target data; the target data includes: node BMC signal data, selected Siwtch interaction signal data and fan Fan interaction signal data; The functional testing module is further used to determine whether the test of the chassis management controller to be tested is completed based on the second test result.

9. A chassis management controller test system, characterized in that: include: A chassis management controller test circuit and a test device as claimed in any one of claims 1 to 4; the test device is used to execute a chassis management controller test method as claimed in any one of claims 5 to 7.

10. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the chassis management controller testing method according to any one of claims 5 to 7 when executing the program.

11. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the steps of the chassis management controller testing method according to any one of claims 5 to 7 are implemented.

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