Memory control method and storage device

Abstract

The invention provides a memory control method and a storage device. The method comprises the following steps: obtaining first data from a host system; processing the first data into first compressed data through a first compression mechanism; storing the first compressed data and the first compressed information to a first entity unit; collecting second data from a second entity unit; processing the second data into second compressed data through a second compression mechanism, wherein the data compression rate of the second compression mechanism for the second data is higher than the data compression rate of the first compression mechanism for the first data; and storing the second compression data and the second compression information to the third entity unit. Therefore, the capacity of the storage device can be effectively improved, and the service life of the storage device is prolonged.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory control method and a storage device. Background Art

[0002] With the advancement of computer technology and the booming development of artificial intelligence technology, people have higher and higher requirements for the capacity of storage devices. Generally speaking, in order to increase the capacity of a storage device, the capacity of the storage device can be directly expanded (for example, increasing the hard disk space or increasing the number of bits that can be stored per unit hard disk area) or by compressing the data to increase the amount of data that can be stored per unit hard disk area. However, directly expanding the capacity of a storage device will lead to a significant increase in production costs. Therefore, by compressing the data, the effect of controlling costs and increasing the capacity of the storage device can be achieved.

[0003] However, the existing general data compression technology has the problem that the data compression efficiency varies in different operating scenarios, causing serious troubles for developers in product performance evaluation and product development. Summary of the invention

[0004] The present invention provides a memory control method and a memory device, which can improve the above problems.

[0005] The present invention provides a memory control method and a memory device, which can effectively increase the capacity of the memory device and extend the service life of the memory device without increasing the production cost of the memory device by improving the data compression rate used when performing internal data consolidation (such as data migration) on the memory device.

[0006] An embodiment of the present invention provides a memory control method, which is used in a memory module. The memory module includes a plurality of entity units, and the memory control method includes: obtaining first data from a host system; processing the first data into first compressed data through a first compression mechanism, wherein the data volume of the first compressed data is less than the original data volume of the first data; storing the first compressed data and first compression information corresponding to the first compressed data to a first entity unit among the plurality of entity units, wherein the first compression information is related to the first compression mechanism; collecting second data from a second entity unit among the plurality of entity units; processing the second data into second compressed data through a second compression mechanism, wherein the data volume of the second compressed data is less than the original data volume of the second data, and the data compression rate of the second compression mechanism for the second data is higher than the data compression rate of the first compression mechanism for the first data; and storing the second compressed data and second compression information corresponding to the second compressed data to a third entity unit among the plurality of entity units, wherein the second compression information is related to the second compression mechanism.

[0007] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of entity units, and the memory controller is used to: obtain first data from the host system; process the first data into first compressed data through a first compression mechanism, wherein the data volume of the first compressed data is less than the original data volume of the first data; store the first compressed data and first compression information corresponding to the first compressed data to a first entity unit among the plurality of entity units, wherein the first compression information is related to the first compression mechanism; collect second data from a second entity unit among the plurality of entity units; process the second data into second compressed data through a second compression mechanism, wherein the data volume of the second compressed data is less than the original data volume of the second data, and the data compression rate of the second compression mechanism for the second data is higher than the data compression rate of the first compression mechanism for the first data; and store the second compressed data and second compression information corresponding to the second compressed data to a third entity unit among the plurality of entity units, wherein the second compression information is related to the second compression mechanism. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of a host write operation and a data consolidation operation according to an embodiment of the present invention;

[0012] Figure 5 is a schematic diagram of a data compression circuit according to an embodiment of the present invention;

[0013] Figure 6 is a flow chart of a memory control method according to an embodiment of the present invention;

[0014] Figure 7 is a flow chart of a memory control method according to an embodiment of the present invention;

[0015] Figure 8 is a flow chart of a memory control method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0017] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The host system 11 may be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a vehicle-mounted computer. However, the type of the host system 11 is not limited thereto. The storage device 12 may be connected to the host system 11 and may be used to store data. For example, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0018] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. The storage device 12 may communicate with the host system 11 (e.g., exchange signals, instructions, and / or data) via the connection interface 121.

[0019] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0020] The memory module 122 can receive a command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence. For example, when data is to be stored, the memory controller 123 can send a write command sequence to the memory module 122 to instruct the memory module 122 to store the data in a specific storage unit. When data is to be read, the memory controller 123 can send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. When data is to be deleted, the memory controller 123 can send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in the specific storage unit. In addition, the memory controller 123 can also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform corresponding operations, which is not limited by the present invention.

[0021] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be responsible for controlling and / or managing the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In addition, the memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. In one embodiment, the memory controller 123 includes a flash memory controller.

[0022] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, a data compression circuit 23, an encoding circuit 24, and a memory control circuit 25. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] The data compression circuit 23 is used to compress the data to be stored in the memory module 122. The compressed data may have a smaller (or the same) data length (or data amount) to save the storage space of the memory module 122. For example, the data compression circuit 23 may use various data compression algorithms such as Huffman Coding algorithm, LZ4 or Zstandard (Zstd) to perform data compression. The Huffman coding algorithm can assign a binary code with a specific length to a specific symbol according to the frequency of occurrence of the specific symbol in the data to be compressed. For example, a symbol with a relatively high frequency of occurrence can be represented by a shorter length binary code, while a symbol with a relatively low frequency of occurrence can be represented by a longer length binary code, thereby achieving the purpose of data compression. LZ4 is a very fast lossless compression algorithm. Generally speaking, LZ4 can provide a higher data compression and decompression speed. Therefore, LZ4 is quite suitable for storage devices that pursue data access speed. However, compared with the Huffman coding algorithm, LZ4 may have a lower data compression rate for compressed data. Zstd provides an adjustable compression level. For example, when a lower compression level is adopted, the data compression / decompression performance of Zstd is close to that of LZ4; and when a higher compression level is adopted, the data compression / decompression performance of Zstd will be slightly reduced. In addition, Zstd supports multi-threaded compression and decompression. Therefore, Zstd is also quite suitable for storage devices that pursue data access speed. In addition, the data compression circuit 23 can also adopt a dictionary method or other data compression algorithms, which are not limited by the present invention. On the other hand, the data compression circuit 23 can also be used to restore compressed data. For example, the data compression circuit 23 can be used to decompress the compressed data to restore the original data.

[0024] The encoding circuit 24 is used to encode the data to be stored in the memory module 122. For example, the encoding circuit 24 can add an error correction code (ECC) to a certain data to form an ECC frame. This ECC frame can be stored in the memory module 122. When reading data, this ECC frame can be read out and the ECC in this ECC frame can be used to correct the error bits in the corresponding data. For example, the encoding circuit 24 can use a low-density parity check code (LDPC code), a BCH code, a Reed-Solomon code (RScode), an exclusive OR (XOR) code, etc.

[0025] In one embodiment, the data compression circuit 23 may also be included in the encoding circuit 24 or combined with the encoding circuit 24 as a single circuit module. In one embodiment, the data compression circuit 23 may also be implemented by software or firmware, which is not limited by the present invention. In one embodiment, the memory controller 123 may also include a buffer memory, a power management circuit and / or other types of various circuit modules, which are not limited by the present invention. The buffer memory is used to cache data. The power management circuit is used to manage the power supply of the storage device 12.

[0026] The memory control circuit 25 is connected to the host interface 21, the memory interface 22, the data compression circuit 23, and the encoding circuit 24. The memory control circuit 25 can be used to control the whole or part of the operation of the memory controller 123. For example, the memory control circuit 25 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. The memory control circuit 25 can control or instruct the data compression circuit 23 to compress and decompress the data. In addition, the memory control circuit 25 can control or instruct the encoding circuit 24 to encode and decode the data. For example, the memory control circuit 25 may include a control circuit such as an embedded controller or a microcontroller.

[0027] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used to store data in a non-volatile manner.

[0028] In one embodiment, a physical unit may include one or more physical programming units. For example, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 8 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the data capacity of a physical programming unit may be 4 kilobytes (4KB), and the present invention is not limited thereto.

[0029] In one embodiment, a physical programming unit is the minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit can be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to the physical programming unit to change the threshold voltage of at least part of the memory cells in the physical programming unit. The threshold voltage of each memory cell can reflect the bit data stored in the memory cell.

[0030] In one embodiment, a physical erase unit may include a plurality of physical programming units. The plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the plurality of physical programming units in the physical erase unit to change the threshold voltages of at least some of the storage cells in the physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared.

[0031] In one embodiment, the memory controller 123 may logically associate the physical units 301(1)-301(A) with the data area 31 and associate the physical units 301(A+1)-301(B) with the spare area 32. The physical units 301(1)-301(A) in the data area 31 are used to store data (also referred to as user data) from the host system 11. For example, each physical unit in the data area 31 may store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the spare area 32 do not store data (i.e., valid data).

[0032] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In one embodiment, the idle area 32 is also called a free pool. In addition, the physical unit associated with the idle area 32 can be erased to clear the data in the physical unit.

[0033] In one embodiment, when data (i.e., user data) from the host system 11 needs to be stored, the memory controller 123 may select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data from the host system 11 into the selected physical units. At the same time, the selected physical units may be associated with the data area 31.

[0034] In one embodiment, the memory controller 123 may configure a plurality of logical units 302 (1) to 302 (C) to map the physical units 301 (1) to 301 (A) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management unit. A logical unit may be mapped to one or more physical units in the data area 31.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory controller 123 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory controller 123 may determine that the physical unit does not currently store any valid data.

[0036] In one embodiment, the memory controller 123 may record the mapping relationship between the logical unit and the physical unit in a logical-to-physical mapping table. When receiving an access instruction (such as a read instruction, a write instruction, a delete instruction, or other types of instructions) from the host system 11, the memory controller 123 may instruct the memory module 122 to perform a corresponding operation according to the information in the logical-to-physical mapping table.

[0037] Figure 4 is a schematic diagram of a host write operation and a data consolidation operation according to an embodiment of the present invention. Figure 4 , the memory controller 123 may obtain a write instruction from the host system 11. The write instruction may indicate to store data 401. The memory controller 123 may cache the data 401 in the cache area 41 according to the write instruction. For example, the cache area 41 may be located in the memory controller 123. Then, the memory controller 123 may store the data 401 cached in the cache area 41 in the start unit 410. For example, the start unit 410 may include physical units 411(0) to 411(D). For example, the physical units 411(0) to 411(D) may be from Figure 3 The total number of physical units 411(0)-411(D) may be one or more. It should be noted that after the storage device 12 is used for a period of time, the total number of physical units 301(A+1)-301(B) in the idle area 32 will gradually decrease.

[0038] In one embodiment, the memory controller 123 may also perform a data consolidation operation to move valid data from the source physical unit 420 to the target physical unit 430. For example, in the data consolidation operation, the memory controller 123 may collect data 402 from the source physical unit 420 and cache the data 402 in the cache area 42. For example, the source physical unit 420 may include physical units 421(0)-421(E). For example, the physical units 421(0)-421(E) may be from Figure 3 The total number of entity units 421(0) to 421(E) may be multiple. The collected data 402 includes valid data. The cache area 42 may be located in the memory controller 123 or the memory module 122. Then, the memory controller 123 may centrally store the data 402 cached in the cache area 42 in the target entity unit 430. For example, the target entity unit 430 may include entity units 431(0) to 431(F). For example, the entity units 431(0) to 431(F) may be selected from Figure 3 The total number of entity units 431(0)-431(F) may be one or more.

[0039] In particular, in the data consolidation operation, if all valid data stored in the source physical unit 420 has been collected and stored in the target physical unit 430, the source physical unit 420 can be erased and associated or added to the idle area 32 as a new physical unit (also called an idle physical unit). In one embodiment, the data consolidation operation may include a garbage collection (GC) operation. By performing the data consolidation operation, the total number of physical units 301 (A+1) to 301 (B) in the idle area 32 can gradually increase. In one embodiment, the data consolidation operation may also include various operations involving the movement of valid data within the memory module 122, such as a wear leveling operation and / or a bad block replacement operation, which are not limited by the present invention.

[0040] In one embodiment, the memory controller 123 may obtain data (also referred to as first data) from the host system 11. For example, the first data may include Figure 4data 401 in the buffer area 41. After obtaining the first data, the memory controller 123 may process the first data into compressed data (also referred to as first compressed data) through a specific compression mechanism (also referred to as a first compression mechanism). In particular, the data volume of the first compressed data may be smaller than the original data volume of the first data. For example, in the first compression mechanism, the memory controller 123 may instruct the data compression circuit 23 to perform data compression on the data 401 cached in the buffer area 41 based on a specific compression mode (also referred to as a first compression mode) to obtain the compressed first data (i.e., the first compressed data). At the same time, the memory controller 123 may obtain compression information corresponding to the first compressed data (also referred to as the first compression information). The first compression information is related to the first compression mechanism. For example, the first compression information may reflect the data length of the first compressed data and / or the compression mode (i.e., the first compression mode) used in the first compression mechanism to process (e.g., compress) the first data.

[0041] In one embodiment, the memory controller 123 may instruct the memory module 122 to store the first compressed data and the first compressed information in a specific physical unit (also referred to as a first physical unit). For example, the first physical unit may be Figure 4 For example, the first compressed data may be stored in a data area of ​​the first physical unit, and the first compressed information may be stored in an idle area (also called a redundant bit area) of the first physical unit.

[0042] In one embodiment, when reading the first compressed data from the first physical unit, the memory controller 123 may also read the first compression information from the first physical unit. The memory controller 123 may instruct the data compression circuit 23 to decompress the first compressed data according to the first compression information to restore the first data.

[0043] In one embodiment, after obtaining the first compressed data, the memory controller 123 may instruct the encoding circuit 24 to encode the first compressed data to generate an error correction code (also referred to as a first error correction code) corresponding to the first compressed data. In one embodiment, the memory controller 123 may determine or adjust the bit rate of the first error correction code according to the first compression mode. In one embodiment, if the first compression mode (or the data compression algorithm used in the first compression mode) changes, the memory controller 123 may instruct the encoding circuit 24 to adjust the bit rate of the first error correction code accordingly.

[0044] In one embodiment, the memory controller 123 may instruct the memory module 122 to synchronously store the first compressed data, the first compressed information, and the first error correction code in the first physical unit. For example, the first compressed data may be stored in the data area of ​​the first physical unit, and the first compressed information and the first error correction code may be stored in the idle area (i.e., the redundant bit area) of the first physical unit.

[0045] In one embodiment, when reading the first compressed data from the first physical unit, the memory controller 123 may read the first compression information and the first error correction code from the first physical unit. The memory controller 123 may instruct the encoding circuit 24 to decode the read first compressed data based on the first error correction code to correct errors in the read first compressed data. After successfully decoding the first compressed data (i.e., correcting all errors in the read first compressed data), the memory controller 123 may instruct the data compression circuit 23 to decompress the first compressed data according to the first compression information to restore the first data.

[0046] In one embodiment, the memory controller 123 may collect data (also referred to as second data) from at least one physical unit (also referred to as a second physical unit) in the memory module 122. For example, the second physical unit may be Figure 4 At least one of the entity units 421(0) to 421(E) in the embodiment, and the second data may include Figure 4 After obtaining the second data, the memory controller 123 may process the second data into compressed data (also referred to as second compressed data) through a specific compression mechanism (also referred to as a second compression mechanism). In particular, the data volume of the second compressed data may be less than the original data volume of the second data. For example, in the second compression mechanism, the memory controller 123 may instruct the data compression circuit 23 to perform data compression on the data 402 cached in the cache area 42 based on a specific compression mode (also referred to as a second compression mode) to obtain the compressed second data (i.e., the second compressed data). The first compression mode may be different from the second compression mode. For example, the data compression algorithm used in the first compression mode may be different from the data compression algorithm used in the second compression mode. At the same time, the memory controller 123 may obtain compression information corresponding to the second compressed data (also referred to as second compression information). The second compression information is related to the second compression mechanism. For example, the second compression information may reflect the data length of the second compressed data and / or the compression mode used in the second compression mechanism for processing (e.g., compressing) the second data.

[0047] In one embodiment, the data compression rate of the second compression mechanism for the second data (also referred to as the second data compression rate) may be higher than the data compression rate of the first compression mechanism for the first data (also referred to as the first data compression rate). For example, the first data compression rate may reflect (e.g., be positively correlated with) the efficiency of the data compression circuit 23 performing data compression on the first data based on the first compression mode, and the second data compression rate may reflect (e.g., be positively correlated with) the efficiency of the data compression circuit 23 performing data compression on the second data based on the second compression mode. In one embodiment, the second data compression rate is higher than the first data compression rate, indicating that the efficiency of the data compression circuit 23 performing data compression on the second data based on the second compression mode is higher than the efficiency of the data compression circuit 23 performing data compression on the first data based on the first compression mode.

[0048] In one embodiment, the first data compression rate and the second data compression rate can be obtained according to the following formulas (1.1) and (1.2), respectively.

[0049] S(1)=1-(DC(1) / D(1))(1.1)

[0050] S(2)=1-(DC(2) / D(2))(1.2)

[0051] In formulas (1.1) and (1.2), D(1) represents the original data volume of the first data, DC(1) represents the total data volume of the first compressed data, D(2) represents the original data volume of the second data, DC(2) represents the total data volume of the second compressed data, S(1) represents the first data compression rate, and S(2) represents the second data compression rate. It should be noted that formulas (1.1) and (1.2) can also be adjusted according to practical needs, and the present invention is not limited thereto.

[0052] In one embodiment, the memory controller 123 may instruct the memory module 122 to store the second compressed data and the second compressed information in a specific physical unit (also referred to as a third physical unit). For example, the third physical unit may be Figure 4 For example, the second compressed data may be stored in a data area of ​​a third physical unit, and the second compressed information may be stored in an idle area (ie, a redundant bit area) of the third physical unit.

[0053] In one embodiment, when reading the second compressed data from the third physical unit, the memory controller 123 may also read the second compression information from the third physical unit. The memory controller 123 may instruct the data compression circuit 23 to decompress the second compressed data according to the second compression information to restore the second data.

[0054] In one embodiment, after obtaining the second compressed data, the memory controller 123 may instruct the encoding circuit 24 to encode the second compressed data to generate an error correction code (also referred to as a second error correction code) corresponding to the second compressed data. In one embodiment, the memory controller 123 may determine or adjust the bit rate of the second error correction code according to the second compression mode. In one embodiment, if the second compression mode (or the data compression algorithm used in the second compression mode) changes, the memory controller 123 may instruct the encoding circuit 24 to adjust the bit rate of the second error correction code accordingly.

[0055] In one embodiment, the memory controller 123 may instruct the memory module 122 to store the second compressed data, the second compressed information, and the second error correction code synchronously in the third physical unit. For example, the second compressed data may be stored in the data area of ​​the third physical unit, and the second compressed information and the second error correction code may be stored in the idle area (i.e., the redundant bit area) of the third physical unit.

[0056] In one embodiment, when reading the second compressed data from the third physical unit, the memory controller 123 may read the second compression information and the second error correction code from the third physical unit. The memory controller 123 may instruct the encoding circuit 24 to decode the read second compressed data based on the second error correction code to correct errors in the read second compressed data. After successfully decoding the second compressed data (i.e., correcting all errors in the read second compressed data), the memory controller 123 may instruct the data compression circuit 23 to decompress the second compressed data according to the second compression information to restore the second data.

[0057] In one embodiment, the memory controller 123 may control the data compression rate of the second compression mechanism for the second data (i.e., the second data compression rate) to be higher than the data compression rate of the first compression mechanism for the first data (i.e., the first data compression rate). In one embodiment, by controlling the second data compression rate to be higher than the first data compression rate, in addition to performing basic data compression on the data obtained from the host system 11 (i.e., the first data), more efficient data compression may be performed on the data collected from the memory module 122 (i.e., the second data) in the data consolidation operation. Therefore, the storage space of the memory module 122 may be further saved and the service life of the memory module 122 may be extended.

[0058] In one embodiment, since the second data is data collected from the memory module 122, in the worst case, even if a more efficient data compression mode is used to compress the second data, resulting in the second data being damaged or unable to be successfully restored, the second data can still be retrieved from the memory module 122. Therefore, in one embodiment, by further improving the second data compression rate, in addition to further saving the storage space of the memory module 122, the system stability during the operation of the storage device 12 can still be taken into account.

[0059] In one embodiment, the memory controller 123 may determine whether the currently executed data consolidation operation is a foreground data consolidation operation or a background data consolidation operation. For example, the data consolidation operation includes collecting the second data.

[0060] In one embodiment, the memory controller 123 can determine whether the currently executed data consolidation operation is a foreground executed data consolidation operation or a background executed data consolidation operation according to the startup mode of the data consolidation operation. Figure 3 The memory controller 123 may determine that the data consolidation operation currently being executed belongs to the data consolidation operation executed in the foreground if the total number of the physical units 301(A+1)-301(B) in the memory is less than a critical value (also referred to as the first critical value). Alternatively, if the data consolidation operation currently being executed is initiated because the total number of the physical units 301(A+1)-301(B) in the memory is less than another critical value (also referred to as the second critical value), the memory controller 123 may determine that the data consolidation operation currently being executed belongs to the data consolidation operation executed in the background. The first critical value may be different from the second critical value. For example, the first critical value may be higher or lower than the second critical value, depending on practical needs.

[0061] In one embodiment, the memory controller 123 may determine whether the currently executed data consolidation operation belongs to a data consolidation operation executed in the foreground or a data consolidation operation executed in the background according to whether the memory controller 123 (or the memory module 122) is simultaneously executing a data write operation for the host system 11 during the execution of the data consolidation operation. For example, this data write operation is used to store the first data. For example, if the memory controller 123 (or the memory module 122) is simultaneously executing a data write operation for the host system 11 during the execution of the data consolidation operation, the memory controller 123 may determine that the currently executed data consolidation operation belongs to a data consolidation operation executed in the foreground. Alternatively, if the memory controller 123 (or the memory module 122) is not simultaneously executing a data write operation for the host system 11 during the execution of the data consolidation operation, the memory controller 123 may determine that the currently executed data consolidation operation belongs to a data consolidation operation executed in the background.

[0062] In one embodiment, the memory controller 123 may determine whether the currently executed data consolidation operation belongs to a data consolidation operation executed in the foreground or a data consolidation operation executed in the background according to the working state of the storage device 12 during the execution of the data consolidation operation. For example, if the working state of the storage device 12 is a busy state during the execution of the data consolidation operation, the memory controller 123 may determine that the currently executed data consolidation operation belongs to a data consolidation operation executed in the foreground. Alternatively, if the working state of the storage device 12 is an idle state (or a standby state) during the execution of the data consolidation operation, the memory controller 123 may determine that the currently executed data consolidation operation belongs to a data consolidation operation executed in the background.

[0063] In one embodiment, if the currently executed data consolidation operation belongs to the data consolidation operation executed in the foreground, the memory controller 123 may use a certain compression mechanism (also referred to as a first sub-compression mechanism) to compress the second data. In one embodiment, if the currently executed data consolidation operation belongs to the data consolidation operation executed in the background, the memory controller 123 may use another compression mechanism (also referred to as a second sub-compression mechanism) to compress the second data. The compression rate used by the first sub-compression mechanism is different from the compression rate used by the second sub-compression mechanism. For example, the compression rate used by the first sub-compression mechanism may be lower than the compression rate used by the second sub-compression mechanism.

[0064] In one embodiment, by configuring appropriate compression mechanisms for the data consolidation operation executed in the foreground and the data consolidation operation executed in the background, a good balance can be achieved between performing data compression to save storage space and maintaining the working efficiency of the storage device 12. For example, by configuring a compression mechanism with a relatively low compression rate for the data consolidation operation executed in the foreground, it is possible to avoid the data compression performed in the data consolidation operation affecting the working efficiency of the storage device 12 (for example, reducing the host write speed). On the other hand, by configuring a compression mechanism with a relatively high compression rate for the data consolidation operation executed in the background, the storage space used for the executed data consolidation operation can be effectively saved. As a result, the operating stability of the storage device 12 can be effectively improved.

[0065] In one embodiment, the memory controller 123 may control or affect the first data compression rate by setting or changing the data compression algorithm (also referred to as the first data compression algorithm) used by the data compression circuit 23 based on the first compression mode. Similarly, in one embodiment, the memory controller 123 may control or affect the second data compression rate by setting or changing the data compression algorithm (also referred to as the second data compression algorithm) used by the data compression circuit 23 based on the second compression mode.

[0066] In one embodiment, the memory controller 123 may obtain target data. For example, the target data may include at least one of the aforementioned first data and second data. The memory controller 123 may detect the type of the target data. Then, the memory controller 123 may select one of the compression modes (also referred to as candidate compression modes) as the target compression mode according to the type of the target data, so as to process (e.g., compress) the target data based on the target compression mode. For example, each candidate compression mode may correspond to a data compression algorithm, and the plurality of candidate compression modes may correspond to a plurality of different data compression algorithms, respectively. For example, under a certain candidate compression mode, the data compression circuit 23 may use a specific data compression algorithm to process the target data. Under different candidate compression modes, the data compression circuit 23 may use different data compression algorithms to process the target data.

[0067] In one embodiment, assuming that the target data is the first data, the memory controller 123 may select one of the candidate compression modes as the target compression mode according to the type of the first data. Then, in the first compression mechanism, the memory controller 123 may instruct the data compression circuit 23 to use the corresponding data compression algorithm (i.e., the first data compression algorithm) to compress the first data based on the target compression mode (i.e., the first compression mode) to obtain the first compressed data. Alternatively, in one embodiment, assuming that the target data is the second data, the memory controller 123 may select one of the candidate compression modes as the target compression mode according to the type of the second data. Then, in the second compression mechanism, the memory controller 123 may instruct the data compression circuit 23 to use the corresponding data compression algorithm (i.e., the second data compression algorithm) to compress the second data based on the target compression mode (i.e., the second compression mode) to obtain the second compressed data.

[0068] In one embodiment, the type of the target data may reflect that the target data is first-class data or second-class data. If the target data is first-class data, the memory controller 123 may select a candidate compression mode (also referred to as a first candidate compression mode) from the plurality of candidate compression modes as the target compression mode. However, if the target data is second-class data, the memory controller 123 may select another candidate compression mode (also referred to as a second candidate compression mode) from the plurality of candidate compression modes as the target compression mode. The first candidate compression mode may be different from the second candidate compression mode. In addition, the data compression rate of the first candidate compression mode for the target data may be different from the data compression rate of the second candidate compression mode for the target data.

[0069] In one embodiment, the memory controller 123 may determine the type of the target data according to at least one of the data content, purpose, data format, life cycle and data access mode of the target data. In one embodiment, the data content of the target data may reflect at least one of whether a specific string (also referred to as a target string) exists in the target data, the total number of target strings in the target data and the proportion of the target string in the target data. In one embodiment, the target string may be a series of identical numerical combinations (e.g., multiple "0"s or multiple "1"s) or numerical combinations with specific rules (e.g., "01", "010" or "101", etc.). In one embodiment, the target string may be a string with specific meaning or a commonly used string, such as a common word in a text, a common sequence of numbers, a common header mark or a common tail mark, etc.

[0070] In one embodiment, the memory controller 123 may calculate the hash value of one or more strings in the target data, and compare the calculated hash value with a plurality of predetermined hash values. If the hash value of a certain string is the same as a predetermined hash value, the memory controller 123 may determine that the string belongs to the target string. Conversely, if the hash value of a certain string is different from the predetermined hash value, the memory controller 123 may determine that the string does not belong to the target string. In one embodiment, the aforementioned operation of determining the target string by comparing the hash value can effectively improve the efficiency of identifying the target string (including repeated data and / or easily compressed data) in the target data.

[0071] In one embodiment, the purpose of the target data may reflect whether the target data belongs to one of system data, application data, user data, database data, image data and backup data. For example, system data may include operating system (OS), driver, system library, configuration file, log file, etc., which are the basis for maintaining the normal operation of the system (such as host system 11 or storage device 12). Application data may include various applications installed on the host system 11 and their related files (such as executable files, library files, settings files, temporary files, etc.), which are used to implement specific functions or provide services. User data may include various files created, edited, and downloaded by users, such as documents, pictures, music, videos, emails, chat records, browser caches, etc. Database data may include table data, indexes, logs, etc. of relational databases or NoSQL databases, which are used to store and manage structured or semi-structured data. Image data may include virtual machine images, container images, snapshots, etc., which encapsulate the complete operating environment and applications of the system. Backup data may include systems, applications, user data, etc. that are backed up regularly or in real time, which are used for disaster recovery or data migration.

[0072] In one embodiment, the data format of the target data reflects that the target data belongs to one of text data, binary data, database files, structured data, semi-structured data and unstructured data. For example, text data may include plain text files, XML / JSON files, source code, log files, configuration files, etc., which are mainly composed of ASCII or Unicode bits. Binary data may include executable programs, library files, images, audio, video, compressed files, encrypted files, database files, etc., which are stored in binary form. Database files include specific format files of specific database management systems (such as MySQL, PostgreSQL, MongoDB, etc.), which include table structures, indexes and data records, etc. Structured data may include CSV, Excel tables, database tables, etc., in which data is organized according to certain rules for easy query and analysis. Semi-structured data may include XML, JSON, YAML, etc., in which data has a certain structure but is more flexible and is generally used for data exchange and configuration. Unstructured data may include documents, pictures, audio, video, etc., which have no fixed structure and have a large variety of data types and contents.

[0073] In one embodiment, the life cycle of the target data reflects whether the target data is one of temporary data, persistent data and archived data. For example, temporary data may include cache, temporary files, logs, etc. generated when the program is running, which have a short life cycle and are usually cleared after the program exits or the system is restarted. Persistent data may include user documents, database records, and system configurations, which need to be stored for a long time and will not disappear unless the user actively deletes them or the system fails. Archived data may include historical data or backup data that is no longer frequently accessed by users or systems but still needs to be retained, which may be stored in a dedicated storage area or in the cloud.

[0074] In one embodiment, the data access mode of the target data reflects whether the target data belongs to one of sequential access data, random access data, read-intensive data and write-intensive data. For example, sequential access data may include log files, video streams, large data streams that are continuously written, etc., which are usually written or read continuously in chronological order. Random access data may include database records, archives and indexes in archive systems, etc., whose data locations are scattered and whose access patterns have no fixed rules. Read-intensive data may include static resources and database query results on web servers, etc., which are mainly read. Write-intensive data may include log records, transaction records, cache updates, etc., which are mainly written or modified.

[0075] In one embodiment, the memory controller 123 may classify the target data according to the above one or more information related to the target data. Then, the memory controller 123 may select one of the candidate compression modes as the target compression mode according to the classification result (i.e., the type of the target data), and then perform data compression on the target data based on the target compression mode. For example, the target data may refer to the above first data and / or second data.

[0076] In one embodiment, a specific target compression mode is selected according to the type of target data to compress the target data, and the data compression rate corresponding to each type of data can be controlled within a predetermined (or preferred) value range as much as possible. For example, for more important and / or difficult to recover data, the memory controller 123 can control the data compression rate corresponding to this data within a relatively low value range to reduce the probability of errors when the data is subsequently decompressed. Alternatively, for data that is less easy to compress, the memory controller 123 can also control the data compression rate corresponding to this data within a relatively low value range to avoid wasting system resources on invalid data compression of this data. In addition, for less important, easier to compress and / or easier to recover data, the memory controller 123 can control the data compression rate corresponding to this data within a relatively high value range, so as to effectively save the storage space of the memory module 122 by improving the data compression rate without affecting the stability of system operation (such as data access) as much as possible.

[0077] In one embodiment, after obtaining the target data, the memory controller 123 may also determine whether to compress the target data according to at least one of the type of the target data, the source of the target data, and the predetermined storage location of the target data. The type of the target data and the classification basis have been described in detail above and will not be repeated here. The source of the target data may reflect that the target data is obtained from the host system 11 or read from the memory module 122. The predetermined storage location of the target data reflects that the target data will be stored in at least one physical unit in the memory module 122.

[0078] In one embodiment, if at least one of the type of target data, the source of target data, and the predetermined storage location of target data meets a specific condition, the memory controller 123 may determine that the target data needs to be compressed. For example, this specific condition may limit the target data to be a specific type of data (e.g., first type of data or second type of data), the source of the target data to be a specific source (e.g., the host system 11 or the memory module 122), and / or the predetermined storage location of the target data to be a specific physical unit in the memory module 122. In addition, this specific condition may be formulated or adjusted according to practical needs, and the present invention is not limited thereto.

[0079] In one embodiment, if it is determined that the target data needs to be compressed, the memory controller 123 may instruct the data compression circuit 23 to compress the target data. The relevant operation details have been described above and will not be repeated here. However, if at least one of the type of the target data, the source of the target data, and the predetermined storage location of the target data does not meet the specific conditions, the memory controller 123 may determine that the target data does not need to be compressed. It should be noted that if the memory controller 123 can determine that the target data does not need to be compressed, the memory controller 123 can refer to Figure 4 An embodiment of the invention stores target data in a conventional form.

[0080] Figure 5 is a schematic diagram of a data compression circuit according to an embodiment of the present invention. Figure 5 The data compression circuit 23 includes a decision maker 51, a classifier 52 and a compressor 53. After the data 501 (i.e., the target data) is input into the data compression circuit 23, the decision maker 51 can determine whether to compress the data 501. The details of how to determine whether to compress the data 501 have been described above and will not be repeated here.

[0081] In one embodiment, after determining that the data 501 needs to be compressed, the classifier 52 may classify the data 501 and select one of the compression modes 521(1) to 521(G) (i.e., candidate compression modes) as a target compression mode according to the classification result (i.e., the type of the data 501). Then, the compressor 53 may compress the data 501 based on the target compression mode and generate compressed data 502. In one embodiment, the data 501 and the compressed data 502 may be first data and first compressed data, respectively. In one embodiment, the data 501 and the compressed data 502 may be second data and second compressed data, respectively. In one embodiment, if the decision maker 51 determines that the data 501 does not need to be compressed, the data compression circuit 23 may not perform subsequent operations and does not generate compressed data 502.

[0082] In one embodiment, the memory controller 123 may determine whether the type of the target data is compressible data or incompressible data. Then, the memory controller 123 may determine whether to compress the target data and / or based on which compression mode to process (e.g., compress) the target data according to the type of the target data (e.g., compressible data or incompressible data).

[0083] In one embodiment, the compressible data includes uncompressed text files, source code files, database files, log files or multimedia files. Text files usually contain a large number of repeated characters and patterns, such as blank characters, punctuation marks, etc. Common examples include documents (such as .doc, .txt), web page files (such as .html), emails, etc. Source code files usually contain a large number of repeated patterns, such as comments, keywords, etc. Common examples include source code files of programming languages ​​(such as .java, .cpp, .py). Database files usually contain a large number of repeated data items, such as key-value pairs, indexes, etc. Common examples include SQLite database files, MySQL database files, etc. Log files usually contain a large number of repeated patterns, such as date and time stamps, error messages, etc. Common examples include system logs, application logs, etc. Multimedia files include audio and video files, such as .wav, .aiff, etc.

[0084] In one embodiment, incompressible data includes compressed files, encrypted files, binary files, system files, executable files and random data. Compressed files include files that have been compressed, such as .zip, .rar, .gz, etc. These files have been compressed themselves, and the effect of re-compression is usually not obvious or even ineffective. Encrypted files include encrypted files, such as files encrypted using encryption algorithms such as AES and RSA. Encrypted data is usually randomly distributed and has almost no repetitive patterns, so it is difficult to be further compressed. Binary files include multimedia files such as images (such as .jpg, .png), videos (such as .mp4, .avi), and audio (such as .mp3, .mp4a). These files are usually encoded, and although some encoding formats already include certain compression mechanisms, they are usually not recompressible. System files and executable files include operating system files (such as .dll, .exe of Windows), .so, .elf and other files of Linux. These files are usually compiled and linked, and contain machine code or bytecode without obvious repetitive patterns. Random data includes any data that is generated completely randomly, such as random number sequences, the results of certain types of scientific calculations, etc. Random data has no obvious patterns or repetitions, so it is difficult to compress.

[0085] In one embodiment, the memory controller 123 may determine to use a specific compression mode and / or encoding mode to compress and encode the target data according to which of the above multiple data types the target data is. The relevant operation details have been described above and will not be repeated here.

[0086] In one embodiment, the memory controller 123 may store the composite data in a certain physical unit (also referred to as a fourth physical unit) in the memory module 122. For example, the fourth physical unit may include one or more physical programming units. The composite data includes multiple sub-data. The multiple sub-data include incompressible data, data processed by the first compression mechanism, and data processed by the second compression mechanism. In one embodiment, the multiple sub-data are encoded based on different encoding modes. For example, the sub-data encoded by different encoding modes may have different bit rates and / or different encoding characteristics. In other words, in one embodiment, incompressible data, data processed by multiple compression mechanisms, and / or data encoded by different encoding modes may be stored in a single physical page or multiple physical pages, thereby meeting the usage requirements in different operating scenarios.

[0087] In one embodiment, the memory controller 123 may establish a hash table. The hash table is used to record mapping information between logical units and physical units. In one embodiment, the hash table may be used to record at least first mapping information and second mapping information. The first mapping information reflects the mapping relationship between at least one logical unit (also referred to as the first logical unit) to which the compressed data (also referred to as the first target data) belongs and a physical unit (also referred to as the first target physical unit) in the memory module 122. The second mapping information reflects the mapping relationship between at least one logical unit (also referred to as the second logical unit) to which another compressed data (also referred to as the second target data) belongs and another physical unit (also referred to as the second target physical unit) in the memory module 122.

[0088] In one embodiment, the compression rate of the compressed first target data is greater than the compression rate of the compressed second target data, the total number of the first target physical units is the same as the total number of the second target physical units, and the total number of the first target logical units is greater than the total number of the second target logical units. For example, assuming that the compressed first target data belongs to 4 logical units (i.e., the first target logical units, such as LBA(1) to LBA(4)), and the compressed second target data belongs to 2 logical units (i.e., the second target logical units, such as LBA(5) and LBA(6)), the compression rate of the compressed first target data is greater than the compression rate of the compressed second target data. In addition, assuming that the compressed first target data is stored in the first target physical unit (e.g., PBA(1)) and the compressed second target data is stored in the second target physical unit (e.g., PBA(2)), the first mapping information can reflect the mapping relationship between the first target logical unit (e.g., LBA(1) to LBA(4)) and the first target physical unit (e.g., PBA(1)), and the second mapping information can reflect the mapping relationship between the second target logical unit (e.g., LBA(5) and LBA(6)) and the second target physical unit (e.g., PBA(2)).

[0089] In one embodiment, the memory controller 123 may obtain a hash value according to the logical unit to be read (also referred to as the third target logical unit). This hash value may correspond to the third target logical unit. The memory controller 123 may query the hash table according to the hash value to obtain the physical unit mapped by the third target logical unit (also referred to as the third target physical unit). For example, assuming that the third target logical unit is LBA(1) to LBA(4), the memory controller 123 may query the hash table according to the hash value to obtain the physical unit mapped by LBA(1) to LBA(4) (i.e., PBA(1)). Alternatively, assuming that the third target logical unit is LBA(5) and LBA(6), the memory controller 123 may query the hash table according to the hash value to obtain the physical unit mapped by LBA(5) and LBA(6) (i.e., PBA(2)).

[0090] Figure 6 is a flow chart of a memory control method according to an embodiment of the present invention. Figure 6 In step S601, first data is obtained from a host system. In step S602, the first data is processed into first compressed data by a first compression mechanism, wherein the data volume of the first compressed data is less than the original data volume of the first data. In step S603, the first compressed data and first compression information corresponding to the first compressed data are stored in a first entity unit, wherein the first compression information is related to the first compression mechanism.

[0091] Figure 7is a flow chart of a memory control method according to an embodiment of the present invention. Figure 7 In step S701, second data is collected from a second entity unit. In step S702, the second data is processed into second compressed data by a second compression mechanism, wherein the data volume of the second compressed data is less than the original data volume of the second data, and the data compression rate of the second compression mechanism for the second data is higher than the data compression rate of the first compression mechanism for the first data. In step S703, the second compressed data and second compression information corresponding to the second compressed data are stored in a third entity unit, wherein the second compression information is related to the second compression mechanism.

[0092] Figure 8 is a flow chart of a memory control method according to an embodiment of the present invention. Figure 8 In step S801, the target data is obtained. For example, the target data may be Figure 6 The first data or Figure 7 In step S802, the type of the target data is detected. In step S803, one of the candidate compression modes is selected as the target compression mode according to the type of the target data, so as to process the target data based on the target compression mode.

[0093] However, Figures 6 to 8 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figures 6 to 8 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figures 6 to 8 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0094] In summary, the present invention provides a memory control method and a memory device, which can further improve the compression rate of the data read when performing internal data consolidation (such as data migration) on the memory device, compared with the data obtained from the host system. Therefore, the memory control method and the memory device provided by the present invention can effectively increase the capacity of the memory device and extend the service life of the memory device without increasing the production cost of the memory device and without reducing the system operation stability.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method, It is characterized in that For a memory module, wherein the memory module includes a plurality of physical units, and the memory control method includes: Obtaining first data from a host system; Processing the first data into first compressed data by a first compression mechanism, wherein the data volume of the first compressed data is smaller than the original data volume of the first data; storing the first compressed data and first compression information corresponding to the first compressed data in a first entity unit among the plurality of entity units, wherein the first compression information is related to the first compression mechanism; In response to the data consolidation procedure being initiated, collecting second data from a second physical unit among the plurality of physical units; Processing the second data into second compressed data by a second compression mechanism, wherein the data volume of the second compressed data is smaller than the original data volume of the second data, and the data compression rate of the second compression mechanism for the second data is higher than the data compression rate of the first compression mechanism for the first data; and The second compressed data and second compression information corresponding to the second compressed data are stored in a third physical unit among the plurality of physical units, wherein the second compression information is related to the second compression mechanism.

2. The memory control method according to claim 1, further comprising: include: Initiating the data consolidation operation to move valid data from a source physical unit among the plurality of physical units to a target physical unit among the plurality of physical units, The source entity unit includes the second entity unit, and the target entity unit includes the third entity unit.

3. The memory control method according to claim 1, further comprising: include: detecting a type of target data, wherein the target data includes at least one of the first data and the second data; as well as According to the type of the target data, one of the candidate compression modes is selected as a target compression mode to process the target data based on the target compression mode.

4. The memory control method according to claim 3, wherein the step of selecting one of the plurality of candidate compression modes as the target compression mode according to the type of the target data is as follows: include: If the target data is first type data, selecting a first candidate compression mode from the multiple candidate compression modes as the target compression mode; as well as If the target data is the second type of data, selecting a second candidate compression mode from the multiple candidate compression modes as the target compression mode, The data compression rate of the first candidate compression mode for the target data is different from the data compression rate of the second candidate compression mode for the target data.

5. The memory control method according to claim 3, further comprising: include: The type of the target data is determined according to at least one of data content, usage, data format, life cycle, and data access mode of the target data.

6. The memory control method according to claim 5, wherein the data content of the target data reflects at least one of whether a target word string exists in the target data, the total number of the target word strings in the target data, and the proportion of the target word strings in the target data, The purpose of the target data reflects whether the target data belongs to one of system data, application data, user data, database data, image data and backup data. The data format of the target data reflects that the target data belongs to one of text data, binary data, database file, structured data, semi-structured data and unstructured data, The life cycle of the target data reflects whether the target data is one of temporary data, persistent data and archived data, and The data access mode of the target data reflects whether the target data is one of sequential access data, random access data, read-intensive data, and write-intensive data.

7. The memory control method according to claim 1, further comprising: include: Whether to compress the target data is determined according to at least one of the type, source, and predetermined storage location of the target data, wherein the target data includes at least one of the first data and the second data.

8. The memory control method according to claim 1, further comprising: include: The composite data is stored in a fourth physical unit among the plurality of physical units, wherein the composite data includes a plurality of sub-data, and the plurality of sub-data includes incompressible data, data processed by the first compression mechanism, and data processed by the second compression mechanism. 9 . The memory control method according to claim 8 , wherein the plurality of sub-data are encoded based on different encoding modes, respectively.

10. The memory control method according to claim 1, further comprising: include: A hash table is established, wherein the hash table is used to record first mapping information and second mapping information, wherein the first mapping information reflects a mapping relationship between a first logical unit to which the compressed first target data belongs and a first target physical unit among the multiple physical units, and the second mapping information reflects a mapping relationship between a second logical unit to which the compressed second target data belongs and a second target physical unit among the multiple physical units, The compression rate of the compressed first target data is greater than the compression rate of the compressed second target data, the total number of the first target physical units is the same as the total number of the second target physical units, and the total number of the first target logical units is greater than the total number of the second target logical units.

11. A storage device, It is characterized in that include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to: Obtain first data from the host system; Processing the first data into first compressed data by a first compression mechanism, wherein the data volume of the first compressed data is smaller than the original data volume of the first data; storing the first compressed data and first compression information corresponding to the first compressed data in a first entity unit among the plurality of entity units, wherein the first compression information is related to the first compression mechanism; In response to the data consolidation procedure being initiated, collecting second data from a second physical unit among the plurality of physical units; Processing the second data into second compressed data by a second compression mechanism, wherein the data volume of the second compressed data is smaller than the original data volume of the second data, and the data compression rate of the second compression mechanism for the second data is higher than the data compression rate of the first compression mechanism for the first data; as well as The second compressed data and second compression information corresponding to the second compressed data are stored in a third physical unit among the plurality of physical units, wherein the second compression information is related to the second compression mechanism.

12. The storage device according to claim 11, wherein the memory controller is further configured to: Initiating a data consolidation operation to move valid data from a source physical unit among the plurality of physical units to a target physical unit among the plurality of physical units, The source entity unit includes the second entity unit, and the target entity unit includes the third entity unit.

13. The storage device according to claim 11, wherein the memory controller is further configured to: detecting a type of target data, wherein the target data includes at least one of the first data and the second data; and According to the type of the target data, one of the candidate compression modes is selected as a target compression mode to process the target data based on the target compression mode.

14. The storage device according to claim 13, wherein the memory controller selects one of the plurality of candidate compression modes as the target compression mode according to the type of the target data. include: If the target data is first type data, selecting a first candidate compression mode from the multiple candidate compression modes as the target compression mode; as well as If the target data is the second type of data, selecting a second candidate compression mode from the multiple candidate compression modes as the target compression mode, The data compression rate of the first candidate compression mode for the target data is different from the data compression rate of the second candidate compression mode for the target data.

15. The storage device according to claim 13, wherein the memory controller is further configured to: The type of the target data is determined according to at least one of data content, usage, data format, life cycle, and data access mode of the target data.

16. The storage device according to claim 15, wherein the data content of the target data reflects at least one of whether a target word string exists in the target data, the total number of the target word strings in the target data, and the proportion of the target word strings in the target data, The purpose of the target data reflects whether the target data belongs to one of system data, application data, user data, database data, image data and backup data. The data format of the target data reflects whether the target data is one of text data, binary data, database file, structured data, semi-structured data and unstructured data. The life cycle of the target data reflects whether the target data is one of temporary data, persistent data and archived data, and The data access mode of the target data reflects whether the target data is one of sequential access data, random access data, read-intensive data, and write-intensive data.

17. The storage device according to claim 11, wherein the memory controller is further configured to: Whether to compress the target data is determined according to at least one of the type, source, and predetermined storage location of the target data, wherein the target data includes at least one of the first data and the second data.

18. The storage device according to claim 11, wherein the memory controller is further configured to: The composite data is stored in a fourth physical unit among the plurality of physical units, wherein the composite data includes a plurality of sub-data, and the plurality of sub-data includes incompressible data, data processed by the first compression mechanism, and data processed by the second compression mechanism. The storage device according to claim 18 , wherein the plurality of sub-data are encoded based on different encoding modes, respectively.

20. The storage device according to claim 11, wherein the memory controller is further configured to: A hash table is established, wherein the hash table is used to record first mapping information and second mapping information, wherein the first mapping information reflects a mapping relationship between a first logical unit to which the compressed first target data belongs and a first target physical unit among the multiple physical units, and the second mapping information reflects a mapping relationship between a second logical unit to which the compressed second target data belongs and a second target physical unit among the multiple physical units, The compression rate of the compressed first target data is greater than the compression rate of the compressed second target data, the total number of the first target physical units is the same as the total number of the second target physical units, and the total number of the first target logical units is greater than the total number of the second target logical units.

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