Heterogeneous CPU cluster resource allocation method, electronic device and medium

Abstract

The present invention relates to the field of chip technology, and in particular to a heterogeneous CPU cluster resource allocation method, electronic device and medium, the method comprising: step S1, constructing a first database, the first database being used to store basic information of each CPU in the heterogeneous CPU cluster; step S2, based on the first database, running the test cases in the test case sample set of each IP to be tested in the chip regression test to be run under different heterogeneous CPU combination modes, generating a second database; step S3, constructing a third database, the third database being used to store resource utilization information of each CPU in the heterogeneous CPU cluster during the chip regression test running process; step S4, allocating CPU computing resources of the heterogeneous CPU cluster to each IP to be tested in the chip regression test to be run based on the information of the first database, the second database and the third database. The present invention improves the efficiency of chip regression testing.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a heterogeneous CPU cluster resource allocation method, electronic equipment and medium. Background Art

[0002] During the chip regression test, simulation verification is mainly divided into three stages: the first stage compiles the common library written in high-level languages ​​such as C++ and C; the second stage compiles the IP (Intellectual Property) of different forms of chip design; the third stage will build test cases (test) corresponding to each IP form for regression testing. Some test cases are written based on SystemVerilog, and some test cases are written based on related codes of high-level languages ​​such as C++ and C. The operation of the test cases in the third stage needs to be linked to the common library in the first stage. All the tasks involving calculations in the above three stages will be distributed to the heterogeneous CPU (Central Processing Unit) cluster for execution. Heterogeneous CPU cluster refers to a CPU cluster composed of different CPUs, and different CPUs refer to CPUs with different instruction sets and / or compilers. In the prior art, all the tasks involving calculations in the above three stages are directly assigned to the heterogeneous CPU cluster for execution, but memory out-of-bounds, pointer offset, etc. often occur, resulting in simulation failure. When the simulation fails, the prior art cannot clearly identify the cause of the simulation failure, but adopts the method of re-starting the execution from the first stage to solve it, resulting in low efficiency of chip regression testing. Summary of the invention

[0003] The present invention aims to provide a heterogeneous CPU cluster resource allocation method, electronic equipment and medium, thereby improving chip regression test efficiency.

[0004] According to a first aspect of the present invention, a method for allocating resources in a heterogeneous CPU cluster is provided, comprising:

[0005] Step S1, constructing a first database, wherein the first database is used to store basic information of each CPU in the heterogeneous CPU cluster, and the first database is updated in real time;

[0006] Step S2, based on the test cases in the test case sample set of each IP to be tested in the chip regression test to be run under different heterogeneous CPU combination modes, the first database generates a second database, wherein the second database is used to store the running results of each IP to be tested under different heterogeneous CPU combination modes, the chip regression test to be run is a regression test including test cases written in a preset high-level language, and each IP to be tested corresponds to a form of an IP in the chip regression test to be run;

[0007] Step S3, constructing a third database, wherein the third database is used to store resource utilization information of each CPU in the heterogeneous CPU cluster during the chip regression test operation, and the third database is updated in real time;

[0008] Step S4: Allocate CPU computing resources of a heterogeneous CPU cluster to each IP to be tested in the chip regression test to be executed based on the information in the first database, the second database, and the third database.

[0009] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the heterogeneous CPU cluster resource allocation method, electronic device and medium provided by the present invention can achieve considerable technical advancement and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:

[0012] The present invention can obtain basic information of each CPU in a heterogeneous CPU cluster from a constructed first database, obtain the operation results of each IP to be tested under different heterogeneous CPU combination modes from a second database, and obtain resource utilization information of each CPU in the heterogeneous CPU cluster from a third database. Based on the information of the first database, the second database and the third database, CPU computing resources of the heterogeneous CPU cluster are allocated to each IP to be tested in the chip regression test to be run, which greatly reduces the occurrence of simulation failures in the chip regression test process and improves the chip regression test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flow chart of a heterogeneous CPU cluster resource allocation method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a method for allocating resources of a heterogeneous CPU cluster. Figure 1 As shown, including:

[0017] Step S1, constructing a first database, wherein the first database is used to store basic information of each CPU in a heterogeneous CPU cluster, and the first database is updated in real time.

[0018] Among them, a heterogeneous CPU cluster refers to a CPU cluster composed of different CPUs. The basic information of the CPU includes a category identifier, a version identifier, and the total number of CPU computing resources, and the category identifier includes a first category identifier and a second category identifier. It should be noted that CPUs from the same manufacturer with the same CPU instruction set and compiler have the same version identifier. The addition, reduction or replacement of CPUs in a heterogeneous CPU cluster will result in changes in the basic information of the CPUs in the heterogeneous CPU cluster. When the CPUs in the heterogeneous CPU cluster are updated, the information in the first database is updated in real time. CPU computing resources include CPU cores.

[0019] Step S2, based on the test cases in the test case sample set of each IP to be tested in the chip regression test to be run under different heterogeneous CPU combination modes, generate a second database, the second database is used to store the running results of each IP to be tested under different heterogeneous CPU combination modes, the chip regression test to be run is a regression test including test cases written in a preset high-level language, and each IP to be tested corresponds to a form of an IP in the chip regression test to be run.

[0020] It should be noted that regression testing, including test cases written in preset high-level languages, is sensitive to the processing of heterogeneous CPUs. Some test cases may not be compatible with CPUs of different structures executing different stages of the test process, resulting in simulation failure. In the prior art, the problem of simulation failure is usually solved by directly re-running. During the re-running process, the allocated CPU resources may or may not meet the requirements of the test cases, and multiple re-runs are required. The embodiment of the present invention obtains the running results of each IP to be tested in the chip regression test to be run in different heterogeneous CPU combination modes in advance before re-running, and allocates CPU resources in the heterogeneous CPU cluster to each IP to be tested more accurately according to the running results, thereby reducing the occurrence of simulation failures in regression testing and improving the efficiency of chip regression testing. Among them, the preset high-level language is specifically C++, C language, etc.

[0021] The chip regression test to be run is a regression test including test cases written in a preset high-level language. Since the test cases involving only SystemVerilog will not be affected by heterogeneous CPU resources, the heterogeneous CPU cluster resource allocation process of the embodiment of the present invention only needs to be executed for the regression test including test cases written in a preset high-level language.

[0022] Step S3: construct a third database, wherein the third database is used to store resource utilization information of each CPU in the heterogeneous CPU cluster during the chip regression test operation, and the third database is updated in real time.

[0023] Step S4: Allocate CPU computing resources of a heterogeneous CPU cluster to each IP to be tested in the chip regression test to be executed based on the information in the first database, the second database, and the third database.

[0024] It should be noted that, based on the basic information of each CPU in the heterogeneous CPU cluster in the first database, the operating results of each IP to be tested in different heterogeneous CPU combination modes in the second database, and the resource utilization information of each CPU in the heterogeneous CPU cluster during the chip regression test in the third database, it is possible to comprehensively consider the CPU computing resources required for each IP to be tested and the implementation of CPU computing resources in the CPU cluster to more reasonably allocate CPU computing resources to each IP to be tested, reduce the occurrence of simulation failures in regression testing, and improve the efficiency of chip regression testing.

[0025] The chip regression test includes a first stage, a second stage and a third stage. The first stage is used to compile a common library, the second stage is used to compile IPs of different forms of chip design, and the third stage is used to construct test cases corresponding to each IP form for regression testing. The third stage depends on the first stage. Both the first stage and the third stage may involve processing of a preset high-level language. Therefore, the operation of the first stage and the third stage is affected by heterogeneous CPU resource allocation. The second stage does not involve processing of a preset high-level language, and the operation of the second stage is not affected by heterogeneous CPU resource allocation.

[0026] As an embodiment, step S2 includes:

[0027] Step S21: construct a test case sample set for each IP to be tested in the chip regression test to be run, wherein the test case sample set includes test cases of different complexity levels corresponding to each IP to be tested.

[0028] It should be noted that, in the initial state, test cases of different complexity levels corresponding to the IP to be tested can be set in the test case sample set of the IP to be tested to meet the training requirements of different complexity levels. With the subsequent running of regression tests, the test case sample set can be further improved according to the running results of the regression tests to improve the accuracy of obtaining the running results of each IP to be tested in different heterogeneous CPU combination modes.

[0029] Step S22: construct different heterogeneous CPU combination modes based on the first database, where the heterogeneous CPU combination modes include a first combination mode, a second combination mode and a third combination mode.

[0030] The first combination mode allocates CPU computing resources with a specified version identifier of the first category identifier in the first stage, and allocates CPU computing resources with a random version identifier of the first category identifier in the third stage; the second combination mode allocates CPU computing resources with a specified version identifier of the second category identifier in the first stage, and allocates CPU computing resources with a random version identifier of the second category identifier in the third stage; the third combination mode allocates CPU computing resources with a random version identifier of the first category identifier in the first stage, and allocates CPU computing resources with a random version identifier of the second category identifier in the third stage.

[0031] It should be noted that the first combination pattern covers the combination of CPU computing resources of different versions of the first category identification, the second combination pattern covers the combination of CPU computing resources of different versions of the second category identification, and the third combination pattern covers the combination of CPU computing resources of the first category identification and the second category identification.

[0032] Step S23: If all test cases in the test case sample set of the IP to be tested are successfully executed in the heterogeneous CPU combination mode, the running result of the IP to be tested in the heterogeneous CPU combination mode is feasible; otherwise, the running result of the IP to be tested in the heterogeneous CPU combination mode is infeasible.

[0033] Step S24: Generate the second database based on the operation results of each IP to be tested in different heterogeneous CPU combination modes.

[0034] As an embodiment, the step S4 further includes;

[0035] Step S5: If there is a test case of the IP to be tested that fails to run, the test case of the IP to be tested that fails to run is added to the test case sample set corresponding to the IP to be tested.

[0036] It should be noted that after the test case sample set is updated, step S2 can be re-executed to update the second database in real time, thereby continuously improving the accuracy of the running results of the IP to be tested in the second database in the heterogeneous CPU combination mode.

[0037] As an embodiment, step S4 includes:

[0038] Step S41: If the corresponding operation result of the IP to be tested in the third combination mode is feasible, execute step S42; otherwise, execute step S43.

[0039] Step S42: randomly allocate CPU computing resources of the heterogeneous CPU cluster to the first and third phases corresponding to the IP to be tested, and execute step S47.

[0040] It should be noted that if the corresponding running result of the IP to be tested in the third combination mode is feasible, it means that the IP to be tested will not be affected by the CPU computing resource allocation of the heterogeneous CPU cluster. Therefore, the CPU computing resources of the heterogeneous CPU cluster can be randomly allocated to the first and third stages corresponding to the IP to be tested.

[0041] Step S43: If the operating results of the IP to be tested in the first combination mode and the second combination mode are both feasible, execute step S44; if only one operating result is feasible, execute step S45; if all operating results are infeasible, execute step S46.

[0042] Step S44, randomly assign CPU computing resources with the same category identifier to the first and third stages corresponding to the IP to be tested, and execute step S47.

[0043] It should be noted that if the operating results of the IP to be tested in the first combination mode and the second combination mode are both feasible, it means that the IP to be tested will not be affected by the allocation of CPU computing resources of different versions under the same type of CPU. Therefore, the CPU computing resources with the first category of identification can be randomly allocated to the first and third stages corresponding to the IP to be tested, and the CPU computing resources with the second category of identification can also be randomly allocated to the first and third stages corresponding to the IP to be tested.

[0044] Step S45, randomly assigning CPU computing resources with feasible category identifiers as the running results for the first and third phases corresponding to the IP to be tested, and executing step S47.

[0045] It should be noted that if the operating results of the IP to be tested are feasible only in one of the first combination mode and the second combination mode, it means that the IP to be tested will not be affected by the allocation of CPU computing resources of the CPU type corresponding to the combination modes in which the operating results are all feasible. Therefore, it is necessary to randomly allocate CPU computing resources with category identifiers with feasible operating results for the first and third stages corresponding to the IP to be tested.

[0046] Step S46, allocate CPU computing resources with the same category identifier and version identifier to the first stage and the third stage corresponding to the IP to be tested, and execute step S47.

[0047] It should be noted that if the operating results of the IP under test in the first combination mode and the second combination mode are both infeasible, it means that the IP under test will be affected by the allocation of CPU computing resources of any heterogeneous CPU type. Therefore, it is necessary to allocate CPU computing resources with the same category identifier and version identifier for the first and third stages corresponding to the IP under test.

[0048] Step S47, determine whether all the IPs to be tested in the chip regression test to be run are allocated CPU computing resources, if so, end the process, otherwise, return to step S41.

[0049] As an embodiment, in order to further improve the efficiency of regression testing, the CPU resource utilization information includes the current number of available CPU computing resources and the current CPU load rate. In step S42, step S44 and step S45, among the optional CPU computing resources, the CPU computing resources are evenly allocated based on the current number of available CPU computing resources and the current CPU load rate. That is, when randomly selecting CPU computing resources, the balance of CPU computing resources is ensured as much as possible.

[0050] As an embodiment, step S46 includes:

[0051] Step S461, in the first phase of the IP to be tested, obtain a CPU whose available CPU computing resources of the current CPU meet the first phase requirements of the IP to be tested. If there is a CPU, execute step S462, otherwise, execute step S463.

[0052] Step S462, select the CPU with the lowest current CPU load rate as the first target CPU from the CPUs that meet the first stage requirements of the IP to be tested, allocate the first target CPU to the first stage of the IP to be tested, and execute step S464.

[0053] Step S463: Select the CPU with the lowest current CPU load rate as the first target CPU, allocate the first target CPU to the first stage of the IP to be tested, and execute step S464.

[0054] Step S464: In the third stage of the IP to be tested, determine whether there is a CPU whose available CPU computing resources meet the third stage requirements of the IP to be tested and whose category identifier and version identifier are the same as those of the first target CPU. If so, execute step S465; otherwise, execute step S466.

[0055] Step S465: Select the CPU with the lowest current CPU load rate from the CPUs whose available CPU computing resources meet the third stage requirements of the IP to be tested and whose category identifier and version identifier are the same as those of the first target CPU as the CPU to be allocated to the third stage of the IP to be tested.

[0056] Step S466: Select a CPU with the lowest current CPU load rate and the same category identifier and version identifier as the first target CPU and allocate it to the third stage of the IP to be tested.

[0057] It should be noted that, through steps S461 to S466, the number of CPU computing resources and the CPU load rate are comprehensively considered to allocate CPU computing resources with the same category identifier and version identifier to the IP under test in the first and third stages, which can not only improve the efficiency of regression testing, but also ensure load balancing and improve the overall performance of the system.

[0058] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0059] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0060] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0061] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A method for allocating resources in a heterogeneous CPU cluster, characterized in that: include: Step S1, constructing a first database, wherein the first database is used to store basic information of each CPU in the heterogeneous CPU cluster, and the first database is updated in real time; Step S2, based on the test cases in the test case sample set of each IP to be tested in the chip regression test to be run under different heterogeneous CPU combination modes, the first database generates a second database, wherein the second database is used to store the running results of each IP to be tested under different heterogeneous CPU combination modes, the chip regression test to be run is a regression test including test cases written in a preset high-level language, and each IP to be tested corresponds to a form of an IP in the chip regression test to be run; Step S3, constructing a third database, wherein the third database is used to store resource utilization information of each CPU in the heterogeneous CPU cluster during the chip regression test operation, and the third database is updated in real time; Step S4, the chip regression test includes a first stage, a second stage and a third stage. Based on the information of the first database, the second database and the third database, and according to the running results of each IP to be tested in different heterogeneous CPU combination modes, the CPU computing resources of the heterogeneous CPU cluster are allocated to the first stage, the second stage and the third stage corresponding to each IP to be tested in the chip regression test to be run; The first stage is used to compile the common library, the second stage is used to compile IPs of different forms of chip design, the third stage is used to build test cases corresponding to each IP form for regression testing, the third stage depends on the first stage, the operation of the first stage and the third stage is affected by heterogeneous CPU resource allocation, and the operation of the second stage is not affected by heterogeneous CPU resource allocation; The step S4 comprises: Step S41: If the operation result corresponding to the IP to be tested in the third combination mode is feasible, execute step S42; otherwise, execute step S43; Step S42, randomly allocating CPU computing resources of the heterogeneous CPU cluster to the first stage and the third stage corresponding to the IP to be tested, and executing step S47; Step S43: If the operation results of the IP to be tested in the first combination mode and the second combination mode are both feasible, then execute step S44; if only one of the operation results is feasible, then execute step S45; if the operation results are all infeasible, then execute step S46; Step S44, randomly assigning CPU computing resources with the same category identifier to the first and third phases corresponding to the IP to be tested, and executing step S47; Step S45, randomly assigning CPU computing resources with feasible category identifiers as the running results for the first and third phases corresponding to the IP to be tested, and executing step S47; Step S46, allocating CPU computing resources with the same category identifier and version identifier to the first stage and the third stage corresponding to the IP to be tested, and executing step S47; Step S47, determine whether all the IPs to be tested in the chip regression test to be run are allocated CPU computing resources, if so, end the process, otherwise, return to step S41.

2. The method according to claim 1, characterized in that The basic information of the CPU includes a category identifier, a version identifier, and the total number of CPU computing resources. The category identifier includes a first category identifier and a second category identifier.

3. The method according to claim 2, characterized in that The step S2 comprises: Step S21, constructing a test case sample set for each IP to be tested in the chip regression test to be run, wherein the test case sample set includes test cases of different complexity levels corresponding to each IP to be tested; Step S22: construct different heterogeneous CPU combination modes based on the first database, where the heterogeneous CPU combination modes include a first combination mode, a second combination mode, and a third combination mode; The first combination mode is to allocate CPU computing resources with a specified version identifier of the first category in the first stage, and allocate CPU computing resources with a random version identifier of the first category in the third stage; the second combination mode is to allocate CPU computing resources with a specified version identifier of the second category in the first stage, and allocate CPU computing resources with a random version identifier of the second category in the third stage; the third combination mode is to allocate CPU computing resources with a random version identifier of the first category in the first stage, and allocate CPU computing resources with a random version identifier of the second category in the third stage; Step S23: If all test cases in the test case sample set of the IP to be tested are successfully run in the heterogeneous CPU combination mode, the running result of the IP to be tested in the heterogeneous CPU combination mode is feasible; otherwise, the running result of the IP to be tested in the heterogeneous CPU combination mode is infeasible; Step S24: Generate the second database based on the operation results of each IP to be tested in different heterogeneous CPU combination modes.

4. The method according to claim 3, characterized in that After the step S4 also includes; Step S5: If there is a test case of the IP to be tested that fails to run, the test case of the IP to be tested that fails to run is added to the test case sample set corresponding to the IP to be tested.

5. The method according to claim 1, characterized in that: The CPU resource utilization information includes the current number of available CPU computing resources and the current CPU load rate. In steps S42, S44 and S45, the CPU computing resources are evenly allocated among the optional CPU computing resources based on the current number of available CPU computing resources and the current CPU load rate.

6. The method according to claim 1, characterized in that The step S46 comprises: Step S461, in the first stage of the IP to be tested, obtain a CPU whose available CPU computing resources of the current CPU meet the requirements of the first stage of the IP to be tested. If there is a CPU, execute step S462, otherwise, execute step S463; Step S462, select the CPU with the lowest current CPU load rate from the CPUs that meet the first stage requirements of the IP to be tested as the first target CPU, allocate the first target CPU to the first stage of the IP to be tested, and execute step S464; Step S463, select the CPU with the lowest current CPU load rate as the first target CPU, allocate the first target CPU to the first stage of the IP to be tested, and execute step S464; Step S464, in the third stage of the IP to be tested, determine whether there is a CPU whose available CPU computing resources meet the third stage requirements of the IP to be tested and whose category identifier and version identifier are the same as those of the first target CPU. If so, execute step S465; otherwise, execute step S466; Step S465, selecting a CPU with the lowest current CPU load rate from the CPUs whose available CPU computing resources meet the requirements of the third stage of the IP to be tested and whose category identifier and version identifier are the same as those of the first target CPU as the CPU to be allocated to the third stage of the IP to be tested; Step S466: Select a CPU with the lowest current CPU load rate and the same category identifier and version identifier as the first target CPU and allocate it to the third stage of the IP to be tested.

7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method according to any one of the preceding claims 1-6.

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