A test case reuse system for hardware accelerator platform

Abstract

The present invention relates to the field of chip design, and in particular to a test case reuse system for a hardware accelerator platform, which comprises a first system to be tested, a first high-speed interface and a simulator, wherein the simulator is connected to the first system to be tested via the first high-speed interface; the system also comprises a second system to be tested, a second high-speed interface and an emulator, wherein the emulator is connected to the second system to be tested via the second high-speed interface; the system also comprises a first module and a second module, wherein the first module comprises a test case library and a test interface, the second module comprises an intermediate layer and an interactive interface, the test case library is connected to the test interface, the test interface is respectively connected to the first high-speed interface and the intermediate layer, and the intermediate layer is connected to the second high-speed interface via the interactive interface; the embodiment of the present invention realizes the reuse of test cases and shortens the verification cycle at the same time.

Description

Technical Field

[0001] The invention relates to the field of chip design, and in particular to a test case reuse system for a hardware accelerator platform. Background Art

[0002] A hardware acceleration platform is a computer system that contains specialized hardware designed to accelerate specific types of computing tasks. These hardware are often called accelerators and can be graphics processing units (GPUs), field programmable gate arrays (FPGAs), or application-specific integrated circuits (ASICs). The goal of a hardware acceleration platform is to increase computing speed while keeping power consumption low, especially when processing large amounts of data or complex mathematical operations.

[0003] The traditional hardware acceleration platform consists of two systems under test, each of which has its own memory (MEM) and PCI Express (PCIE) interface. The two systems under test are connected to a hardware accelerator through the PCIE interface. The accelerator is divided into two parts: the simulator (Simu) and the emulator (EMU). The simulator (Simu) and the emulator (EMU) are both parts of the hardware accelerator, and each has its own test case library (Testcase Lib). For the simulator (Simu), the test cases in its test case library are sent to the simulator (Simu) through the PCIE interface after passing through the test interface (test API). For the emulator (EMU), the test cases in its test case library are sent to the emulator (EMU) through the PCIE interface after passing through the kernel driver (KernelDriver). Since the test case library of the emulator (Simu) is written by hardware engineers, and the test case library of the emulator (EMU) is written by software engineers, the hardware engineers and software engineers focus on different aspects, and the details of the written test cases are different, resulting in the inability to reuse test cases, slowing down the verification process and causing a long verification cycle. Summary of the invention

[0004] In response to the above technical problems, the technical solution adopted by the present invention is: a test case reuse system for a hardware accelerator platform, the system comprising a first system to be tested, a first high-speed interface and a simulator, wherein the simulator is connected to the first system to be tested via the first high-speed interface.

[0005] The system further includes a second system under test, a second high-speed interface and a simulator, wherein the simulator is connected to the second system under test via the second high-speed interface.

[0006] The system also includes a first module and a second module, wherein the first module includes a test case library and a test interface, and the second module includes an intermediate layer and an interactive interface, the test case library is connected to the test interface, the test interface is respectively connected to the first high-speed interface and the intermediate layer, and the intermediate layer is connected to the second high-speed interface through the interactive interface.

[0007] When reusing test cases, the test cases in the test case library call the test interface and send it to the first high-speed interface or the middle layer; when the middle layer receives the call of the test case, it sends the call of the test case to the second high-speed interface through the interactive interface.

[0008] The present invention has at least the following beneficial effects:

[0009] The embodiment of the present invention provides a test case reuse system for a hardware accelerator platform, which enables the test case to maintain consistent calls in the simulator and the emulator through an intermediate layer, thereby realizing the reuse of test cases, improving the flexibility and efficiency of the test, and shortening the verification cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0011] Figure 1 A block diagram of a test case reuse system for a hardware accelerator platform provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0013] See also Figure 1 , which shows a test case reuse system for a hardware accelerator platform, the system comprising a first system to be tested, a first high-speed interface and a simulator, wherein the simulator is connected to the first system to be tested via the first high-speed interface.

[0014] The first system to be tested is a simulated target system.

[0015] Optionally, the first system to be tested is a SOC (System on Chip) system, a microprocessor or a multi-chip module. The SOC system at least includes a processor core, a memory subsystem, an input / output interface, etc. Other types of first systems to be tested also fall within the protection scope of the present invention.

[0016] Optionally, the processor core is a CPU, a GPU, a digital signal processor (DSP) and / or other types of processors. Other types of processor cores also fall within the protection scope of the present invention.

[0017] The memory subsystem includes different types of memories. Optionally, the memory is SRAM (static random access memory), DRAM (dynamic random access memory) or ROM (read-only memory). Other types of memories also fall within the protection scope of the present invention.

[0018] Among them, the high-speed interface is a channel for data transmission between the system under test and the simulator.

[0019] Optionally, the high-speed interface adopts the PCIe (Peripheral Component Interconnect Express) standard. High-speed interfaces that comply with other standards fall within the protection scope of the present invention.

[0020] Among them, the simulator is a model that runs the design in a pure software environment. This model can simulate the behavior of the circuit according to the description of the circuit (such as the chip design written in Verilog or VHDL) to verify the function of the circuit.

[0021] Optionally, the simulator is a VCS (Verilog Compiler Simulator). Other types of simulators also fall within the protection scope of the present invention.

[0022] Furthermore, the system also includes a second system under test, a second high-speed interface and a simulator, wherein the simulator is connected to the second system under test via the second high-speed interface.

[0023] It should be noted that the second system to be tested is a simulated target system.

[0024] Optionally, the second system to be tested is a SOC system, a microprocessor or a multi-chip module. The second system to be tested may be the same as or different from the first system to be tested.

[0025] It should be noted that, for ease of understanding and description, the terms "first" and "second" are used to distinguish high-speed interfaces that are not the same, and the terms "first" and "second" do not indicate order or importance. The first high-speed interface and the second high-speed interface may be the same or different.

[0026] Among them, simulators are used to simulate the behavior of the system under test under different conditions, and are usually used to verify and test the correctness of the design before the actual hardware is completed. Simulators usually focus on simulating hardware behavior or physical processes.

[0027] Optionally, the emulator is a hardware emulation platform based on FPGA (Field Programmable Gate Array) or other configurable hardware. The chip design is mapped to FPGA or other configurable hardware so that the chip design can run at a speed close to that of the actual hardware. Other types of emulators also fall within the protection scope of the present invention.

[0028] Furthermore, the system also includes a first module and a second module, wherein the first module includes a test case library and a test interface, and the second module includes an intermediate layer and an interactive interface, the test case library is connected to the test interface, the test interface is respectively connected to the first high-speed interface and the intermediate layer, and the intermediate layer is connected to the second high-speed interface through the interactive interface.

[0029] Among them, the test case library of the first module includes a large number of test cases. The test cases in the test case library are specially written by hardware engineers for the simulator and are used to provide test stimuli to the simulation environment to verify the functions and behaviors of the system under test under different conditions.

[0030] Optionally, the test case is written in C language or C++ language. Test cases written in other programming languages ​​in the prior art also fall within the protection scope of the present invention.

[0031] The test API in the first module includes a direct programming interface (DPI) function, the upper layer of which is connected to the test case in the test case library, and the lower layer is connected to the first high-speed interface or the middle layer.

[0032] The middle layer (test API) is used to receive DPI function calls and forward the calls to the interactive interface.

[0033] Optionally, a unified interface is defined inside the middle layer, which defines all the methods required to interact with the hardware.

[0034] Optionally, the interactive interface is a kernel mode driver. Other types of interactive interfaces also fall within the protection scope of the present invention.

[0035] As a preferred embodiment, the test interface further includes a channel determination module for selecting the first high-speed interface or the intermediate layer according to the value of a configuration variable.

[0036] Optionally, the channel judgment module is implemented through conditional branching or macro definition. Specifically, when the channel judgment module is implemented through conditional branching, the value of the configuration variable is used to indicate whether to use the intermediate layer. If the value of the configuration variable indicates that the intermediate layer is used, the relevant function of the intermediate layer is called; if the value of the configuration variable indicates that the intermediate layer is not used, the relevant function of the first high-speed interface is called. When the channel judgment module is implemented through macro definition, a macro is defined, and the macro is defined as a function that calls the intermediate layer or the first high-speed interface according to the value of the configuration variable. Other ways of implementing the channel judgment module also fall within the protection scope of the present invention.

[0037] Furthermore, when test cases are reused, the test cases in the test case library call the test interface and send them to the first high-speed interface or the middle layer; when the middle layer receives the call of the test case, the call of the test case is sent to the second high-speed interface through the interactive interface.

[0038] Specifically, the middle layer receives calls from test cases, that is, DPI function calls, parses the DPI function calls to determine the specific method of the calls, and sends the parsed results to the interactive interface. The interactive interface receives calls from the middle layer, processes the calls, and prepares data to send to the second high-speed interface. The second high-speed interface receives data from the interactive interface and communicates with the system under test; the system under test receives data from the second high-speed interface, performs corresponding operations and interacts with the simulator. When the data is returned, the system under test returns the results to the interactive interface through the second high-speed interface, the interactive interface processes the results and returns them to the middle layer, and the middle layer forwards the results back to the test case. In this way, the middle layer acts as a unified interface, allowing test cases to maintain consistent calls in different underlying hardware or software environments, thereby achieving the reuse of test cases.

[0039] The embodiment of the present invention enables the test case to maintain the same call in the simulator as in the emulator through the middle layer, realizes the reuse of the test case, and improves the flexibility and efficiency of the test. In addition, the test case is decoupled from the underlying hardware or software environment through the middle layer, so that the test case does not need to care about the underlying implementation details, improves the maintainability and portability of the test case, and does not need to modify the test case even if the underlying hardware or software environment changes.

[0040] As a preferred embodiment, the system also includes a backdoor filling unit, which is used to inject the environmental data loaded in the simulator into the second system under test, and synchronize the environmental data to the emulator through the second system under test, which can ensure that the environmental data remains consistent between the emulator and the simulator, and further ensure that there is the same data basis between the emulator and the simulator, so that the test cases can be called consistently in different environments.

[0041] The backdoor filling unit is a special hardware or software component used to inject environmental data into the second system under test.

[0042] The environment data is data loaded in the simulator. Optionally, the environment data is configuration parameters and / or test vectors, and other types of environment data also fall within the protection scope of the present invention.

[0043] As a preferred embodiment, the system further includes a firmware filling unit, which is used to inject the initialization configuration data already loaded in the simulator into the second system under test, and synchronize the initialization configuration data to the simulator through the second system under test. This can ensure that the initialization configuration data is consistent between the simulator and the simulator, and further ensure that there is the same data basis between the simulation environment and the simulator, so that the test cases can be called consistently in different environments and achieve consistency in the test results.

[0044] The firmware filling unit (formware, FW) is a special hardware or software component used to inject initialization configuration data into the second system under test.

[0045] The initialization configuration data is data already loaded in the simulator. Optionally, the initialization configuration data is an initialization state and / or firmware settings, and other types of initialization configuration data also fall within the protection scope of the present invention.

[0046] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0047] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A test case reuse system for a hardware accelerator platform, characterized in that: The system comprises a first system to be tested, a first high-speed interface and a simulator, wherein the simulator is connected to the first system to be tested via the first high-speed interface; The system further comprises a second system under test, a second high-speed interface and a simulator, wherein the simulator is connected to the second system under test via the second high-speed interface; The system further comprises a first module and a second module, wherein the first module comprises a test case library and a test interface, the second module comprises an intermediate layer and an interactive interface, the test case library is connected to the test interface, the test interface is respectively connected to the first high-speed interface and the intermediate layer, and the intermediate layer is connected to the second high-speed interface via the interactive interface; When reusing test cases, the test cases in the test case library call the test interface and send it to the first high-speed interface or the middle layer; when the middle layer receives the call of the test case, it sends the call of the test case to the second high-speed interface through the interactive interface.

2. The system according to claim 1, characterized in that The test interface also includes a channel judgment module, which is used to select the first high-speed interface or the intermediate layer according to the value of the configuration variable.

3. The system according to claim 2, characterized in that The channel judgment module is implemented through conditional branching or macro definition.

4. The system according to claim 1, characterized in that The system further comprises a backdoor filling unit, which is used for injecting the environment data loaded in the simulator into the second system under test, and synchronizing the environment data to the simulator through the second system under test.

5. The system according to claim 1, characterized in that The system further comprises a firmware filling unit, which is used for injecting the initialization configuration data already loaded in the simulator into the second system under test, and synchronizing the initialization configuration data to the simulator through the second system under test.

6. The system according to claim 1, characterized in that The first system to be tested is a SOC system.

7. The system according to claim 1, characterized in that The interactive interface is a kernel driver.

8. The system according to claim 1, characterized in that The high-speed interface adopts the PCIe standard.

9. The system according to claim 1, characterized in that The test interface includes a DPI function.

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