Bus interconnect module, computing device, system on chip, and bus communication method

Abstract

The embodiment of the application provides a bus interconnection module, a computing device, a system on chip and a bus communication method, and the scheme is suitable for various chips including a CISC instruction set, a RISC reduced instruction set (especially a RISC-V instruction set) or a VLIM instruction set architecture, such as an Internet of Things chip, an audio / video chip and the like. The bus interconnection module comprises a plurality of master control units and a plurality of slave control units; the master control unit is used for, after receiving an address read-write request, if the address read-write request meets a reverse channel deadlock condition, temporarily storing the address read-write request, and after determining that the address read-write request does not meet the reverse channel deadlock condition, sending the address read-write request to a corresponding slave control unit; and the slave control unit is used for, after receiving the address read-write request, issuing the address read-write request. The scheme can evade the reverse channel deadlock while ensuring the bus utilization.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a bus interconnect module, computing device, system-on-a-chip, and bus communication method. Background Technology

[0002] The Advanced eXtensible Interface (AXI) bus protocol is a high-performance, high-bandwidth on-chip bus protocol widely used in system-on-chip (SoC) systems. The AXI bus employs a read / write separation and address / control / data separation transmission mechanism, utilizing five independent transmission channels: Read Address Channel (AR), Read Data Channel (R), Write Address Channel (AW), Write Data Channel (W), and Write Response Channel (B), to improve transmission efficiency. Data exchange between multiple masters and multiple slaves is achieved through bus interconnect modules. However, because the bus interconnect modules support out-of-order (OoO) access, reverse channel deadlock can easily occur on the AXI bus.

[0003] Currently, reverse channel deadlock can be avoided by using a single slave device or the same transaction identifier that can only be used by a single slave device (Single Slave PerID, SPI).

[0004] However, when the SPI mechanism is triggered, it will block the entire bus of the master device, causing subsequent transactions that have no possibility of deadlock to also be blocked, resulting in low bus utilization. Summary of the Invention

[0005] In view of this, embodiments of this application provide a bus interconnect module, a computing device, a system-on-a-chip, and a bus communication method to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, a bus interconnection module is provided, including: a plurality of master control units and a plurality of slave control units; the master control unit is configured to, upon receiving an address read / write request, temporarily store the address read / write request if the address read / write request satisfies the reverse channel deadlock condition, and send the address read / write request to the corresponding slave control unit after determining that the address read / write request does not satisfy the reverse channel deadlock condition; the slave control unit is configured to, upon receiving the address read / write request, issue the address read / write request.

[0007] According to a second aspect of the embodiments of this application, a plurality of master devices, a plurality of slave devices, and a bus interconnect module according to the first aspect described above are provided; the master devices are configured to send address read / write requests to the slave devices through the bus interconnect module; the slave devices are configured to, in response to the address read / write requests, send stored data to be read to the master devices through the bus interconnect module, or receive data to be written sent by the master devices through the bus interconnect module.

[0008] According to a third aspect of the embodiments of this application, a system-on-a-chip (SoC) is provided, comprising: a plurality of master devices and a bus interconnect module as described in the first aspect above; the master devices are configured to send address read / write requests to slave devices through the bus interconnect module, the slave devices being included in the SoC or connected to the SoC through an I / O interface on the SoC; the slave devices are configured to, in response to the address read / write requests, send stored data to be read to the master devices through the bus interconnect module, or receive data to be written sent by the master devices through the bus interconnect module.

[0009] According to a fourth aspect of the embodiments of this application, a bus communication method is provided, comprising: after receiving an address read / write request, if the address read / write request satisfies a reverse channel deadlock condition, temporarily storing the address read / write request, and after determining that the address read / write request does not satisfy the reverse channel deadlock condition, sending the address read / write request to a corresponding slave control unit; and after receiving the address read / write request, the slave control unit sends the address read / write request.

[0010] According to the bus interconnect module provided in this application embodiment, after receiving an address read / write request, the master control unit can determine whether the address read / write request meets the reverse channel deadlock condition. If the address read / write request meets the reverse channel deadlock condition, the address read / write request is temporarily stored. After the address read / write request no longer meets the reverse channel deadlock condition, the address read / write request is sent to the slave control unit, which then distributes the address read / write request. By temporarily storing address read / write requests that may cause reverse channel deadlock, the occurrence of reverse channel deadlock can be avoided. After temporarily storing address read / write requests that may cause reverse channel deadlock, subsequent address read / write requests that have no possibility of deadlock can still be transmitted normally, thereby improving bus utilization while avoiding reverse channel deadlock. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0012] Figure 1 This is a schematic diagram of a computing device according to an embodiment of this application;

[0013] Figure 2 This is a schematic diagram of an embodiment of the system-on-a-chip of this application;

[0014] Figure 3 This is a schematic diagram of a bus interconnect module according to an embodiment of this application;

[0015] Figure 4 This is a schematic diagram of a reverse channel deadlock according to an embodiment of this application;

[0016] Figure 5 This is a schematic diagram of the main control unit according to an embodiment of this application;

[0017] Figure 6 This is a schematic diagram of a bus interconnect module according to another embodiment of this application;

[0018] Figure 7 This is a schematic diagram of a forward channel deadlock according to an embodiment of this application;

[0019] Figure 8 This is a schematic diagram of a control unit according to an embodiment of this application;

[0020] Figure 9 This is a schematic diagram of a bus interconnect module according to yet another embodiment of this application;

[0021] Figure 10 This is a flowchart of a bus communication method according to an embodiment of this application. Detailed Implementation

[0022] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0023] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows.

[0024] Advanced eXtensible Interface (AXI) bus protocol: The Advanced eXtensible Interface (AXI) bus protocol is a high-performance, high-bandwidth on-chip bus protocol that is widely used in system-on-chip (SoC).

[0025] Bus Interconnect Module: In the AXI bus protocol, multiple master devices and multiple slave devices exchange data through bus interconnect modules (Interconnect), which are also known as bus matrices.

[0026] Deadlock: In the AXI bus protocol, deadlock refers to a state in which at least one master device and / or at least one slave device is unable to continue effective communication due to improper management of bus transactions or defects in the protocol implementation.

[0027] Reverse channel deadlock: During AXI bus transmission, the master device uses an ID number to mark each transmission. The bus interconnect module distinguishes different master devices by expanding the ID number of each master device. For different transmissions issued by the same master device using the same ID, the different transmissions need to be performed in sequence. However, the slave device can return transmissions with different ID numbers in an out-of-order (OoO) manner. This mechanism may form a cyclic dependency between handshake signals when multiple master devices access multiple slave devices at the same time, thus causing a deadlock. Since this type of deadlock is caused by the out-of-order mechanism of the slave device in the write response channel (B), this type of deadlock is called reverse channel deadlock.

[0028] Forward channel deadlock: During AXI bus transmission, for the same slave device, it is only allowed to receive the next transmission's write data after the write data of one transmission has been received. Therefore, although a master device can simultaneously initiate multiple address / control commands on the write address channel (AW) to negotiate access rights to multiple slave devices, within a transmission cycle, a slave device is only allowed to exchange data with a single master device that has been granted access rights on the write data channel (W). Due to the above mechanism, there is a risk of deadlock when multiple master devices and multiple slave devices exchange data. This type of deadlock is called forward channel deadlock.

[0029] computing devices

[0030] Figure 1A schematic block diagram of a computing device 10 according to one embodiment of this application is shown. The computing device 10 is, for example, a computer system, which may be built based on various processors currently on the market and driven by an operating system such as Windows, UNIX, or Linux. The computing device 10 may be a laptop computer, desktop computer, workstation, personal digital assistant (PDA), server, blade server, mainframe computer, or mobile communication device, etc. The computing device 10 in the embodiments of this application is not limited to any specific combination of hardware circuitry and software.

[0031] like Figure 1 As shown, computing device 10 includes multiple master devices 12. Each master device 12 possesses data processing capabilities known in the art. The master device 12 may be a CISC architecture, RISC architecture, VLIW architecture, or a combination of the aforementioned instruction sets, or any processor device built for a specific purpose. Exemplarily, the master device 12 includes a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a General-Purpose Computing on Graphics Processing Units (GPGPU), a Neural Network Processing Unit (NPU), a Tensor Processing Unit (TPU), a Deep Learning Processing Unit (DPU), or an Infrastructure Processing Unit (IPU), etc. The master device 12 may include one or more processor cores for processing and executing instructions, the processing and execution of which can be controlled by a user (e.g., through an application) and / or the system platform.

[0032] The computing device 10 also includes multiple slave devices 14 and a bus interconnect module 16. The master device 12 and the slave devices 14 are coupled to the bus interconnect module 16. The bus interconnect module 16 can be an interconnect circuit for connecting the master device 12 and the slave devices 14, and this interconnect circuit can support various interconnect protocols and interface circuits, thereby enabling communication between the master device 12 and the slave devices 14. In one example, the bus interconnect module 16 supports the AXI bus protocol, and the master device 12 and the slave devices 14 communicate through the bus interconnect module 16 based on the AXI bus protocol.

[0033] Slave device 14 can be various types of input / output (I / O) devices, such as memory, input devices, output devices, storage devices, communication devices, etc. Memory is used to store instruction information and / or data information represented by digital signals; memory can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, or other types of memory. Input devices can be keyboards, mice, microphones, cameras, etc. Output devices can be various types of displays, speakers, etc. Storage devices can be disks, optical discs, etc. Communication devices can be network interface cards (NICs), modems, wireless transceivers, etc. Communication devices allow computing device 10 to exchange information or data with other devices or systems through computer networks such as the Internet and / or various telecommunications networks.

[0034] It should be noted that the structure of different computing devices 10 may vary depending on the motherboard, operating system, and instruction set architecture. For example, some computing devices 10 currently have an input / output control center connected between the bus interconnect module 16 and the master device 12 or slave device 14, and this input / output control center may be integrated into the master device 12 or slave device 14 or set up independently of the master device 12 and slave device 14. This application embodiment does not limit this.

[0035] This application focuses on the process of transmitting requests and data between the master device 12 and the slave device 14 through the bus interconnect module 16, in order to reduce the risk of reverse channel deadlock and forward channel deadlock during communication between multiple devices 12 and multiple slave devices 14. The specific details of the structure of the bus interconnect module 16 and the data transmission process will be described in detail later.

[0036] System-on-a-Chip

[0037] Figure 2A schematic block diagram of a system-on-a-chip (SoC) 20 according to one embodiment of this application is shown. An SoC can be manufactured and sold as a standalone device or combined with other components to form a new device for manufacturing and sale. The SoC 20 can be manufactured using a variety of processors currently on the market and can be driven by operating systems such as Windows™, UNIX, Linux, Android, and RTOS. The SoC 20 can be implemented in computer devices, handheld devices, and embedded devices. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, PDAs, and personal computers (PCs). Some examples of embedded devices may include network PCs, set-top boxes, network hubs, wide area network (WAN) switches, etc., and embedded devices can also be any other system executing one or more instructions.

[0038] like Figure 2 As shown, the system-on-a-chip 20 includes multiple master devices 22. Each master device 22 possesses data processing capabilities known in the art. The master device 22 may be a CISC architecture, RISC architecture, VLIW architecture, or a combination of the aforementioned instruction sets, or any processor device built for a specific purpose. Exemplarily, the master device 22 includes a CPU, GPU, GPGPU, NPU, TPU, DPU, IPU, etc. The master device 22 may include one or more processor cores. The master device 22 is used to process and execute instructions, and the processing and execution of instructions can be controlled by a user (e.g., through an application) and / or the system platform.

[0039] The system-on-a-chip 20 also includes a bus interconnect module 26. The master device 22 is coupled to the bus interconnect module 26, which can be an interconnect circuit for connecting the master device 22 and the slave device 24. For example, the bus interconnect module 26 can support the AXI bus protocol, and the master device 22 and the slave device 24 communicate via the bus interconnect module 26 based on the AXI bus protocol. With the increasing complexity of SOC design and the continuous improvement of processor capabilities, the choice of bus interconnect module 26 for the SOC can be diverse, and this application does not limit this choice.

[0040] Slave device 24 can be an I / O device such as DRAM, SRAM, or flash memory included in system-on-chip 20. SRAM and flash memory are used to store instruction information and / or data information represented by digital signals. For example, SRAM can serve as the runtime space for various applications (APPs), creating heaps, stacks, and storing intermediate data for various applications. Flash memory can store executable code for various applications and executable code for the operating system.

[0041] The system-on-a-chip 20 may also include various input / output (I / O) interfaces 28 coupled to the bus interconnect module 26. The I / O interfaces 28 include, but are not limited to, the following interface types: Secure Digital High Capacity (SDHC) interface, Inter-Integrated Circuit (I2C), Serial Peripheral Interface (SPI), Universal Asynchronous Receiver Transmitter (UART), Universal Serial Bus (USB), General-purpose input / output (GPIO), and Bluetooth UART. Based on the I / O interfaces 28, the system-on-a-chip 20 can be coupled to peripheral devices of the corresponding interface types, such as USB devices, memory cards, message transceivers, Bluetooth devices, etc. The slave device 24 may be an I / O device coupled to the system-on-a-chip 20 via the I / O interfaces 28.

[0042] It should be noted that, Figure 1 The computing device 10 shown and Figure 2 The system-on-chip 20 shown is used to exemplify some application scenarios of the embodiments of this application, but is not intended to limit the embodiments of this application. The embodiments of this application implement improvements to the bus interconnect module, and therefore can theoretically be applied to any device or system that includes a bus interconnect module.

[0043] Bus interconnect module

[0044] Figure 3 This is a schematic block diagram of a bus interconnect module 30 according to an embodiment of this application. The bus interconnect module 30 may have the same or similar structure as the bus interconnect module 16 and bus interconnect module 26 described above.

[0045] like Figure 3As shown, the bus interconnect module 30 includes multiple master control units 32 and multiple slave control units 34. Upon receiving an address read / write request, the master control unit 32 can determine whether the request satisfies the reverse channel deadlock condition. If it determines that the request satisfies the condition, it temporarily stores the request. During this temporary storage, the master control unit 32 further determines whether the request satisfies the reverse channel deadlock condition. If it determines that the request does not satisfy the condition, it sends the request to the corresponding slave control unit 34. Upon receiving the address read / write request from the master control unit 32, the slave control unit 34 forwards the request.

[0046] The reverse channel deadlock condition is used to determine whether an address read / write request may trigger a reverse channel deadlock. If an address read / write request meets the reverse channel deadlock condition, then the address read / write request may trigger a reverse channel deadlock after being sent. If the address read / write request does not meet the reverse channel deadlock condition, then the address read / write request will not trigger a reverse channel deadlock after being sent.

[0047] Address read / write requests can be either read or write requests, and both can potentially lead to a reverse channel deadlock. Read requests are transmitted via the read address channel (AR) to obtain the read address from the slave device. After obtaining the read address, the master device can use the read data channel (R) to read data from the slave device. Write requests are transmitted via the write address channel (AW) to obtain the write address from the slave device. After obtaining the write address, the master device can use the write data channel (W) to write data to the slave device.

[0048] The following example illustrates the occurrence of reverse channel deadlock. Figure 4As shown, master device 0 and master device 1 send address read / write requests to slave devices A and B using the same ID. Slave devices A and B return responses to master devices 0 and 1. Master device 0 first sends address read / write request M01 to slave device A, then sends address read / write request M02 to slave device B. Master device 0 needs to receive slave device A's response SA0 first, then slave device B's response SB0. Master device 1 first sends address read / write request M11 to slave device B, then sends address read / write request M12 to slave device A. Master device 1 needs to receive slave device B's response SB1 first, then slave device A's response SA1. Because slave devices can return responses to received address read / write requests out of order, the order in which slave devices return responses may differ from the order in which the address read / write requests were sent. Slave device A needs to respond to master device 1 first, and slave device B needs to respond to master device 0 first. In this case, master device 0, master device 1, slave device A, and slave device B form a circular dependency, leading to a reverse channel deadlock.

[0049] Upon receiving an address read / write request that might cause a reverse channel deadlock, the master control unit 32 will temporarily store the request. As the slave device completes its response to other address read / write requests, this request will no longer cause a reverse channel deadlock. The master control unit 32 will then send the request to the corresponding slave control unit 34, which will then distribute the request. After temporarily storing a potential reverse channel deadlock address read / write request, the master control unit 32 can also receive subsequent read / write requests. If these subsequent requests will not cause a reverse channel deadlock, the master control unit 32 can send them to the slave control unit 32 before the stored request, and the slave control unit 32 will then distribute the subsequent requests before the stored request.

[0050] In this embodiment, after receiving an address read / write request, the master control unit 32 can determine whether the address read / write request meets the reverse channel deadlock condition. If the address read / write request meets the reverse channel deadlock condition, it temporarily stores the address read / write request. After the address read / write request no longer meets the reverse channel deadlock condition, it sends the address read / write request to the slave control unit 34, which then distributes the address read / write request. By temporarily storing address read / write requests that may cause reverse channel deadlock, the occurrence of reverse channel deadlock can be avoided. After temporarily storing address read / write requests that may cause reverse channel deadlock, subsequent address read / write requests that have no possibility of deadlock can still be transmitted normally, thereby improving bus utilization while avoiding reverse channel deadlock.

[0051] In one possible implementation, such as Figure 5The schematic block diagram of the main control unit 32 shown includes a first detection subunit 321, a second detection subunit 322, a first buffer 323, a first output subunit 324, and a first arbitration subunit 325.

[0052] The first detection subunit 321 can receive address write requests and update the detection information of the received address write requests into the first detection information. The detection information of the address write request includes the identification information of the address write request and the identification information of the destination slave device of the address write request. The identification information of the address write request is used to identify the address write request, and different address write requests correspond to different identification information. The destination slave device of the address write request is the transmission destination of the address write request. The first detection information may include the detection information of multiple address write requests.

[0053] After the first detection subunit 321 updates the detection information of the received address write request to the first detection information, it can detect whether the address write request meets the reverse channel deadlock condition according to the first detection information. If the address write request does not meet the reverse channel deadlock condition, the address write request is sent to the first output subunit 324. If the address write request meets the reverse channel deadlock condition, the address write request is temporarily stored in the last bit of the first buffer 323.

[0054] The first detection information includes detection information for address write requests that have been temporarily stored, and detection information for address write requests that have been sent to the slave control unit 34 but for which no corresponding response information has yet been received. The response information is sent by the destination slave device of the address write request based on the address write request. The first detection subunit 321 can match the first detection information with the reverse channel deadlock condition to determine whether the newly received address write request may cause a reverse channel deadlock. Address write requests that are single-slave or that can only be used by a single slave device with the same ID will not cause a reverse channel deadlock. The reverse channel deadlock condition can be set based on this rule. The first detection subunit 321 can use various deadlock detection algorithms based on the reverse channel deadlock condition to detect whether the address write request may cause a reverse channel deadlock. If the address write request may cause a reverse channel deadlock, then the address write request meets the reverse channel deadlock condition. If the address write request will not cause a reverse channel deadlock, then the address write request does not meet the reverse channel deadlock condition.

[0055] The first buffer 323 temporarily stores address write requests in the form of a queue. The address write request that is temporarily stored first is located before the address write request that is temporarily stored later. After the first detection subunit 321 determines that the received address write request meets the reverse channel deadlock condition, it temporarily stores the address write request at the end of the first buffer 323, that is, it temporarily stores the address write request at the tail of the address write request queue in the first buffer 323.

[0056] The second detection subunit 322 can detect whether the address write request at the head of the first buffer 323 meets the reverse channel deadlock condition based on the first detection information. After determining that the address write request at the head of the first buffer 323 does not meet the reverse channel deadlock condition, the second detection subunit 322 sends the address write request at the head of the address write request queue in the first buffer 323 to the first output subunit 324. The address write request at the head of the first buffer 323 refers to the address write request located at the head of the address write request queue in the first buffer 323.

[0057] The detection information for the received address write request is removed from the first detection information. This removal indicates that the address write request has been successfully transmitted, and the completion of this transmission may prevent one or more temporarily stored address write requests from causing a reverse channel deadlock. After the detection information for the address write request is removed from the first detection information, the second detection subunit 322 checks, based on the first detection information, whether the address write request at the beginning of the first buffer 323 meets the reverse channel deadlock condition. If it is determined that the address write request at the beginning of the first buffer 323 does not meet the reverse channel deadlock condition, the address write request is sent to the first output subunit 324.

[0058] After receiving an address write request from either the first detection subunit 321 or the second detection subunit 322, the first output subunit 324 sends the address write request to the corresponding slave control unit 34, which then forwards the address write request. The transmission path corresponding to the address write request is determined based on the type of the address write request, the master device that issued the address write request, and the destination slave device of the address write request. The transmission path consists of at least one set of master control units 32 and slave control units 34, so that the first output subunit 324 can send the address write request to the corresponding slave control unit 34 according to the transmission path corresponding to the address write request.

[0059] The first arbitration subunit 325 can receive the response information corresponding to the address write request sent from the control unit 34. After receiving the response information corresponding to a certain address write request, it deletes the detection information of the address write request from the first detection information, so that the address write requests in the first buffer 323 that have a circular dependency with the address write request can be determined by the second detection subunit 322 as no longer satisfying the reverse channel deadlock condition, and thus continue to be transmitted.

[0060] After receiving the response information corresponding to a write request for a certain address, the first arbitration subunit 325 will upload the response information. The write request and the corresponding response information are transmitted through the same transmission path. The write request is transmitted through the write address channel constructed by the master control unit 32 and the slave control unit 34 in the transmission path, and the response information is transmitted through the write response channel constructed by the master control unit 32 and the slave control unit 34 in the transmission path. The transmission direction of the write address channel is from the master device to the slave device, and the transmission direction of the write response channel is from the slave device to the master device.

[0061] The first arbitration subunit 325 can be connected to the master device. In this case, the first arbitration subunit 325 will upload the received response information to the connected master device. The first arbitration subunit 325 can also be connected to another slave control unit 34. In this case, the first arbitration subunit 325 will receive response information from one slave control unit 34 and upload the received response information to the other slave control unit 34.

[0062] When the first arbitration subunit 325 receives multiple response messages simultaneously, it will, based on the arbitration algorithm, sequentially delete the detection information of the write request corresponding to each response message from the first detection information, and then upload each response message accordingly. The arbitration algorithm can be any suitable algorithm, such as determining the priority of the response messages according to the priority of the corresponding master device or slave device, and uploading the response messages according to the priority. This application embodiment does not limit the arbitration algorithm.

[0063] In this embodiment, after receiving an address write request, the first detection subunit 321 checks whether the address write request meets the reverse channel deadlock condition. If the address write request does not meet the reverse channel deadlock condition, it sends the address write request to the first output subunit 324. If the address write request meets the reverse channel deadlock condition, it temporarily stores the address write request in the first buffer 323. After the second detection subunit 322 determines that the address write request no longer meets the reverse channel deadlock condition, it sends the address write request to the first output subunit 324. After receiving the address write request, the second output subunit 324 sends the received address write request to the corresponding slave control unit 34. This ensures that a reverse channel deadlock will not occur while preventing bus blockage. Address write requests with no possibility of deadlock can still be transmitted normally, improving bus utilization.

[0064] The first detection subunit 321 stores the detection information of the address write request that has been temporarily stored, as well as the detection information of the address write request that has been sent to the slave control unit 34 but has not yet received the corresponding response information, in the first detection information. The first arbitration subunit 325 deletes the detection information of the address write request corresponding to the received response information from the first detection information. This allows the first detection subunit 321 to accurately determine whether the received address write request will cause a reverse channel deadlock based on the first detection information, and allows the second detection subunit 322 to accurately determine whether the temporarily stored address write request will cause a reverse channel deadlock based on the first detection information. This avoids sending address write requests that may cause a reverse channel deadlock and reduces the risk of a reverse channel deadlock.

[0065] In one possible implementation, such as Figure 5 As shown, the main control unit 32 also includes a third detection subunit 326, a second buffer 327, a third buffer 328, and a second output subunit 329.

[0066] After determining that the address write request meets the reverse channel deadlock condition, the first detection subunit 321 temporarily stores the address write request in the last position of the first buffer 323, and simultaneously stores the destination device identification information of the address write request in the last position of the third buffer 328. After receiving the data to be written, the third detection subunit 326 compares the number of data entries to be written in the second buffer 327 with the number of slave device identification information entries in the third buffer 328. If the number of data entries to be written in the second buffer 327 is less than the number of slave device identification information entries in the third buffer 328, the received data to be written is temporarily stored in the last position of the second buffer 327. If the number of data entries to be written in the second buffer 327 is equal to the number of slave device identification information entries in the third buffer 328, the received data to be written is sent to the second output subunit 329.

[0067] The order in which the same main control unit 32 receives multiple address write requests matches the order in which the corresponding data to be written is received. That is, the nth data to be written received by the third detection subunit 326 is the data to be written corresponding to the nth address write request received by the first detection subunit 321. After the first detection subunit 321 temporarily stores the received nth address write request in the last position of the first buffer 323, it stores the identification information of the destination slave device of the address write request in the last position of the third buffer 328. After the third detection subunit 326 receives the nth data to be written, since the number of data to be written in the second buffer 327 is less than the number of slave device identification information entries in the third buffer 328, the third detection subunit 326 will temporarily store the received nth data to be written in the last position of the second buffer 327.

[0068] If the number of slave device identification information entries in the third buffer 328 is equal to the number of data entries to be written in the second buffer 327, it indicates that the newly received address write request from the first detection subunit 321 has not been temporarily stored in the first buffer 323. Correspondingly, the third detection subunit 326 does not need to temporarily store the newly received data to be written in the second buffer 327, but directly sends the newly received data to be written to the second output subunit 329. If the number of slave device identification information entries in the third buffer 328 is greater than the number of data entries to be written in the second buffer 327, it indicates that the address write request corresponding to the newly received data to be written by the third detection subunit 326 has been temporarily stored in the first buffer 323. Therefore, the third detection subunit 326 temporarily stores the newly received data to be written at the end of the second buffer 327.

[0069] The second buffer 327 temporarily stores data to be written in the form of a queue, with the data to be written being temporarily stored first preceding the data to be written later. The third buffer 328 temporarily stores the identification information of slave devices in the form of a queue, with the identification information of slave devices being temporarily stored first preceding the identification information of slave devices later. The slave device identified by the identification information of the i-th slave device in the third buffer 328 is the destination slave device of the i-th data to be written in the second buffer 327.

[0070] When the first output subunit 324 sends the address write request from the first detection subunit 321 to the corresponding slave control unit 34, the second output subunit 329 sends the data to be written from the third detection subunit 326 to the corresponding slave control unit 34. When the first output subunit 324 sends the address write request from the second detection subunit, the second output subunit 329 takes the data to be written at the beginning of the second buffer 327 from the second buffer 327 and sends it to the corresponding slave control unit 34.

[0071] If the first detection subunit 321 sends an address write request to the first output subunit 324, it indicates that the address write request does not meet the reverse channel deadlock condition. The address write request will be sent by the first output subunit 324 to the corresponding slave control unit 34. The data to be written sent by the corresponding third detection subunit 326 to the second output subunit 329 is the data to be written corresponding to the address write request. Therefore, the second output subunit 329 sends the data to be written from the third detection subunit 326 to the corresponding slave control unit 34. If the second detection subunit 322 sends an address write request to the first output subunit 324, it indicates that the address write request no longer meets the reverse channel deadlock condition after temporary storage. The address write request will be sent by the first output subunit 324 to the corresponding slave control unit 34. The data to be written at the beginning of the corresponding second buffer 327 is the data to be written corresponding to the address write request. Therefore, the second output subunit 329 retrieves the data to be written at the beginning of the second buffer 327 and sends it to the corresponding slave control unit 34.

[0072] After the second output subunit 329 sends the write-to-be-written data at the beginning of the second buffer 327 to the corresponding slave control unit 34, the third detection subunit 326 deletes the slave device identification information at the beginning of the third buffer 328, ensuring that the identification information of the i-th slave device in the third buffer 328 can indicate the slave device corresponding to the i-th write-to-be-written data in the second buffer 327.

[0073] In this embodiment, after the first detection subunit 321 temporarily stores the address write request that satisfies the reverse channel deadlock in the first buffer 323, the third detection subunit 326 temporarily stores the data to be written corresponding to the address write request in the second buffer 327. When the first output subunit 324 sends the address write request from the first detection subunit 321 to the slave control unit 34, the second output subunit 329 sends the data to be written from the third detection subunit 326 to the slave control unit 34. When the first output subunit 324 sends the address write request from the second detection subunit 322 to the slave control unit 34, the second output subunit 329 sends the data to be written at the beginning of the second buffer 327 to the slave control unit 34, ensuring that the data to be written corresponding to the address write request is sent in the order of the address write request, thereby avoiding the occurrence of reverse channel deadlock and ensuring the correctness of the data written to the slave device.

[0074] In one possible implementation, such as Figure 5 As shown, the main control unit 32 includes a fourth detection subunit 3210, a fifth detection subunit 3211, a fourth buffer 3212, a third output subunit 3213, and a second arbitration subunit 3214.

[0075] Upon receiving an address read request, the fourth detection subunit 3210 updates the detection information of the address read request to the second detection information, and checks whether the address read request meets the reverse channel deadlock condition based on the second detection information. If the address read request does not meet the reverse channel deadlock condition, it sends the address read request to the third output subunit 3213. If the address read request meets the reverse channel deadlock condition, it temporarily stores the address read request in the last bit of the fourth buffer 3212. The detection information of the address read request includes the identification information of the address read request and the identification information of the destination slave device of the address read request.

[0076] The fifth detection subunit 3211 can detect whether the address read request at the beginning of the fourth buffer 3212 meets the reverse channel deadlock condition based on the second detection information, and after determining that the address read request at the beginning of the fourth buffer 3212 does not meet the reverse channel deadlock condition, it sends the address read request at the beginning of the fourth buffer 3212 to the third output subunit 3213.

[0077] The third output subunit 3213 can send an address read request from the fourth detection subunit 3210 or the fifth detection subunit 3211 to the corresponding slave control unit 34.

[0078] The second arbitration subunit 3214 can, after receiving the data to be read corresponding to the address read request, delete the detection information of the address read request from the second detection information and upload the data to be read corresponding to the address read request.

[0079] It should be noted that the processing method for address read requests is similar to that for address write requests. The difference is that when processing address read requests, it is not necessary to temporarily store the data to be written. The processing process for address read requests can be found in the processing process for address write requests in the aforementioned embodiments, and the processing process for address read requests will not be described again here.

[0080] In this embodiment, after receiving an address read request, the fourth detection subunit 3210 checks whether the address read request meets the reverse channel deadlock condition. If the address read request does not meet the reverse channel deadlock condition, the address write request is sent to the third output subunit 3213. If the address read request meets the reverse channel deadlock condition, the address write request is temporarily stored in the fourth buffer 3212. After the fifth detection subunit 3211 determines that the address read request no longer meets the reverse channel deadlock condition, the address read request is sent to the third output subunit 3213. After receiving the address read request, the third output subunit 3213 sends the received address read request to the corresponding slave control unit 34. This ensures that a reverse channel deadlock will not occur while preventing bus blockage. Address read requests with no possibility of deadlock can still be transmitted normally, improving bus utilization.

[0081] In one possible implementation, such as Figure 6 The schematic block diagram of the bus interconnect module 30 shown may further include a timing maintenance module 36. The timing maintenance module 36 can generate timing information corresponding to slave devices. Different slave devices correspond to different timing information. The timing information of a slave device can indicate the order in which address write requests sent to that slave device are issued by the master device. After receiving an address write request sent by the master control unit 32, the slave control unit 34 can, according to the timing information corresponding to the destination slave device of the address write request, forward the address write request, ensuring that address write requests that could cause a forward channel deadlock are forwarded sequentially in the order they were issued.

[0082] The following example illustrates the occurrence of forward path deadlock. Figure 7 As shown, master device 0 first sends address write request M01 to slave device 0, and then sends address write request M02 to slave device 0. However, address write request M01 is temporarily stored between switching module A and switching module B, which are included in the bus interconnect module, for at least one clock cycle, causing slave device 0 to receive address write request M02 first, thus causing forward channel deadlock.

[0083] In this embodiment, forward channel deadlock is caused by address write requests from different or the same master devices being sent to slave devices in the order they are sent. The timing maintenance module 36 can generate corresponding timing information for each slave device and record the order in which address write requests from different or the same master devices are sent to the slave device through the timing information. Then, the control unit 34 sends address write requests to the slave device according to the timing information corresponding to the slave device and in the order in which the address write requests are sent, so that the address write requests are sent first and arrive first, thereby avoiding the occurrence of forward channel deadlock.

[0084] In one possible implementation, such as Figure 8The schematic block diagram shown is of the control unit 34, which includes a first selection subunit 341, a second selection subunit 342, and a fifth buffer 343.

[0085] After receiving an address write request from either the first detection subunit 321 or the second detection subunit 322, if the third buffer 328 does not contain any slave device identification information, the first output subunit 324 sets a priority flag for the received address write request and sends it to the corresponding slave control unit 34. The third buffer 328 stores the destination slave device identification information of temporarily stored address write requests. After the data to be written corresponding to the temporarily stored address write request is sent to the slave control unit 34, the third detection subunit 326 deletes the destination slave device identification information from the third buffer 328. Therefore, when the third buffer 328 does not contain any slave device identification information, it means that there are no temporarily stored address write requests in the first buffer 323. In this case, the first output subunit 324 sending the received address write request will not cause a forward channel deadlock. Thus, the first output subunit 324 can set a priority flag for the received address write request, enabling the slave control unit 34 to quickly send the request after receiving it.

[0086] After receiving an address write request from the first output subunit 324, the first selection subunit 341 checks whether the address write request includes a priority identifier. If the address write request includes a priority identifier, it directly sends the address write request and stores the path identifier of the transmission path of the address write request in the bus interconnect module 30 in the fifth buffer 343. After the first selection subunit 341 sends the address write request including the priority identifier, the second selection subunit 342 receives the data to be written transmitted through the transmission path indicated by the path identifier of the address write request in the fifth buffer 343, sends the received data to be written, and then deletes the path identifier of the address write request from the fifth buffer 343.

[0087] It should be noted that the path identifiers of address write requests issued by different master devices are different, and when there are multiple transmission paths from the same master device to a certain slave device for transmitting address write requests, the path identifiers of these multiple transmission paths are different to prevent self-locking in forward channel deadlock.

[0088] In this embodiment, when the first output subunit 324 receives an address write request, if the third buffer 328 does not contain any slave device identification information, the address write request will not cause a forward channel deadlock. The first output subunit 324 sets a priority flag for the address write request and sends it to the first selection subunit 341. After receiving the address write request with the priority flag, the first selection subunit 341 sends the address write request directly without waiting, thereby improving transmission efficiency. After sending the address write request, the first selection subunit 341 stores the path flag of the address write request in the fifth buffer 343. The second selection subunit 342 receives the data to be written transmitted through the transmission path indicated by the path flag, sends the received data to be written, and then deletes the path flag of the address write request from the fifth buffer 343, ensuring that the data to be written corresponding to the address write request is sent in the order of the address write requests, thereby ensuring the correctness of data writing.

[0089] In one possible implementation, such as Figure 8 As shown, the timing information includes a full queue. After the master device sends an address write request for the slave device corresponding to the timing information, if the address write request does not include a priority identifier, the timing maintenance module 36 stores the path identifier of the transmission path of the address write request in the bus interconnection module 30 to the tail of the full queue. The first selection subunit 341 receives the address write request transmitted through the transmission path indicated by the path identifier located at the head of the full queue, sends down the received address write request, and stores the path identifier in the fifth buffer 343.

[0090] In this embodiment, for a certain slave control unit 34, the timing maintenance module 36 takes the address write requests sent by each master device to a certain slave device and stores the path identifier corresponding to the address write request in the order in which the address write requests are sent by the master devices to the tail of the full queue corresponding to the slave control unit 34 and the slave device. The first selection subunit 341 included in the slave control unit 34 receives the address write request transmitted through the transmission path indicated by the path identifier at the head of the full queue, sends the received address write request down, stores the path identifier in the fifth buffer 343, and deletes the path identifier from the full queue, ensuring that the address write request sent first is sent down first by the slave control unit 34, thereby avoiding the occurrence of forward channel deadlock.

[0091] In one possible implementation, such as Figure 8 As shown, the timing information includes not only the full queue but also a priority queue. The timing maintenance module 36 updates the timing information according to the following rules:

[0092] If multiple master devices issue write requests to the same slave device's address within a single clock cycle, the waiting time is determined based on the logical length and / or physical distance between the master and the slave device. The waiting time can be one clock cycle or multiple clock cycles.

[0093] If the waiting time is one clock cycle, or if the waiting time is longer than one clock cycle but the multiple address write requests issued within the same clock cycle do not include address write requests with a priority flag, then the multiple address write requests are stored sequentially at the tail of the full queue.

[0094] If the waiting time is longer than one clock cycle, and among the multiple address write requests issued within the same clock cycle is an address write request with a priority flag, and the time it takes for the address write request with the priority flag to be transmitted to the first selection subunit 341 is less than the waiting time, then after the first selection subunit 341 issues the address write request with the priority flag, it stores the path flag of the address write request with the priority flag in the priority queue.

[0095] After the waiting period, based on the path identifiers stored in the priority queue, the other address write requests (excluding those whose corresponding path identifiers are recorded in the priority queue) are sequentially stored at the tail of the full queue, and the path identifiers stored in the priority queue are deleted.

[0096] If one or more master devices and slave devices cannot determine the address write request sent by the master device in one frame due to logical length or physical distance, it is necessary to complete the frame for all master devices as a whole before updating the full queue, i.e., wait for the specified duration before updating the full queue. If the time it takes for an address write request with a priority flag to be transmitted to the first selection subunit 341 is less than the waiting duration, and the address write request with the priority flag has already been sent by the first selection subunit 341 within the waiting duration, the path identifier of the address write request will be stored in the priority queue. When updating the full queue after the waiting duration, since the address write request with the priority flag has already been sent, it is not necessary to store the path identifier of the address write request in the full queue again.

[0097] It should be noted that the priority queue is used to store the path identifiers of address write requests that have a priority identifier and whose transmission time to the first selection subunit 341 is less than the waiting time. Since the number of address write requests that meet the above requirements is small, the priority queue only needs to be shallow.

[0098] In this embodiment of the application, the timing maintenance module 36 maintains a priority queue so that address write requests with priority flags can be sent quickly, while ensuring that the path flags of address write requests that have been sent and have priority flags are not stored in the full queue. This avoids the situation of repeatedly sending address write requests and ensures the correctness of data transmission.

[0099] In one possible implementation, such as Figure 8 As shown, the control unit 34 also includes a third arbitration subunit 344. The third arbitration subunit 344 can receive an address read request sent by the main control unit 32 (such as the third output 3213) and send the received address read request down. It can also receive the data to be read corresponding to the address read request and send the received data to be read to the second arbitration subunit 3214.

[0100] In this embodiment, since the address read request will not cause forward channel deadlock, the third arbitration subunit 344 directly sends the address read request after receiving it, and after receiving the data to be read corresponding to the address read request, it directly sends it to the second arbitration subunit 3214. This ensures the normal transmission of the address read / write request, the data to be written, and the data to be read while avoiding forward channel deadlock.

[0101] In one possible implementation, such as Figure 9 As shown, one end of the main control unit 32 is connected to a master device or a slave control unit 34, and the other end of the main control unit 32 is connected to at least one slave control unit 34. One end of the slave control unit 34 is connected to at least one main control unit 32, and the other end of the slave control unit 34 is connected to a master control unit 32 or a slave device.

[0102] In this embodiment, the bus interconnect module 30 may include multiple cascaded master control units 32 and slave control units 34. Each master control unit 32 may be connected to multiple slave control units 34, and each slave control unit 34 may be connected to one master control unit 32 or one slave device, in order to cope with application scenarios with different numbers of master devices and slave devices, and different layouts of master devices and slave devices, thereby improving the applicability of the bus interconnect module 30.

[0103] It should be noted that, in Figure 5 and Figure 8 In this context, AW represents the write address channel, W represents the write data channel, AR represents the read address channel, R represents the read data channel, and B represents the write response channel.

[0104] Bus communication method

[0105] Figure 10This is a flowchart of a bus communication method according to an embodiment of this application. This bus communication method can be executed by the bus interconnection module 30 in the above embodiment. Figure 10 As shown, the bus communication method includes the following steps:

[0106] Step 1001: After receiving the address read / write request, if the address read / write request meets the reverse channel deadlock condition, the main control unit temporarily stores the address read / write request, and after determining that the address read / write request does not meet the reverse channel deadlock condition, sends the address read / write request to the corresponding slave control unit.

[0107] Step 1002: After receiving the address read / write request, the control unit sends the address read / write request out.

[0108] In this embodiment, after receiving an address read / write request, the master control unit can determine whether the request satisfies the reverse channel deadlock condition. If the request satisfies the condition, it is temporarily stored. Once the request no longer satisfies the deadlock condition, it is sent to the slave control unit, which then distributes the request. By temporarily storing address read / write requests that may lead to a deadlock, the deadlock can be avoided. After this temporary storage, subsequent read / write requests without the potential for deadlock can still be transmitted normally, thus improving bus utilization while mitigating the deadlock.

[0109] It should be noted that the details of the bus communication method in the embodiments of this application have been described in detail in conjunction with the structural diagram in the bus interconnection module section of the above embodiments. For the specific process, please refer to the description in the aforementioned bus interconnection module embodiments, and will not be repeated here.

[0110] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0111] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0112] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0113] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0114] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A bus interconnect module, comprising: Multiple master control units and multiple slave control units; The main control unit is configured to, upon receiving an address read / write request, temporarily store the address read / write request if the address read / write request satisfies the reverse channel deadlock condition, and send the address read / write request to the corresponding slave control unit after determining that the address read / write request does not satisfy the reverse channel deadlock condition. The slave control unit is used to send the address read / write request after receiving the address read / write request; The main control unit includes: a first detection subunit, a second detection subunit, a first buffer, a first output subunit, and a first arbitration subunit. The first detection subunit, upon receiving an address write request, updates the detection information of the address write request to first detection information, and checks whether the address write request meets the reverse channel deadlock condition based on the first detection information. If the address write request does not meet the reverse channel deadlock condition, it sends the address write request to the first output subunit. If the address write request meets the reverse channel deadlock condition, it temporarily stores the address write request at the end of the first buffer. The detection information of the address write request includes the identifier information of the address write request and the address write request's... The purpose is to obtain the device's identification information; the second detection subunit is used to detect whether the address write request at the beginning of the first buffer satisfies the reverse channel deadlock condition based on the first detection information, and after determining that the address write request at the beginning of the first buffer does not satisfy the reverse channel deadlock condition, send the address write request at the beginning of the first buffer to the first output subunit; the first output subunit is used to send the received address write request to the corresponding slave control unit; the first arbitration subunit is used to delete the detection information of the address write request from the first detection information after receiving the response information corresponding to the address write request sent by the slave control unit, and upload the response information corresponding to the address write request; The main control unit further includes: a third detection subunit, a second buffer, a third buffer, and a second output subunit; the first detection subunit is configured to, after determining that the address write request satisfies the reverse channel deadlock condition, store the destination slave device identification information of the address write request in the last position of the third buffer; the third detection subunit is configured to, upon receiving data to be written, if the number of data entries to be written in the second buffer is less than the number of slave device identification information entries in the third buffer, temporarily store the data to be written in the last position of the second buffer; if the number of data entries to be written in the second buffer is equal to the number of slave device identification information entries in the third buffer, send the data to be written to the second output subunit. The first output subunit, after the second output subunit sends the first data to be written in the second buffer to the corresponding slave control unit, deletes the slave device identification information at the beginning of the third buffer; the second output subunit is used to send the data to be written from the third detection subunit to the corresponding slave control unit after the first output subunit sends the address write request from the first detection subunit to the corresponding slave control unit, and to retrieve the first data to be written in the second buffer from the second buffer and send it to the corresponding slave control unit after the first output subunit sends the address write request from the second detection subunit to the corresponding slave control unit; The bus interconnect module further includes: a timing maintenance module; the timing maintenance module is used to generate timing information corresponding to the slave devices, the timing information being used to indicate the order in which address write requests sent to the corresponding slave devices are issued by the master devices, and different slave devices correspond to different timing information; the slave control unit is used to, after receiving the address write request sent by the master control unit from the same or different master devices, to send the address write request down according to the timing information corresponding to the destination slave device of the address write request, so that address write requests that could cause forward channel deadlock are sent down sequentially in the order they were sent.

2. The bus interconnection module according to claim 1, wherein, The control unit includes: a first selection subunit, a second selection subunit, and a fifth buffer; The first output subunit is configured to, upon receiving an address write request, if the third buffer does not contain the identification information of the slave device, set a priority flag for the received address write request and then send it to the corresponding slave control unit. The first selection subunit is configured to, upon receiving an address write request including the priority identifier, send out the address write request information and store the path identifier of the transmission path of the address write request in the bus interconnect module into the fifth buffer. The second selection subunit is configured to receive data to be written transmitted through the transmission path indicated by the path identifier stored in the fifth buffer, send the received data to be written, and delete the path identifier from the fifth buffer.

3. The bus interconnection module according to claim 2, wherein, The timing information includes the entire queue; The timing maintenance module is used to store the path identifier of the transmission path of the address write request in the bus interconnect module to the tail of the full queue if the address write request does not include the priority identifier after the master device sends an address write request for the slave device corresponding to the timing information. The first selection subunit is configured to issue an address write request transmitted via the transmission path indicated by the path identifier located at the head of the full queue, and store the path identifier in the fifth buffer.

4. The bus interconnection module according to claim 3, wherein, The timing information also includes a priority queue, and the timing maintenance module is used to perform the following operations: When multiple master devices issue write requests to multiple addresses of the slave device corresponding to the timing information within a clock cycle, the waiting time is determined based on the logical length and / or physical distance between the master device and the slave device corresponding to the timing information. If the waiting time is greater than one clock cycle, and the plurality of address write requests include address write requests with priority identifiers, and the time taken for the address write requests with priority identifiers to be transmitted to the first selection subunit is less than the waiting time, then after the first selection subunit sends out the address write requests with priority identifiers, the path identifier of the transmission path of the address write requests with priority identifiers in the bus interconnect module is stored in the priority queue. After the specified waiting time, based on the path identifiers stored in the priority queue, the address write requests (excluding those whose corresponding path identifiers are recorded in the priority queue) are sequentially stored at the tail of the full queue, and the path identifiers in the priority queue are deleted.

5. The bus interconnect module according to claim 1, wherein, The main control unit includes: a fourth detection subunit, a fifth detection subunit, a fourth buffer, a third output subunit, and a second arbitration subunit; The fourth detection subunit is used to update the detection information of the address read request to the second detection information after receiving the address read request, and to detect whether the address read request meets the reverse channel deadlock condition according to the second detection information. If the address read request does not meet the reverse channel deadlock condition, the address read request is sent to the third output subunit. If the address read request meets the reverse channel deadlock condition, the address read request is temporarily stored in the last position of the fourth buffer. The detection information of the address read request includes the identification information of the address read request and the identification information of the destination slave device of the address read request. The fifth detection subunit is used to detect whether the address read request at the beginning of the fourth buffer satisfies the reverse channel deadlock condition based on the second detection information, and after determining that the address read request at the beginning of the fourth buffer does not satisfy the reverse channel deadlock condition, it sends the address read request at the beginning of the fourth buffer to the third output subunit. The third output subunit is used to send the received address read request to the corresponding slave control unit; The second arbitration subunit is used to delete the detection information of the address read request from the second detection information after receiving the data to be read corresponding to the address read request, and to upload the data to be read corresponding to the address read request.

6. The bus interconnect module according to claim 5, wherein, The slave control unit includes: The third arbitration subunit is used to send the address read request after receiving the address read request sent by the main control unit, and to send the received data to be read corresponding to the address read request to the second arbitration subunit.

7. The bus interconnect module according to any one of claims 1-6, wherein, One end of the main control unit is connected to the master device or one of the slave control units, and the other end of the main control unit is connected to at least one of the slave control units; One end of the slave control unit is connected to at least one of the master control units, and the other end of the slave control unit is connected to one of the master control units or a slave device.

8. A computing device, comprising: Multiple master devices, multiple slave devices, and a bus interconnect module according to any one of claims 1-7; The master device is used to send address read / write requests to the slave device through the bus interconnection module; The slave device is configured to, in response to the address read / write request, send the stored data to be read to the master device via the bus interconnect module, or receive the data to be written sent by the master device via the bus interconnect module.

9. A system-on-a-chip, comprising: Multiple master devices and a bus interconnect module according to any one of claims 1-7; The master device is used to send address read / write requests to the slave device through the bus interconnect module. The slave device is included in the system-on-a-chip or connected to the system-on-a-chip through an I / O interface on the system-on-a-chip. The slave device is configured to, in response to the address read / write request, send the stored data to be read to the master device via the bus interconnect module, or receive the data to be written sent by the master device via the bus interconnect module.

10. The system-on-a-chip according to claim 9, wherein, The master device includes a processing unit, and the slave device includes I / O devices.

11. A bus communication method, comprising: After receiving an address read / write request, if the address read / write request meets the reverse channel deadlock condition, the main control unit will temporarily store the address read / write request. If it is determined that the address read / write request does not meet the reverse channel deadlock condition, the main control unit will send the address read / write request to the corresponding slave control unit. After receiving the address read / write request, the slave control unit sends the address read / write request out. The main control unit includes: a first detection subunit, a second detection subunit, a first buffer, a first output subunit, and a first arbitration subunit. Upon receiving an address write request, the first detection subunit updates the detection information of the address write request into first detection information, and checks whether the address write request meets the reverse channel deadlock condition based on the first detection information. If the address write request does not meet the reverse channel deadlock condition, it sends the address write request to the first output subunit. If the address write request meets the reverse channel deadlock condition, it temporarily stores the address write request at the end of the first buffer. The detection information of the address write request includes the identifier information of the address write request and the address write... The purpose of the request is to obtain the device's identification information; the second detection subunit detects whether the address write request at the beginning of the first buffer satisfies the reverse channel deadlock condition based on the first detection information, and after determining that the address write request at the beginning of the first buffer does not satisfy the reverse channel deadlock condition, sends the address write request at the beginning of the first buffer to the first output subunit; the first output subunit sends the received address write request to the corresponding slave control unit; after receiving the response information corresponding to the address write request sent by the slave control unit, the first arbitration subunit deletes the detection information of the address write request from the first detection information and uploads the response information corresponding to the address write request; The main control unit further includes: a third detection subunit, a second buffer, a third buffer, and a second output subunit; after determining that the address write request satisfies the reverse channel deadlock condition, the first detection subunit stores the destination device identification information of the address write request in the last position of the third buffer; after receiving the data to be written, if the number of data entries to be written in the second buffer is less than the number of slave device identification information entries in the third buffer, the third detection subunit temporarily stores the data to be written in the last position of the second buffer; if the number of data entries to be written in the second buffer is equal to the number of slave device identification information entries in the third buffer, the third detection subunit sends the data to be written to the second output subunit. The second output subunit, after sending the first data to be written in the second buffer to the corresponding slave control unit, deletes the slave device identification information at the beginning of the third buffer; the second output subunit, after sending the address write request from the first detection subunit to the corresponding slave control unit, sends the data to be written from the third detection subunit to the corresponding slave control unit, and after sending the address write request from the second detection subunit to the corresponding slave control unit, retrieves the first data to be written in the second buffer from the second buffer and sends it to the corresponding slave control unit; A timing maintenance module generates timing information corresponding to the slave devices. The timing information is used to indicate the order in which address write requests sent to the corresponding slave devices are issued by the master devices. Different slave devices correspond to different timing information. After receiving the address write request from the same or different master devices sent by the master control unit, the slave control unit sends the address write request according to the timing information corresponding to the destination slave device of the address write request, so that address write requests that may cause forward channel deadlock are sent out in the order they were sent.

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