Time sequence optimization method and device based on OPC, equipment and storage medium

Abstract

The invention relates to the field of integrated circuit manufacturing, in particular to a time sequence optimization method, device and equipment based on OPC and a storage medium. Performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optical correction GDSII file; inputting the optical correction GDSII file and a preset correction circuit diagram file into a parasitic parameter extraction tool to obtain a correction parasitic parameter file; and performing time sequence analysis and time sequence convergence on the optical correction GDSII file according to the correction parasitic parameter file. According to the method, the parasitic parameter file is not directly calculated according to the provided original GDSII file, optical proximity effect correction and relocation simulation are carried out on the original GDSII file, so that the corrected parasitic parameter file is closer to parasitic parameters of a layout actually obtained after production, and the accuracy of time sequence analysis of a chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to an OPC-based timing optimization method, device, equipment and storage medium. Background Art

[0002] Currently, the physical design of the chip does not take into account the changes to the layout in the subsequent production and manufacturing process, but in fact, during the production process, the factory will first perform OPC (optical proximity correction) retarget operation on the original design layout, which will change the graphic shape of the original layout and add some additional auxiliary graphics to obtain a corrected layout. The next step of optical compensation optimization is then performed based on this corrected layout, and finally a mask layout is generated and sent to the factory for production.

[0003] Currently, in the physical design stage of a chip, sufficient margin is usually left for the chip's timing (during the design, the impact of manufacturing on timing is considered as pessimistically as possible). However, as process nodes continue to advance, the complexity of chip logic circuits continues to increase, which will gradually reduce the timing margin left by chip designers for the manufacturing end. It is becoming increasingly difficult to complete chip timing convergence with less and less margin. Even in actual production, there are times when the chip's timing cannot converge at all, greatly increasing the design and processing costs of the chip.

[0004] Therefore, how to improve the timing convergence rate of the chip and reduce the design and processing cost of the chip is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] The purpose of the present invention is to provide a timing optimization method, device, equipment and storage medium based on OPC to solve the problems in the prior art.

[0006] In order to solve the above technical problems, the present invention provides a timing optimization method based on OPC, comprising:

[0007] Receive original GDSII files;

[0008] Performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file;

[0009] Inputting the optically corrected GDSII file and the preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file;

[0010] The optical correction GDSII file is subjected to timing analysis and timing closure according to the corrected parasitic parameter file.

[0011] Optionally, in the OPC-based timing optimization method, before obtaining the corrected parasitic parameter file, the method further includes:

[0012] According to the optically corrected GDSII file, a metal conductor layer-through hole layer connection relationship set is obtained;

[0013] A revised circuit diagram file is determined according to the metal conductor layer-through hole layer connection relationship set.

[0014] Optionally, in the OPC-based timing optimization method, after obtaining the corrected circuit diagram file, the method further includes:

[0015] Comparing the revised circuit diagram file with the original circuit diagram file corresponding to the original GDSII file to determine whether there is a circuit structure difference;

[0016] When there is a circuit structure difference between the revised circuit diagram file and the original circuit diagram file, a revision error alert is sent.

[0017] Optionally, in the OPC-based timing optimization method, performing optical proximity effect correction and repositioning on the original GDSII file to obtain the optically corrected GDSII file includes:

[0018] Determine the layer to be corrected in the original GDSII file;

[0019] The optical proximity effect correction and repositioning are performed on the layer to be corrected to obtain an optically corrected GDSII file.

[0020] Optionally, in the OPC-based timing optimization method, before performing timing analysis and timing closure on the optically corrected GDSII file according to the corrected parasitic parameter file, the method further includes:

[0021] Inputting the original GDSII file and the preset modified circuit diagram file into a parasitic parameter extraction tool to obtain an original parasitic parameter file;

[0022] Determining whether a difference between the modified parasitic parameter file and the original parasitic parameter file exceeds a first threshold;

[0023] When a difference between the modified parasitic parameter file and the original parasitic parameter file exceeds a first threshold, a potential problem alert is sent.

[0024] A timing optimization device based on OPC, comprising:

[0025] A receiving module, used for receiving the original GDSII file;

[0026] An OPC module is used to perform optical proximity correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file;

[0027] A parasitic detection module, used for inputting the optical correction GDSII file and the preset correction circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file;

[0028] A timing module is used to perform timing analysis and timing closure on the optical correction GDSII file according to the correction parasitic parameter file.

[0029] Optionally, in the OPC-based timing optimization device, the parasitic detection module further includes:

[0030] A metal structure detection unit, used to obtain a metal wire layer-through hole layer connection relationship set according to the optically corrected GDSII file;

[0031] The metal structure analysis unit is used to determine the revised circuit diagram file according to the metal wire layer-through hole layer connection relationship set.

[0032] Optionally, in the OPC-based timing optimization device, the parasitic detection module further includes:

[0033] A circuit structure determination unit, used for comparing the revised circuit diagram file with the original circuit diagram file corresponding to the original GDSII file to determine whether there is a circuit structure difference;

[0034] The structure difference alarm unit is used to send a correction error alarm when there is a circuit structure difference between the corrected circuit diagram file and the original circuit diagram file.

[0035] A timing optimization device based on OPC, comprising:

[0036] Memory for storing computer programs;

[0037] A processor is used to implement the steps of any one of the above-mentioned OPC-based timing optimization methods when executing the computer program.

[0038] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any one of the above-mentioned OPC-based timing optimization methods are implemented.

[0039] The present invention provides an OPC-based timing optimization method, which includes receiving an original GDSII file; performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; inputting the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; and performing timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file.

[0040] The present invention takes into account the change of layout shape caused by optical proximity effect correction and repositioning in the physical design stage of the chip, and the change of layout shape will affect the parasitic parameters of the circuit. Therefore, the present invention no longer directly calculates the parasitic parameter file based on the original GDSII file provided, but simulates the optical proximity effect correction and repositioning of the original GDSII file, and calculates the parasitic parameter file of the optically corrected GDSII file obtained after the simulation (that is, the corrected parasitic parameter file), so that the corrected parasitic parameter file is closer to the parasitic parameters of the layout actually obtained after production, improves the accuracy of the timing analysis of the chip, makes the timing convergence result of the chip more representative, has stronger guiding significance for production, improves the virtual convergence rate of the chip, and avoids long-term timing convergence calculation and rework, reducing the design and processing cost of the chip. The present invention also provides an OPC-based timing optimization device, equipment and storage medium with the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] FIG1 is a flow chart of a specific implementation of the OPC-based timing optimization method provided by the present invention;

[0043] FIG2 is a flow chart of another specific implementation of the OPC-based timing optimization method provided by the present invention;

[0044] FIG3 is a flow chart of another specific implementation of the OPC-based timing optimization method provided by the present invention;

[0045] FIG. 4 is a flow chart of a specific implementation of the OPC-based timing optimization device provided by the present invention.

[0046] In the figure, it includes 100-receiving module, 200-OPC module, 300-parasitic detection module, and 400-timing module. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0048] The core of the present invention is to provide a timing optimization method based on OPC, a flowchart of a specific implementation method thereof is shown in FIG1 , which is referred to as specific implementation method 1, and includes:

[0049] S101: Receive the original GDSII file.

[0050] GDSII file, also known as Graphic Design System file, is a data format commonly used in the field of electronic design automation (EDA) for integrated circuit or layout data exchange. The original GDSII file is usually a file that the chip designer directly gives to the manufacturer.

[0051] S102: Perform optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file.

[0052] In this step, an OPC retarget (optical proximity correction repositioning) operation is performed on the layer in the original GDSII file to obtain a brand new GDSII file (that is, the optically corrected GDSII file) whose layer shape becomes the OPC target. The metal shape in the optically corrected GDSII file is closer to the shape of the integrated circuit after actual production.

[0053] Furthermore, this step includes:

[0054] A1: Determine the layer to be modified in the original GDSII file.

[0055] Not all layers in the original GDSII file need to be corrected and repositioned for optical proximity effect. In this step, the layers that need to be corrected and repositioned for optical proximity effect can be specified according to preset rules or manually as the layers to be corrected.

[0056] A2: Perform optical proximity effect correction and repositioning on the layer to be corrected to obtain an optically corrected GDSII file.

[0057] In this step, the optical proximity effect correction and repositioning of the layers to be corrected in step A1 are performed to obtain the correction result layers corresponding to each layer to be corrected, and then all the correction result layers replace the corresponding layers to be corrected in the original GDSII file to obtain the optically corrected GDSII file.

[0058] In this preferred implementation, each layer in the original GDSII file is further subdivided, and only individual layers that need to be corrected for optical proximity effect and repositioned are selected for processing, which can greatly reduce the calculation time of the optically corrected GDSII file and improve processing efficiency.

[0059] S103: Inputting the optically corrected GDSII file and the preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file.

[0060] The modified circuit diagram file may be a pre-stored circuit diagram file, or may be a circuit diagram file further calculated based on the data obtained in the aforementioned steps, and the present invention is not limited thereto.

[0061] To obtain the corrected parasitic parameters of the metal layer in the optically corrected GDSII file, we need the optically corrected GDSII file, the technology file and the corrected circuit diagram file. The optically corrected GDSII file contains the complete physical information of the corresponding layout. The technology file mainly includes the process library file (lef), the rule file (nxtgrd), the layer mapping file (mapping), etc. The technology file contains the three-dimensional space size of the process and the dielectric constants of various materials. The corrected circuit diagram file (def) contains the structural distribution of the circuit. Through these files, the distribution of spatial RC parameters (parasitic parameters) can be established.

[0062] S104: Performing timing analysis and timing closure on the optical correction GDSII file according to the corrected parasitic parameter file.

[0063] As a preferred implementation, before performing timing analysis and timing closure on the optical correction GDSII file according to the corrected parasitic parameter file, the method further includes:

[0064] B1: Inputting the original GDSII file and the preset modified circuit diagram file into a parasitic parameter extraction tool to obtain an original parasitic parameter file.

[0065] This step calculates the parasitic parameters corresponding to the original GDSII file, that is, obtains the original parasitic parameter file.

[0066] B2: Determine whether the difference between the modified parasitic parameter file and the original parasitic parameter file exceeds a first threshold.

[0067] The modified parasitic parameter file and the original parasitic parameter file both include parasitic parameters of various circuit structures. In this step, only when the difference between the parasitic parameters of a group of corresponding circuit structures between the modified parasitic parameter file and the original parasitic parameter file exceeds the first threshold value, it is considered that the difference between the modified parasitic parameter file and the original parasitic parameter file exceeds the first threshold value.

[0068] The first threshold value may be a preset fixed value, or may be determined according to the original parasitic parameter file. For example, the first threshold value may be a fixed percentage of the parasitic parameters in the original parasitic parameter file, such as 15% or 20%.

[0069] B3: When the difference between the modified parasitic parameter file and the original parasitic parameter file exceeds a first threshold, a potential problem alert is sent.

[0070] In the preferred embodiment, after obtaining the corrected parasitic parameter file, the user does not rush to use the corrected parasitic parameter file for timing analysis and timing convergence. Instead, the user first determines whether the changes of each parasitic parameter in the optically corrected GDSII file after the optical proximity effect correction and repositioning are within a reasonable range (that is, the difference between the two does not exceed the first threshold value). If it is not within a reasonable range, it can be considered that there are risks or hidden dangers in the optical proximity effect correction and repositioning. At this time, the potential problem alarm is sent to remind the staff to check.

[0071] Of course, if the difference between the modified parasitic parameter file and the original parasitic parameter file does not exceed the first threshold value after the judgment in step B2, step S104 may be continued.

[0072] The present invention provides an OPC-based timing optimization method, which includes receiving an original GDSII file; performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; inputting the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; and performing timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file. The present invention takes into account the change of the layout shape caused by the correction and repositioning of the optical proximity effect during the physical design stage of the chip, and the change of the layout shape will affect the parasitic parameters of the circuit. Therefore, the present invention no longer directly calculates the parasitic parameter file based on the provided original GDSII file, but simulates the correction and repositioning of the optical proximity effect on the original GDSII file, and calculates the parasitic parameter file of the optically corrected GDSII file obtained after the simulation (that is, the corrected parasitic parameter file), so that the corrected parasitic parameter file is closer to the parasitic parameters of the layout actually obtained after production, improves the accuracy of the timing analysis of the chip, makes the timing convergence result of the chip more representative, has a stronger guiding significance for production, improves the virtual convergence rate of the chip, and avoids long-term timing convergence calculation and rework, thereby reducing the design and processing cost of the chip.

[0073] On the basis of the first specific implementation mode, the acquisition process of the modified circuit diagram file is further improved to obtain a second specific implementation mode, the corresponding flow chart of which is shown in FIG2 , including:

[0074] S201: Receive the original GDSII file.

[0075] S202: Perform optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file.

[0076] S203: Obtaining a metal conductor layer-via layer connection relationship set according to the optically corrected GDSII file.

[0077] S204: Determine a revised circuit diagram file according to the metal conductor layer-via layer connection relationship set.

[0078] S205: Inputting the optically corrected GDSII file and the corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file.

[0079] S206: Performing timing analysis and timing closure on the optical correction GDSII file according to the corrected parasitic parameter file.

[0080] The difference between this specific implementation and the above specific implementation is that this specific implementation further provides a method for obtaining a circuit diagram file, and the remaining steps are the same as those in the above specific implementation, which will not be elaborated here.

[0081] In this specific implementation, a method for determining the modified circuit diagram file is further disclosed, that is, by scanning the optically modified GDSII file, the connection relationship and position relationship between the metal wire layer and the through-hole layer in the optically modified GDSII file are obtained, and then the circuit structure is calculated through a preset model, that is, the modified circuit diagram file. In some actual production scenarios, the manufacturer of the integrated circuit does not have the circuit structure of the chip, which adds many obstacles to the timing analysis. However, this preferred implementation can directly obtain the corresponding circuit diagram file through the GDSII file, which greatly improves the versatility of the present invention.

[0082] On the basis of the second specific implementation mode, the modified circuit diagram file is further checked to obtain a third specific implementation mode, the corresponding flow chart of which is shown in FIG3 , including:

[0083] S301: Receive the original GDSII file.

[0084] S302: Perform optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file.

[0085] S303: Obtaining a metal conductor layer-via layer connection relationship set according to the optically corrected GDSII file.

[0086] S304: Determine a revised circuit diagram file according to the metal conductor layer-via layer connection relationship set.

[0087] S305: Compare the revised circuit diagram file with the original circuit diagram file corresponding to the original GDSII file to determine whether there is a circuit structure difference.

[0088] The original circuit diagram file corresponding to the original GDSII file may be pre-stored, or received together with the original GDSII file, or, like the revised circuit diagram file, may be calculated through the metal wire layer-via layer connection relationship set of the original GDSII file, and the present invention is not limited thereto.

[0089] S306: When there is a circuit structure difference between the revised circuit diagram file and the original circuit diagram file, a revision error alarm is sent.

[0090] S307: When there is no circuit structure difference between the revised circuit diagram file and the original circuit diagram file, the optically revised GDSII file and the revised circuit diagram file are input into a parasitic parameter extraction tool to obtain a revised parasitic parameter file.

[0091] S308: Performing timing analysis and timing closure on the optical correction GDSII file according to the corrected parasitic parameter file.

[0092] The difference between this specific implementation and the above specific implementation is that this specific implementation further checks whether the GDSII file after optical proximity effect correction and repositioning is consistent with the original GDSII file in the circuit. The remaining steps are the same as the above specific implementation and will not be elaborated here.

[0093] In this specific implementation, before performing timing analysis and timing convergence, the optically corrected GDSII file that has been corrected and repositioned after optical proximity effect is first checked to see if the circuit structure has changed compared to the original GDSII file. If the circuit structure has changed, there is no need to calculate the parasitic parameters later. Therefore, when there is a circuit structure difference between the corrected circuit diagram file and the original circuit diagram file, a correction error alarm is sent to the staff to remind them to intervene manually to avoid wasting computing power. Of course, if there is no circuit structure difference between the corrected circuit diagram file and the original circuit diagram file, it is sufficient to continue to calculate the corrected parasitic parameter file, that is, step S306 and step S307 are two situations after step S305, and there is no order relationship between step S306 and step S307.

[0094] The following is an introduction to an OPC-based timing optimization device provided in an embodiment of the present invention. The OPC-based timing optimization device described below and the OPC-based timing optimization method described above can refer to each other.

[0095] FIG. 4 is a structural block diagram of an OPC-based timing optimization device provided by an embodiment of the present invention. Referring to FIG. 4 , the OPC-based timing optimization device may include:

[0096] The receiving module 100 is used to receive the original GDSII file;

[0097] The OPC module 200 is used to perform optical proximity correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file;

[0098] The parasitic detection module 300 is used to input the optical correction GDSII file and the preset correction circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file;

[0099] The timing module 400 is used to perform timing analysis and timing closure on the optical correction GDSII file according to the correction parasitic parameter file.

[0100] As a preferred implementation, the parasitic detection module 300 further includes:

[0101] A metal structure detection unit, used to obtain a metal wire layer-through hole layer connection relationship set according to the optically corrected GDSII file;

[0102] The metal structure analysis unit is used to determine the revised circuit diagram file according to the metal wire layer-through hole layer connection relationship set.

[0103] As a preferred implementation, the parasitic detection module 300 further includes:

[0104] A circuit structure determination unit, used for comparing the revised circuit diagram file with the original circuit diagram file corresponding to the original GDSII file to determine whether there is a circuit structure difference;

[0105] The structure difference alarm unit is used to send a correction error alarm when there is a circuit structure difference between the corrected circuit diagram file and the original circuit diagram file.

[0106] As a preferred implementation, the OPC module 200 includes:

[0107] A layer identification unit, used for determining the layer to be corrected in the original GDSII file;

[0108] The layer correction unit is used to perform optical proximity effect correction and repositioning on the layer to be corrected to obtain an optically corrected GDSII file.

[0109] As a preferred implementation, the parasitic detection module 300 further includes:

[0110] An original parasitic detection unit, used for inputting the original GDSII file and the preset modified circuit diagram file into a parasitic parameter extraction tool to obtain an original parasitic parameter file;

[0111] a parasitic difference judgment unit, configured to judge whether a difference between the modified parasitic parameter file and the original parasitic parameter file exceeds a first threshold;

[0112] The parasitic difference alarm unit is used to send a potential problem alarm when the difference between the modified parasitic parameter file and the original parasitic parameter file exceeds a first threshold.

[0113] The present invention provides an OPC-based timing optimization device, comprising a receiving module 100 for receiving an original GDSII file; an OPC module 200 for performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; a parasitic detection module 300 for inputting the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; and a timing module 400 for performing timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file. The present invention takes into account the change of the layout shape caused by the correction and repositioning of the optical proximity effect during the physical design stage of the chip, and the change of the layout shape will affect the parasitic parameters of the circuit. Therefore, the present invention no longer directly calculates the parasitic parameter file based on the provided original GDSII file, but simulates the correction and repositioning of the optical proximity effect on the original GDSII file, and calculates the parasitic parameter file of the optically corrected GDSII file obtained after the simulation (that is, the corrected parasitic parameter file), so that the corrected parasitic parameter file is closer to the parasitic parameters of the layout actually obtained after production, improves the accuracy of the timing analysis of the chip, makes the timing convergence result of the chip more representative, has a stronger guiding significance for production, improves the virtual convergence rate of the chip, and avoids long-term timing convergence calculation and rework, thereby reducing the design and processing cost of the chip.

[0114] The OPC-based timing optimization device of this embodiment is used to implement the aforementioned OPC-based timing optimization method. Therefore, the specific implementation of the OPC-based timing optimization device can be seen in the embodiment part of the OPC-based timing optimization method in the previous text. For example, the receiving module 100, the OPC module 200, the parasitic detection module 300, and the timing module 400 are respectively used to implement steps S101, S102, S103 and S104 in the aforementioned OPC-based timing optimization method. Therefore, its specific implementation can refer to the description of the corresponding embodiments of each part, which will not be repeated here.

[0115] The present invention also provides a timing optimization device based on OPC, comprising:

[0116] Memory for storing computer programs;

[0117] A processor is used to implement the steps of any of the above-mentioned OPC-based timing optimization methods when executing the computer program. The OPC-based timing optimization method provided by the present invention receives an original GDSII file; performs optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; inputs the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; and performs timing analysis and timing closure on the optically corrected GDSII file according to the corrected parasitic parameter file. The present invention takes into account the change of the layout shape caused by the correction and repositioning of the optical proximity effect during the physical design stage of the chip, and the change of the layout shape will affect the parasitic parameters of the circuit. Therefore, the present invention no longer directly calculates the parasitic parameter file based on the provided original GDSII file, but simulates the correction and repositioning of the optical proximity effect on the original GDSII file, and calculates the parasitic parameter file of the optically corrected GDSII file obtained after the simulation (that is, the corrected parasitic parameter file), so that the corrected parasitic parameter file is closer to the parasitic parameters of the layout actually obtained after production, improves the accuracy of the timing analysis of the chip, makes the timing convergence result of the chip more representative, has a stronger guiding significance for production, improves the virtual convergence rate of the chip, and avoids long-term timing convergence calculation and rework, thereby reducing the design and processing cost of the chip.

[0118] The present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above-mentioned OPC-based timing optimization methods are implemented. The OPC-based timing optimization method provided by the present invention receives an original GDSII file; performs optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; inputs the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; and performs timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file. The present invention takes into account the change of the layout shape caused by the correction and repositioning of the optical proximity effect during the physical design stage of the chip, and the change of the layout shape will affect the parasitic parameters of the circuit. Therefore, the present invention no longer directly calculates the parasitic parameter file based on the provided original GDSII file, but simulates the correction and repositioning of the optical proximity effect on the original GDSII file, and calculates the parasitic parameter file of the optically corrected GDSII file obtained after the simulation (that is, the corrected parasitic parameter file), so that the corrected parasitic parameter file is closer to the parasitic parameters of the layout actually obtained after production, improves the accuracy of the timing analysis of the chip, makes the timing convergence result of the chip more representative, has a stronger guiding significance for production, improves the virtual convergence rate of the chip, and avoids long-term timing convergence calculation and rework, thereby reducing the design and processing cost of the chip.

[0119] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0120] It should be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0121] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0122] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0123] The above is a detailed introduction to the OPC-based timing optimization method, device, equipment and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A timing optimization method based on OPC, characterized in that: include: Receive original GDSII files; Performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; Inputting the optically corrected GDSII file and the preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; The optical correction GDSII file is subjected to timing analysis and timing closure according to the corrected parasitic parameter file.

2. The OPC-based timing optimization method according to claim 1, characterized in that: Before obtaining the modified parasitic parameter file, the method further includes: According to the optically corrected GDSII file, a metal conductor layer-through hole layer connection relationship set is obtained; A revised circuit diagram file is determined according to the metal conductor layer-through hole layer connection relationship set.

3. The OPC-based timing optimization method according to claim 2, characterized in that: After obtaining the modified circuit diagram file, the method further includes: Comparing the revised circuit diagram file with the original circuit diagram file corresponding to the original GDSII file to determine whether there is a circuit structure difference; When there is a circuit structure difference between the revised circuit diagram file and the original circuit diagram file, a revision error alert is sent.

4. The OPC-based timing optimization method according to claim 1, characterized in that: Performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file includes: Determine the layer to be corrected in the original GDSII file; The optical proximity effect correction and repositioning are performed on the layer to be corrected to obtain an optically corrected GDSII file.

5. The OPC-based timing optimization method according to claim 1, characterized in that: Before performing timing analysis and timing closure on the optical correction GDSII file according to the corrected parasitic parameter file, the method further includes: Inputting the original GDSII file and the preset modified circuit diagram file into a parasitic parameter extraction tool to obtain an original parasitic parameter file; Determining whether a difference between the modified parasitic parameter file and the original parasitic parameter file exceeds a first threshold; When a difference between the modified parasitic parameter file and the original parasitic parameter file exceeds a first threshold, a potential problem alert is sent.

6. A timing optimization device based on OPC, characterized in that: include: A receiving module, used for receiving the original GDSII file; An OPC module is used to perform optical proximity correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; A parasitic detection module, used for inputting the optical correction GDSII file and the preset correction circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; A timing module is used to perform timing analysis and timing closure on the optical correction GDSII file according to the correction parasitic parameter file.

7. The OPC-based timing optimization device according to claim 6, characterized in that: The parasitic detection module further includes: A metal structure detection unit, used to obtain a metal wire layer-through hole layer connection relationship set according to the optically corrected GDSII file; The metal structure analysis unit is used to determine the revised circuit diagram file according to the metal wire layer-through hole layer connection relationship set.

8. The OPC-based timing optimization device according to claim 7, characterized in that: The parasitic detection module further includes: A circuit structure determination unit, used for comparing the revised circuit diagram file with the original circuit diagram file corresponding to the original GDSII file to determine whether there is a circuit structure difference; The structure difference alarm unit is used to send a correction error alarm when there is a circuit structure difference between the corrected circuit diagram file and the original circuit diagram file.

9. A timing optimization device based on OPC, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the OPC-based timing optimization method as described in any one of claims 1 to 5 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the OPC-based timing optimization method according to any one of claims 1 to 5 are implemented.

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