Quantum bit mapping method

Abstract

The invention provides a quantum bit mapping method, which is characterized in that on one hand, by constructing a noisy distance matrix, a hardware error rate is converted into an estimation correct rate similar to that of a physical topology distance, and the estimation correct rate executed by a corresponding circuit is added on the basis of a topology distance between every two physical bits; therefore, error rate information of hardware is considered, and the execution success rate of a final circuit is improved. On the other hand, after a to-be-inserted swap gate is selected according to the nearest neighbor heuristic function, whether the swap gate is repeated within preset insertion times or not is judged, if yes, the construction mode of the swap gate is temporarily changed, a two-bit gate is selected from a front layer, a shortest path is searched for the two-bit gate in a topological constraint graph according to current mapping, and then the swap gate is inserted into the topological constraint graph; constructing a swap gate along the shortest path to enable the selected two-bit gate to meet topological constraints, and inserting the constructed swap gate into optimization structure information; in this way, it can be avoided that many repeated swap gates appear in a short time, and the final circuit depth is reduced.

Description

Technical Field

[0001] The present invention relates to the field of quantum computing technology, specifically to the field of quantum circuit compilation technology, and more specifically to a quantum bit mapping method. Background Art

[0002] Quantum computing uses information processing and computing methods based on the principles of quantum mechanics, and its outstanding processing capabilities have aroused great interest in scientific research and industry. Quantum bits can be in a superposition of multiple states, which, as a core feature of quantum mechanics, gives quantum computers unique computing advantages. At the specific application level, compared with traditional computing, the superiority of quantum computing has been demonstrated in many fields, including but not limited to machine learning, encryption technology, solving linear equations, and simulation research in quantum chemistry. Considering the acceleration capabilities of quantum computers, related technologies, algorithms, and equipment have undergone extensive and in-depth exploration and development over the past few decades.

[0003] Quantum bit mapping refers to mapping the logic circuit to the physical circuit: when designing quantum algorithm circuits, algorithm designers often assume that all quantum bits can directly interact with each other through two-bit gates. However, in actual quantum hardware, only specific physical bits can directly interact with each other through two-bit gates. Mapping represents the current position of the logical bit in the logic circuit on the physical device, which is a single shot from the logical bit to the physical bit.

[0004] In this case, in order to enable the logic circuit to be executed on physical hardware, additional exchange gates are generally introduced into the logic circuit to exchange the positions of the logic bits so that the two-bit gates that need to be acted on satisfy the topological constraint graph.

[0005] At present, the mainstream method for dealing with quantum bit mapping algorithms is to use heuristic algorithms based on nearest neighbor functions. Among them, the SABRE algorithm (SWAP-based BidiREctional heuristic search algorithm, bidirectional search heuristic algorithm based on swap gates, literature: ASPLOS'19, Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices) is currently recognized as the best quantum bit mapping heuristic algorithm with the best performance and effect.

[0006] In the process of quantum bit mapping, the algorithm divides the two-bit gates to be executed into the following three categories according to the execution dependencies of quantum gates:

[0007] 1. The front-layer two-bit gate represents the set of all executable two-bit gates in the current state;

[0008] 2. The two-bit gates of the extended layer are a set of constant two-bit gates that are closest to the two-bit gates of the previous layer in the breadth-first search topological order;

[0009] 3. Other irrelevant two-bit gates.

[0010] The function used by this algorithm to evaluate the current mapping is the sum of the weighted distances of the two-bit gates in the previous layer and the expansion layer. This distance refers to the distance between the two bits of the two-bit gate on the physical topology constraint graph; the weights of all gates in the previous layer are the same, and the weights of all gates in the expansion set are the same, but the weights of the gates in the expansion set are lower than the weights of the gates in the previous layer.

[0011] The reason for using distance as the heuristic function is that the distance between bits on the physical topology constraint graph determines how many switch gates need to be introduced to make them adjacent.

[0012] The reason why only the front layer and the expansion layer are considered and the weight of the gates in the expansion layer is lower than that of the gates in the front layer is that the two-bit gates on the quantum circuit must be executed in a certain order and have dependencies. The first gate that can be executed is the gate in the front layer, and the subsequent gates can only be executed after the predecessor gates they depend on are executed.

[0013] Since inserting a swap gate will change the current mapping, the algorithm can select the swap gate with the best score after swapping (a low score means a short distance, so the lower the score, the better) according to the score changes caused by introducing different swap gates. The algorithm continuously introduces swap gates when there are no executable two-bit gates until an executable two-bit gate appears. After execution, the two sets of the previous layer and the extended layer are updated, and the above steps are repeated until the entire circuit is successfully executed.

[0014] Indicatively, see Figure 1 , giving a simple example of quantum bit mapping:

[0015] 1) Figure 1 Figure a shows a quantum logic circuit, which includes 5 logic bits, q1 to q5, and 5 quantum gates, CNOT(q2,q1), CNOT(q5,q5), CNOT(q2,q3), CNOT(q1,q3), CNOT(q3,q4);

[0016] 2) Figure 1Figure b shows a quantum physics hardware topology constraint diagram, which includes 5 physical bits, namely Q1~Q5. Two-bit gates can only be directly used between physical bits connected by edges in the topology constraint diagram. If it is assumed that the length of each edge is 1, the distance matrix D can be obtained, and the values ​​of the elements in it are: D[1][2]=1, D[1][3]=2, D[1][4]=2, D[1][5]=3, D[2][3]=1, D[2][4]=1, D[2][5]=2, D[3][4]=2, D[3][5]=3, D[4][5]=1;

[0017] 3) For simplicity, assume that the initially generated mapping is a one-to-one mapping, that is, π(q i )=Q i ;

[0018] 4) The quantum gates that can be initially attempted to be executed include CNOT(q2,q1) and CNOT(q4,q5). Since π(q2)=Q2 and π(q1)=Q1 are directly connected, the first gate can satisfy the topological constraint, and the second gate also satisfies the topological constraint in the same way.

[0019] 5) After executing these two gates, CNOT(q2,q3) can also be tried. Similarly, if the topological constraints are met, it can be executed;

[0020] 6) CNOT(q1,q3) can also be tried, but π(q1)=Q1 and π(q3)=Q3 are not directly connected, so a swap gate can be inserted. Assume that the positions of q2 and q3 are swapped by inserting a swap gate.

[0021] 7) After inserting the exchange gate to update the current mapping, it is found that all subsequent gates can be executed, and then we get Figure 2 The final circuit shown, where the gates with ×'s across their ends are swap gates.

[0022] However, the prior art has the following defects:

[0023] Defect 1: The switch gate is selected based only on the topological distance determined by the topological constraint graph, resulting in the performance of the final circuit to be improved;

[0024] Defect 2: During the process of inserting the switch gate, some repetitive insertion actions may be performed, which may result in a higher depth of the final circuit.

[0025] It should be noted that this background technology is only used to introduce the relevant information of the present invention to help understand the technical solution of the present invention, but it does not mean that the relevant information is necessarily the prior art. The relevant information is submitted and disclosed together with the present invention solution. If there is no evidence that the relevant information has been disclosed before the application date of the present invention, the relevant information shall not be regarded as the prior art. Summary of the invention

[0026] Therefore, the object of the present invention is to overcome the defects of the above-mentioned prior art and provide a quantum bit mapping method.

[0027] The objective of the present invention is achieved through the following technical solutions:

[0028] According to a first aspect of the present invention, a quantum bit mapping method is provided, comprising the following steps: S1: obtaining design structure information of a quantum logic circuit, a topological constraint diagram of quantum hardware, and error rate information, wherein the design structure information includes a plurality of logical bits and a quantum gate sequence constructed based on the logical bits, the topological constraint diagram includes a connection relationship between physical bits on the quantum hardware that can act as a two-bit gate, and the error rate information includes the error rate after a two-bit gate is introduced between each pair of physical bits that can act as a two-bit gate; S2: generating a first matrix according to the topological constraint diagram, which includes the topological distance between every two physical bits on the quantum hardware; S3: generating a second matrix according to the error rate information, which includes the estimated correctness of the circuit execution between every two physical bits; S4: fusing the first matrix and the second matrix to obtain a noisy distance matrix, and generating an initial mapping relationship between each logical bit and the physical bit and an optimized structure information that does not initially contain a quantum gate; S5: selecting a quantum gate from the design structure information according to the execution timing and the execution dependency to update a preset front layer and an extended layer, and judging the front layer respectively. Whether each quantum gate satisfies the topological constraint, if so, the quantum gates satisfying the topological constraint are sequentially added to the optimized structure information and transferred to S9, otherwise, when there are only two-bit gates that do not satisfy the topological constraint in the quantum gates of the previous layer, transfer to S6; S6: using the nearest neighbor heuristic function according to the noisy distance matrix, the previous layer and the extended layer, multiple candidate exchange gates are determined, and a exchange gate to be inserted is randomly selected from them; S7: for the exchange gate to be inserted, the insertion repeated exchange gate check strategy is executed to determine whether the exchange gate is repeated within the preset number of insertions, if so, transfer to S8, if not, the exchange gate is sequentially inserted into the optimized structure information to update the current mapping and transfer to S9; S8: select a two-bit gate from the previous layer, find the shortest path for it in the topological constraint graph according to the current mapping, construct an exchange gate along the shortest path so that the selected two-bit gate meets the topological constraint, and insert the constructed exchange gate into the optimized structure information; S9: determine whether there is a quantum gate in the design structure information that has not been added with the optimized structure information, if so, transfer to S5, otherwise obtain the initial mapping relationship and the final optimized structure information.

[0029] Optionally, the method of generating the second matrix includes: determining the accuracy between each pair of physical bits that can act on a two-bit gate based on error rate information; determining the path between each two physical bits based on the topological constraint graph; determining the estimated accuracy of the circuit execution between each two physical bits based on the accuracy between each pair of physical bits on the path between each two physical bits; and constructing a second matrix based on the number of physical bits, each element of which records the estimated accuracy of the circuit execution between the corresponding physical bits.

[0030] Optionally, the noisy distance matrix can be obtained by:

[0031] D N =ω1D d +ω2D ESP

[0032] Among them, D N represents the noisy distance matrix, D d Denotes the first matrix, D ESP represents the second matrix, ω1 represents D d The weight of D ESP The weights of , ω1 and ω2 are both positive real numbers.

[0033] Optionally, in step S5, the front layer is a set of quantum gates with the earliest execution timing in the quantum gate sequence in the current state and without adding optimized structure information, and the expansion layer is a set of quantum gates that are closest to a preset number of quantum gates in the front layer in the breadth-first search topological order.

[0034] Optionally, step S6 includes:

[0035] S61: Simulate and set multiple exchange gates. For each exchange gate set in the simulation, use the nearest neighbor heuristic function to calculate the corresponding nearest neighbor function value in the following manner:

[0036]

[0037] Where |F| represents the number of two-bit gates in the previous layer F, g represents the two-bit gates in the previous layer F, and D N represents a noisy distance matrix, g.q0 represents a logic bit q0 in a two-bit gate g, g.q1 represents another logic bit q1 in a two-bit gate g, [π(g.q0)] represents the number of the physical bit corresponding to q0 obtained by using the analog mapping π after the exchange gate of the analog setting is changed, [π(g.q1)] represents the number of the physical bit corresponding to q1 obtained by using the analog mapping π after the exchange gate of the analog setting is changed, |E| represents the number of two-bit gates in the extended layer E, and W represents the preset weight;

[0038] S62: selecting a preset number of exchange gates from all exchange gates set in simulation in the order of the nearest neighbor function values ​​from small to large and determining the minimum nearest neighbor function value;

[0039] S63: respectively determining the absolute value of the difference between the nearest neighbor function value corresponding to a preset number of exchange gates and the minimum nearest neighbor function value, and retaining the exchange gates whose absolute values ​​are less than 1;

[0040] S64: Randomly select a switch gate to be inserted from the reserved switch gates.

[0041] Preferably, the preset number is 4.

[0042] Optionally, step S8 includes: constructing a switching gate according to the shortest path to allow two endpoints of the selected two-bit gate to move toward the center of the shortest path, and finally acting on the selected two-bit gate at the intersection.

[0043] According to a second aspect of the present invention, there is provided a computer program product, comprising a computer program / instruction, which implements the steps of the method described in the first aspect when executed by a processor.

[0044] According to a third aspect of the present invention, there is provided an electronic device comprising: one or more processors; and a memory, wherein the memory is used to store executable instructions; the one or more processors are configured to implement the steps of the method described in the first aspect by executing the executable instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0046] Figure 1 A schematic diagram of an exemplary quantum logic circuit and topological constraint diagram;

[0047] Figure 2 A schematic diagram showing how the current mapping is changed after inserting a swap gate in a logic circuit;

[0048] Figure 3 Schematic diagram of the process of a quantum bit mapping method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0050] As mentioned in the background technology section, the prior art has the following defects: Defect 1: The switch gate is selected only based on the topological distance determined by the topological constraint graph, resulting in the performance of the final circuit to be improved; Defect 2: In the process of inserting the switch gate, some repetitive insertion actions may be made, which may result in a higher depth of the final circuit.

[0051] As for defect 1, it is mainly because the existing quantum heuristic algorithm itself does not consider the hardware error rate information, and there is no means to evaluate the final execution accuracy of the circuit. In this regard, the present invention constructs a noisy distance matrix to convert the hardware error rate into an "estimated accuracy" distance similar to the distance in physical topology, and adds the estimated accuracy of the corresponding circuit execution on the basis of the topological distance between every two physical bits, thereby taking into account the hardware error rate information and improving the final circuit execution success rate.

[0052] As for the second defect, it is mainly because the existing quantum heuristic algorithm selects the exchange gate only from the perspective of the nearest neighbor function value, and directly inserts the sequence after selecting the exchange gate. This method may repeatedly insert some identical exchange gates (with the same endpoints) in a short period of time, resulting in a higher depth of the final circuit. In this regard, after selecting the exchange gate to be inserted according to the nearest neighbor heuristic function, the present invention will first determine whether the exchange gate is repeated within the preset number of insertions. If so, the construction method of the exchange gate will be temporarily changed, and a two-bit gate will be selected from the front layer. The shortest path is found for it in the topological constraint graph according to the current mapping, and the exchange gate is constructed along the shortest path so that the selected two-bit gate meets the topological constraint, and the constructed exchange gate is inserted into the optimized structure information; in this way, it can focus on processing a two-bit gate in the front layer first, avoiding the appearance of more repeated exchange gates in a short period of time, so that the front layer and expansion layer information can be updated in advance, and then the heuristic algorithm is optimized to reduce the depth of the final circuit.

[0053] Before specifically introducing the embodiments of the present invention, some of the terms used therein are explained as follows:

[0054] A logical bit, also called a logical qubit, is a quantum bit in a quantum logic circuit.

[0055] A physical bit, also called a physical quantum bit, is a quantum bit in quantum hardware (such as a quantum chip).

[0056] Quantum gates include single-qubit gates and double-qubit gates (two-qubit gates).

[0057] A single-qubit gate is a gate operation that acts on a single qubit and is used to change the state of a single qubit.

[0058] Two-qubit gates are quantum gates that operate on two qubits. They can realize quantum entanglement, quantum error correction, and complex quantum computing operations. Common two-qubit gates include controlled NOT gate (CNOT gate), swap gate (SWAP gate), and controlled Z gate (CZ gate).

[0059] According to one embodiment of the present invention, see Figure 1 , a quantum bit mapping method is provided, comprising steps S1 to S9. In order to better understand the present invention, each step is described in detail below in conjunction with specific embodiments.

[0060] Step S1: Obtain design structure information of the quantum logic circuit, a topological constraint diagram of the quantum hardware, and error rate information, wherein the design structure information includes multiple logical bits and a quantum gate sequence constructed based on the logical bits, the topological constraint diagram includes the connection relationship between the physical bits on the quantum hardware that can act as a two-bit gate, and the error rate information includes the error rate after a two-bit gate is introduced between each pair of physical bits that can act as a two-bit gate.

[0061] According to one embodiment of the present invention, the design structure information (or data structure information) of a quantum logic circuit is a combined storage format of a description of a logical quantum bit and a quantum gate sequence (or an arrangement queue of quantum gates), wherein quantum gates include single-qubit gates and double-qubit gates. The quantum logic circuit includes n logical bits and T quantum gates, and the quantum hardware includes N physical bits, wherein n, T, and N are all positive integers. The number of quantum bits and quantum gates contained in the quantum logic circuit can be customized by the implementer, but the number of physical bits is required to be greater than or equal to the number of logical bits, that is, N ≥ T.

[0062] According to one embodiment of the present invention, the topological constraint graph of quantum hardware includes multiple nodes and edges, each node represents a physical bit, and the edge is used to connect the nodes corresponding to the physical bits that can act as a two-bit gate. Therefore, the topological constraint graph describes which quantum bits can act as a two-bit gate.

[0063] According to an embodiment of the present invention, the error rate information describes the error rate of introducing a two-bit gate between each pair of quantum bits that can act as a two-bit gate. The error rate information can be determined in advance by quantum hardware manufacturers, researchers or implementers through experiments.

[0064] Step S2: Generate a first matrix according to the topological constraint graph, which includes the topological distance between every two physical bits on the quantum hardware.

[0065] According to one embodiment of the present invention, assuming that the distance between every two directly connected nodes in the topological constraint graph is d (for example, set to 1, of course, the implementer can also set it to other values), the shortest distance between every two physical bits is calculated using the all-source shortest path algorithm as the topological distance, which is expressed in matrix form to form a first matrix, which can be represented by the letter D d Indicates. d [i][j] represents the physical bit Q i and Q j The topological distance between them.

[0066] Step S3: Generate a second matrix according to the error rate information, which includes the estimated correct rate of the circuits executed between every two physical bits.

[0067] According to one embodiment of the present invention, the method of generating the second matrix includes: determining the correctness of each pair of physical bits that can act on the two-bit gate according to the error rate information; determining the path between each two physical bits according to the topological constraint graph; determining the estimated correctness of the circuit execution between each two physical bits according to the correctness of each pair of physical bits on the path between each two physical bits; constructing the second matrix according to the number of physical bits, each element of which records the estimated correctness of the circuit execution between the corresponding physical bits. The second matrix can also be called an estimated correctness matrix, or an estimated success rate distance matrix, expressed as D ESP , D EsP [i][j] represents the physical bit Q i and Q j The accuracy of the estimate between .

[0068] Illustratively, the error rate of a two-bit gate refers to the probability of introducing an error after introducing a two-bit gate, and the estimated accuracy rate (estimated success rate) is the result obtained by multiplying the accuracy rates of all two-bit gates in the circuit, which can be used to estimate the final accuracy probability of a circuit.

[0069] Assume that the action is on the physical bit Q i and Q j The two-bit gate on has an execution path in, and This execution path represents the two-bit gates involved in using the exchange gate to make the logical bits on the physical bits adjacent and act on the two-bit gates. Then the estimated accuracy of this substructure is the product of the accuracy of these two-bit gates. Assume the form E[Q a ][Q b ] indicates the effect on the adjacent quantum bit Q a and Q b The error rate of the two-bit gate on , then the estimated accuracy generated in this process is:

[0070]

[0071] However, this formula is a multiplication, and the estimated accuracy calculated using this formula is slightly worse than the topological distance fusion effect. Therefore, according to the properties of logarithmic addition, we can take the logarithm of both sides of the calculation formula and add a negative sign to get the estimated accuracy between two physical bits:

[0072]

[0073] Where m represents any two physical bits Q i and Q j The total number of physical bits contained in the time path, Represents physical bits and The error rate after introducing a two-bit gate,

[0074] This formula has a similar form to the expression of path distance. Then, given a topological constraint graph, the estimation accuracy can be defined.

[0075] For adjacent physical bits Q that can directly perform two-bit gates a and Q b , m = 2, and its estimation accuracy is -log(1-E[Q a ][Q b ]); For non-adjacent physical bits, the estimated accuracy between any two points can also be calculated by the all-source shortest path algorithm; thus, the estimated accuracy matrix can be defined.

[0076] Step S4: The first matrix and the second matrix are merged to obtain a noisy distance matrix, and an initial mapping relationship between each logical bit and a physical bit and initial optimized structure information without quantum gates are generated.

[0077] According to one embodiment of the present invention, a method of obtaining a noisy distance matrix includes:

[0078] D N =ω1D d +ω2D ESP

[0079] Among them, D N represents the noisy distance matrix, D d Denotes the first matrix, D ESP represents the second matrix, ω1 represents D d The weight of D ESP The weights of ω1 and ω2 are both positive real numbers. The distance takes into account both the size of the final circuit and the estimated success rate.

[0080] According to another embodiment of the present invention, the method of obtaining the noisy distance matrix may also adopt other forms, for example, define a positive real number ω, let D N =D d +ωD ESP .

[0081] After obtaining the noisy distance matrix, a random initial mapping relationship is generated as the current mapping π. Of course, the implementer can also select one or more preset mapping relationships as the initial mapping relationship.

[0082] Step S5: Select quantum gates from the design structure information to update the preset front layer and expansion layer according to the execution sequence and execution dependency, and judge whether each quantum gate of the front layer satisfies the topological constraint. If so, add the quantum gates that satisfy the topological constraint to the optimized structure information in sequence and go to S9. Otherwise, when there are only two-bit gates in the front layer that do not satisfy the topological constraint, go to S6.

[0083] According to one embodiment of the present invention, in step S5, the front layer is a set of quantum gates with the earliest execution time in the quantum gate sequence in the current state and without adding the optimized structure information, and the extended layer is a set of quantum gates with the preset number of quantum gates closest to the front layer in the breadth-first search topological order. The definition of the front layer and the extended layer can also refer to the existing quantum bit mapping algorithm, such as the SABRE algorithm. Since quantum gates are divided into single-qubit gates and two-qubit gates, when judging whether each quantum gate in the front layer satisfies the topological constraint, for the single-qubit gate, it is directly regarded as satisfying the topological constraint (because it only needs to act on one physical bit); for the two-bit gate, it is necessary to see whether the physical bits corresponding to the two logical bits related to the two-bit gate under the current mapping are adjacent (directly connected by an edge on the topological constraint graph). If so, the two-bit gate satisfies the topological constraint, and the two-bit gate is added with the optimized structure information and removed from the front layer; if not, the two-bit gate does not satisfy the topological constraint, and the two-bit gate is retained in the front layer to judge whether the next quantum gate satisfies the topological constraint.

[0084] Step S6: using the nearest neighbor heuristic function to determine multiple candidate switch gates according to the noisy distance matrix, the previous layer and the extended layer, and randomly selecting a switch gate to be inserted.

[0085] According to one embodiment of the present invention, step S6 includes:

[0086] S61: Simulate and set multiple exchange gates. For each exchange gate set in the simulation, use the nearest neighbor heuristic function to calculate the corresponding nearest neighbor function value in the following manner:

[0087]

[0088] Where |F| represents the number of two-bit gates in the previous layer F, g represents the two-bit gates in the previous layer F, and D N represents a noisy distance matrix, g.q0 represents a logic bit q0 in a two-bit gate g, g.q1 represents another logic bit q1 in a two-bit gate g, [π(g.q0)] represents the number of the physical bit corresponding to q0 obtained by using the analog mapping π after the exchange gate of the analog setting is changed, [π(g.q1)] represents the number of the physical bit corresponding to q1 obtained by using the analog mapping π after the exchange gate of the analog setting is changed, |E| represents the number of two-bit gates in the extended layer E, and W represents the preset weight;

[0089] S62: selecting N (N is greater than 2, such as 3, 4 or 5, preferably 4) exchange gates from all exchange gates set in simulation in the order of the nearest neighbor function value from small to large, and determining the minimum nearest neighbor function value;

[0090] S63: Determine the absolute value of the difference between the nearest neighbor function value corresponding to the N exchange gates and the minimum nearest neighbor function value, and retain the exchange gates whose absolute value is less than 1;

[0091] S64: Randomly select a switch gate to be inserted from the reserved switch gates.

[0092] The technical solution of this embodiment can at least achieve the following beneficial technical effects: this embodiment selects N exchange gates to ensure that the randomness of the mapping method is not destroyed, and different routes can be explored in multiple runs. Only those exchange gates close to the lowest function value are retained to improve the effectiveness of the screening process.

[0093] Of course, step S6 may also adopt other methods to select the switch gate to be inserted.

[0094] According to another embodiment of the present invention, step S6 comprises:

[0095] S61', same as step S61, which will not be described in detail here;

[0096] S62': selecting a preset number of exchange gates (for example, M exchange gates) from all exchange gates set in simulation in the order of the nearest neighbor function values ​​from small to large;

[0097] S63': Randomly select a switch gate to be inserted from a preset number of switch gates.

[0098] Step S7: For the swap gate to be inserted, execute the insertion repeated swap gate check strategy to determine whether the swap gate is repeated within the preset insertion times. If so, go to S8; if not, insert the swap gate into the optimized structure information in sequence to update the current mapping and go to S9.

[0099] The prior art does not check the swap gates to be inserted, which may result in the short-term insertion of some repeated swap gates. In particular, when the two ends of some two-bit gates are far apart, more repeated swap gates may be inserted, resulting in a higher depth of the final circuit. Therefore, the present invention considers improving it so as to switch the way of constructing the swap gate in time when a repeated swap gate is found.

[0100] According to an embodiment of the present invention, the preset insertion number C is set to 4, 5, 6 or 7. In the process of continuously inserting the exchange gates, if the exchange gates are repeated within the preset insertion number, that is, the two end points of two exchange gates are the same within the preset insertion number, then go to S8. For example, if C is set to 5, the first three exchange gates inserted first do not have a repeat situation, and the fourth exchange gate to be inserted is the same as the first exchange gate of the first three exchange gates, then go to S8.

[0101] Step S8: Select a two-bit gate from the previous layer, find the shortest path for it in the topological constraint graph according to the current mapping, construct a switching gate along the shortest path so that the selected two-bit gate meets the topological constraint, and insert the constructed switching gate into the optimized structure information.

[0102] According to one embodiment of the present invention, step S8 includes: constructing a switching gate according to the shortest path so that the two endpoints of the selected two-bit gate move toward the center of the shortest path, and finally acting on the selected two-bit gate at the intersection. In this step, according to the switching gate sequence inserted continuously before turning to S8, the two-bit gates related to the switching gate sequence in the previous layer can be found, a two-bit gate can be selected from the related two-bit gates, and then a shortest path of the selected two-bit gate on the topological constraint graph is found and executed. In order to ensure that the depth of the final result is small, the switching gate is acted on by moving bits from the two endpoints of the two-bit gate to the center of the path, and the two-bit gate is acted on the intersection.

[0103] Step S9: Determine whether there are quantum gates in the design structure information that do not include the optimized structure information. If so, go to S5; otherwise, obtain the initial mapping relationship and the final optimized structure information.

[0104] According to one embodiment of the present invention, if there are quantum gates that have not yet been added with the optimized structure information, step S5 needs to be repeated, otherwise the final optimized structure information corresponding to the initial mapping relationship and the quantum logic circuit can be obtained. The final optimized structure information is still a quantum gate sequence, which includes the quantum gates in the design structure information and the inserted exchange gates.

[0105] In general, the method of the embodiment of the present invention has significantly improved the circuit depth and estimation accuracy of the final circuit compared with the prior art. The method of the embodiment of the present invention detects repeated exchange gates in time by inserting a repeated exchange gate check strategy, switches the way of constructing exchange gates in time, and constructs a substructure with the minimum depth according to the shortest path, which significantly reduces the depth of the final circuit on various test circuits and quantum topological constraint graphs. Experiments on quantum Fourier transform circuits, quantum approximate optimization algorithm circuits and random circuits show that compared with the most widely used SABRE algorithm, the algorithm combined with this strategy has reduced the depth by up to 19%, 40% and 20% respectively. In terms of the success rate of quantum circuit execution, the method of the embodiment of the present invention generates a noisy distance matrix by combining quantum hardware error rate information and quantum topological constraint graphs, and uses it in the quantum mapping heuristic algorithm, thereby improving the estimation success rate of the final circuit. Experiments on heavy hexagonal lattice and two-dimensional lattice topological constraint graphs show that the method of the embodiment of the present invention has improved the circuit estimation success rate by up to 9% and 12% respectively compared with the most advanced algorithms.

[0106] It should be noted that although the above describes the various steps in a specific order, it does not mean that the various steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0107] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0108] Computer readable storage medium can be a tangible device that holds and stores instructions used by an instruction execution device. Computer readable storage medium can include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination thereof.

[0109] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A quantum bit mapping method, characterized in that: Includes steps: S1: Obtain design structure information of the quantum logic circuit, topological constraint diagram of the quantum hardware, and error rate information, wherein the design structure information includes multiple logical bits and a quantum gate sequence constructed based on the logical bits, the topological constraint diagram includes the connection relationship between the physical bits on the quantum hardware that can act as a two-bit gate, and the error rate information includes the error rate after the two-bit gate is introduced between each pair of physical bits that can act as a two-bit gate; S2: Generate a first matrix according to the topological constraint graph, which includes the topological distance between every two physical bits on the quantum hardware; S3: generating a second matrix according to the error rate information, which includes the estimated correct rate of the circuits executed between each two physical bits; S4: Fusing the first matrix and the second matrix to obtain a noisy distance matrix, and generating an initial mapping relationship between each logical bit and a physical bit and initial optimized structure information without quantum gates; S5: Select quantum gates from the design structure information according to the execution sequence and execution dependency to update the preset front layer and expansion layer, and judge whether each quantum gate of the front layer meets the topological constraint. If so, add the quantum gates that meet the topological constraint to the optimized structure information in order and go to S9. Otherwise, when there are only two-bit gates in the front layer that do not meet the topological constraint, go to S6. S6: using the nearest neighbor heuristic function to determine multiple candidate switch gates according to the noisy distance matrix, the previous layer and the expansion layer, and randomly selecting a switch gate to be inserted; S7: For the exchange gate to be inserted, execute the insertion repeated exchange gate check strategy to determine whether the exchange gate is repeated within the preset insertion times, if so, go to S8, if not, insert the exchange gate into the optimized structure information in order to update the current mapping and go to S9; S8: Select a two-bit gate from the previous layer, find the shortest path for it in the topological constraint graph according to the current mapping, construct a switching gate along the shortest path so that the selected two-bit gate satisfies the topological constraint, and insert the constructed switching gate into the optimized structure information; S9: Determine whether there are quantum gates in the design structure information that do not include the optimized structure information. If so, go to S5; otherwise, obtain the initial mapping relationship and the final optimized structure information.

2. The method according to claim 1, characterized in that Ways to generate the second matrix include: According to the error rate information, the correctness rate between each pair of physical bits that can act on the two-bit gate is determined; According to the topology constraint graph, determine the path between every two physical bits; Determine an estimated correctness of the circuit execution between each two physical bits according to the correctness between each pair of physical bits on the path between each two physical bits; According to the number of physical bits, a second matrix is ​​constructed, each element of which records the estimated correctness of the circuit execution between the corresponding physical bits.

3. The method according to claim 2, characterized in that Ways to obtain a noisy distance matrix include: <h2 style=";text-align:left;direction:ltr">D<h2 style=";text-align:left;direction:ltr"> N <h2 style=";text-align:left;direction:ltr"> (ω1D)<h2 style=";text-align:left;direction:ltr"> d <h2 style=";text-align:left;direction:ltr"> +ω2D<h2 style=";text-align:left;direction:ltr"> ESP Among them, D N represents the noisy distance matrix, D d Denotes the first matrix, D ESP represents the second matrix, ω1 represents D d The weight of D ESP The weights of , ω1 and ω2 are both positive real numbers.

4. The method according to claim 1, characterized in that: In step S5, the front layer is a set of quantum gates with the earliest execution order in the quantum gate sequence in the current state and without adding the optimized structure information, and the expansion layer is a set of quantum gates with the preset number of quantum gates closest to the front layer in the breadth-first search topological order.

5. The method according to claim 1, characterized in that Step S6 includes: S61: Simulate and set multiple exchange gates. For each exchange gate set in the simulation, use the nearest neighbor heuristic function to calculate the corresponding nearest neighbor function value in the following manner: Where |F| represents the number of two-bit gates in the previous layer F, g represents the two-bit gates in the previous layer F, and D N represents a noisy distance matrix, g.q0 represents a logic bit q0 in a two-bit gate g, g.q1 represents another logic bit q1 in a two-bit gate g, [π(g.q0)] represents the number of the physical bit corresponding to q0 obtained by using the analog mapping π after the exchange gate of the analog setting is changed, [π(g.q1)] represents the number of the physical bit corresponding to q1 obtained by using the analog mapping π after the exchange gate of the analog setting is changed, |E| represents the number of two-bit gates in the extended layer E, and W represents the preset weight; S62: selecting a preset number of exchange gates from all exchange gates set in simulation in the order of the nearest neighbor function values ​​from small to large and determining the minimum nearest neighbor function value; S63: respectively determining the absolute value of the difference between the nearest neighbor function value corresponding to a preset number of exchange gates and the minimum nearest neighbor function value, and retaining the exchange gates whose absolute values ​​are less than 1; S64: Randomly select a switch gate to be inserted from the reserved switch gates.

6. The method according to claim 5, characterized in that The preset number is 4.

7. The method according to any one of claims 1 to 6, characterized in that: Step S8 includes: constructing a switching gate according to the shortest path to allow the two endpoints of the selected two-bit gate to move toward the center of the shortest path, and finally acting on the selected two-bit gate at the intersection.

8. A computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: one or more processors; as well as A memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method of any one of claims 1-7 by executing the executable instructions.

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