Display device and working method thereof

Abstract

The invention discloses a display device and a working method thereof. The display device comprises a display panel; a memory storing a plurality of compensation signals respectively corresponding to a plurality of blocks of the display panel; and a driving controller receiving an input image signal, compensating the input image signal according to the plurality of compensation signals, and outputting an output image signal. The driving controller includes first to fourth memories for storing a plurality of compensation signals from the memories. The plurality of compensation signals stored in the memory includes: a first row compensation signal corresponding to a block disposed in a first row among the plurality of blocks; and a second row compensation signal corresponding to a block disposed in a second row among the plurality of blocks, a part of the first row compensation signal being stored in the first memory, another part of the first row compensation signal being stored in the second memory, and a part of the second row compensation signal being stored in the third memory. The other part of the second row compensation signal is stored in the fourth memory.

Description

Technical Field

[0001] The invention relates to a display device and a working method thereof. Background Art

[0002] The display device includes a display panel including a plurality of pixels, each of which can provide any one of various color lights such as red light, green light, and blue light.

[0003] The desired image can be displayed by adjusting the light emission intensity of each of the plurality of pixels. The size and arrangement of each of the plurality of pixels can be varied. Summary of the invention

[0004] An object of the present invention is to provide a display device that can compensate for image quality degradation due to characteristics of a display panel.

[0005] According to a feature of the present invention for achieving such a purpose, a display device includes: a display panel; a memory storing a plurality of compensation signals corresponding to a plurality of blocks of the display panel respectively; and a driving controller receiving an input image signal, compensating the input image signal according to the plurality of compensation signals, and outputting an output image signal. The driving controller includes: a first memory, a second memory, a third memory, and a fourth memory for storing the plurality of compensation signals from the memory; and a compensation unit compensating the input image signal according to the first compensation signal, the second compensation signal, the third compensation signal, and the fourth compensation signal from the first memory to the fourth memory, and outputting the output image signal. The plurality of compensation signals stored in the memory include: a first row compensation signal corresponding to a block arranged in a first row among the plurality of blocks; and a second row compensation signal corresponding to a block arranged in a second row among the plurality of blocks, a portion of the first row compensation signal being stored in the first memory, another portion of the first row compensation signal being stored in the second memory, a portion of the second row compensation signal being stored in the third memory, and another portion of the second row compensation signal being stored in the fourth memory.

[0006] In one embodiment, the compensation unit may read the first compensation signal to the fourth compensation signal from the first memory to the fourth memory simultaneously.

[0007] In one embodiment, the odd-numbered first row compensation signals in the first row compensation signals are stored in the first memory, the even-numbered first row compensation signals in the first row compensation signals are stored in the second memory, the odd-numbered second row compensation signals in the second row compensation signals are stored in the third memory, and the even-numbered second row compensation signals in the second row compensation signals are stored in the fourth memory.

[0008] In one embodiment, the compensation unit may include: a first correction value calculator, which outputs a first correction signal, a second correction signal, a third correction signal and a fourth correction signal corresponding to the input image signal according to the first compensation signal to the fourth compensation signal; a second correction value calculator, which outputs a final compensation signal according to the first correction signal to the fourth correction signal; and a compensator, which compensates the input image signal according to the final compensation signal and outputs the output image signal.

[0009] In one embodiment, the second correction value calculator may output the final compensation signal according to the first to fourth correction signals by bilinear interpolation.

[0010] In one embodiment, each of the first to fourth compensation signals may include a first compensation value related to the first image signal, a second compensation value related to the second image signal, and a third compensation value related to the third image signal.

[0011] In one embodiment, each of the first to fourth memories may include: a first sub-memory and a second sub-memory, used to store the first compensation value; a third sub-memory and a fourth sub-memory, used to store the second compensation value; and a fifth sub-memory and a sixth sub-memory, used to store the third compensation value.

[0012] In one embodiment, odd-numbered first compensation values ​​among the first compensation values ​​are stored in the first sub-memory, and even-numbered first compensation values ​​among the first compensation values ​​are stored in the second sub-memory.

[0013] In one embodiment, the first image signal may correspond to a first color, and the first compensation value may correspond to a plurality of gray levels of the first color.

[0014] In one embodiment, it may be that the first correction value calculator outputs the first correction signal corresponding to the first color of the first image signal based on any one of the odd-numbered first compensation values ​​stored in the first sub-memory and any one of the even-numbered first compensation values ​​stored in the second sub-memory.

[0015] In one embodiment, the display device may further include: a fifth memory for storing any one of the plurality of compensation signals as a reference compensation signal, and the first to fourth memories for storing differences between the plurality of compensation signals from the memory and the reference compensation signal.

[0016] In one embodiment, the sum of the sizes of each of the first memory to the fourth memory may be smaller than the size of the memory.

[0017] A display device according to one feature of the present invention includes: a display panel; a memory storing a plurality of compensation signals corresponding to a plurality of blocks of the display panel respectively; and a drive controller receiving an input image signal, compensating the input image signal according to the plurality of compensation signals, and outputting an output image signal. The drive controller includes a first memory, a second memory, a third memory, and a fourth memory for storing the plurality of compensation signals from the memory; a first correction value calculator outputting a first correction signal, a second correction signal, a third correction signal, and a fourth correction signal corresponding to the input image signal according to the first compensation signal, the second compensation signal, the third compensation signal, and the fourth compensation signal from the first memory to the fourth memory; a second correction value calculator outputting a final compensation signal according to the first correction signal to the fourth correction signal; and a compensator compensating the input image signal according to the final compensation signal and outputting the output image signal. The multiple compensation signals stored in the memory include: a first row compensation signal, corresponding to a block configured in a first row among the multiple blocks; and a second row compensation signal, corresponding to a block configured in a second row among the multiple blocks, a portion of the first row compensation signal is stored in the first memory, another portion of the first row compensation signal is stored in the second memory, a portion of the second row compensation signal is stored in the third memory, and another portion of the second row compensation signal is stored in the fourth memory.

[0018] In one embodiment, the odd-numbered first row compensation signals in the first row compensation signals are stored in the first memory, the even-numbered first row compensation signals in the first row compensation signals are stored in the second memory, the odd-numbered second row compensation signals in the second row compensation signals are stored in the third memory, and the even-numbered second row compensation signals in the second row compensation signals are stored in the fourth memory.

[0019] In one embodiment, each of the first to fourth compensation signals may include a first compensation value related to the first image signal, a second compensation value related to the second image signal, and a third compensation value related to the third image signal.

[0020] In one embodiment, each of the first to fourth memories may include: a first sub-memory and a second sub-memory, used to store the first compensation value; a third sub-memory and a fourth sub-memory, used to store the second compensation value; and a fifth sub-memory and a sixth sub-memory, used to store the third compensation value.

[0021] In one embodiment, odd-numbered first compensation values ​​among the first compensation values ​​are stored in the first sub-memory, and even-numbered first compensation values ​​among the first compensation values ​​are stored in the second sub-memory.

[0022] According to one feature of the present invention, an operating method of a display device including a memory for storing multiple compensation signals respectively corresponding to multiple blocks of a display panel includes: a step of storing a part of first-row compensation signals corresponding to blocks arranged in a first row among the multiple blocks in a first memory, and storing another part in a second memory; a step of storing a part of second-row compensation signals corresponding to blocks arranged in a second row among the multiple blocks in a third memory, and storing another part in a fourth memory; a step of receiving an input image signal; and a step of outputting an output image signal that compensates the input image signal based on the first compensation signal, the second compensation signal, the third compensation signal and the fourth compensation signal from the first memory to the fourth memory.

[0023] In one embodiment, the odd-numbered first row compensation signals in the first row compensation signals are stored in the first memory, the even-numbered first row compensation signals in the first row compensation signals are stored in the second memory, the odd-numbered second row compensation signals in the second row compensation signals are stored in the third memory, and the even-numbered second row compensation signals in the second row compensation signals are stored in the fourth memory.

[0024] In one embodiment, the sum of the sizes of each of the first memory to the fourth memory may be smaller than the size of the memory.

[0025] A display device according to one feature of the present invention includes: a display panel; a memory storing a plurality of compensation signals corresponding to a plurality of blocks of the display panel respectively; and a driving controller receiving an input image signal, compensating the input image signal according to the plurality of compensation signals, and outputting an output image signal. The driving controller includes: a first internal memory storing the plurality of compensation signals from the memory as internal compensation signals; a first memory, a second memory, a third memory, a fourth memory, a fifth memory, and a sixth memory storing the internal compensation signals from the first internal memory; and a compensation unit compensating the input image signal according to a first compensation signal, a second compensation signal, a third compensation signal, and a fourth compensation signal provided from a part of the first memory to the sixth memory, and outputting the output image signal, the plurality of compensation signals stored in the first internal memory including: a first row compensation signal corresponding to a block arranged in a first row among the plurality of blocks; and a second row compensation signal corresponding to a block arranged in a second row among the plurality of blocks, a part of the first row compensation signal being stored in the first memory, the third memory, and the fifth memory, and a part of the second row compensation signal being stored in the second memory, the fourth memory, and the sixth memory.

[0026] In one embodiment, the compensation unit may read the first compensation signal to the fourth compensation signal from a portion of the first memory to the sixth memory at the same time.

[0027] In one embodiment, the compensation unit may simultaneously read the first compensation signal to the fourth compensation signal from the first memory to the fourth memory in the first memory to the sixth memory, store a portion of the first row compensation signal in the fifth memory, and store a portion of the second row compensation signal in the sixth memory.

[0028] In one embodiment, the compensation unit may include: a first correction value calculator, which outputs a first correction signal, a second correction signal, a third correction signal and a fourth correction signal corresponding to the input image signal according to the first compensation signal to the fourth compensation signal; a second correction value calculator, which outputs a final compensation signal according to the first correction signal to the fourth correction signal; and a compensator, which compensates the input image signal according to the final compensation signal and outputs the output image signal.

[0029] In one embodiment, the second correction value calculator may output the final compensation signal according to the first to fourth correction signals by bilinear interpolation.

[0030] In one embodiment, each of the first to fourth compensation signals may include a first compensation value related to the first image signal, a second compensation value related to the second image signal, and a third compensation value related to the third image signal.

[0031] In one embodiment, each of the first to sixth memories may include: a first sub-memory and a second sub-memory, used to store the first compensation value; a third sub-memory and a fourth sub-memory, used to store the second compensation value; and a fifth sub-memory and a sixth sub-memory, used to store the third compensation value.

[0032] In one embodiment, odd-numbered first compensation values ​​among the first compensation values ​​are stored in the first sub-memory, and even-numbered first compensation values ​​among the first compensation values ​​are stored in the second sub-memory.

[0033] In one embodiment, the first image signal may correspond to a first color, and the first compensation value may correspond to a plurality of gray levels of the first color.

[0034] In one embodiment, it may be that the first correction value calculator outputs the first correction signal related to the first color of the first image signal based on any one of the odd-numbered first compensation values ​​stored in the first sub-memory and any one of the even-numbered first compensation values ​​stored in the second sub-memory.

[0035] The drive controller of the display device having such a structure includes first to fourth memories for storing a plurality of compensation signals stored in the memory. The drive controller stores only a portion of the plurality of compensation signals stored in the memory in the first to fourth memories. Therefore, the size of the first to fourth memories in the drive controller can be minimized, and the power consumption of the display device can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a block diagram of a display device according to an embodiment of the present invention.

[0037] Figure 2 is a block diagram showing a structure of a driving controller according to an embodiment of the present invention.

[0038] Figure 3 It is used to illustrate Figure 1 A diagram showing the characteristics of the display panel.

[0039] Figure 4a as well as Figure 4b A diagram for explaining a method of obtaining a compensation signal by sensing characteristics of a display panel.

[0040] Figure 5 The eleventh to sixty-seventh compensation signals stored in the second external memory are exemplarily shown.

[0041] Figure 6 Compensation values ​​respectively corresponding to the first image signal, the second image signal, and the third image signal included in the eleventh compensation signal are exemplarily shown.

[0042] Figure 7 is a block diagram of an image processor according to an embodiment of the present invention.

[0043] Figure 8 is a diagram exemplarily showing first to fourth memories.

[0044] Fig. 9 is a diagram exemplarily showing a method of calculating a compensation signal corresponding to a pixel position of a display panel based on a compensation signal stored in a second external memory.

[0045] Figures 10a to 10f 2 is a diagram exemplarily showing compensation signals stored in the internal memory in order to calculate compensation signals corresponding to pixels in the eleventh to seventeenth blocks and the twenty-first to twenty-seventh blocks.

[0046] Fig.11 2 is a diagram exemplarily showing compensation signals stored in the internal memory in order to calculate compensation signals corresponding to pixels in the 21st to 27th blocks and the 31st to 37th blocks.

[0047] Fig.12a as well as Figure 12b 2 is a diagram exemplarily showing compensation signals stored in the internal memory in order to calculate compensation signals corresponding to pixels in the 21st to 27th blocks and the 31st to 37th blocks.

[0048] Fig.13 2 is a diagram exemplarily showing compensation signals stored in the internal memory in order to calculate compensation signals corresponding to pixels in the eleventh to seventeenth blocks and the twenty-first to twenty-seventh blocks.

[0049] Fig.14 FIG. 4 is a diagram exemplarily showing a structure of a first memory according to an embodiment of the present invention.

[0050] Fig.15 FIG. 4 is a diagram exemplarily showing a structure of a first memory according to an embodiment of the present invention.

[0051] Fig.16 is a block diagram of a display device according to an embodiment of the present invention.

[0052] Fig.17is a block diagram showing a structure of a driving controller according to an embodiment of the present invention.

[0053] Fig.18 is a block diagram of an image processor according to an embodiment of the present invention.

[0054] Figures 19a to 19f FIG. 1 is a diagram exemplarily showing the reading and writing operations of the first to sixth memories.

[0055] Fig. 20 FIG. 4 is a diagram exemplarily showing a structure of a first memory according to an embodiment of the present invention.

[0056] Fig.21 FIG. 4 is a diagram exemplarily showing a structure of a first memory according to an embodiment of the present invention.

[0057] Fig. 22 is a block diagram of an image processor according to an embodiment of the present invention.

[0058] Fig.23a It is shown by way of example Fig.18 A diagram showing the operation timing of a channel between a first memory and a first correction value calculator is shown.

[0059] Figure 23b It is shown by way of example Fig. 22 A diagram showing a channel between a first memory and a first correction value calculator and an operation timing of the channel between the first memory and the first correction value calculator.

[0060] Fig.24a as well as Figure 24b A diagram for explaining a method of obtaining a compensation signal by sensing characteristics of a display panel.

[0061] (Explanation of Reference Numerals)

[0062] DD: Display Device

[0063] DP: Display Panel

[0064] 100: Drive controller

[0065] 102: Image Processor

[0066] 104: Control signal generating unit

[0067] 110: Internal memory

[0068] 120: First correction value calculator

[0069] 130: Second correction value calculator

[0070] 140: Compensator

[0071] 200: Data drive circuit

[0072] 300: Scanning drive circuit

[0073] 400: Voltage generator

[0074] 500: Memory

[0075] M1-M4: first to fourth memory DETAILED DESCRIPTION

[0076] In this specification, when any constituent element (or region, layer, part, etc.) is mentioned as being "on" other constituent elements, "connected to" or "combined to" other constituent elements, it means that it can be directly configured / connected / combined to other constituent elements or a third constituent element can be configured between them.

[0077] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for the effective description of the technical content. "And / or" includes all combinations that can be defined by the associated structure.

[0078] The terms "first", "second" and the like may be used to describe various constituent elements, but the above constituent elements cannot be limited by the above terms. The above terms are used only for the purpose of distinguishing one constituent element from other constituent elements. For example, without departing from the scope of the present invention, the first constituent element may be named as the second constituent element, and similarly, the second constituent element may be named as the first constituent element. Unless clearly indicated differently in the context, a singular expression includes a plural expression.

[0079] In addition, the terms such as “below”, “lower side”, “above”, and “upper side” are used to explain the relationship between the structures shown in the drawings. The above terms are relative concepts and are explained based on the directions shown in the drawings.

[0080] Terms such as "including" or "having" should be understood as specifying the presence of features, numbers, steps, tasks, constituent elements, parts or these combinations recorded in the specification, and do not preclude the existence or additional possibility of one or more other features or numbers, steps, tasks, constituent elements, parts or these combinations.

[0081] Unless defined differently, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those generally understood by those skilled in the art to which the present invention belongs. In addition, terms that are the same as terms defined in commonly used dictionaries should be interpreted as having the same meanings as those in the context of the related art, and unless clearly defined herein, should not be interpreted as having very idealized or overly formalized meanings.

[0082] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0083] Figure 1 is a block diagram of a display device DD according to an embodiment of the present invention.

[0084] Reference Figure 1 , the display device DD includes a driving controller 100, a data driving circuit 200, a scan driving circuit 300, a voltage generator 400, a first external memory 500, a second external memory 600, and a display panel DP.

[0085] The driving controller 100 receives the input image signal I_RGB and the control signal CTRL. The driving controller 100 provides the data control signal DCS and the output image signal O_RGB to the data driving circuit 200. The driving controller 100 provides the scan control signal SCS to the scan driving circuit 300.

[0086] The data driving circuit 200 receives the data control signal DCS and the output image signal O_RGB from the driving controller 100. The data driving circuit 200 converts the output image signal O_RGB into a data signal and outputs the data signal to a plurality of data lines DL1-DLm described later. The data signal is an analog voltage corresponding to the output image signal O_RGB.

[0087] The scan driving circuit 300 receives a scan control signal SCS from the driving controller 100. The scan driving circuit 300 outputs a scan signal to a plurality of scan lines SL1-SLn described later. In one embodiment, the scan signals provided to the plurality of scan lines SL1-SLn may be sequentially transformed into an active level.

[0088] The display panel DP according to an embodiment of the present invention may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting substance. The light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting substance. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, in this embodiment, the display panel DP is described as an organic light-emitting display panel.

[0089] The display panel DP includes scan lines SL1 -SLn, data lines DL1 -DLm, and pixels PX.

[0090] Each of the pixels PX may be connected to a corresponding scan line among the scan lines SL1-SLn and to a corresponding data line among the data lines DL1-DLm. Figure 1 1 and 2. It is shown that one pixel PX is connected to one scan line, but the present invention is not limited thereto. One pixel PX may be electrically connected to more than two scan lines.

[0091] Each pixel PX may include a light emitting element (not shown) and a pixel circuit (not shown) for controlling the light emission of the light emitting element. In one embodiment, the light emitting element may be an organic light emitting diode. However, the present invention is not limited thereto.

[0092] The scan lines SL1-SLn extend from the scan driving circuit 300 in the first direction DR1 and are spaced apart from each other in the second direction DR2. The data lines DL1-DLm extend from the data driving circuit 200 in the second direction DR2 and are spaced apart from each other in the first direction DR1.

[0093] The scan driving circuit 300 may be disposed on the display panel DP. In one embodiment, the pixel PX may be disposed in the display area DA of the display panel DP, and the scan driving circuit 300 may be disposed in the non-display area NDA. In one embodiment, the scan driving circuit 300 may be formed by the same process as the pixel circuit of each pixel PX, but the present invention is not limited thereto.

[0094] In one embodiment, the data driving circuit 200 may be implemented by an integrated circuit and mounted on the display panel DP.

[0095] The voltage generator 400 provides voltages required for the operation of the display panel DP, for example, a first voltage ELVDD, a second voltage ELVSS, and a third voltage VINT. The number of voltages generated by the voltage generator 400 may be variously modified.

[0096] The first external memory 500 stores the compensation signal CCa. The second external memory 600 stores the compensation signal CCb. In one embodiment, the first external memory 500 is a non-volatile memory (eg, flash memory), and the second external memory 600 is a RAM (random access memory) (eg, DDR memory).

[0097] The driving controller 100 may read the compensation signal CCa from the first external memory 500 and store it in the second external memory 600. The driving controller 100 may read the compensation signal CCb from the second external memory 600. The driving controller 100 may compensate the input image signal I_RGB according to the compensation signal CCb and output the output image signal O_RGB.

[0098] In an embodiment, the compensation signal CCb may include a compensation value according to characteristics of the display panel DP.

[0099] Figure 2 is a block diagram showing a structure of a driving controller 100 according to an embodiment of the present invention.

[0100] Reference Figure 1 as well as Figure 2 The driving controller 100 includes an image processor 102 and a control signal generating unit 104 .

[0101] The image processor 102 receives an input image signal I_RGB and a control signal CTRL. The image processor 102 reads a compensation signal CCa from the first external memory 500 and stores it in the second external memory 600. The image processor 102 compensates the input image signal I_RGB according to the compensation signal CCb stored in the second external memory 600, and outputs an output image signal O_RGB. In one embodiment, the compensation signal CCa read from the first external memory 500 and the compensation signal CCb stored in the second external memory 600 may be identical to each other.

[0102] The control signal generating section 104 receives the control signal CTRL. The control signal generating section 104 outputs a data control signal DCS to be supplied to the data driving circuit 200. The control signal generating section 104 outputs a scan control signal SCS to be supplied to the scan driving circuit 300.

[0103] Figure 3 It is used to illustrate Figure 1 A diagram showing characteristics of the display panel DP.

[0104] Reference Figure 1 as well as Figure 3 , the input image signal I_RGB may include a first image signal (referred to as R) corresponding to a first color, a second image signal (referred to as G) corresponding to a second color, and a third image signal (referred to as B) corresponding to a third color.

[0105] exist Figure 3 In the example shown, each of the first image signal R, the second image signal G, and the third image signal B may have a gray scale from 0 to 255.

[0106] The brightness of the image displayed on the display panel DP may be different from each other even if the gray scale of each of the first image signal R, the second image signal G, and the third image signal B is the same. In addition, according to the characteristics of the display panel DP (for example, the characteristics of the light emitting element in the pixel PX and the process deviation of the transistor in the pixel PX, etc.), the brightness of the image related to each of the first image signal R, the second image signal G, and the third image signal B may be different.

[0107] Figure 4a as well as Figure 4b 2 is a diagram for explaining a method of obtaining a compensation signal by sensing the characteristics of the display panel DP.

[0108] Reference Figure 4a The display panel DP may be divided into a plurality of blocks. For example, the display panel DP may be divided into 7 blocks in the first direction DR1 and 6 blocks in the second direction DR2, that is, 42 blocks, that is, the eleventh to sixty-seventh blocks BK11-BK67.

[0109] In a state where the display panel DP displays a predetermined test image, a camera (not shown) or the like captures the display panel DP. In one embodiment, 42 cameras may capture the 11th to 67th blocks BK11-BK67, respectively. Based on the images obtained in the 42 cameras, the brightness of each of the 11th to 67th blocks BK11-BK67 may be sensed.

[0110] Reference Figure 4b , the test device (not shown) may generate eleventh to sixty-seventh compensation signals C11-C67 respectively related to the eleventh to sixty-seventh blocks BK11-BK67 according to the images displayed on the eleventh to sixty-seventh blocks BK11-BK67 and the brightness sensed by the 42 cameras. The eleventh to sixty-seventh compensation signals C11-C67 may be representative values ​​respectively related to the eleventh to sixty-seventh blocks BK11-BK67. Figure 4b In the figure, it is indicated as a circle so that it can be easily understood that the eleventh to sixty-seventh compensation signals C11-C67 correspond to the eleventh to sixty-seventh blocks BK11-BK67, respectively. In addition, it is assumed that the eleventh to sixty-seventh compensation signals C11-C67 correspond to the pixels (hereinafter, the center pixels) located at the center of the eleventh to sixty-seventh blocks BK11-BK67, respectively. For example, the eleventh compensation signal C11 is a representative value of the eleventh block BK11 and corresponds to the center pixel of the eleventh block BK11. The sixty-seventh compensation signal C67 is a representative value of the sixty-seventh block BK67 and corresponds to the center pixel of the sixty-seventh block BK67.

[0111] In one embodiment, a test device (not shown) may provide a data signal corresponding to each of the first image signal R, the second image signal G, and the third image signal B to the display panel DP, and obtain the following: Figure 3 Characteristics of the display panel DP shown.

[0112] The eleventh to sixty-seventh compensation signals C11-C67 are stored in the first external memory 500 (refer to Figure 2 That is, the compensation signal CCa stored in the first external memory 500 may include the eleventh to sixty-seventh compensation signals C11-C67 corresponding to the eleventh to sixty-seventh blocks BK11-BK67 of the display panel DP. The compensation signal CCa stored in the first external memory 500 may be stored in the second external memory 600 through the driving controller 100.

[0113] Figure 5 The compensation signal CCb stored in the second external memory 600 is exemplarily shown.

[0114] Reference Figure 2 as well as Figure 5 The compensation signal CCb stored in the second external memory 600 includes the eleventh to sixty-seventh compensation signals C11-C67. The eleventh to sixty-seventh compensation signals C11-C67 are respectively Figure 4b The eleventh to sixty-seventh blocks BK11 - BK67 of the display panel DP shown correspond.

[0115] Each of the eleventh to sixty-seventh compensation signals C11 - C67 may include a compensation value related to each of the first image signal R, the second image signal G, and the third image signal B included in the input image signal I_RGB.

[0116] Figure 6 Compensation values ​​respectively corresponding to the first image signal R, the second image signal G, and the third image signal B included in the eleventh compensation signal C11 are exemplarily shown.

[0117] In one embodiment, if each of the first image signal R, the second image signal G, and the third image signal B is 13 bits, each of the first image signal R, the second image signal G, and the third image signal B may have a gray scale from 0 to 8191, that is, 8192 gray scales. In one embodiment, each of the eleventh to sixty-seventh compensation signals C11-C67 may include only compensation values ​​associated with predetermined 96 gray scales among the 8192 gray scales from 0 to 8191.

[0118] The eleventh compensation signal C11 includes a first compensation value C11_R related to the first image signal R, a second compensation value C11_G related to the second image signal G, and a third compensation value C11_B related to the third image signal B.

[0119] The first compensation value C11_R includes compensation values ​​a0-a95 related to 96 grayscales of the first image signal R. The second compensation value C11_G includes compensation values ​​b0-b95 related to 96 grayscales of the second image signal G. The third compensation value C11_B includes compensation values ​​c0-c95 related to 96 grayscales of the third image signal B.

[0120] That is, the eleventh compensation signal C11 includes compensation values ​​a0-a95, b0-b95, c0-c95. Each of the compensation values ​​a0-a95, b0-b95, c0-c95 may be 13 bits.

[0121] Figure 5 Each of the eleventh to sixty-seventh compensation signals C11-C67 shown stored in the second external memory 600 may include Figure 6 The first compensation value C11_R, the second compensation value C11_G and the third compensation value C11_B of the eleventh compensation signal C11 are similar to the first compensation value, the second compensation value and the third compensation value.

[0122] Figure 5 The bit width of each of the eleventh to sixty-seventh compensation signals C11 - C67 stored in the second external memory 600 may be shown to be (the number of gray scales)×(the bit width of the compensation value)×(the number of image signals).

[0123] That is, the bit width of each of the eleventh to sixty-seventh compensation signals C11-C67 is 96×13×3=3744 bits.

[0124] If 42 compensation signals, ie, the eleventh to sixty-seventh compensation signals C11 - C67 , are stored in the second external memory 600 , the minimum size of the second external memory 600 is 3744×42=157,248 bits.

[0125] In order to quickly execute the compensation procedure, the image processor 102 loads the compensation signal CCb stored in the second external memory 600 into the internal memory. In this case, the image processor 102 needs to include an internal memory with a minimum size of 157,248 bits.

[0126] Figure 7 is a block diagram of an image processor 102 according to an embodiment of the present invention.

[0127] Reference Figure 7, the image processor 102 includes an internal memory 110 and a compensation unit.

[0128] The internal memory 110 includes first to fourth memories M1, M2, M3, and M4. The compensation signal CCb provided from the second external memory 600 may be stored in the first to fourth memories M1, M2, M3, and M4. In one embodiment, the internal memory 110 may be a volatile memory (e.g., SRAM, DRAM). In one embodiment, each of the first to fourth memories M1, M2, M3, and M4 of the internal memory 110 may be a register.

[0129] The first to fourth memories M1, M2, M3, M4 are physically independent of each other, that is, the first to fourth memories M1, M2, M3, M4 can be accessed at the same time.

[0130] The compensation part compensates the input image signal I_RGB according to the first to fourth compensation signals A, B, C, D read from the first to fourth memories M1, M2, M3, M4, and outputs the output image signal O_RGB. The compensation part includes a first correction value calculator 120, a second correction value calculator 130, and a compensator 140.

[0131] The first correction value calculator 120 reads the first to fourth compensation signals A, B, C, D from the first to fourth memories M1, M2, M3, M4. The first correction value calculator 120 outputs first to fourth correction signals A1, B1, C1, D1 corresponding to the input image signal I_RGB according to the first to fourth compensation signals A, B, C, D.

[0132] The second correction value calculator 130 outputs a final compensation signal CV according to the first to fourth correction signals A1 , B1 , C1 , and D1 .

[0133] The compensator 140 compensates the input image signal I_RGB according to the final compensation signal CV and outputs an output image signal O_RGB.

[0134] Figure 8 2 is a diagram exemplarily showing first to fourth memories M1 , M2 , M3 , and M4 .

[0135] Reference Figure 4a , Figure 5 , Figure 7 as well as Figure 8 Each of the first memory M1 and the third memory M3 has a size capable of storing four compensation signals among the eleventh to sixty-seventh compensation signals C11-C67. Each of the second memory M2 and the fourth memory M4 has a size capable of storing three compensation signals among the eleventh to sixty-seventh compensation signals C11-C67. Figure 8The size of each of the first to fourth memories M1, M2, M3, and M4 shown is only an example, and the present invention is not limited thereto. Figure 4a The number of blocks BK11-BK67 shown, the size of each of the first to fourth memories M1, M2, M3, M4 can be changed. For example, when the number of blocks in the first direction DR1 of the display panel DP is 8, each of the first to fourth memories M1, M2, M3, M4 can have a size capable of storing 4 compensation signals.

[0136] As exemplarily described above, the bit width of each of the eleventh to sixty-seventh compensation signals C11-C67 may be 96×13×3=3744 bits. In this case, the size of each of the first memory M1 and the third memory M3 may be 3744×4=14,976 bits. In addition, the size of each of the second memory M2 and the fourth memory M4 may be 3744×3=11,232 bits. That is, the overall size of the internal memory 110 may be 26,208 bits. The overall size of the internal memory 110, that is, the sum of the sizes of each of the first to fourth memories M1, M2, M3, and M4 is less than the size of the second external memory 600.

[0137] 42 compensation signals, namely, the eleventh to sixty-seventh compensation signals C11-C67, are stored in the second external memory 600, but only 14 compensation signals are stored in the internal memory 110. Figure 8 In the example shown, in order to calculate compensation signals corresponding to pixels in the eleventh to seventeenth blocks BK11 - BK17 and the twenty-first to twenty-seventh blocks BK21 - BK27 , compensation signals C11 - C17 , C21 - C27 may be stored in the internal memory 110 .

[0138] Fig. 9 illustratively shows a method of calculating a compensation signal c corresponding to a pixel position XY of the display panel DP based on the compensation signal CCb stored in the second external memory 600.

[0139] Reference Figure 4a , Figure 5 as well as Fig. 9 , the eleventh to sixty-seventh compensation signals C11-C67 correspond to the eleventh to sixty-seventh blocks BK11-BK67 of the display panel DP, respectively. It is assumed that each of the eleventh to sixty-seventh compensation signals C11-C67 corresponds to a pixel (central pixel) located at the center of a corresponding block in the eleventh to sixty-seventh blocks BK11-BK67.

[0140] The compensation signal c corresponding to the pixels located between the center pixels of the eleventh, twelfth, twenty-first and twenty-second blocks BK11, BK12, BK21 and BK22 can be calculated by interpolation based on the eleventh, twelfth, twenty-first and twenty-second compensation signals C11, C12, C21 and C22.

[0141] exist Fig. 9 In the example shown, the compensation signal a corresponding to the pixel located between the center pixels of the eleventh and twenty-first blocks BK11 and BK21 can be calculated by linear interpolation based on the eleventh and twenty-first compensation signals C11 and C21. The compensation signal b corresponding to the pixel located between the center pixels of the twelfth and twenty-second blocks BK12 and BK22 can be calculated by linear interpolation based on the twelfth and twenty-second compensation signals C12 and C22.

[0142] The compensation signal c can be calculated according to the compensation signal a and the compensation signal b by linear interpolation.

[0143] For example, the compensation signal c can be calculated by equation 1.

[0144] [Mathematical formula 1]

[0145] c=((a×d2)+(b×d1)) / (d1+d2)

[0146] In order to calculate the compensation signal c corresponding to the pixels configured between the eleventh, twelfth, twenty-first and twenty-second blocks BK11, BK12, BK21 and BK22, four compensation signals, namely the eleventh, twelfth, twenty-first and twenty-second compensation signals C11, C12, C21 and C22, are required.

[0147] That is, the compensation signal c can be calculated according to the eleventh, twelfth, twenty-first, and twenty-second compensation signals C11, C12, C21, and C22 by bilinear interpolation.

[0148] Figures 10a to 10f illustratively shows compensation signals stored in the internal memory 110 in order to calculate compensation signals corresponding to pixels in the eleventh to seventeenth blocks BK11 - BK17 and the twenty-first to twenty-seventh blocks BK21 - BK27 .

[0149] Reference Figure 4a , Figure 4b , Figure 7 , Fig. 9 as well as Fig.10a , and the eleventh to seventeenth blocks BK11-BK17 (refer to Figure 4a) corresponding to the eleventh to seventeenth compensation signals C11-C17 (i.e., the first row compensation signals) are stored in the first memory M1 and the second memory M2. The odd-numbered compensation signals C11, C13, C15, and C17 of the eleventh to seventeenth compensation signals C11-C17 are stored in the first memory M1, and the even-numbered compensation signals C12, C14, and C16 are stored in the second memory M2.

[0150] In one embodiment, during the vertical blank period of the control signal CTRL, the eleventh to seventeenth compensation signals C11 - C17 may be stored in the first memory M1 and the second memory M2 .

[0151] The compensation signal corresponding to the pixel arranged on the upper side than the center pixel of each of the eleventh to seventeenth blocks BK11-BK17, that is, the pixel arranged in the first area AA1, can be calculated based on the eleventh to seventeenth compensation signals C11-C17. Therefore, it is preferred that the eleventh to seventeenth compensation signals C11-C17 are stored in the first memory M1 and the second memory M2 during the vertical blank period before the image processor 102 receives the valid input image signal I_RGB in one frame.

[0152] The compensation signal corresponding to the pixel between the center pixel of the eleventh block BK11 and the center pixel of the twelfth block BK12 can be calculated by linear interpolation based on the eleventh and twelfth compensation signals C11 and C12. The compensation signal corresponding to the pixel between the center pixel of the twelfth block BK12 and the center pixel of the thirteenth block BK13 can be calculated by linear interpolation based on the twelfth and thirteenth compensation signals C12 and C13. In this way, the compensation signal corresponding to the pixel between the center pixel of the thirteenth block BK13 and the center pixel of the fourteenth block BK14, the compensation signal corresponding to the pixel between the center pixel of the fourteenth block BK14 and the center pixel of the fifteenth block BK15, the compensation signal corresponding to the pixel between the center pixel of the fifteenth block BK15 and the center pixel of the sixteenth block BK16, and the compensation signal corresponding to the pixel between the center pixel of the sixteenth block BK16 and the center pixel of the seventeenth block BK17 can be calculated.

[0153] The twenty-first to twenty-seventh compensation signals C21-C27 (i.e., second row compensation signals) corresponding to the twenty-first to twenty-seventh blocks BK21-BK27 configured in the second row of the display panel DP are stored in the third memory M3 and the fourth memory M4. The odd-numbered compensation signals C21, C23, C25, and C27 of the twenty-first to twenty-seventh compensation signals C21-C27 are stored in the third memory M3, and the even-numbered compensation signals C22, C24, and C26 are stored in the fourth memory M4.

[0154] In one embodiment, while the image processor 102 calculates the compensation signal of the first area AA1 according to the eleventh to seventeenth compensation signals C11 - C17 , the twenty-first to twenty-seventh compensation signals C21 - C27 need to be stored in the third memory M3 and the fourth memory M4 .

[0155] The second area AA2 is an area between the central pixels of the eleventh to seventeenth blocks BK11-BK17 and the central pixels of the twenty-first to twenty-seventh blocks BK21-BK27. Compensation signals of the pixels of the second area AA2 may be calculated based on the eleventh to seventeenth compensation signals C11-C17 and the twenty-first to twenty-seventh compensation signals C21-C27.

[0156] In order to calculate the compensation signals corresponding to the pixels located between the center pixels of the eleventh, twelfth, twenty-first and twenty-second blocks BK11, BK12, BK21 and BK22, four compensation signals, namely the eleventh, twelfth, twenty-first and twenty-second compensation signals C11, C12, C21 and C22, are required.

[0157] The first correction value calculator 120 receives the eleventh compensation signal C11 from the first memory M1, the twelfth compensation signal C12 from the second memory M2, the twenty-first compensation signal C21 from the third memory M3, and the twenty-second compensation signal C22 from the fourth memory M4 as the first to fourth compensation signals A, B, C, D.

[0158] The first to fourth memories M1, M2, M3, M4 are physically independent from each other and thus can be accessed simultaneously. The first correction value calculator 120 can simultaneously receive the first to fourth compensation signals A, B, C, D from the first to fourth memories M1, M2, M3, M4.

[0159] Therefore, the first correction value calculator 120 can simultaneously receive the eleventh, twelfth, twenty-first and twenty-second compensation signals C11, C12, C21 and C22 for calculating compensation signals corresponding to pixels located between the central pixels of the eleventh, twelfth, twenty-first and twenty-second blocks BK11, BK12, BK21 and BK22.

[0160] The eleventh compensation signal C11 includes Figure 6 The first compensation value C11_R related to the first image signal R, the second compensation value C11_G related to the second image signal G, and the third compensation value C11_B related to the third image signal B are shown.

[0161] exist Figure 6In the example shown, if the grayscale of the first image signal R included in the input image signal I_RGB is 150, the first correction value calculator 120 can calculate the compensation value corresponding to the grayscale of the first image signal R (i.e., 150) by interpolation based on the compensation value a1 when the grayscale is 80 and the compensation value a2 when the grayscale is 162.

[0162] In this way, the first correction value calculator 120 outputs the first correction signal A1 corresponding to the input image signal I_RGB according to the first compensation value C11_R related to the first image signal R, the second compensation value C11_G related to the second image signal G, and the third compensation value C11_B related to the third image signal B of the eleventh compensation signal C11.

[0163] In addition, in the same manner, the first correction value calculator 120 can calculate the first compensation value related to the first image signal R, the second compensation value related to the second image signal G, and the third compensation value related to the third image signal B of each of the twelfth, twenty-first, and twenty-second compensation signals C12, C21, and C22, and output the second to fourth correction signals B1, C1, and D1 corresponding to the input image signal I_RGB.

[0164] The second correction value calculator 130 calculates a compensation signal c corresponding to the pixel position XY according to the first to fourth correction signals A1, B1, C1, D1.

[0165] The second correction value calculator 130 calculates compensation signal a according to the first and third correction signals A1 and C1. The second correction value calculator 130 calculates compensation signal b according to the second and fourth correction signals B1 and D1. The second correction value calculator 130 calculates compensation signal c according to the compensation signals a and b using equation 1.

[0166] In this way, the second correction value calculator 130 can calculate the compensation signal c corresponding to the pixel position XY according to the first to fourth correction signals A1, B1, C1, and D1 by bilinear interpolation.

[0167] The second correction value calculator 130 may output the compensation signal c as a final compensation signal CV.

[0168] Reference Figure 4a , Figure 7 as well as Fig.10b In order to calculate the compensation signals corresponding to the pixels located between the center pixels of the twelfth, thirteenth, twenty-second and twenty-third blocks BK12, BK13, BK22 and BK23, four compensation signals, namely the twelfth, thirteenth, twenty-second and twenty-third compensation signals C12, C13, C22 and C23, are required.

[0169] The first correction value calculator 120 can simultaneously receive the thirteenth compensation signal C13 from the first memory M1, the twelfth compensation signal C12 from the second memory M2, the twenty-third compensation signal C23 from the third memory M3, and the twenty-second compensation signal C22 from the fourth memory M4 as the first to fourth compensation signals A, B, C, and D.

[0170] Reference Figure 4a , Figure 7 as well as Fig.10c In order to calculate the compensation signals corresponding to the pixels located between the center pixels of the thirteenth, fourteenth, twenty-third and twenty-fourth blocks BK13, BK14, BK23 and BK24, four compensation signals are required, namely the thirteenth, fourteenth, twenty-third and twenty-fourth compensation signals C13, C14, C23 and C24.

[0171] The first correction value calculator 120 can simultaneously receive the thirteenth compensation signal C13 from the first memory M1, the fourteenth compensation signal C14 from the second memory M2, the twenty-third compensation signal C23 from the third memory M3, and the twenty-fourth compensation signal C24 from the fourth memory M4 as the first to fourth compensation signals A, B, C, and D.

[0172] Reference Figure 4a , Figure 7 as well as Fig.10d In order to calculate the compensation signals corresponding to the pixels located between the center pixels of the fourteenth, fifteenth, twenty-fourth and twenty-fifth blocks BK14, BK15, BK24 and BK25, four compensation signals are required, namely the fourteenth, fifteenth, twenty-fourth and twenty-fifth compensation signals C14, C15, C24 and C25.

[0173] The first correction value calculator 120 can simultaneously receive the fifteenth compensation signal C15 from the first memory M1, the fourteenth compensation signal C14 from the second memory M2, the twenty-fifth compensation signal C25 from the third memory M3, and the twenty-fourth compensation signal C24 from the fourth memory M4 as the first to fourth compensation signals A, B, C, and D.

[0174] Reference Figure 4a , Figure 7 as well as Fig.10e In order to calculate the compensation signals corresponding to the pixels located between the center pixels of the fifteenth, sixteenth, twenty-fifth and twenty-sixth blocks BK15, BK16, BK25 and BK26, four compensation signals are required, namely the fifteenth, sixteenth, twenty-fifth and twenty-sixth compensation signals C15, C16, C25 and C26.

[0175] The first correction value calculator 120 can simultaneously receive the fifteenth compensation signal C15 from the first memory M1, the sixteenth compensation signal C16 from the second memory M2, the twenty-fifth compensation signal C25 from the third memory M3, and the twenty-sixth compensation signal C26 from the fourth memory M4 as the first to fourth compensation signals A, B, C, and D.

[0176] Reference Figure 4a , Figure 7 as well as Fig.10f In order to calculate the compensation signals corresponding to the pixels located between the center pixels of the sixteenth, seventeenth, twenty-sixth and twenty-seventh blocks BK16, BK17, BK26 and BK27, four compensation signals are required, namely the sixteenth, seventeenth, twenty-sixth and twenty-seventh compensation signals C16, C17, C26 and C27.

[0177] The first correction value calculator 120 can simultaneously receive the seventeenth compensation signal C17 from the first memory M1, the sixteenth compensation signal C16 from the second memory M2, the twenty-seventh compensation signal C27 from the third memory M3, and the twenty-sixth compensation signal C26 from the fourth memory M4 as the first to fourth compensation signals A, B, C, and D.

[0178] As in Figures 10a to 10f As described in , the final compensation signal CV corresponding to the pixels in the eleventh to seventeenth blocks BK11-BK17 and the twenty-first to twenty-seventh blocks BK21-BK27 can be calculated based on the eleventh to seventeenth compensation signals C11-C17 and the twenty-first to twenty-seventh compensation signals C21-C27 stored in the internal memory 110.

[0179] Even if the internal memory 110 stores only a portion of the compensation signals C11-C67 stored in the second external memory 600, the image processor 102 can sufficiently calculate the final compensation signal CV. Further, the first correction value calculator 120 can simultaneously read four compensation signals required to calculate the compensation signal corresponding to one pixel from the internal memory 110, thereby preventing the operating speed of the first correction value calculator 120 from being reduced.

[0180] Can be achieved through Figures 10a to 10f Calculated in the same way as described in Figure 4b The compensation signals of the pixels in the third area AA3, the fourth area AA4, the fifth area AA5, the sixth area AA6 and the seventh area AA7 are shown.

[0181] Fig.112 is a diagram exemplarily showing compensation signals stored in the internal memory 110 in order to calculate compensation signals corresponding to pixels in the twenty-first to twenty-seventh blocks BK21 - BK27 and the thirty-first to thirty-seventh blocks BK31 - BK37 .

[0182] As previously Figure 8 As described in , in order to calculate compensation signals corresponding to pixels in the eleventh to seventeenth blocks BK11 - BK17 and the twenty-first to twenty-seventh blocks BK21 - BK27 , the internal memory 110 stores compensation signals C11 - C17 , C21 - C27 .

[0183] Reference Figure 4a , Figure 7 as well as Fig.11 , the twenty-first to twenty-seventh compensation signals C21-C27 corresponding to the twenty-first to twenty-seventh blocks BK21-BK27 configured in the second row of the display panel DP have been stored in the third memory M3 and the fourth memory M4. Therefore, the thirty-first to thirty-seventh compensation signals C31-C37 corresponding to the thirty-first to thirty-seventh blocks BK31-BK37 configured in the third row of the display panel DP are stored in the first memory M1 and the second memory M2. The odd-numbered compensation signals C31, C33, C35, and C37 of the thirty-first to thirty-seventh compensation signals C31-C37 are stored in the first memory M1, and the even-numbered compensation signals C32, C34, and C36 are stored in the second memory M2.

[0184] Fig.12a as well as Figure 12b 2 is a diagram exemplarily showing compensation signals stored in the internal memory 110 in order to calculate compensation signals corresponding to pixels in the twenty-first to twenty-seventh blocks BK21 - BK27 and the thirty-first to thirty-seventh blocks BK31 - BK37 .

[0185] Reference Figure 4a , Figure 7 as well as Fig.12a In order to calculate the compensation signals corresponding to the pixels located between the center pixels of the twenty-first, twenty-second, thirty-first and thirty-second blocks BK21, BK22, BK31 and BK32, four compensation signals, namely the twenty-first, twenty-second, thirty-first and thirty-second compensation signals C21, C22, C31 and C32, are required.

[0186] The first correction value calculator 120 can simultaneously receive the thirty-first compensation signal C31 from the first memory M1, the thirty-second compensation signal C32 from the second memory M2, the twenty-first compensation signal C21 from the third memory M3, and the twenty-second compensation signal C22 from the fourth memory M4 as the first to fourth compensation signals A, B, C, and D.

[0187] Reference Figure 4a , Figure 7 as well as Figure 12b In order to calculate the compensation signals corresponding to the pixels located between the center pixels of the twenty-second, twenty-third, thirty-second and thirty-third blocks BK22, BK23, BK32 and BK33, four compensation signals, namely the twenty-second, twenty-third, thirty-second and thirty-third compensation signals C22, C23, C32 and C33, are required.

[0188] The first correction value calculator 120 can simultaneously receive the thirty-third compensation signal C33 from the first memory M1, the thirty-second compensation signal C32 from the second memory M2, the twenty-third compensation signal C23 from the third memory M3, and the twenty-second compensation signal C22 from the fourth memory M4 as the first to fourth compensation signals A, B, C, and D.

[0189] In this way, the first correction value calculator 120 may calculate compensation signals corresponding to pixels within the twenty-first to twenty-seventh blocks BK21 - BK27 and the thirty-first to thirty-seventh blocks BK31 - BK37 .

[0190] Fig.13 illustratively shows compensation signals stored in the internal memory 110 a in order to calculate compensation signals corresponding to pixels in the eleventh to seventeenth blocks BK11 - BK17 and the twenty-first to twenty-seventh blocks BK21 - BK27 .

[0191] Fig.13 The internal memory 110a shown includes first to fifth memories M1-M5.

[0192] Reference Figure 5 as well as Fig.13Each of the first memory M1 and the third memory M3 has a size capable of storing compensation signals C11a / C21a, C13a / C23a, C15a / C25a, and C17a / C27a corresponding to four compensation signals among the eleventh to sixty-seventh compensation signals C11-C67 from the second external memory 600. Each of the second memory M2 and the fourth memory M4 has a size capable of storing compensation signals C12a / C22a, C14a / C24a, and C16a / C26a corresponding to three compensation signals among the eleventh to sixty-seventh compensation signals C11-C67 from the second external memory 600.

[0193] The fifth memory M5 has a size capable of storing one compensation signal among the eleventh to sixty-seventh compensation signals C11-C67. The fifth memory M5 stores one compensation signal that becomes a reference among the eleventh to sixty-seventh compensation signals C11-C67. The fifth memory M5 can store one compensation signal that becomes a reference among the eleventh to sixty-seventh compensation signals C11-C67. Figure 4a The compensation signal (eg, C44 ) corresponding to any one of the blocks BK11 - BK67 (eg, the block BK44 located at the center of the display panel DP) is shown as the reference compensation signal CX.

[0194] Each of the compensation signals C11a-C17a stored in the first and second memories M1, M2 may be a difference between the reference compensation signal CX stored in the fifth memory M5 and each of the eleventh to seventeenth compensation signals C11-C17. Each of the compensation signals C21a-C27a stored in the third and fourth memories M3, M4 may be a difference between the reference compensation signal CX stored in the fifth memory M5 and each of the twenty-first to twenty-seventh compensation signals C21-C27.

[0195] For example, the compensation signal C11 a is the difference between the reference compensation signal CX and the compensation signal C11 , and the compensation signal C21 a is the difference between the reference compensation signal CX and the compensation signal C21 .

[0196] As exemplarily described above, the bit width of each of the eleventh to sixty-seventh compensation signals C11-C67 may be 96 (the number of gray scales)×13 (the first to third compensation values ​​C11_R, C11_G, C11_B (refer to Figure 6 )×3(R, G, B)=3744 bits.

[0197] When the bit width of each of the compensation signals C11a-C17a, C21a-C27a stored in the first to fourth memories M1-M4 (i.e., the bit width of each of the first to third compensation values ​​C11_R, C11_G, C11_B) is set to less than 13 bits, the size of the first to fourth memories M1-M4 can be reduced.

[0198] For example, if the bit width of each of the first to third compensation values ​​C11_R, C11_G, and C11_B is changed to 7 bits, the size of each of the first memory M1 and the third memory M3 is 96×7×3×4=8064 bits. In addition, the size of each of the second memory M2 and the fourth memory M4 can be 96×7×3×3=6048 bits.

[0199] The bit width of each of the first to third compensation values ​​C11_R, C11_G, C11_B in the compensation signals C11a-C17a, C21a-C27a stored in the first to fourth memories M1-M4 may be variously changed.

[0200] Fig.14 FIG. 4 is a diagram exemplarily showing a structure of a first memory M1 according to an embodiment of the present invention.

[0201] Reference Fig.14 , the first memory M1 includes a first sub-memory M1_R, a second sub-memory M1_G and a third sub-memory M1_B.

[0202] The eleventh compensation signal C11 stored in the first memory M1 includes a first compensation value C11_R related to the first image signal R, a second compensation value C11_G related to the second image signal G, and a third compensation value C11_B related to the third image signal B.

[0203] The first sub-memory M1_R stores a first compensation value C11_R related to the first image signal R. The second sub-memory M1_G stores a second compensation value C11_G related to the second image signal G. The third sub-memory M1_B stores a third compensation value C11_B related to the third image signal B.

[0204] In one embodiment, the first compensation value C11_R, the second compensation value C11_G, and the third compensation value C11_B may be Figure 6 The examples shown are the same.

[0205] Each of the thirteenth, fifteenth, and seventeenth compensation signals C13 , C15 , C17 stored in the first memory M1 may include first to third compensation values ​​similar to the eleventh compensation signal C11 .

[0206] The first memory M1 may include not only the first sub-memory M1_R, the second sub-memory M1_G, and the third sub-memory M1_B for storing the eleventh compensation signal C11, but also the sub-memory for storing the thirteenth, fifteenth, and seventeenth compensation signals C13, C15, and C17. The sub-memory for storing the thirteenth, fifteenth, and seventeenth compensation signals C13, C15, and C17 may include a structure similar to that of the first sub-memory M1_R, the second sub-memory M1_G, and the third sub-memory M1_B.

[0207] Fig.15 FIG. 4 is a diagram exemplarily showing a structure of a first memory M1 according to an embodiment of the present invention.

[0208] Reference Fig.15 , the first memory M1 includes first to sixth sub-memories M1_R1, M1_R2, M1_G1, M1_G2, M1_B1, and M1_B2.

[0209] The eleventh compensation signal C11 stored in the first memory M1 includes a first compensation value C11_R related to the first image signal R, a second compensation value C11_G related to the second image signal G, and a third compensation value C11_B related to the third image signal B.

[0210] The first compensation value C11_R includes a first sub-compensation value C11_R1 and a second sub-compensation value C11_R2. The first sub-memory M1_R1 stores the first sub-compensation value C11_R1. The second sub-memory M1_R2 stores the second sub-compensation value C11_R2.

[0211] The first sub-compensation value C11_R1 includes odd-numbered first compensation values ​​a0, a2, ..., a94 of the first compensation value C11_R. The second sub-compensation value C11_R2 includes even-numbered first compensation values ​​a1, a3, ..., a95 of the first compensation value C11_R.

[0212] The second compensation value C11_G includes a third sub-compensation value C11_G1 and a fourth sub-compensation value C11_G2. The third sub-memory M1_G1 stores the third sub-compensation value C11_G1. The fourth sub-memory M1_G2 stores the fourth sub-compensation value C11_G2.

[0213] The third sub-compensation value C11_G1 includes odd-numbered second compensation values ​​b0, b2, ..., b94 of the second compensation value C11_G. The fourth sub-compensation value C11_G2 includes even-numbered second compensation values ​​b1, b3, ..., b95 of the second compensation value C11_G.

[0214] The third compensation value C11_B includes a fifth sub-compensation value C11_B1 and a sixth sub-compensation value C11_B2. The fifth sub-memory M1_B1 stores the fifth sub-compensation value C11_B1. The sixth sub-memory M1_B2 stores the sixth sub-compensation value C11_B2.

[0215] The fifth sub-compensation value C11_B1 includes the odd-numbered third compensation values ​​c0, c2, ..., c94 of the third compensation value C11_B. The sixth sub-compensation value C11_B2 includes the even-numbered third compensation values ​​c1, c3, ..., c95 of the third compensation value C11_B.

[0216] The first memory M1 may include not only the first to sixth sub-memories M1_R1, M1_R2, M1_G1, M1_G2, M1_B1, M1_B2 for storing the eleventh compensation signal C11, but also sub-memories for storing the thirteenth, fifteenth and seventeenth compensation signals C13, C15, C17. The sub-memories for storing the thirteenth, fifteenth and seventeenth compensation signals C13, C15, C17 may include structures similar to those of the first to sixth sub-memories M1_R1, M1_R2, M1_G1, M1_G2, M1_B1, M1_B2.

[0217] If the grayscale of the first image signal R included in the input image signal I_RGB is 150, then Figure 7 The illustrated first correction value calculator 120 calculates a compensation value corresponding to the gray scale (ie, 150) of the first image signal R based on a compensation value a1 when the gray scale is 80 and a compensation value a2 when the gray scale is 162.

[0218] The compensation value a1 when the gray scale is 80 is stored in the second sub-memory M1_R2, and the compensation value a2 when the gray scale is 162 is stored in the first sub-memory M1_R1. Therefore, the first correction value calculator 120 can read the compensation values ​​a1 and a2 from the first sub-memory M1_R1 and the second sub-memory M1_R2 at the same time. Therefore, the operating speed of the first correction value calculator 120 can be prevented from being reduced.

[0219] Fig.16 is a block diagram of a display device DDa according to an embodiment of the present invention.

[0220] Reference Fig.16 The display device DDa includes a driving controller 1000, a data driving circuit 200, a scan driving circuit 300, a voltage generator 400, a first external memory 500, and a display panel DP. Figure 1The data driving circuit 200 , the scan driving circuit 300 , the voltage generator 400 , the first external memory 500 , and the display panel DP of the display device DD are the same, and thus are denoted by the same reference numerals, and repeated descriptions are omitted.

[0221] The first external memory 500 stores the compensation signal CCa. The driving controller 1000 may compensate the input image signal I_RGB according to the compensation signal CCa read from the first external memory 500 and output the output image signal O_RGB. In an embodiment, the compensation signal CCa may include a compensation value according to characteristics of the display panel DP.

[0222] Fig.17 is a block diagram showing a structure of a driving controller 1000 according to an embodiment of the present invention.

[0223] Reference Fig.16 as well as Fig.17 The driving controller 1000 includes an image processor 1020 and a control signal generating unit 1040 .

[0224] The image processor 1020 receives an input image signal I_RGB and a control signal CTRL. The image processor 1020 compensates the input image signal I_RGB according to a compensation signal CCa stored in the first external memory 500, and outputs an output image signal O_RGB.

[0225] The control signal generating part 1040 receives the control signal CTRL. The control signal generating part 1040 outputs the data control signal DCS to be provided to the data driving circuit 200. The control signal generating part 1040 outputs the scan control signal SCS to be provided to the scan driving circuit 300.

[0226] Fig.18 is a block diagram of an image processor 1020 according to an embodiment of the present invention.

[0227] Reference Fig.18 , the image processor 1020 includes a first internal memory 1100, a second internal memory 1200, and a compensation unit.

[0228] The compensation signal CCa provided from the first external memory 500 may be stored in the first internal memory 1100 as an internal compensation signal CCc.

[0229] The second internal memory 1200 includes first to sixth memories M11, M12, M13, M14, M15, and M16. The internal compensation signal CCc provided from the first internal memory 1100 may be stored in the first to sixth memories M11, M12, M13, M14, M15, and M16.

[0230] In one embodiment, the first external memory 500 may be a non-volatile memory (e.g., flash memory), and the first internal memory 1100 and the second internal memory 1200 may be volatile memories (e.g., SRAM, DRAM). In one embodiment, each of the first to sixth memories M11, M12, M13, M14, M15, and M16 of the second internal memory 1200 may be composed of registers.

[0231] To help understand the present embodiment, it is assumed that the internal compensation signal CCc provided by the first internal memory 1100 is Figure 5 That is, the internal compensation signal CCc includes the eleventh to sixty-seventh compensation signals C11-C67. The eleventh to sixty-seventh compensation signals C11-C67 are Figure 4a Each of the eleventh to sixty-seventh blocks BK11 - BK67 of the display panel DP shown corresponds.

[0232] The first to sixth memories M11, M12, M13, M14, M15, M16 are physically independent of each other, that is, the first to sixth memories M11, M12, M13, M14, M15, M16 can be accessed at the same time.

[0233] The compensation part compensates the input image signal I_RGB according to the first to sixth compensation signals A, B, C, D, E, F read from the first to sixth memories M11, M12, M13, M14, M15, M16, and outputs the output image signal O_RGB. The compensation part includes a first correction value calculator 1300, a second correction value calculator 1400, and a compensator 1500.

[0234] The first correction value calculator 1300 reads the first to sixth compensation signals A, B, C, D, E, F from the first to sixth memories M11, M12, M13, M14, M15, M16. The first correction value calculator 1300 outputs first to sixth correction signals A1, B1, C1, D1, E1, F1 corresponding to the input image signal I_RGB according to the first to sixth compensation signals A, B, C, D, E, F.

[0235] The second correction value calculator 1400 outputs a final compensation signal CV according to the first to sixth correction signals A1 , B1 , C1 , D1 , E1 , and F1 .

[0236] The compensator 1500 compensates the input image signal I_RGB according to the final compensation signal CV and outputs an output image signal O_RGB.

[0237] exist Fig.182 exemplarily shows and explains that the number of channels CH between the second internal memory 1200 and the first correction value calculator 1300 is 6 for the convenience of explanation, but the present invention is not limited thereto.

[0238] For example, the number of channels CH between the second internal memory 1200 and the first correction value calculator 1300 may be 4. The first correction value calculator 1300 may receive compensation signals from 4 memories of the first to sixth memories M11, M12, M13, M14, M15, and M16, and output 4 correction signals corresponding to the input image signal I_RGB according to the 4 compensation signals. This will be described in detail below.

[0239] Figures 19a to 19f 1 is a diagram exemplarily showing the reading and writing operations of the first to sixth memories M11 , M12 , M13 , M14 , M15 , and M16 .

[0240] Reference Figure 4a , Figure 5 , Fig.18 as well as Fig.19a The eleventh, twelfth and thirteenth compensation signals C11, C12 and C13 corresponding to the eleventh, twelfth and thirteenth blocks BK11, BK12 and BK13 arranged in the first row of the display panel DP are stored in the first, third and fifth memories M11, M13 and M15. The twenty-first, twenty-second and twenty-third compensation signals C21, C22 and C23 corresponding to the twenty-first, twenty-second and twenty-third blocks BK21, BK22 and BK23 arranged in the second row of the display panel DP are stored in the second, fourth and sixth memories M12, M14 and M16.

[0241] like Fig. 9 As shown, in order to calculate the compensation signal c corresponding to the pixel position XY, the first correction value calculator 1300 can simultaneously read the eleventh, twenty-first, twelfth, and twenty-second compensation signals C11, C21, C12, and C22 from the first to fourth memories M11, M12, M13, and M14 as the first to fourth compensation signals A, B, C, and D. During the period in which the first correction value calculator 1300 reads the eleventh, twenty-first, twelfth, and twenty-second compensation signals C11, C21, C12, and C22 from the first to fourth memories M11, M12, M13, and M14, the thirteenth and twenty-third compensation signals C13 and C23 in the internal compensation signal CCc stored in the first internal memory 1100 are stored in the fifth and sixth memories M15 and M16.

[0242] The first correction value calculator 1300 outputs first to fourth correction signals A1, B1, C1, D1 corresponding to the input image signal I_RGB according to the first to fourth compensation signals A, B, C, D.

[0243] The second correction value calculator 1400 calculates a compensation signal c corresponding to a pixel position XY located between the eleventh, twelfth, twenty-first, and twenty-second blocks BK11, BK12, BK21, and BK22 with the center position of each of the eleventh, twelfth, twenty-first, and twenty-second blocks BK11, BK12, BK21, and BK22 as a reference based on the first to fourth correction signals A1, B1, C1, and D1.

[0244] The second correction value calculator 1400 calculates the compensation signal a according to the first and third correction signals A1 and C1. The second correction value calculator 1400 calculates the compensation signal b according to the second and fourth correction signals B1 and D1. The second correction value calculator 130 calculates the compensation signal c according to the compensation signals a and b using equation 1.

[0245] Thus, the second correction value calculator 1400 can calculate the compensation signal c corresponding to the pixel position XY according to the first to fourth correction signals A1, B1, C1, D1 by bilinear interpolation and output the compensation signal c as the final compensation signal CV.

[0246] Reference Fig.18 as well as Fig.19b , the first correction value calculator 1300 can simultaneously read the twelfth, twenty-second, thirteenth, and twenty-third compensation signals C12, C22, C13, and C23 from the third to sixth memories M13, M14, M15, and M16 as the third to sixth compensation signals C, D, E, and F. During the period in which the first correction value calculator 1300 reads the third to sixth compensation signals C, D, E, and F from the third to sixth memories M13, M14, M15, and M16, the fourteenth and twenty-fourth compensation signals C14 and C24 in the internal compensation signal CCc stored in the first internal memory 1100 are stored in the first and second memories M11 and M12.

[0247] The first correction value calculator 1300 outputs third to sixth correction signals C1, D1, E1, F1 corresponding to the input image signal I_RGB according to the third to sixth compensation signals C, D, E, F.

[0248] The second correction value calculator 1400 calculates a final compensation signal CV according to the third to sixth correction signals C1 , D1 , E1 , and F1 .

[0249] Reference Fig.18 as well as Fig.19c, the first correction value calculator 1300 can simultaneously read the thirteenth, twenty-third, fourteenth, and twenty-fourth compensation signals C13, C23, C14, and C24 from the fifth, sixth, first, and second memories M15, M16, M11, and M12 as the fifth, sixth, first, and second compensation signals E, F, A, and B. During the period in which the first correction value calculator 1300 reads the thirteenth, twenty-third, fourteenth, and twenty-fourth compensation signals C13, C23, C14, and C24 from the fifth, sixth, first, and second memories M15, M16, M11, and M12, the fifteenth and twenty-fifth compensation signals C15 and C25 among the internal compensation signals CCc stored in the first internal memory 1100 are stored in the third and fourth memories M13 and M14.

[0250] The first correction value calculator 1300 outputs fifth, sixth, first and second correction signals E1, F1, A1, B1 corresponding to the input image signal I_RGB according to the fifth, sixth, first and second compensation signals E, F, A, B.

[0251] The second correction value calculator 1400 calculates a final compensation signal CV according to the fifth, sixth, first and second correction signals E1 , F1 , A1 , B1 .

[0252] Reference Fig.18 as well as Fig.19d , the first correction value calculator 1300 can simultaneously read the fourteenth, twenty-fourth, fifteenth, and twenty-fifth compensation signals C14, C24, C15, and C25 from the first to fourth memories M11, M12, M13, and M14 as the first to fourth compensation signals A, B, C, and D. During the period in which the first correction value calculator 1300 reads the fourteenth, twenty-fourth, fifteenth, and twenty-fifth compensation signals C14, C24, C15, and C25 from the first to fourth memories M11, M12, M13, and M14, the sixteenth and twenty-sixth compensation signals C16 and C26 among the internal compensation signals CCc stored in the first internal memory 1100 are stored in the fifth and sixth memories M15 and M16.

[0253] The first correction value calculator 1300 outputs first to fourth correction signals A1, B1, C1, D1 corresponding to the input image signal I_RGB according to the first to fourth compensation signals A, B, C, D.

[0254] The second correction value calculator 1400 calculates a final compensation signal CV according to the first to fourth correction signals A1 , B1 , C1 , and D1 .

[0255] Reference Fig.18 as well as Fig.19e, the first correction value calculator 1300 can simultaneously read the fifteenth, twenty-fifth, sixteenth, and twenty-sixth compensation signals C15, C25, C16, and C26 from the third to sixth memories M13, M14, M15, and M16 as the third to sixth compensation signals C, D, E, and F. During the period in which the first correction value calculator 1300 reads the third to sixth compensation signals C, D, E, and F from the third to sixth memories M13, M14, M15, and M16, the seventeenth and twenty-seventh compensation signals C17 and C27 among the internal compensation signals CCc stored in the first internal memory 1100 are stored in the first and second memories M11 and M12.

[0256] The first correction value calculator 1300 outputs third to sixth correction signals C1, D1, E1, F1 corresponding to the input image signal I_RGB according to the third to sixth compensation signals C, D, E, F.

[0257] The second correction value calculator 1400 calculates a final compensation signal CV according to the third to sixth correction signals C1 , D1 , E1 , and F1 .

[0258] Reference Fig.18 as well as Fig.19f , the first correction value calculator 1300 can simultaneously read the sixteenth, twenty-sixth, seventeenth, and twenty-seventh compensation signals C16, C26, C17, and C27 from the fifth, sixth, first, and second memories M15, M16, M11, and M12 as the fifth, sixth, first, and second compensation signals E, F, A, and B.

[0259] The first correction value calculator 1300 outputs fifth, sixth, first and second correction signals E1, F1, A1, B1 corresponding to the input image signal I_RGB according to the fifth, sixth, first and second compensation signals E, F, A, B.

[0260] The second correction value calculator 1400 calculates a final compensation signal CV according to the fifth, sixth, first and second correction signals E1 , F1 , A1 , B1 .

[0261] The image processor 1020 may be Figures 19a to 19f In the manner shown, the internal compensation signal CCc stored in the first internal memory 1100 is sequentially stored in the first to sixth memories M11-M16. In addition, the image processor 1020 can Figures 19a to 19f In the manner shown, the first to sixth memories M11-M16 are read in sequence. Figure 5 The eleventh to sixty-seventh compensation signals C11 - C67 are integrally output as the output image signal O_RGB.

[0262] Fig. 20FIG. 4 is a diagram exemplarily showing a structure of a first memory M11 according to an embodiment of the present invention.

[0263] Reference Fig. 20 , the first memory M11 includes a first sub-memory M11_R, a second sub-memory M11_G and a third sub-memory M11_B.

[0264] The eleventh compensation signal C11 stored in the first memory M11 includes a first compensation value C11_R related to the first image signal R, a second compensation value C11_G related to the second image signal G, and a third compensation value C11_B related to the third image signal B.

[0265] The first sub-memory M11_R stores a first compensation value C11_R related to the first image signal R. The second sub-memory M11_G stores a second compensation value C11_G related to the second image signal G. The third sub-memory M11_B stores a third compensation value C11_B related to the third image signal B.

[0266] In one embodiment, the first compensation value C11_R, the second compensation value C11_G, and the third compensation value C11_B may be Figure 6 The examples shown are the same.

[0267] Each of the compensation signals stored in the second to sixth memories M12 , M13 , M14 , M15 , M16 may include first to third compensation values ​​similar to the eleventh compensation signal C11 .

[0268] Fig.21 FIG. 4 is a diagram exemplarily showing a structure of a first memory M11 according to an embodiment of the present invention.

[0269] Reference Fig.21 , the first memory M11 includes first to sixth sub-memories M11_R1, M11_R2, M11_G1, M11_G2, M11_B1, and M11_B2.

[0270] The eleventh compensation signal C11 stored in the first memory M11 includes a first compensation value C11_R related to the first image signal R, a second compensation value C11_G related to the second image signal G, and a third compensation value C11_B related to the third image signal B.

[0271] The first compensation value C11_R includes a first sub-compensation value C11_R1 and a second sub-compensation value C11_R2. The first sub-memory M11_R1 stores the first sub-compensation value C11_R1. The second sub-memory M11_R2 stores the second sub-compensation value C11_R2.

[0272] The first sub-compensation value C11_R1 includes odd-numbered first compensation values ​​a0, a2, ..., a94 of the first compensation value C11_R. The second sub-compensation value C11_R2 includes even-numbered first compensation values ​​a1, a3, ..., a95 of the first compensation value C11_R.

[0273] The second compensation value C11_G includes a third sub-compensation value C11_G1 and a fourth sub-compensation value C11_G2. The third sub-memory M11_G1 stores the third sub-compensation value C11_G1. The fourth sub-memory M11_G2 stores the fourth sub-compensation value C11_G2.

[0274] The third sub-compensation value C11_G1 includes odd-numbered second compensation values ​​b0, b2, ..., b94 of the second compensation value C11_G. The fourth sub-compensation value C11_G2 includes even-numbered second compensation values ​​b1, b3, ..., b95 of the second compensation value C11_G.

[0275] The third compensation value C11_B includes a fifth sub-compensation value C11_B1 and a sixth sub-compensation value C11_B2. The fifth sub-memory M1_B1 stores the fifth sub-compensation value C11_B1. The sixth sub-memory M1_B2 stores the sixth sub-compensation value C11_B2.

[0276] The fifth sub compensation value C11_B1 stores odd-numbered third compensation values ​​c0, c2, ..., c94 of the third compensation value C11_B. The sixth sub compensation value C11_B2 stores even-numbered third compensation values ​​c1, c3, ..., c95 of the third compensation value C11_B.

[0277] If the grayscale of the first image signal R included in the input image signal I_RGB is 150, then Fig.18 The illustrated first correction value calculator 1300 calculates a compensation value corresponding to the gray scale (ie, 150) of the first image signal R based on a compensation value a1 when the gray scale is 80 and a compensation value a2 when the gray scale is 162.

[0278] The compensation value a1 when the gray scale is 80 is stored in the second sub-memory M11_R2, and the compensation value a2 when the gray scale is 162 is stored in the first sub-memory M11_R1. Thus, the first correction value calculator 1300 can read the compensation values ​​a1 and a2 from the first sub-memory M11_R1 and the second sub-memory M11_R2 at the same time. Therefore, the operating speed of the first correction value calculator 1300 can be prevented from being reduced.

[0279] In one embodiment, Fig.18 Each of the second to sixth memories M12-M16 shown may include Fig.21The first to sixth sub-memories M11_R1, M11_R2, M11_G1, M11_G2, M11_B1, and M11_B2 of the first memory M11 shown have the same structure.

[0280] Fig. 22 is a block diagram of an image processor 2000 according to an embodiment of the present invention.

[0281] Reference Fig. 22 The image processor 2000 includes a first internal memory 1100 , a second internal memory 1210 , a third internal memory 1220 , and a compensation unit. The compensation unit includes a first correction value calculator 1310 , a second correction value calculator 1410 , and a compensator 1510 .

[0282] The compensation signal CCa provided from the first external memory 500 may be stored in the first internal memory 1100 .

[0283] The second internal memory 1210 includes first to sixth memories M21, M22, M23, M24, M25, and M26. A portion of the internal compensation signal CCc provided from the first internal memory 1100 may be stored in the first to sixth memories M21, M22, M23, M24, M25, and M26.

[0284] The third internal memory 1220 includes first to sixth memories M31, M32, M33, M34, M35, and M36. A portion of the internal compensation signal CCc provided from the first internal memory 1100 may be stored in the first to sixth memories M31, M32, M33, M34, M35, and M36.

[0285] The first to sixth memories M21, M22, M23, M24, M25, M26 of the second internal memory 1210 and the first to sixth memories M31, M32, M33, M34, M35, M36 of the third internal memory 1220 are physically independent of each other. That is, the first to sixth memories M21, M22, M23, M24, M25, M26 of the second internal memory 1210 and the first to sixth memories M31, M32, M33, M34, M35, M36 of the third internal memory 1220 can be accessed at the same time.

[0286] The first correction value calculator 1310 outputs first to sixth correction signals A1, B1, C1, D1, E1, F1 corresponding to the input image signal I_RGB based on the first to sixth compensation signals Aa, Ba, Ca, Da, Ea, Fa read from the first to sixth memories M21, M22, M23, M24, M25, M26 of the second internal memory 1210.

[0287] The first correction value calculator 1310 outputs first to sixth correction signals A2, B2, C2, D2, E2, F2 corresponding to the input image signal I_RGB based on the first to sixth compensation signals Ab, Bb, Cb, Db, Eb, Fb read from the first to sixth memories M31, M32, M33, M34, M35, M36 of the third internal memory 1220.

[0288] The second correction value calculator 1410 outputs a final compensation signal CV1 according to the first to sixth correction signals A1, B1, C1, D1, E1, F1, and outputs a final compensation signal CV2 according to the first to sixth correction signals A2, B2, C2, D2, E2, F2.

[0289] The compensator 1510 compensates the input image signal I_RGB according to the final compensation signals CV1 and CV2 and outputs an output image signal O_RGB.

[0290] Fig.23a It is shown by way of example Fig.18 FIG. 1 is a diagram showing an operation timing of a channel CH between the first memory M11 and the first correction value calculator 1300. FIG.

[0291] Figure 23b It is shown by way of example Fig. 22 13 is a diagram showing the operation timing of a channel CHa between the first memory M21 and the first correction value calculator 1310 and a channel CHb between the first memory M31 and the first correction value calculator 1310.

[0292] In the following instructions, it is assumed that the configuration is Fig.16 The number of pixels PX in one row of the display panel DP, that is, the number of pixels PX arranged in the same row in the first direction DR1, is 3840.

[0293] Reference Fig.18 as well as Fig.23a , when the driving frequency of the image processor 1020 is 60 Hz, the first compensation signal A corresponding to 3840 pixels may be transmitted through the channel CH during one frame F1.

[0294] Reference Fig. 22 as well as Figure 23b When the driving frequency of the image processor 2000 is 120 Hz, the first compensation signal Aa corresponding to 1920 pixels may be transmitted through the channel CHa during one frame F1. In addition, the first compensation signal Ab corresponding to 1920 pixels may be transmitted through the channel CHb during one frame F1.

[0295] The image processor 2000 may include the second internal memory 1210 and the third internal memory 1220 while accessing the second internal memory 1210 and the third internal memory 1220 at the same time.

[0296] Thus, even if the driving frequency of the image processor 2000 becomes higher, sufficient time for transmitting the first compensation signal Aa and the first compensation signal Ab transmitted through the channels Cha and CHb can be ensured.

[0297] In one embodiment, it may be that Fig. 22 In the case where the image processor 2000 shown includes not only the second internal memory 1210 and the third internal memory 1220 but also the fourth internal memory, Fig. 20 The first compensation value C11_R related to the first image signal R is stored in the third internal memory 1220, the second compensation value C11_G related to the second image signal G is stored in the second internal memory 1210, and the third compensation value C11_B related to the third image signal B is stored in the fourth internal memory.

[0298] That is, by storing the compensation values ​​related to the first image signal R, the second image signal G, and the third image signal B separately in the second to fourth internal memories, even if the driving frequency of the image processor 2000 becomes high, the time for transmitting the signal through the channel between the second to fourth internal memories and the first correction value calculator 1310 can be sufficiently ensured. As a result, even if the display device DDa (refer to Fig.16 )’s driving frequency becomes higher, which can also improve working reliability.

[0299] Fig.24a as well as Figure 24b 2 is a diagram for explaining a method of obtaining a compensation signal by sensing the characteristics of the display panel DP.

[0300] Reference Fig.24a The display panel DP may be divided into a plurality of blocks. For example, the display panel DP may be divided into 7 blocks in the first direction DR1 and 6 blocks in the second direction DR2, that is, 42 blocks, that is, the eleventh to sixty-seventh blocks BK11a-BK67a.

[0301] In a state where the display panel DP displays a predetermined test image, a camera (not shown) or the like captures the display panel DP. In one embodiment, 42 cameras may capture the 11th to 67th blocks BK11a-BK67a, respectively. Based on the images obtained in the 42 cameras, the brightness of each of the 11th to 67th blocks BK11a-BK67a may be sensed.

[0302] Fig.24aThe lengths y1, y2, y3, y4, y5, y6 of each of the first to sixth rows in the eleventh to sixty-seventh blocks BK11a-BK67a of the display panel DP shown may be different from each other. The lengths x1, x2, x3, x4, x5, x6, x7 of each of the first to seventh columns in the eleventh to sixty-seventh blocks BK11a-BK67a of the display panel DP may be different from each other.

[0303] In one embodiment, the length y1, y2, y3, y4, y5, y6 of each of the first to sixth rows and the length x1, x2, x3, x4, x5, x6, x7 of each of the first to seventh columns may be determined according to characteristics of the display panel DP.

[0304] Reference Figure 24b , the test device (not shown) may generate eleventh to sixty-seventh compensation signals C11a-C67a respectively related to the eleventh to sixty-seventh blocks BK11a-BK67a according to the images displayed on the eleventh to sixty-seventh blocks BK11a-BK67a and the brightness sensed by the 42 cameras. The eleventh to sixty-seventh compensation signals C11a-C67a may be representative values ​​respectively related to the eleventh to sixty-seventh blocks BK11a-BK67a. Figure 24b In the figure, circles are shown to make it easy to understand that the eleventh to sixty-seventh compensation signals C11a-C67a correspond to the eleventh to sixty-seventh blocks BK11a-BK67a, respectively. In addition, it is assumed that the eleventh to sixty-seventh compensation signals C11a-C67a correspond to pixels located at the center of the eleventh to sixty-seventh blocks BK11a-BK67a, respectively.

[0305] In one embodiment, a test device (not shown) may provide a data signal corresponding to each of the first image signal R, the second image signal G, and the third image signal B to the display panel DP, and obtain the following: Figure 3 Characteristics of the display panel DP shown.

[0306] The eleventh to sixty-seventh compensation signals C11a-C67a are stored in the first external memory 500 (refer to Figure 2 That is, the compensation signal CCa stored in the first external memory 500 may include the eleventh to sixty-seventh compensation signals C11a-C67a corresponding to the eleventh to sixty-seventh blocks BK11a-BK67a of the display panel DP. The compensation signal CCa stored in the first external memory 500 may be stored in the second external memory 600 through the driving controller 100.

[0307] As in Fig. 9As described in , the compensation signal c corresponding to the pixel position XY of the display panel DP can be calculated by bilinear interpolation. By setting the length y1, y2, y3, y4, y5, y6 of each of the first to sixth rows and the length x1, x2, x3, x4, x5, x6, x7 of each of the first to seventh columns of the eleventh to sixty-seventh blocks BK11a-BK67a according to the characteristics of the display panel DP, the compensation signal c can be calculated in a manner suitable for the characteristics of each of the eleventh to sixty-seventh blocks BK11a-BK67a.

[0308] The above description is made with reference to the preferred embodiments of the present invention, but a person skilled in the art or a person with ordinary knowledge in the art will understand that various modifications and changes can be made to the present invention without departing from the concept and technical scope of the present invention as recorded in the attached claims. Therefore, the technical scope of the present invention is not limited to the contents recorded in the detailed description of the specification, but should be determined only by the claims.

Claims

1. A display device, in, include: Display panel; a memory storing a plurality of compensation signals respectively corresponding to a plurality of blocks of the display panel; as well as a driving controller that receives an input image signal, compensates the input image signal according to the plurality of compensation signals, and outputs an output image signal, The drive controller comprises: a first memory, a second memory, a third memory, and a fourth memory, for storing the plurality of compensation signals from the memory; and a compensation unit that compensates the input image signal according to the first compensation signal, the second compensation signal, the third compensation signal, and the fourth compensation signal from the first memory to the fourth memory, and outputs the output image signal, The plurality of compensation signals stored in the memory include: a first row compensation signal corresponding to blocks arranged in a first row among the plurality of blocks; and a second row compensation signal corresponding to blocks arranged in a second row among the plurality of blocks, A portion of the first row compensation signal is stored in the first memory, another portion of the first row compensation signal is stored in the second memory, a portion of the second row compensation signal is stored in the third memory, and another portion of the second row compensation signal is stored in the fourth memory.

2. The display device according to claim 1, in, The compensation section simultaneously reads the first compensation signal to the fourth compensation signal from the first memory to the fourth memory.

3. The display device according to claim 1, in, The odd-numbered first-row compensation signals among the first-row compensation signals are stored in the first memory, and the even-numbered first-row compensation signals among the first-row compensation signals are stored in the second memory, The odd-numbered second-row compensation signals among the second-row compensation signals are stored in the third memory, and the even-numbered second-row compensation signals among the second-row compensation signals are stored in the fourth memory.

4. The display device according to claim 1, in, The compensation unit comprises: a first correction value calculator, which outputs a first correction signal, a second correction signal, a third correction signal and a fourth correction signal corresponding to the input image signal according to the first compensation signal to the fourth compensation signal; a second correction value calculator, outputting a final compensation signal according to the first to fourth correction signals; and A compensator compensates the input image signal according to the final compensation signal and outputs the output image signal.

5. The display device according to claim 4, in, The second correction value calculator outputs the final compensation signal through bilinear interpolation according to the first to fourth correction signals.

6. The display device according to claim 4, in, Each of the first to fourth compensation signals includes a first compensation value related to the first image signal, a second compensation value related to the second image signal, and a third compensation value related to the third image signal.

7. The display device according to claim 6, in, Each of the first to fourth memories includes: A first sub-memory and a second sub-memory, used to store the first compensation value; A third sub-memory and a fourth sub-memory are used to store the second compensation value; and The fifth sub-memory and the sixth sub-memory are used to store the third compensation value.

8. The display device according to claim 7, in, The odd-numbered first compensation values ​​among the first compensation values ​​are stored in the first sub-memory, An even-numbered first compensation value among the first compensation values ​​is stored in the second sub-memory.

9. The display device according to claim 8, in, The first image signal corresponds to a first color, The first compensation values ​​correspond to a plurality of gray levels of the first color respectively.

10. The display device according to claim 9, in, The first correction value calculator outputs the first correction signal corresponding to the first color of the first image signal according to any one of the odd-numbered first compensation values ​​stored in the first sub-memory and any one of the even-numbered first compensation values ​​stored in the second sub-memory.

11. The display device according to claim 1, in, The display device further comprises: a fifth memory, storing any one of the plurality of compensation signals as a reference compensation signal, The first to fourth memories store differences between the plurality of compensation signals from the memory and the reference compensation signal.

12. The display device according to claim 1, in, A sum of the sizes of each of the first to fourth memories is smaller than the size of the memory.

13. A display device, in, include: Display panel; a memory storing a plurality of compensation signals respectively corresponding to a plurality of blocks of the display panel; as well as a driving controller that receives an input image signal, compensates the input image signal according to the plurality of compensation signals, and outputs an output image signal, The drive controller comprises: A first memory, a second memory, a third memory and a fourth memory, configured to store the plurality of compensation signals from the memory; a first correction value calculator, outputting a first correction signal, a second correction signal, a third correction signal and a fourth correction signal corresponding to the input image signal according to the first compensation signal, the second compensation signal, the third compensation signal and the fourth compensation signal from the first memory to the fourth memory; a second correction value calculator, outputting a final compensation signal according to the first to fourth correction signals; and a compensator, compensating the input image signal according to the final compensation signal, and outputting the output image signal, The plurality of compensation signals stored in the memory include: a first row compensation signal corresponding to blocks arranged in a first row among the plurality of blocks; and a second row compensation signal corresponding to blocks arranged in a second row among the plurality of blocks, A portion of the first row compensation signal is stored in the first memory, another portion of the first row compensation signal is stored in the second memory, a portion of the second row compensation signal is stored in the third memory, and another portion of the second row compensation signal is stored in the fourth memory.

14. The display device according to claim 13, in, The odd-numbered first-row compensation signals among the first-row compensation signals are stored in the first memory, and the even-numbered first-row compensation signals among the first-row compensation signals are stored in the second memory, The odd-numbered second-row compensation signals among the second-row compensation signals are stored in the third memory, and the even-numbered second-row compensation signals among the second-row compensation signals are stored in the fourth memory.

15. The display device according to claim 13, in, Each of the first to fourth compensation signals includes a first compensation value related to the first image signal, a second compensation value related to the second image signal, and a third compensation value related to the third image signal.

16. The display device according to claim 15, in, Each of the first to fourth memories includes: A first sub-memory and a second sub-memory, used to store the first compensation value; A third sub-memory and a fourth sub-memory are used to store the second compensation value; and The fifth sub-memory and the sixth sub-memory are used to store the third compensation value.

17. The display device according to claim 16, in, The odd-numbered first compensation values ​​among the first compensation values ​​are stored in the first sub-memory, An even-numbered first compensation value among the first compensation values ​​is stored in the second sub-memory.

18. A method for operating a display device, the display device comprising a memory storing a plurality of compensation signals respectively corresponding to a plurality of blocks of a display panel, in, The working method of the display device comprises: A step of storing a portion of first-row compensation signals corresponding to blocks arranged in a first row among the plurality of blocks in a first memory, and storing another portion in a second memory; A step of storing a part of the second row compensation signals corresponding to the blocks arranged in the second row among the plurality of blocks in a third memory, and storing another part in a fourth memory; The step of receiving an input image signal; and The step of outputting an output image signal that compensates the input image signal according to the first compensation signal, the second compensation signal, the third compensation signal, and the fourth compensation signal from the first memory to the fourth memory.

19. The operating method of the display device according to claim 18, in, The odd-numbered first-row compensation signals among the first-row compensation signals are stored in the first memory, and the even-numbered first-row compensation signals among the first-row compensation signals are stored in the second memory, The odd-numbered second-row compensation signals among the second-row compensation signals are stored in the third memory, and the even-numbered second-row compensation signals among the second-row compensation signals are stored in the fourth memory.

20. The operating method of the display device according to claim 19, in, A sum of the sizes of each of the first to fourth memories is smaller than the size of the memory.

21. A display device, in, include: Display panel; a memory storing a plurality of compensation signals respectively corresponding to a plurality of blocks of the display panel; as well as a driving controller that receives an input image signal, compensates the input image signal according to the plurality of compensation signals, and outputs an output image signal, The drive controller comprises: a first internal memory storing the plurality of compensation signals from the memory as internal compensation signals; a first memory, a second memory, a third memory, a fourth memory, a fifth memory, and a sixth memory storing the internal compensation signal from the first internal memory; and a compensation unit that compensates the input image signal according to a first compensation signal, a second compensation signal, a third compensation signal, and a fourth compensation signal provided from a portion of the first memory to the sixth memory, and outputs the output image signal, The plurality of compensation signals stored in the first internal memory include: a first row compensation signal corresponding to blocks arranged in a first row among the plurality of blocks; and a second row compensation signal corresponding to blocks arranged in a second row among the plurality of blocks, A portion of the first row compensation signal is stored in the first memory, the third memory, and the fifth memory, and a portion of the second row compensation signal is stored in the second memory, the fourth memory, and the sixth memory.

22. The display device according to claim 21, in, The compensation section simultaneously reads the first to fourth compensation signals from a portion of the first to sixth memories.

23. The display device according to claim 22, in, The compensation unit simultaneously performs the work of reading the first compensation signal to the fourth compensation signal from the first memory to the fourth memory in the first memory to the sixth memory, storing a part of the first row compensation signal in the fifth memory, and storing a part of the second row compensation signal in the sixth memory.

24. The display device according to claim 21, in, The compensation unit comprises: a first correction value calculator, which outputs a first correction signal, a second correction signal, a third correction signal and a fourth correction signal corresponding to the input image signal according to the first compensation signal to the fourth compensation signal; a second correction value calculator, outputting a final compensation signal according to the first to fourth correction signals; and A compensator compensates the input image signal according to the final compensation signal and outputs the output image signal.

25. The display device according to claim 24, in, The second correction value calculator outputs the final compensation signal through bilinear interpolation according to the first to fourth correction signals.

26. The display device according to claim 24, in, Each of the first to fourth compensation signals includes a first compensation value related to the first image signal, a second compensation value related to the second image signal, and a third compensation value related to the third image signal.

27. The display device according to claim 26, in, Each of the first to sixth memories includes: A first sub-memory and a second sub-memory, used to store the first compensation value; A third sub-memory and a fourth sub-memory are used to store the second compensation value; and The fifth sub-memory and the sixth sub-memory are used to store the third compensation value.

28. The display device according to claim 27, in, The odd-numbered first compensation values ​​among the first compensation values ​​are stored in the first sub-memory, An even-numbered first compensation value among the first compensation values ​​is stored in the second sub-memory.

29. The display device according to claim 28, in, The first image signal corresponds to a first color, The first compensation values ​​correspond to a plurality of gray levels of the first color respectively.

30. The display device according to claim 29, in, The first correction value calculator outputs the first correction signal related to the first color of the first image signal according to any one of the odd-numbered first compensation values ​​stored in the first sub-memory and any one of the even-numbered first compensation values ​​stored in the second sub-memory.

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