Semiconductor package structure and semiconductor packaging method

Abstract

The present disclosure provides a semiconductor package structure and a semiconductor packaging method, and relates to the technical field of semiconductor. The semiconductor package structure comprises a package substrate, a random access memory chip bonded with a first connecting part on the package substrate, a package layer covering the random access memory chip on the package substrate, a redistribution layer on the package layer, a second conductive wire at least partially located in the package layer and connecting a second connecting part on the package substrate and a bottom surface of the redistribution layer, and a flash memory chip on the redistribution layer and bonded with a top surface of the redistribution layer. The redistribution layer comprises a signal line and a reference line, the signal line is used for signal transmission between the flash memory chip and the package substrate, and the reference line is used for providing a reference plane for signal transmission. The present disclosure can improve the warping, delamination and other problems of semiconductor devices, and improve signal integrity and power integrity.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and a semiconductor packaging method. Background Technology

[0002] In semiconductor packaging processes, an interposer is typically used as a platform to bond multiple chips to a packaging substrate, thereby packaging multiple chips into a single device.

[0003] However, there may be a mismatch in the coefficients of thermal expansion between the interposer and the packaging material. As the semiconductor device heats up during use, it is prone to defects such as device warping and delamination, which can affect the normal use of the device. Summary of the Invention

[0004] This disclosure provides a semiconductor packaging structure and a semiconductor packaging method to at least partially solve problems such as warpage and delamination in semiconductor devices.

[0005] According to a first aspect of this disclosure, a semiconductor packaging structure is provided, comprising: a packaging substrate; a random access memory chip bonded to a first connection portion on the packaging substrate; a packaging layer located on the packaging substrate and covering the random access memory chip; a redistribution layer located on the packaging layer; a second conductive line located at least partially within the packaging layer and connecting the second connection portion on the packaging substrate to the bottom surface of the redistribution layer; and a flash memory chip located on the redistribution layer and bonded to the top surface of the redistribution layer; the redistribution layer includes signal lines and reference lines, the signal lines being used for signal transmission between the flash memory chip and the packaging substrate, and the reference lines being used to provide a reference plane for signal transmission.

[0006] Optionally, the second connection portion is a pad on the packaging substrate, and the second conductive line is a bonding wire that connects the second connection portion to the pad on the bottom surface of the redistribution layer.

[0007] Optionally, the ratio of the projection dimension of the second conductive line on the plane of the packaging substrate to the vertical dimension of the second conductive line is less than a preset ratio value.

[0008] Optionally, the second conductive lines are distributed in multiple directions of the random access memory chip.

[0009] Optionally, the bounding box of the projection of the connection point between the signal line and the bottom surface of the redistribution layer onto the reference plane is located within the bounding box of the projection of the connection point between the reference line and the bottom surface of the redistribution layer onto the reference plane; the reference plane is parallel to the top surface of the packaging substrate.

[0010] Optionally, the reference line includes a power line and a ground line; the bounding box of the projection of the connection point of the signal line and the bottom surface of the redistribution layer on the reference plane is located within the bounding box of the projection of the connection point of the ground line and the bottom surface of the redistribution layer on the reference plane; the bounding box of the projection of the connection point of the ground line and the bottom surface of the redistribution layer on the reference plane is located within the bounding box of the projection of the connection point of the power line and the bottom surface of the redistribution layer on the reference plane.

[0011] Optionally, the redistribution layer is a stacked structure formed by a signal layer, a power layer, and a ground layer; the signal layer is located between the power layer and the ground layer; the signal lines include horizontal signal lines parallel to the reference plane and vertical signal lines perpendicular to the reference plane, the horizontal signal lines being located within the signal layer; the reference lines include power lines and ground lines; the power lines include horizontal power lines parallel to the reference plane and vertical power lines perpendicular to the reference plane, the horizontal power lines being located within the power layer; the ground lines include horizontal ground lines parallel to the reference plane and vertical ground lines perpendicular to the reference plane, the horizontal ground lines being located within the ground layer; the reference plane is parallel to the top surface of the package substrate.

[0012] Optionally, the diameter of the second conductive wire connected to the power supply line is larger than the diameter of the second conductive wire connected to the grounding line.

[0013] Optionally, the second conductive wire connecting the grounding line is disposed on the outer periphery of the second conductor connecting the signal line, and the second conductive wire connecting the power signal is disposed on the outer periphery of the second conductive wire connecting the grounding signal.

[0014] According to a second aspect of this disclosure, a semiconductor packaging method is provided, comprising: providing a packaging substrate, a random access memory (RAM) chip to be packaged, and a flash memory chip; bonding the RAM chip to a first connection portion on the packaging substrate; forming a second conductive line, the second conductive line connecting to the second connection portion on the packaging substrate and extending upward; forming an encapsulation layer on the packaging substrate, covering the RAM chip and at least partially covering the second conductive line; forming a redistribution layer on the encapsulation layer, the second conductive line connecting to the bottom surface of the redistribution layer; the redistribution layer including signal lines and reference lines, the signal lines being used for signal transmission between the flash memory chip and the packaging substrate, and the reference lines being used to provide a reference plane for signal transmission; and bonding the flash memory chip to the top surface of the redistribution layer.

[0015] The technical solution disclosed herein has the following beneficial effects:

[0016] Firstly, instead of using an interposer, a redistribution layer is used to bond the flash memory chip to the packaging substrate. The redistribution layer is located above, rather than within, the packaging layer. Even if there is a mismatch in the coefficients of thermal expansion between the redistribution layer and the packaging layer, warping and delamination are less likely to occur when the semiconductor device heats up. Secondly, a suitable insulating medium can be used as a carrier in the redistribution layer. Compared to an interposer, there is greater flexibility in medium selection to match the coefficient of thermal expansion of the packaging layer, further improving warping and delamination and ensuring the performance of the semiconductor device. Thirdly, the wiring between the flash memory chip and the packaging substrate includes a second conductive line, traces within the redistribution layer, and the bonding portion between the flash memory chip and the redistribution layer. Compared to existing packaging structures, the length of the second conductive line is shorter than the traces from the interposer to the packaging substrate, and the traces within the redistribution layer are shorter than those within the interposer. Therefore, this solution can shorten the wiring length between the flash memory chip and the packaging substrate, improving signal integrity and power integrity. Fourthly, placing both signal lines and reference lines in the redistribution layer simplifies the packaging structure. The reference line provides a reference plane for signal transmission. Located in the redistribution layer, it provides good shielding and prevents electromagnetic coupling between the redistribution layer and external interference sources. Under the influence of the reference plane, the signal line can be regarded as a microstrip line with better signal transmission characteristics, which also improves signal integrity. Attached Figure Description

[0017] Figure 1 A schematic diagram of a semiconductor packaging structure is shown.

[0018] Figure 2 A schematic diagram of a lead wire is shown.

[0019] Figure 3 A schematic diagram of a semiconductor package structure is shown in this exemplary embodiment.

[0020] Figure 4A A schematic diagram of a projection and its bounding box is shown in this exemplary embodiment.

[0021] Figure 4B A schematic diagram of another projection and its bounding box in this exemplary embodiment is shown.

[0022] Figure 5 A top view of the redistribution layer in this exemplary embodiment is shown.

[0023] Figure 6 A schematic diagram of another semiconductor packaging structure is shown in this exemplary embodiment.

[0024] Figure 7A A comparison chart of insertion loss values ​​is shown.

[0025] Figure 7B A comparison chart of return loss values ​​is shown.

[0026] Figure 7C A comparison graph of impedances is shown.

[0027] Figure 8 A flowchart of a semiconductor packaging method in this exemplary embodiment is shown.

[0028] The reference numerals in the attached figures are as follows: 101, packaging substrate; 1011, first connection portion; 1012, second connection portion; 102, random access memory chip; 1021, random access memory chip particle; 1022, chip adhesive film; 103, encapsulation layer; 104, redistribution layer; 1041, insulating layer; 1042, signal line; 1043, reference line; 1044, power line; 1045, ground line; 1046, power layer; 1047, signal layer; 1048, ground layer; 105, second conductive line; 106, flash memory chip; 107, first conductive line. Detailed Implementation

[0029] Exemplary embodiments of this disclosure will be described more fully below with reference to the accompanying drawings.

[0030] The accompanying drawings are illustrative illustrations of this disclosure and are not necessarily drawn to scale. The technical solutions of this disclosure can be implemented in various forms and should not be construed as limited to the examples set forth herein. The features, structures, or characteristics described in this disclosure can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a sufficient description of embodiments of this disclosure. However, those skilled in the art will understand that one or more specific details may be omitted when implementing the technical solutions of this disclosure, or other methods, components, structures, etc., may be used to replace one or more specific details.

[0031] Figure 1 A schematic diagram of a semiconductor packaging structure is shown. The interposer serves as the interconnect between the UFS (Universal Flash Storage) chip and the DRAM (Dynamic Random Access Memory) chip. The UFS chip is bonded to the interposer and then to the packaging substrate via wire bonding. The DRAM chip is also wire bonded to the packaging substrate. The packaging layer covers the DRAM chip and the interposer for protection.

[0032] The inventors have discovered that encapsulation layers typically use injection-molded materials, such as EMC (Epoxy Molding Composites). There is often a mismatch in the coefficients of thermal expansion (CTE) between the interposer and encapsulation layers, meaning their CTEs differ significantly. This results in the portion of the encapsulation layer attached to the interposer expanding differently from other parts when the semiconductor device heats up, causing device warping. Alternatively, the different expansion rates of the interposer and encapsulation layers can lead to cracking or delamination at the interface, affecting the normal operation of the device.

[0033] Figure 1 The relatively large thickness of the intermediate packaging layer affects heat dissipation. Furthermore, the leads from the interposer to the packaging substrate are concentrated in one direction (for example, if the lead from the DRAM chip to the packaging substrate is on the left side of the DRAM chip, then the lead from the interposer to the packaging substrate is on the right side), leading to severe localized heat generation. Both of these factors make the aforementioned warping and delamination phenomena more likely to occur.

[0034] The inventors also discovered that, in reference Figure 2 As shown, the UFS chip and the packaging substrate are wire-bonded through an interlayer. Due to the wire bonding rules, the bonding wires are bonded in a single row in the X direction. This results in a maximum of two ground bonding wires distributed along the X-axis on both sides of the high-speed signal or power signal. This has limited improvement on the reference effect of the high-speed signal and the coupling effect between the power and ground. Furthermore, the power signal is concentrated in the X-axis direction and led out side by side, which is not conducive to reducing the impedance of the PDN (Power Delivery Network).

[0035] The inventors also discovered that the wiring from the UFS chip to the packaging substrate includes: a bonding portion between the UFS chip and the interposer, traces inside the interposer, and a bonding portion between the interposer and the packaging substrate. Excessive wiring length increases the signal delay of the UFS chip, affecting the device's signal integrity (SI) and power integrity (PI).

[0036] In view of one or more of the above-mentioned problems, exemplary embodiments of this disclosure first provide a semiconductor packaging structure. (Reference) Figure 3As shown, the semiconductor packaging structure may include: a packaging substrate 101; a random access memory (RAM) chip 102 bonded to a first connection portion 1011 on the packaging substrate 101; a packaging layer 103 located on the packaging substrate 101 and covering the RAM chip 102; a redistribution layer 104 located on the packaging layer 103; a second conductive line 105, at least partially located within the packaging layer 103, connecting the second connection portion 1012 on the packaging substrate 101 to the bottom surface of the redistribution layer 104; and a flash memory chip 106 located on the redistribution layer 104 and bonded to the top surface of the redistribution layer 104. The redistribution layer 104 includes a signal line 1042 and a reference line 1043. The signal line 1042 is used for signal transmission between the flash memory chip 106 and the packaging substrate 101, and the reference line 1043 is used to provide a reference plane for signal transmission. This semiconductor packaging structure can package the RAM chip 102 and the flash memory chip 106 into a single device to achieve combined storage.

[0037] The following section provides a detailed explanation of each part of the semiconductor packaging structure.

[0038] The packaging substrate 101 serves as a carrier for packaging the random access memory chip 102 and the flash memory chip 106, providing electrical connection, protection, support, heat dissipation, and assembly functions. The packaging substrate 101 has a first connection portion 1011 and a second connection portion 1012. The first connection portion 1011 is for electrically connecting to the random access memory chip 102, and the second connection portion 1012 is for electrically connecting to the flash memory chip 106. In one embodiment, the first connection portion 1011 and the second connection portion 1012 can be solder pads on the packaging substrate 101.

[0039] Random Access Memory (RAM) chips can be DRAM or SRAM (Static Random Access Memory) chips, etc. In one embodiment, the RAM chip 102 can be a stacked structure formed by multiple RAM chip particles 1021 and a die-attached film (DAF). The number of RAM chip particles 1021 can be set according to actual needs; for example, four DRAM particles can be set in one device.

[0040] The random access memory (RAM) chip 102 is bonded to a first connection portion 1011 on the packaging substrate 101. In one embodiment, the RAM chip 102 can be bonded to the first connection portion 1011 via flip-chip bonding, and the first connection portion 1011 can be a pad corresponding to a solder ball of the RAM chip 102. In another embodiment, the RAM chip 102 can be bonded to the first connection portion 1011 via wire bonding, and the first connection portion 1011 can be a pad corresponding to a bonding wire.

[0041] In one embodiment, the semiconductor package structure may further include a first conductive line 107 for electrically connecting the random access memory chip 102 and the package substrate 101. For example, the first conductive line 107 may be a bonding wire that bonds the random access memory chip 102 to the first connection portion 1011, such as... Figure 3 The situation is illustrated. Alternatively, the first conductive line 107 may be an electrical connection structure provided outside the bonding portion between the random access memory chip 102 and the packaging substrate 101, such as a patterned conductive film layer, which can enable a more stable electrical connection between the random access memory chip 102 and the packaging substrate 101.

[0042] The encapsulation layer 103 is located on the encapsulation substrate 101. It should be noted that in this exemplary embodiment, the direction in which the random access memory chip 102 and the flash memory chip 106 are positioned relative to the encapsulation substrate 101 is referred to as "upper," and vice versa as "lower." The top surface refers to the uppermost surface, and the bottom surface refers to the lowermost surface. The encapsulation layer 103 covers the top surface of the encapsulation substrate 101, encapsulates the random access memory chip 102, and encapsulates part or all of the second conductive line 105. The encapsulation layer 103 can be formed using an injection molding material (such as EMC) through an injection molding process.

[0043] The re-distribution layer 104 (RDL) is located on the package layer 103. Figure 1 Unlike the intermediate layer, the redistribution layer 104 does not need to be located within the encapsulation layer 103. The redistribution layer 104 typically consists of conductive lines (such as signal lines 1042 and reference lines 1043) and an insulating layer 1041 covering the conductive lines. The conductive lines can be made of metals such as aluminum and copper or their alloys, or non-metallic conductive materials. The conductive lines connect the bottom and top surfaces of the redistribution layer 104, forming an internal pathway. The insulating layer 1041 provides isolation, insulation, and protection for the conductive lines, and can be made of insulating dielectric materials such as PI (Polyimide). The redistribution layer 104 can include any number of insulating layers 1041, and different insulating layers 1041 can be made of different materials.

[0044] The second conductive line 105 connects the second connection portion 1012 on the packaging substrate 101 to the bottom surface of the redistribution layer 104, thereby achieving an electrical connection between the packaging substrate 101 and the redistribution layer 104. The second conductive line 105 may be entirely located within the packaging layer 103, or the upper end of the second conductive line 105 may extend outside the packaging layer 103. For example, the second conductive line 105 may be a bonding wire or a patterned conductive film layer.

[0045] The flash memory chip 106, such as a UFS chip, is located on the redistribution layer 104 and bonded to the top surface of the redistribution layer 104. For example, the flash memory chip 106 can be bonded to the top surface of the redistribution layer 104 via flip-chip bonding. The top surface of the redistribution layer 104 may have pads. Solder balls are formed on the active surface of the flash memory chip 106, and then the flash memory chip 106 is flip-chip bonded so that the solder balls are bonded to the pads on the top surface of the redistribution layer 104. Alternatively, the flash memory chip 106 can also be bonded to the top surface of the redistribution layer 104 via wire bonding. Thus, the flash memory chip 106 is bonded to the packaging substrate 101 via the redistribution layer 104, establishing a pathway from the second connection portion 1012 to the second conductive line 105, the conductive layer 1041 within the redistribution layer 104, and the flash memory chip 106.

[0046] In this exemplary embodiment, the redistribution layer 104 includes a signal line 1042 and a reference line 1043. The signal line 1042 and the second conductive line 105 connected to the signal line 1042 form a signal transmission path between the flash memory chip 106 and the packaging substrate 101, which can be used to transmit high-speed signals of the flash memory chip 106, etc. The reference line 1043 is used to provide a reference plane for signal transmission. When a high-speed signal is transmitted in the signal line 1042, a return current is generated in the reference line 1043 due to the induction of electromagnetic fields, etc. Therefore, the reference line 1043 can serve as a return path for the signal and provide a reference plane for signal transmission. The reference line 1043 can be a power line 1044 and / or a ground line 1045.

[0047] Based on the semiconductor packaging structure in this exemplary embodiment, the following technical effects can be achieved: First, instead of using an interposer, a redistribution layer 104 is used to bond the flash memory chip 106 to the packaging substrate 101. The redistribution layer 104 is located above the packaging layer 103 rather than within it. Even if there is a mismatch in the coefficient of thermal expansion between the redistribution layer 104 and the packaging layer 103, warping and delamination are less likely to occur when the semiconductor device heats up. Second, a suitable insulating medium can be used as a carrier in the redistribution layer 104. Compared to an interposer, there is greater flexibility in medium selection to match the coefficient of thermal expansion of the packaging layer 103, thereby further improving warping and delamination and ensuring the performance of the semiconductor device. Third, the wiring between the flash memory chip 106 and the packaging substrate 101 includes the second conductive line 105, the wiring within the redistribution layer 104, and the bonding portion between the flash memory chip 106 and the redistribution layer 104. Compared to... Figure 1 In the circuitry, the length of the second conductive line 105 is shorter than the trace from the interposer to the packaging substrate, and the trace within the redistribution layer 104 is shorter than the trace within the interposer. Therefore, this solution can shorten the line length between the flash memory chip 106 and the packaging substrate 101, improving signal integrity and power integrity. Fourthly, placing both the signal line 1042 and the reference line 1043 in the redistribution layer 104 simplifies the packaging structure. The reference line 1043 provides a reference plane for signal transmission. Located in the redistribution layer 104, it provides good shielding, preventing electromagnetic coupling between the redistribution layer 104 and external interference sources. Under the influence of the reference plane, the signal line 1042 can be considered a microstrip line with better signal transmission characteristics, which also improves signal integrity.

[0048] In one embodiment, the second connection portion 1012 is a pad on the packaging substrate 101, and the second conductive line 105 can be a bonding wire, connecting the second connection portion 1012 to the pad on the bottom surface of the redistribution layer 104 to achieve bonding between the two pads. This simplifies the bonding process.

[0049] The second conductive line 105 can form a vertical connection between the packaging substrate 101 and the redistribution layer 104. That is, the second conductive line 105 can be perpendicular to the packaging substrate 101. Considering that it is difficult to guarantee the absolute perpendicularity of the second conductive line 105 in actual manufacturing processes, in one embodiment, the ratio of the projected size of the second conductive line 105 on the plane of the packaging substrate 101 to the vertical size of the second conductive line 105 can be less than a preset ratio value. In this document, the plane of the packaging substrate 101 (such as the top surface of the packaging substrate 101) can be denoted as the XY plane, and the direction perpendicular to this plane can be denoted as the Z-axis direction. The projected size of the second conductive line 105 on the XY plane can be the maximum size between any two points on the projection pattern of the second conductive line 105 on the XY plane, which represents the lateral span of the second conductive line 105, and the vertical size of the second conductive line 105 is the height along the Z-axis. The preset ratio value can be determined based on experience and the dimensions of various components in the semiconductor packaging structure. Setting the ratio of the projected size to the vertical size to be less than the preset ratio value (e.g., 0.2-0.3) ensures that the ratio of the projected size to the vertical size is at a low level. This means that the lateral span of the second conductive line 105 is smaller than its vertical size, implying that the second conductive line 105 is vertical or nearly vertical. This allows for a further reduction in the length of the second conductive line 105, simplifying the process and further shortening the line length between the flash memory chip 106 and the packaging substrate 101.

[0050] In one embodiment, in order to ensure the vertical shape of the second conductive line 105, the diameter of the second conductive line 105 can be set to be not less than 50μm, so that the second conductive line 105 can maintain a certain rigidity and is not easy to deviate.

[0051] In one embodiment, the second conductive lines 105 can be distributed in multiple directions of the random access memory chip 102. For example, the portion of the encapsulation layer 103 outside the random access memory chip 102 can be divided into four or more regions, such as a region east of the random access memory chip 102, a region south of the random access memory chip 102, a region west of the random access memory chip 102, and a region north of the random access memory chip 102 (north, south, east, and west can be four mutually perpendicular directions in the XY plane), and the second conductive lines 105 can be distributed in multiple of these regions. For example, the second conductive lines 105 can be evenly distributed in the four directions of the random access memory chip 102. Figure 1In the structure, the leads between the interposer and the package substrate 101 are typically distributed on one side of the random access memory chip 102 to avoid the influence of the random access memory chip 102. In this exemplary embodiment, the second conductive line 105 is an electrical connection structure between the package substrate 101 and the bottom surface of the redistribution layer 104. Since the redistribution layer 104 has a large area and the vertical or near-vertical bonding structure is not affected by the wire bonding rules, there is more space to set the second conductive line 105, which is distributed in multiple directions of the random access memory chip 102. In this way, the distribution of the second conductive line 105 is more dispersed, which helps to improve the problem of local heat generation.

[0052] In one embodiment, the first conductive line 107 is a bonding wire that bonds the random access memory chip 102 to the first connection portion 1011. The thickness of the encapsulation layer 103 can be the distance between the highest point of the first conductive line 107 and the encapsulation substrate 101 plus a margin. (Reference) Figure 3 As shown, the encapsulation layer 103 needs to cover the random access memory chip 102 and the first conductive line 107. Therefore, the thickness of the encapsulation layer 103 is greater than the height of the highest point of the random access memory chip 102 and the first conductive line 107, which is the distance between the highest point of the first conductive line 107 and the encapsulation substrate 101. Based on this, in order to achieve full coverage by the encapsulation layer 103, a certain margin value can be set so that the encapsulation layer 103 is higher than the highest point of the first conductive line 107 by the margin value.

[0053] In one embodiment, if the random access memory chip 102 is flip-bonded to the first connection portion 1011, the thickness of the encapsulation layer 103 can be the distance between the highest point of the random access memory chip 102 and the encapsulation substrate 101 plus a margin value.

[0054] The method described above for determining the thickness of the encapsulation layer 103 can effectively reduce the thickness of the encapsulation layer 103. Especially compared to... Figure 1 With this structure, the encapsulation layer 103 does not need to cover the interposer, thus reducing its thickness. This improves device heat dissipation, making the aforementioned warping and delamination less likely to occur.

[0055] In one embodiment, the bounding box of the projection of the connection point between the signal line 1042 and the bottom surface of the redistribution layer 104 onto the reference plane is located within the bounding box of the projection of the connection point between the reference line 1043 and the bottom surface of the redistribution layer 104 onto the reference plane. The reference plane is parallel to the top surface of the packaging substrate 101, and is thus the XY plane. Figure 4AThe projection of the connection point between signal line 1042 and the bottom surface of redistribution layer 104 on a reference plane and its bounding box A are shown. The connection point between signal line 1042 and the bottom surface of redistribution layer 104, that is, the connection point between signal line 1042 and the second conductive line 105, can be the bottom surface pad of redistribution layer 104 to which signal line 1042 is connected. In this exemplary embodiment, the bounding box refers to the smallest rectangle (or other shape) that surrounds the projection. Figure 4A The projection of the connection point between the reference line 1043 and the bottom surface of the redistribution layer 104 onto the reference plane and its bounding box B are also shown. The connection point between the reference line 1043 and the bottom surface of the redistribution layer 104, i.e., the connection point between the reference line 1043 and the second conductive line 105, can be the bottom surface pad of the redistribution layer 104 to which the reference line 1043 is connected. The bounding box A is located within the bounding box B, which indicates that on the reference plane, the range of the reference line 1043 is larger than the range of the signal line 1042. The reference line 1043 can be a larger plane, and the signal line 1042 can be a smaller plane. Alternatively, it can be understood that the bottom surface pad connected to the reference line 1043 surrounds the bottom surface pad connected to the signal line 1042. This provides a more complete reference plane for the signal line 1042, which helps to reduce the impedance of the return path. The signal current returns through the reference plane, which can reduce the signal transmission delay and power consumption, and improve the signal transmission quality.

[0056] In one embodiment, the bounding box of the projection of the connection point between the signal line 1042 and the top surface of the redistribution layer 104 onto the reference plane is located within the bounding box of the projection of the connection point between the reference line 1043 and the top surface of the redistribution layer 104 onto the reference plane. That is, in the top surface pads (or solder balls of the flash memory chip 106) of the redistribution layer 104, the distribution range of the top surface pads (or solder balls) connected to the signal line 1042 is within the distribution range of the top surface pads (or solder balls) connected to the reference line 1043. This can be understood as the top surface pads (or solder balls) connected to the reference line 1043 surrounding the top surface pads (or solder balls) connected to the signal line 1042. This also provides a relatively complete reference plane for the signal line 1042, which helps to reduce the impedance of the return path, reduce signal transmission delay and power consumption, and improve signal transmission quality.

[0057] In one embodiment, reference line 1043 includes a power line 1044 and a ground line 1045. Power line 1044 is used for power transmission between flash memory chip 106 and package substrate 101, providing power to flash memory chip 106. Ground line 1045 connects flash memory chip 106 to a ground terminal. The bounding box of the projection of the connection point between signal line 1042 and the bottom surface of redistribution layer 104 onto a reference plane is located within the bounding box of the projection of the connection point between ground line 1045 and the bottom surface of redistribution layer 104 onto the reference plane. The bounding box of the projection of the connection point between ground line 1045 and the bottom surface of redistribution layer 104 onto the reference plane is located within the bounding box of the projection of the connection point between power line 1044 and the bottom surface of redistribution layer 104 onto the reference plane.

[0058] Figure 4B The diagram shows the projection of the connection point between signal line 1042 and the bottom surface of redistribution layer 104 onto the reference plane, along with its bounding box A; the projection of the connection point between power line 1045 and the bottom surface of redistribution layer 104 onto the reference plane, along with its bounding box B1; and the projection of the connection point between ground line 1044 and the bottom surface of redistribution layer 104 onto the reference plane, along with its bounding box B2. Bounding box A is located within bounding box B2, and bounding box B2 is located within bounding box B1. This indicates that on the reference plane, the range of power line 1044 is larger than the range of ground line 1044, and the range of ground line 1044 is larger than the range of signal line 1042. Alternatively, it can be understood that the bottom surface pads connected to power line 1044 surround the bottom surface pads connected to ground line 1044, and the bottom surface pads connected to ground line 1044 in turn surround the bottom surface pads connected to signal line 1042. This not only provides a more complete reference plane for signal line 1042, but also increases the coupling between power line 1044 and ground line 1045, and reduces the impedance of power line 1044.

[0059] In one embodiment, the bounding box of the projection of the connection point between the signal line 1042 and the top surface of the redistribution layer 104 onto the reference plane is located within the bounding box of the projection of the connection point between the ground line 1045 and the top surface of the redistribution layer 104 onto the reference plane. That is, in the top surface pads (or solder balls of the flash memory chip 106) of the redistribution layer 104, the distribution range of the top surface pads (or solder balls) connected to the signal line 1042 is within the distribution range of the top surface pads (or solder balls) connected to the ground line 1045, and the distribution range of the top surface pads (or solder balls) connected to the ground line 1045 is within the distribution range of the top surface pads (or solder balls) connected to the power line 1044. Figure 5The diagram shows a top view of the redistribution layer 104, with the central area being the region bonded to the flash memory chip 106, which is provided with top surface pads. This can be understood as follows: the top surface pads (or solder balls) connected to the power line 1044 surround the top surface pads (or solder balls) connected to the ground line 1045, and the top surface pads (or solder balls) connected to the ground line 1045 surround the top surface pads (or solder balls) connected to the signal line 1042. This also provides a relatively complete reference plane for the signal line 1042, increases the coupling between the power line 1044 and the ground line 1045, and reduces the impedance of the power line 1044.

[0060] In one implementation, reference Figure 6 The redistribution layer 104 can be a stacked structure formed by the signal layer 1047, the power layer 1046, and the ground layer 1048. The signal layer 1047 is located between the power layer 1046 and the ground layer 1048, that is, it can be the middle layer of the redistribution layer 104. Figure 6 The power layer 1046 is located at the bottom of the redistribution layer 104, thereby reducing the length of the second conductive line 105, reducing the power transmission path, thereby reducing the voltage drop and ensuring power integrity. The ground layer 1048 is located at the top of the redistribution layer 104. This disclosure does not limit this; for example, the power layer 1046 can also be located at the top of the redistribution layer 104, and the ground layer 1048 can also be located at the bottom of the redistribution layer 104.

[0061] Signal line 1042 includes horizontal signal wiring parallel to the reference plane (i.e. Figure 3 or Figure 6 The horizontal segment of signal line 1042 (where the horizontal segment is a plane) and the vertical signal wiring perpendicular to the reference plane (i.e. Figure 3 or Figure 6 The vertical segment of the signal line 1042 may include a vertical segment connected to the bottom surface of the redistribution layer 104 and a vertical segment connected to the top surface of the redistribution layer 104, and the horizontal signal wiring is located within the signal layer 1047. It should be understood that the signal layer 1047 may include the horizontal signal wiring and an insulating medium covering the horizontal signal wiring.

[0062] Reference line 1043 includes power line 1044 and ground line 1045. Power line 1044 includes horizontal power wiring parallel to the reference plane (i.e., Figure 6 The horizontal segment of power line 1044 (where the horizontal segment is a plane) and the vertical power line perpendicular to the reference plane (i.e. Figure 6The vertical segment of the power supply line 1044 may include a vertical segment connected to the bottom surface of the redistribution layer 104 and a vertical segment connected to the top surface of the redistribution layer 104. The horizontal power supply wiring is located within the power layer 1046. It should be understood that the power layer 1046 may include the horizontal power supply wiring and an insulating medium covering the horizontal power supply wiring. The grounding line 1045 includes horizontal grounding wiring parallel to the reference plane (i.e.,...). Figure 6 The horizontal section of the grounding line 1045 (where the horizontal section is a plane) and the vertical grounding line perpendicular to the reference plane (i.e. Figure 6 The vertical section of the grounding line 1045 may include a vertical section connected to the bottom surface of the redistribution layer 104 and a vertical section connected to the top surface of the redistribution layer 104. The horizontal grounding line is located within the grounding layer 1048. It should be understood that the grounding layer 1048 may include the horizontal grounding line and the insulating medium covering the horizontal grounding line.

[0063] As can be seen from the above, the signal layer 1047 is located between the power layer 1046 and the ground layer 1048, thus providing a reference plane in both the vertical and horizontal directions of signal transmission, which can further reduce the impedance of the return path and improve signal integrity.

[0064] like Figure 6 As shown, in some embodiments, the horizontal plane of the power line 1044 can be set to correspond to the horizontal plane of the ground line 1045, that is, the two can have the same area, and the area of ​​both is larger than the area of ​​the signal line 1042, thereby forming a complete reference plane, providing a low-impedance return path, so that the signal current can return through the reference plane, thereby reducing the signal transmission delay and power consumption, and further improving the signal transmission quality.

[0065] like Figure 6 As shown, in some embodiments, the second conductive line 105 connecting to the power line 1044 can be defined as a power conductive line, the second conductive line 105 connecting to the ground line 1045 can be defined as a ground conductive line, and the second conductive line 105 connecting to the signal line 1042 can be defined as a signal conductive line. The diameter of the power conductive line can be larger than the diameter of the ground conductive line, thereby making the voltage drop on the power conductive line smaller and ensuring power integrity.

[0066] like Figure 6 As shown, in some embodiments, the grounding conductor can be disposed around the signal conductor, and the power supply conductor can be disposed around the grounding conductor. For example, see reference... Figure 4BAs shown, the projected position of the connection point between signal line 1042 and the bottom surface of redistribution layer 104 can be equated to the projected position of the signal conductor; the projected position of the connection point between power line 1044 and the bottom surface of redistribution layer 104 can be equated to the projected position of the power conductor; and the projected position of the connection point between ground line 1045 and the bottom surface of redistribution layer 104 can be equated to the projected position of the ground conductor. On the reference plane, the ground conductor is located around the signal conductor, and the power conductor is located around the ground conductor. This provides a return path for the signal conductor, reducing impedance.

[0067] In this exemplary embodiment, the second connection portion 1012 on the packaging substrate 101, or the bottom pad of the redistribution layer 104, or the top pad of the redistribution layer 104, can be staggered in the X-axis and Y-axis directions. This allows for flexible arrangement of the signal lines 1042, power lines 1044, and ground lines 1045, resulting in a more rational distribution. Figure 4B The arrangement shown has grounding lines 1045 distributed around both signal line 1042 and power line 1044, compared to Figure 2 The single-row punched wire shown enhances the signal's immunity to electromagnetic interference, increases mutual capacitance, and reduces capacitive impedance.

[0068] In one implementation, the semiconductor packaging structure can be referenced. Figure 6As shown, the package includes: a packaging substrate 101; a random access memory (RAM) chip 102, comprising at least two RAM chip particles 1021 and at least two chip adhesive films 1022, wherein the RAM chip 102 is bonded to a first connection portion 1011 on the packaging substrate 101 via a first conductive line 107; a packaging layer 103, located on the packaging substrate 101, covering the RAM chip 102, the first conductive line 107, and the second conductive line 105; and a redistribution layer 104, located on the packaging layer 103, including signal lines 1042, power lines 1044, ground lines 1045, a power layer 1046, a signal layer 1047, and a ground layer 1048. The horizontal signal traces in signal line 1042 are located within signal layer 1047, and the vertical signal traces extend into power layer 1046 and ground layer 1048, connecting the bottom and top pads of redistribution layer 104. The horizontal power traces in power line 1044 are located within power layer 1046, and the vertical power traces extend into signal layer 1047 and ground layer 1048, connecting the bottom and top pads of redistribution layer 104. The horizontal ground traces in ground line 1045 are located within ground layer 1048, and the vertical signal traces extend into signal layer 1047 and power layer 1046, connecting the bottom and top pads of redistribution layer 104. Power layer 1046, signal layer 1047, and ground layer 1048 may each include one or more insulating media to cover signal line 1042, power line 1044, and ground line 1045. The second conductive line 105 is located within the encapsulation layer 103 and connects the second connection portion 1012 on the encapsulation substrate 101 to the bottom pad of the redistribution layer 104. The flash memory chip 106 is located on the redistribution layer 104 and forms a flip-chip bond with the top pad of the redistribution layer 104.

[0069] based on Figure 6 The semiconductor packaging structure shown can achieve better signal integrity and power integrity. Figure 7A and Figure 7B The improvement in the S-parameters of the differential signal, i.e., the improvement in signal integrity of the flash memory chip 106, is shown. dB[S(3,7)] is the insertion loss value implemented based on this exemplary embodiment, and dB[S(2,6)] is the insertion loss value based on the existing structure. Taking 5.8GHz as an example, dB[S(3,7)] is -0.715dB, and dB[S(2,6)] is -0.780dB. dB[S(8,8)] is the return loss value implemented based on this exemplary embodiment, and dB[S(6,6)] is the return loss value based on the existing structure. Taking 5.8GHz as an example, dB[S(8,8)] is -16.058dB, and dB[S(6,6)] is -13.506dB. It is evident that this exemplary embodiment improves signal integrity.

[0070] Figure 7C The improvement in DC impedance of the power supply, i.e., the improvement in power integrity of the flash memory chip 106, is shown. The impedance difference between Z(1,1) and Z(2,2) is 5mΩ. It is evident that this exemplary embodiment improves power integrity.

[0071] Exemplary embodiments of this disclosure also provide a semiconductor packaging method. (See reference...) Figure 8 As shown, the method may include the following steps S810 to S860:

[0072] Step S810: Provide a packaging substrate 101, a random access memory chip 102 to be packaged, and a flash memory chip 106.

[0073] In one embodiment, multiple random access memory chip particles 1021 can be stacked and glued together using a chip adhesive film 1022 to form a stacked random access memory chip 102.

[0074] In step S820, the random access memory chip 102 is bonded to the first connection portion 1011 on the packaging substrate 101.

[0075] For example, wire bonding or flip bonding can be used to bond the random access memory chip 102 to the first connection portion 1011 on the packaging substrate 101.

[0076] In step S830, a second conductive line 105 is formed, which connects to the second connection portion 1012 on the packaging substrate 101 and extends upward.

[0077] In one embodiment, the second conductive wire 105 may be a bonding wire. Step S630 may specifically include: bonding balls onto the second connection portion 1012 on the packaging substrate 101, pulling the bonding wire into an arc shape to form a wedge-shaped weak point, then pulling the bonding wire upward to form a vertical or near-vertical shape, and breaking the wedge-shaped weak point, thereby forming a complete second conductive wire 105.

[0078] In step S840, an encapsulation layer 103 is formed on the encapsulation substrate 101 to cover the random access memory chip 102 and at least partially cover the second conductive line 105.

[0079] For example, an encapsulation layer 103 can be formed through injection molding or similar processes. This layer covers the random access memory chip 102 and at least partially covers the second conductive line 105. Additionally, it can also cover the first conductive line 107.

[0080] In one embodiment, after forming the packaging layer 103 on the packaging substrate 101, the semiconductor packaging method may further include the following steps:

[0081] The top surface of the encapsulation layer 103 is ground to expose the top tip of the second conductive line 105.

[0082] When forming the encapsulation layer 103 through processes such as injection molding, the encapsulation layer may extend beyond the top of the second conductive line 105. A process such as chemical mechanical polishing can be used to polish the top surface of the encapsulation layer 103 to expose the top of the second conductive line 105. This allows the redistribution layer 104 to be formed on the encapsulation layer 103, enabling the bottom pads of the redistribution layer 104 to contact the top of the second conductive line 105 and form a bond.

[0083] In step S850, a redistribution layer 104 is formed on the packaging layer 103, and a second conductive line 105 is connected to the bottom surface of the redistribution layer 104. The redistribution layer 104 includes a signal line 1042 and a reference line 1043. The signal line 1042 is used for signal transmission between the flash memory chip 106 and the packaging substrate 101, and the reference line 1043 is used to provide a reference plane for signal transmission.

[0084] For example, one or more insulating layers 1041 can be first patterned using photolithography and etching processes to leave out portions of signal lines 1042 and reference lines 1043. Then, signal lines 1042 and reference lines 1043 are formed, with the bottoms of signal lines 1042 and reference lines 1043 able to contact the top of the second conductive line 105. The top surfaces of signal lines 1042, reference lines 1043, and insulating layers 1041 are then processed using processes such as chemical mechanical polishing to expose the top surface pads, forming the final redistribution layer 104.

[0085] In one embodiment, a passivation layer may also be formed on the redistribution layer 104 to protect the redistribution layer 104.

[0086] In step S860, the flash memory chip 106 is bonded to the top surface of the redistribution layer 104.

[0087] For example, wire bonding or flip bonding can be used to bond the flash memory chip 106 to the top surface of the redistribution layer 104.

[0088] In one embodiment, the bonding of the flash memory chip 106 to the top surface of the redistribution layer 104 may include the following steps:

[0089] Solder balls are formed at the bottom of the flash memory chip 106 and bonded to pads on the top surface of the redistribution layer 104.

[0090] For example, a flip-chip bonding process can be used. After flipping the flash memory chip 106, solder balls are formed on its bottom (i.e., the top before flipping). The solder balls can be formed according to the conductive positions in the bottom conductive layer. Pads corresponding to the solder balls are formed on the top surface of the redistribution layer 104. The bottom solder balls of the flash memory chip 106 can be bonded to the pads to form the connection of the redistribution layer 104 of the flash memory chip 106. Using solder ball bonding can make the distribution of solder balls more reasonable and uniform, improve heat dissipation and signal transmission, and help simplify the structure and process.

[0091] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. This application is intended to cover any variations, uses, or adaptations of the technical solutions that follow the general principles of this disclosure and include common knowledge or customary technical means in the art not disclosed herein. The content of this specification is to be considered exemplary only, and the scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor package structure, comprising: The semiconductor package structure comprises: a package substrate; a random access memory chip, which is connected to a first connection part on the package substrate through a first conductive wire; a package layer, which is located on the package substrate and covers the random access memory chip and the first conductive wire; a redistribution layer, which is located on the package layer; a second conductive wire, which is at least partially located in the package layer and connects a second connection part on the package substrate and a bottom surface of the redistribution layer; a flash memory chip, which is located on the redistribution layer and is connected to a top surface of the redistribution layer through a bonding wire; the redistribution layer comprises signal lines and reference lines, the signal lines are used for signal transmission between the flash memory chip and the package substrate, and the reference lines are used for providing a reference plane for signal transmission; the reference lines comprise power lines and ground lines; a diameter of the second conductive wire connected to the power lines is greater than a diameter of the second conductive wire connected to the ground lines.

2. The semiconductor package structure of claim 1, wherein, The second connection part is a pad on the package substrate, and the second conductive wire is a bonding wire, which connects the second connection part and a pad on the bottom surface of the redistribution layer.

3. The semiconductor package structure of claim 2, wherein, A ratio of a projection size of the second conductive wire on a plane of the package substrate to a vertical size of the second conductive wire is less than a preset proportion value.

4. The semiconductor package structure of claim 1, wherein, The second conductive wire is distributed in multiple directions of the random access memory chip.

5. The semiconductor package structure of any one of claims 1-4, wherein, A projection of a connection point of the signal lines and the bottom surface of the redistribution layer on a reference plane is located within a projection of a connection point of the reference lines and the bottom surface of the redistribution layer on the reference plane; the reference plane is parallel to a top surface of the package substrate.

6. The semiconductor package structure according to claim 5, wherein a projection of a connection point of the signal lines and the bottom surface of the redistribution layer on the reference plane is located within a projection of a connection point of the ground lines and the bottom surface of the redistribution layer on the reference plane; and a projection of a connection point of the ground lines and the bottom surface of the redistribution layer on the reference plane is located within a projection of a connection point of the power lines and the bottom surface of the redistribution layer on the reference plane.

7. The semiconductor package structure of claim 1, wherein, The redistribution layer is a laminated structure formed by a signal layer, a power layer and a ground layer; the signal layer is located between the power layer and the ground layer; the signal lines comprise horizontal signal lines parallel to a reference plane and vertical signal lines perpendicular to the reference plane, and the horizontal signal lines are located in the signal layer; the power lines comprise horizontal power lines parallel to the reference plane and vertical power lines perpendicular to the reference plane, and the horizontal power lines are located in the power layer; and the ground lines comprise horizontal ground lines parallel to the reference plane and vertical ground lines perpendicular to the reference plane, and the horizontal ground lines are located in the ground layer; the reference plane is parallel to the top surface of the package substrate.

8. The semiconductor package structure of claim 7, wherein, The second conductive wire connected to the ground line is arranged at the outer periphery of the second conductive wire connected to the signal line, and the second conductive wire connected to the power line is arranged at the outer periphery of the second conductive wire connected to the ground line.

9. A semiconductor packaging method, characterized by, Comprise: A packaging substrate, a random access memory chip to be packaged, and a flash memory chip are provided; The random access memory chip is bonded to a first connection portion on the packaging substrate through a first conductive wire; A second conductive wire is formed, which is connected to a second connection portion on the packaging substrate and extends upward; A packaging layer is formed on the packaging substrate, which covers the random access memory chip and the first conductive wire, and at least partially covers the second conductive wire; A redistribution layer is formed on the packaging layer, and the second conductive wire is connected to the bottom surface of the redistribution layer; The redistribution layer comprises a signal line and a reference line, the signal line is used for signal transmission between the flash memory chip and the packaging substrate, and the reference line is used for providing a reference plane for signal transmission; the reference line comprises a power line and a ground line; The diameter of the second conductive wire connected to the power line is greater than the diameter of the second conductive wire connected to the ground line; The flash memory chip is bonded to the top surface of the redistribution layer.

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