A super junction trench MOSFET structure and its manufacturing method

Abstract

A superjunction trench MOSFET structure and its manufacturing method belong to the technical field of superjunction MOSFETs. A superjunction trench MOSFET structure includes an N+ substrate, a first cell structure, and a second cell structure. Among them, both the first cell structure and the second cell structure are regular hexagons. The first cell structure includes a first N pillar region and a first P pillar region surrounding the first N pillar region, and a first source trench is provided on the first N pillar region. The second cell structure includes a second N pillar region and a second P pillar region surrounding the second N pillar region, and a second source trench is provided on the second N pillar region. A number of second cell structures surround the first cell structure. The second cell structure further includes a gate trench, a first channel is formed between the gate trench and the first source trench, a second channel is formed between the gate trench and the second source trench, and the lengths of the first channel and the second channel are different. By setting a regularly tiled cell structure in the shape of a regular hexagon and having an asymmetric double channel, the present application not only improves the channel density but also provides a good gate oxide protection effect.

Description

Technical Field

[0001] The present invention belongs to the technical field of superjunction MOSFETs, and particularly relates to a superjunction trench MOSFET structure and a manufacturing method thereof. Background Art

[0002] In recent years, with the rapid development of new energy technologies and electric vehicles, higher requirements have been put forward for the loss control and efficiency improvement of power electronic devices. As an important part of power electronic devices, power MOSFET devices have received extensive attention in the industry.

[0003] After long-term research, great progress has been made in MOSFET power devices, and the performance of conventional devices has approached its one-dimensional theoretical limit. However, how to break through this limit and further reduce the specific on-resistance and conduction loss of the device is a huge challenge faced by current MOSFET power devices.

[0004] Among many technologies, the superjunction technology is considered to be one of the mature technologies to break through the one-dimensional theoretical performance limit of unipolar devices. The superjunction technology breaks the original restrictive relationship between the specific on-resistance and the breakdown voltage of silicon-based devices by optimizing the device structure design, significantly improves the conduction performance of the device, and successfully realizes industrialization and popularization.

[0005] For example, Chinese Patent No. CN117293181A discloses a floating junction type superjunction MOSFET structure and a manufacturing method thereof, which includes: a first dielectric layer, a stacked structure, a sidewall region, a current diffusion region, a channel region, a source contact region, a gate structure, and a first connection region; the first dielectric layer has a first doping type; the stacked structure extends into the first dielectric layer, and the stacked structure includes a plurality of doped regions stacked in sequence along the extension direction, adjacent two doped regions have different doping types, and the outermost doped region in the stacked structure has a second doping type; the sidewall region extends into the first dielectric layer and is used to separate the dielectric layer from the stacked structure; the current diffusion region, the channel region, and the source contact region are stacked on the first dielectric layer in sequence; the first connection region penetrates through the source contact region, the channel region, and the current diffusion region. This floating junction type superjunction MOSFET structure can obtain a superjunction device with low cost and a high charge balance window.

[0006] However, although the superjunction technology has made remarkable progress and reduced the epitaxial resistance of MOSFET devices, MOSFET devices still have a relatively large channel resistance at present, and there is still a large room for improvement in its channel density.

[0007] Therefore, it is urgent to develop a superjunction trench MOSFET structure and a manufacturing method thereof to solve the problems in the prior art. Summary of the Invention

[0008] The object of the present invention is to provide a superjunction trench MOSFET structure and a manufacturing method thereof, which have a high channel density to solve the problem of insufficient channel density of superjunction MOSFETs.

[0009] To solve the above technical problems, the specific technical solution of the present invention is as follows:

[0010] A superjunction trench MOSFET structure includes an N + substrate and a first cell structure and a second cell structure densely paved on the N + substrate; wherein, the shapes of the first cell structure and the second cell structure in the top view are both regular hexagons;

[0011] The first cell structure includes a first N pillar region and a first P pillar region surrounding the first N pillar region, and a first source trench is arranged on the first N pillar region;

[0012] The second cell structure includes a second N pillar region and a second P pillar region surrounding the second N pillar region, and a second source trench is arranged on the second N pillar region; there are several second cell structures, and several second cell structures surround the first cell structure;

[0013] The second cell structure further includes a gate trench, the gate trench surrounds the second source trench, a first channel is formed between the gate trench and the first source trench, a second channel is formed between the gate trench and the second source trench, and the lengths of the first channel and the second channel are different.

[0014] Furthermore, the superjunction trench MOSFET structure includes at least one cell, one cell includes one first cell structure and six second cell structures; when there are several cells, two adjacent cells share two second cell structures.

[0015] Furthermore, when there are several cells, at least one second cell structure is shared by three first cell structures.

[0016] Furthermore, the length of the first channel is greater than the length of the second channel; one side of the gate trench is arranged on the second P pillar region, and the other side is arranged on the second N pillar region.

[0017] Furthermore, the first N pillar region, the first P pillar region, the second N pillar region and the second P pillar region are arranged on the upper surface of the N + substrate.

[0018] Furthermore, an N-type epitaxial layer is further arranged on the upper surface of the N + substrate, and the first N pillar region, the first P pillar region, the second N pillar region and the second P pillar region are arranged on the upper surface of the N-type epitaxial layer.

[0019] Further, a first P-well is formed between the first source trench and the gate trench. The first P-well surrounds the first source trench and is in the shape of a hollow regular hexagon in a top view.

[0020] A surface P + region and a first N + are formed on the first P-well. The surface P + region surrounds the upper end of the first P-well, and the first N + surrounds the surface P + region. The surface P + region is in the shape of a hollow regular hexagon in a top view, and the first N + is also in the shape of a hollow regular hexagon in a top view.

[0021] A second P-well is provided between the second source trench and the gate trench. The second P-well surrounds the second source trench and is in the shape of a hollow regular hexagon in a top view.

[0022] A second N + is further formed on the upper surface of the second P-well. The second N + surrounds the second source trench, and the second N + is also in the shape of a hollow regular hexagon in a top view.

[0023] A gate oxide layer is provided in the gate trench, and the gate oxide layer is disposed at the bottom of the gate trench, on the side close to the first source trench, and on the side close to the second source trench.

[0024] A method for manufacturing a superjunction trench MOSFET structure includes the following steps:

[0025] Construct an N-type epitaxial layer and a P-type epitaxial layer on an N + substrate to form a P-column region and a plurality of N-column regions. Among them, the N-column regions are in the shape of regular hexagons in a top view, and the P-column region surrounds each of the N-column regions.

[0026] Construct a PW channel region and a source contact region on the N-column regions and the P-column region.

[0027] Construct a first source trench, a second source trench, and a gate trench. Among them, the N-column regions include a first N-column region and a second N-column region. The first source trench is disposed in the first N-column region, the second source trench is disposed in the second N-column region. One side of the gate trench is disposed in the second N-column region, and the other side is disposed in the P-column region. The gate trench penetrates through the PW channel region, and the distance between the gate trench and the first source trench is greater than the distance between the second source trench and the gate trench.

[0028] Further, the step of constructing on the N +Construct an N-type epitaxial layer and a P-type epitaxial layer on a substrate to form a P-column region and a plurality of N-column regions, including the following steps:

[0029] On the N + Construct an N-type epitaxial layer on the substrate; the N-type epitaxial layer has an electron-type doping;

[0030] Construct a first trench in the N-type epitaxial layer, the first trench penetrating or not penetrating the N-type epitaxial layer, so that the N-type epitaxial layer forms a plurality of N-column regions with a regular hexagon shape in a top view;

[0031] Form a P-type epitaxial layer in the first trench, the first trench being filled without voids by the P-type epitaxial layer, and the P-type epitaxial layer having a hole-type doping.

[0032] Further, the construction of the first source trench, the second source trench and the gate trench includes the following steps:

[0033] Select the position of the first N-column region;

[0034] According to the position of the first N-column region, select the position of the second N-column region;

[0035] According to the position of the first N-column region, construct the first source trench;

[0036] According to the position of the second N-column region, construct the second source trench and the gate trench;

[0037] Among them, the superjunction trench MOSFET structure includes at least one cell; when there are a plurality of cells, one cell includes a first N-column region and six second N-column regions, and two second N-column regions are shared between adjacent two cells.

[0038] Further, the construction of the PW channel region and the source contact region on the N-column region and the P-column region includes the following steps:

[0039] Through two ion implantation processes, a PW channel region and a source contact region are sequentially formed on the P-column region and the N-column region, wherein the PW channel region has a medium-concentration hole-type doping; the source contact region has a high-concentration electron-type doping.

[0040] The present invention has the following advantages:

[0041] 1) In the asymmetric source trench regular hexagon superjunction trench MOSFET structure of the present application, since the projection of the first cell structure and the second cell structure on the top view is a regular hexagon and has an asymmetric double channel. Compared with the traditional strip cell superjunction MOSFET, the present invention has a higher channel density. Based on the smallest cell unit of this design and with reference to the conventional MOSFET design line width, assuming the side length of the regular hexagon cell is L, the theoretical calculation shows that the channel length per unit area of this design is: 。

[0042] Under the same process conditions, the equivalent cell width of the conventional strip cell is , and the channel length per unit area of the strip cell is: 。

[0043] It can be seen therefrom that the present invention is expected to increase the channel density of the superjunction MOSFET by 66.7%.

[0044] 2) In the superjunction trench MOSFET structure of the present application, due to the matching design of the superjunction and the MOSFET, and having an asymmetric channel design, it is realized that the peak of the trench gate oxide electric field is located inside the P region of the superjunction. This is beneficial to reducing the gate oxide electric field, thereby realizing gate oxide protection, improving the reliability of the gate oxide of the superjunction trench MOSFET device, and solving the gate bias reliability problem of the silicon carbide MOSFET device.

[0045] Other features and advantages of the present invention will be disclosed in detail in the following specific embodiments and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a partial structural cross-sectional view of Embodiment 1;

[0047] Figure 2 is a top view of the cell structure of Embodiment 1;

[0048] Figure 3 is a cross-sectional view of the AA' structure of Embodiment 1;

[0049] Figure 4 is a cross-sectional view of the structure after constructing the N-type epitaxial layer in Embodiment 1;

[0050] Figure 5 is a cross-sectional view of the structure after constructing the first trench in Embodiment 1;

[0051] Figure 6 is a cross-sectional view of the structure after constructing the P-type epitaxial layer in Embodiment 1;

[0052] Figure 7 is a cross-sectional view of the structure after constructing the PW channel region and the source contact region in Embodiment 1;

[0053] Figure 8 is a cross-sectional view of the structure after constructing the trench in Embodiment 1;

[0054] Figure 9 is a cross-sectional view of the structure after constructing the first source trench and the second source trench in Embodiment 1;

[0055] Figure 10 is a cross-sectional view of the structure after constructing the gate trench in Embodiment 1;

[0056] Figure 11 Cross-sectional view of the structure after constructing the first trench in the second embodiment.

[0057] Marking description in the figure: 1. N + Substrate; 2. Second N pillar region; 3. P pillar region; 4. First N pillar region; 51. First P well; 52. Second P well; 6. Surface P + region; 71. First N + region; 72. Second N + region; 8. Gate oxide layer; 9. Second P + region; 10. First P + region; 101. N-type epitaxial layer; 102. PW channel region; 103. Source contact region. Detailed implementation manners

[0058] To better understand the purpose, structure and function of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0059] A superjunction trench MOSFET structure, as Figures 1 to 3 shown, includes:

[0060] N + substrate 1;

[0061] The first cell structure, the first cell structure is disposed on the N + substrate 1;

[0062] The second cell structure, the second cell structure is disposed on the N + substrate 1, and a plurality of the second cell structures are provided;

[0063] The first cell structure is connected to the second cell structure; the shapes of the first cell structure and the second cell structure in the top view are both regular hexagons; six of the second cell structures are surrounded by one of the first cell structures. Optionally, at least two of the second cell structures are provided beside one of the first cell structures.

[0064] In this embodiment, the first cell structure includes:

[0065] The first N pillar region 4, the first N pillar region 4 is disposed on the upper surface of the N + substrate 1, and the first N pillar region 4 is disposed at the middle position of the horizontal cross-section of the first cell structure; the shape of the first N pillar region 4 in the top view is a regular hexagon;

[0066] The first P pillar region, the first P pillar region is disposed on the N +The upper surface of the substrate 1, the first P pillar region surrounds the first N pillar region 4; the shape of the first P pillar region in a top view is a regular hexagon;

[0067] The first source trench, the first source trench is arranged on the first N pillar region 4, a groove is formed on the first N pillar region 4, and a first P + region 10 is arranged in the first source trench; the shape of the first source trench in a top view is a regular hexagon.

[0068] In this embodiment, the cell second structure includes:

[0069] The second N pillar region 2, the second N pillar region 2 is arranged on the upper surface of the N + substrate 1, and the second N pillar region 2 is arranged at the middle position of the horizontal section of the cell second structure; the shape of the second N pillar region 2 in a top view is a regular hexagon;

[0070] The second P pillar region, the second P pillar region is arranged on the upper surface of the N + substrate 1, the second P pillar region surrounds the second N pillar region 2; the shape of the second P pillar region in a top view is a regular hexagon; in this embodiment, the second P pillar region and the first P pillar region are of an integral structure and have the same material, and the second P pillar region and the first P pillar region together form the P pillar region 3;

[0071] The second source trench, the second source trench is arranged on the second N pillar region 2, a groove is formed on the second N pillar region 2, and a second P + region 9 is arranged in the second source trench; the shape of the second source trench in a top view is a regular hexagon.

[0072] The gate trench surrounds the second source trench, a first channel is formed between the gate trench and the first source trench, a second channel is formed between the gate trench and the second source trench, and the lengths of the first channel and the second channel are different; the shape of the gate trench in a top view is a regular hexagon. In this embodiment, the length of the first channel refers to the distance between the first source trench and the gate trench, and the length of the second channel refers to the distance between the second source trench and the gate trench.

[0073] A gate oxide layer 8 is disposed in the gate trench. The gate oxide layer 8 is disposed at the bottom of the gate trench, on one side close to the first source trench, and on one side close to the second source trench. The gate oxide layer 8 covers the bottom of the gate trench, and a side wall of the gate oxide layer 8 surrounds the outside of the second source trench. When six cell second structures surround the cell first structure of a regular hexagon, the first source trench is also surrounded by another side wall of the gate oxide layer 8. In this embodiment, a second N+ region 72, a second P well 52, and a second N pillar region 2 are provided between the gate oxide layer 8 and the second source trench, and a first N+ region 71, a surface P+ region 6, a first P well 51, a first P pillar region, and a first N pillar region 4 are provided between the gate oxide layer 8 and the first source trench.

[0074] A first P well 51 is provided between the first source trench and the gate trench. The first P well 51 surrounds the first source trench, and the first P well 51 is a hollow regular hexagon in a top view. Specifically, in this embodiment, the hollow regular hexagon means that a regular hexagon is hollowed out at the center of the regular hexagon. The first P well 51 is used to form a first channel.

[0075] The vertical cross-section passing through the center point of the first P well 51 is a hollow convex shape, and it is a hollow regular hexagon on the top view plane. A surface P + region 6 and a first N + region 71 are formed on the first P well 51. The surface P + region 6 surrounds the upper end of the first P well 51, and the first N + region 71 surrounds the surface P + region 6. The surface P + region 6 is a hollow regular hexagon in a top view, and the first N + region 71 is also a hollow regular hexagon in a top view.

[0076] A second P well 52 is provided between the second source trench and the gate trench. The second P well 52 surrounds the second source trench, and the second P well 52 is a hollow regular hexagon in a top view. The second P well 52 is used to form a second channel.

[0077] A second N + region 72 is further formed on the upper surface of the second P well 52. The second N + region 72 surrounds the second source trench, and the second N + region 72 is also a hollow regular hexagon in a top view.

[0078] The superjunction trench MOSFET structure includes at least one cell. One cell includes one cell first structure and six cell second structures. When there are several cells, two adjacent cells share two cell second structures. Preferably, at least one cell second structure is shared by three cell first structures.

[0079] Specifically, the setting for realizing that at least one second cell structure is shared by three first cell structures is as follows:

[0080] Six second cell structures are densely paved and surrounded beside a first cell structure; the distance between two adjacent first cell structures is the side length of a second cell. Through the sharing of the second cell structure in this application, it is convenient to save manufacturing costs.

[0081] In this embodiment, the first cell structure is axisymmetric, and the second cell structure is also axisymmetric, so as to facilitate the sharing of the second cell structure by different first cell structures.

[0082] A method for manufacturing a superjunction trench MOSFET structure, as Figures 4 to 10 , includes the following steps:

[0083] S1: Construct an N-type epitaxial layer 101 and a P-type epitaxial layer on an N + substrate 1 to form a P pillar region 3 and several N pillar regions; wherein, the shape of the N pillar region in a top view is a regular hexagon, and the P pillar region 3 surrounds each N pillar region;

[0084] S2: Construct a PW channel region 102 and a source contact region 103 on the N pillar region and the P pillar region 3;

[0085] S3: Construct a first source trench, a second source trench, and a gate trench; wherein, the N pillar region includes a first N pillar region 4 and a second N pillar region 2; the first source trench is arranged in the first N pillar region 4, the second source trench is arranged in the second N pillar region 2; one side of the gate trench is arranged in the second N pillar region 2, and the other side is arranged in the P pillar region 3 and penetrates through the PW channel region 102, and the distance between the gate trench and the first source trench is greater than the distance between the second source trench and the gate trench to form an asymmetric bilateral channel region and a channel region.

[0086] As Figure 4 , Figure 5 and Figure 6 shown, in this embodiment, S1 includes the following steps:

[0087] Construct an N-type epitaxial layer 101 on an N + substrate 1; the N-type epitaxial layer 101 has an n-type doping; the thickness of the N-type epitaxial layer 101 is 5 μm - 60 μm;

[0088] Construct a first trench in the N-type epitaxial layer 101, and the first trench penetrates through the N-type epitaxial layer 101;

[0089] A P-type epitaxial layer is formed in the first trench, and the first trench needs to be filled without voids by the P-type epitaxial layer, and the P-type epitaxial layer has hole-type doping.

[0090] As Figure 7 shown, in this embodiment, S2 includes the following steps:

[0091] Through two ion implantation processes, a PW channel region 102 and a source contact region 103 are formed successively. Among them, the PW channel region 102 is designed with medium-concentration hole-type doping according to the requirements of threshold and mobility; the source contact region 103 is designed with high-concentration electron-type doping according to the requirements of ohmic contact.

[0092] As Figure 8 , Figure 9 and Figure 10 shown, in this embodiment, S3 includes the following steps:

[0093] Through an etching process, a first source trench, a second source trench, and a gate trench are formed simultaneously. Among them, the first source trench and the second source trench are located in the N-type epitaxial layer 101; one side of the gate trench is located in the N-type epitaxial layer 101, and the other side is located in the P pillar region 3. The gate trench needs to penetrate through the PW channel region 102 to form an asymmetric bilateral channel region and a channel region.

[0094] Through an ion implantation process, a surface P + region 6 and P + regions inside the first source trench and the second source trench are formed simultaneously. Among them, the surface P + region 6 realizes the grounding of the superjunction P pillar region 3. The second source trench and the P + region inside it realize the protection of the gate oxide at the second channel. The P pillar region 3 realizes the protection of the gate oxide at the first channel.

[0095] Through thermal oxidation / deposition and other methods, a gate oxide layer 8 is filled inside the gate trench. According to the requirements of threshold voltage and mobility, the thickness of the gate oxide layer 8 is 30 nm - 150 nm. Optionally, the fabrication processes of the first source trench, the second source trench, the gate trench, etc. can all be prior art, and will not be elaborated in this application.

[0096] Optionally, the preparation of the superjunction trench MOSFET structure further includes the following steps:

[0097] A phosphorus-doped polysilicon layer is filled inside the gate trench and used as the gate of the MOSFET. An interlayer dielectric is covered on the surface of the phosphorus-doped polysilicon layer to achieve gate-source isolation. A source metal is filled inside the source trench to form a source ohmic contact alloy. A thick metal and a passivation layer are formed on the front side of the device to complete the front-side process of the device. Finally, processes such as thinning and ohmic contact are performed on the back side of the device to complete the asymmetric source trench hexagonal superjunction trench MOSFET structure.

[0098] A hexagonal cell superjunction structure in which the N pillar region is surrounded by the P pillar region 3 is adopted. A gate trench is etched on the superjunction P pillar region 3, and one side of the gate trench is located at the center of the superjunction P pillar region 3, and the other side is located in the superjunction N pillar region. A source trench is etched on the top of the superjunction N pillar region, and ion implantation is performed in the trench to form P + region. A surface P + region 6 is implanted on one side of the gate trench at the top of the superjunction P pillar region 3. + Among them, the surface P

[0099] Adopting the technical solution provided by the present invention, compared with the prior art, it has the following beneficial effects:

[0100] 1) In this asymmetric source trench hexagonal superjunction trench MOSFET structure, since the cell arrangement is hexagonal and has an asymmetric double-channel. Compared with the traditional strip cell superjunction MOSFET, the present invention has a higher channel density. Based on the smallest cell unit of this design and with reference to the conventional MOSFET design line width, assuming the side length of the hexagonal cell is L, the theoretical calculation shows that the channel length per unit area of this design is: .

[0101] Under the same process conditions, the equivalent cell width of the conventional strip cell is , and the channel length per unit area of the strip cell is: .

[0102] It can be seen from this that the present invention is expected to increase the channel density of the superjunction MOSFET by 66.7%.

[0103] 2) In this asymmetric source trench hexagonal superjunction trench MOSFET structure, due to the matching design of the superjunction and the MOSFET and the asymmetric channel design, it is realized that the peak of the trench gate oxide electric field is located inside the P region of the superjunction. This is beneficial to reducing the gate oxide electric field, thereby realizing gate oxide protection and improving the reliability of the gate oxide of the superjunction trench MOSFET device.

[0104] Example 2

[0105] The difference between this embodiment and Embodiment 1 is that an N-type epitaxial layer is further provided on the upper surface of the N + substrate 1, and the first N pillar region 4, the first P pillar region, the second N pillar region 2, and the second P pillar region are provided on the upper surface of the N-type epitaxial layer.

[0106] In this embodiment, the preparation of the superjunction trench MOSFET structure includes the following steps:

[0107] S1: Construct an N-type epitaxial layer and a P-type epitaxial layer on the N + substrate 1 to form a P pillar region and a plurality of N pillar regions; wherein, the shape of the N pillar region in a top view is a regular hexagon, and the P pillar region surrounds each N pillar region;

[0108] S2: Construct a PW channel region and a source contact region on the N pillar region and the P pillar region;

[0109] S3: Construct a first source trench, a second source trench, and a gate trench; wherein, the N pillar region includes a first N pillar region 4 and a second N pillar region 2; the first source trench is disposed in the first N pillar region 4, and the second source trench is disposed in the second N pillar region 2; one side of the gate trench is disposed in the second N pillar region 2, and the other side is disposed in the P pillar region and penetrates through the PW channel region. The distance between the gate trench and the first source trench is greater than the distance between the second source trench and the gate trench to form an asymmetric bilateral channel region and a channel region.

[0110] Among them, as Figure 11 shown, S1 includes the following steps:

[0111] Construct an N-type epitaxial layer on the N + substrate 1; the N-type epitaxial layer has an electron-type doping;

[0112] Construct a first trench in the N-type epitaxial layer, and the first trench does not penetrate the N-type epitaxial layer;

[0113] Form a P-type epitaxial layer in the first trench, and the first trench needs to be filled without voids by the P-type epitaxial layer, and the P-type epitaxial layer has a hole-type doping.

[0114] It will be understood that the present invention is described by way of some embodiments, and those skilled in the art will appreciate that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the present invention. Additionally, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the scope protected by the present invention.

[0115] In addition, it should be understood that although this specification is described in terms of embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A super junction trench MOSFET structure, characterized in that: Including N + The substrate is provided in the N + A first cellular structure and a second cellular structure on a substrate; wherein the first cellular structure and the second cellular structure are both regular hexagonal in shape when viewed from above; The first cell structure includes a first N column region and a first P column region surrounding the first N column region, and a first source groove is disposed on the first N column region; The second cell structure includes a second N column region and a second P column region surrounding the second N column region, and a second source groove is arranged on the second N column region; the second cell structure is provided with a plurality of second cell structures, and the plurality of second cell structures surround the first cell structure; the first P column region and the second P column region are an integrated structure; The second cell structure further includes a gate groove, the gate groove surrounds the second source groove, a first channel is formed between the gate groove and the first source groove, a second channel is formed between the gate groove and the second source groove, and the lengths of the first channel and the second channel are different; the length of the first channel refers to the distance between the first source groove and the gate groove, and the length of the second channel refers to the distance between the second source groove and the gate groove; The length of the first channel is greater than that of the second channel; one side of the gate groove is arranged on the second P column region, and the other side is arranged on the second N column region.

2. The super junction trench MOSFET structure according to claim 1, characterized in that: The super junction trench MOSFET structure includes at least one cell, and one cell includes one cell first structure and six cell second structures; when there are multiple cells, two adjacent cells share two cell second structures.

3. The super junction trench MOSFET structure according to claim 2, characterized in that: When there are a plurality of cells, at least one cell second structure is shared by three cell first structures.

4. The super junction trench MOSFET structure according to any one of claims 1 to 3, characterized in that: The first N column region, the first P column region, the second N column region and the second P column region are arranged in the N + The upper surface of the substrate.

5. The super junction trench MOSFET structure according to any one of claims 1 to 3, characterized in that: The N + An N-type epitaxial layer is also disposed on the upper surface of the substrate, and the first N-column region, the first P-column region, the second N-column region and the second P-column region are disposed on the upper surface of the N-type epitaxial layer.

6. The super junction trench MOSFET structure according to claim 4, characterized in that: A first P-well is formed between the first source groove and the gate groove, the first P-well surrounds the first source groove, and the first P-well is a hollow regular hexagon in a top view; The first P well is formed with a surface P + Area and First N + , the surface P + The first N + Surrounding the surface P + area, the surface P + The area is a hollow regular hexagon in top view, and the first N + It also appears as a hollow regular hexagon when viewed from above; A second P-well is disposed between the second source groove and the gate groove, the second P-well surrounds the second source groove, and the second P-well is a hollow regular hexagon in a top view; The upper surface of the second P well is also formed with a second N + , the second N + Surrounding the second source slot, the second N + It also appears as a hollow regular hexagon when viewed from above; A gate oxide layer is arranged in the gate groove, and the gate oxide layer is arranged at the bottom of the gate groove, a side close to the first source groove, and a side close to the second source groove.

7. The super junction trench MOSFET structure according to claim 5, characterized in that: A first P-well is formed between the first source groove and the gate groove, the first P-well surrounds the first source groove, and the first P-well is a hollow regular hexagon in a top view; A surface P+ region and a first N+ are formed on the first P well, the surface P+ region surrounds the upper end of the first P well, the first N+ surrounds the surface P+ region, the surface P+ region is a hollow regular hexagon in a top view, and the first N+ is also a hollow regular hexagon in a top view; A second P-well is disposed between the second source groove and the gate groove, the second P-well surrounds the second source groove, and the second P-well is a hollow regular hexagon in a top view; A second N+ is also formed on the upper surface of the second P well, the second N+ surrounds the second source groove, and the second N+ is also a hollow regular hexagon in a top view; A gate oxide layer is arranged in the gate groove, and the gate oxide layer is arranged at the bottom of the gate groove, a side close to the first source groove, and a side close to the second source groove.

8. A method for manufacturing a super junction trench MOSFET structure, characterized in that: The method for manufacturing the super junction trench MOSFET structure according to any one of claims 1 to 7 comprises the following steps: In N + An N-type epitaxial layer and a P-type epitaxial layer are constructed on the substrate to form a P column region and a plurality of N column regions; wherein the shape of the N column region in a top view is a regular hexagon, and the P column region surrounds each of the N column regions; Construct P on the N column area and P column area W a channel region and a source contact region; A first source trench, a second source trench and a gate trench are constructed; wherein the N column region includes a first N column region and a second N column region; the first source trench is arranged in the first N column region, and the second source trench is arranged in the second N column region; one side of the gate trench is arranged in the second N column region, and the other side is arranged in the P column region, and the gate trench penetrates the P column region. W The channel region, the distance between the gate trench and the first source trench is greater than the distance between the second source trench and the gate trench.

9. The method for manufacturing a super junction trench MOSFET structure according to claim 8, characterized in that: The N + An N-type epitaxial layer and a P-type epitaxial layer are constructed on a substrate to form a P column region and a plurality of N column regions, including the following steps: In N + An N-type epitaxial layer is constructed on the substrate; the N-type epitaxial layer has electronic type doping; Constructing a first trench in the N-type epitaxial layer, wherein the first trench penetrates or does not penetrate the N-type epitaxial layer, so that the N-type epitaxial layer forms a plurality of N column regions having a regular hexagonal shape in top view; A P-type epitaxial layer is formed in the first trench, the first trench is filled with the P-type epitaxial layer without voids, and the P-type epitaxial layer has hole-type doping.

10. The method for manufacturing a super junction trench MOSFET structure according to claim 8, characterized in that: The construction of the first source trench, the second source trench and the gate trench comprises the following steps: Selecting the location of the first N column region; Selecting a position of a second N column region according to a position of the first N column region; According to the position of the first N column region, constructing a first source trench; According to the position of the second N column region, construct a second source trench and a gate trench; The super junction trench MOSFET structure includes at least one cell; when there are several cells, one cell includes one first N column region and six second N column regions, and two adjacent cells share two second N column regions.

11. The method for manufacturing a super junction trench MOSFET structure according to claim 8, characterized in that: The P column region and the P column region are constructed W The channel region and the source contact region include the following steps: Through two ion implantation processes, P column area and N column area are formed in turn. W Channel region and source contact region, where P W The channel region is doped with medium-concentration hole type; the source contact region is doped with high-concentration electron type.

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