A Wide Bandgap Semiconductor Trench MOSFET Device Structure and Its Fabrication Method

Abstract

The present invention provides a wide-bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof. The above structure includes an epitaxial layer grown on a substrate; a multi-level P-type shielding region disposed vertically in the epitaxial layer and having a width dimension gradually decreasing in the vertical direction; a multi-level N-type doping region wrapped on the outer wall side of the multi-level P-type shielding region; a source P+ region and a source N+ region arranged side by side and disposed in the epitaxial layer, and the source P+ region is electrically connected to the multi-level P-type shielding region through a P-well region; a source electrode disposed on the top of the source P+ region and the source N+ region; a drain electrode disposed at the bottom of the substrate; a gate structure penetrating through the source P+ region and the source N+ region into the epitaxial layer and contacting the multi-level P-type shielding region at the bottom; a P-type connection layer disposed on the outer wall side of a part of the gate structure and contacting the multi-level P-type shielding region and the multi-level N-type doping region at the bottom for grounding the multi-level P-type shielding region. This structure has the effects of high power density, low power consumption, and high breakdown voltage performance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly relates to a wide-bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof. Background Art

[0002] Due to the limitations of its own material properties, the performance improvement of traditional silicon-based devices has approached a bottleneck and it is difficult to meet the growing demands for high power density and low power consumption. Therefore, researching and developing semiconductor materials with higher performance has become an inevitable trend.

[0003] The third-generation and fourth-generation wide-bandgap semiconductor materials represented by silicon carbide (SiC) and gallium oxide ( ), have emerged as the times require. Compared with traditional silicon materials, wide-bandgap semiconductor materials have significant advantages in key physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. Research shows that the Baliga figures of merit of SiC and are 340 times and 3400 times that of silicon materials respectively. Power devices prepared based on SiC and , such as diodes, transistors, and power integrated circuits, not only have a smaller chip area but also exhibit more excellent electrical characteristics. The research value and market application prospects of SiC and materials are particularly prominent.

[0004] In the doping technology of wide-bandgap semiconductor materials, P-type doping of silicon carbide (SiC) devices can be achieved by ion implantation or epitaxial growth. However, for materials with a larger bandgap width, such as gallium nitride (GaN), gallium oxide ( ), diamond (C), and aluminum nitride (AlN), it is difficult to achieve P-type doping by ion implantation. Currently, there are mainly two technical solutions: one is the " semi-wrapped asymmetric trench structure" adopted by Infineon Technologies AG in Germany, and the other is the scheme adopted by Rohm Co., Ltd. in Japan of constructing source double trenches on both sides of the gate trench to shield the bottom of the middle gate trench. However, these existing technologies still have the following defects:

[0005] 1. High electric field problem: The high electric field in the material drift region will cause a significant increase in the electric field strength on the gate dielectric layer, especially at the trench corners, where this problem is more prominent. At high drain voltages, the gate dielectric layer is prone to rapid breakdown and has poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit.

[0006] 2. On-resistance problem: The depletion region of the PN junction formed by the P shield region set at the bottom of the trench and the N drift region cannot conduct current, resulting in an increase in the on-resistance of the device and affecting the overall performance of the device.

[0007] 3. Process limitation problem: Due to the limited depth of ion implantation, many targeted trench gate protection structures and surge protection designs are difficult to implement in the process, which limits the further improvement of device performance.

[0008] In summary, there are still many deficiencies in the prior art in terms of high power density, low power consumption, and high breakdown voltage performance. There is an urgent need for a new technical solution to solve the above problems to meet the growing market demand. Summary of the Invention

[0009] Based on the above description, the present invention provides a wide bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof, which can effectively solve the technical problems that there are many deficiencies in the MOSFET device structure in the prior art in terms of high power density, low power consumption, and high breakdown voltage performance.

[0010] The technical solution of the present invention to solve the above technical problems is as follows:

[0011] In the first aspect, the present invention provides a wide bandgap semiconductor trench MOSFET device structure, including:

[0012] An epitaxial layer grown on a substrate;

[0013] A multi-level P-type shielding region disposed in the epitaxial layer along the vertical direction, and the width dimension gradually decreases along the vertical direction;

[0014] A multi-level N-type doping region wrapped on the outer wall side of the multi-level P-type shielding region;

[0015] A source P+ region and a source N+ region disposed side by side in contact in the epitaxial layer, and the source P+ region is electrically connected to the multi-level P-type shielding region through a P-well region;

[0016] A source disposed on the tops of the source P+ region and the source N+ region;

[0017] A drain disposed at the bottom of the substrate;

[0018] A gate structure penetrating through the source P+ region and the source N+ region into the epitaxial layer, and the bottom thereof is in contact with the multi-level P-type shielding region;

[0019] A P-type connection layer disposed on the outer wall side of a part of the gate structure, and the bottom thereof is in contact with the multi-level P-type shielding region and the multi-level N-type doping region, for grounding the multi-level P-type shielding region.

[0020] On the basis of the above technical solution, the present invention can also be improved as follows.

[0021] Further, the device structure further includes multi-level gate trenches;

[0022] The multi-level gate trench is disposed in the epitaxial layer in the vertical direction, and the bottom of the multi-level gate trench has a radian;

[0023] The multi-level P-type shielding region is formed by implantation from the bottom of the multi-level gate trench, and the width of the multi-level P-type shielding region gradually decreases in the depth direction of the multi-level gate trench.

[0024] Further, the multi-level gate trench includes a first-level gate trench and a second-level gate trench;

[0025] The overall cross-section of the first-level gate trench and the second-level gate trench is in a stepped shape.

[0026] Further, the multi-level P-type shielding region includes a first-level P-type shielding region and a second-level P-type shielding region;

[0027] The first-level P-type shielding region and the second-level P-type shielding region are arranged in sequence in the vertical direction;

[0028] There is a first overlapping region between the first-level P-type shielding region and the second-level P-type shielding region, and the P-type doping concentration in the first overlapping region is higher than that in the non-first overlapping region.

[0029] Further, the multi-level N-type doping region includes a first-level N-type doping region and a second-level N-type doping region;

[0030] The first-level N-type doping region and the second-level N-type doping region are arranged in sequence in the vertical direction, and are respectively arranged in a corresponding wrapping manner with the first-level P-type shielding region and the second-level P-type shielding region;

[0031] There is a second overlapping region between the first-level N-type doping region and the second-level N-type doping region, and the N-type doping concentration in the second overlapping region is higher than that in the non-second overlapping region.

[0032] Further, the gate structure includes a gate dielectric layer and gate polysilicon;

[0033] The gate dielectric layer is disposed on the inner wall side of the multi-level gate trench;

[0034] The gate polysilicon is filled in the trench inside the gate dielectric layer.

[0035] Further, the device structure further includes an interlayer dielectric layer;

[0036] The interlayer dielectric layer is disposed on the top of the gate dielectric layer and the gate polysilicon.

[0037] Further, the device structure further includes a P buried layer;

[0038] The P buried layer is disposed in the epitaxial layer; the P buried layer overlaps with the multi-stage P-type shielding region in the vertical direction to ground the multi-stage P-type shielding region.

[0039] In a second aspect, the present invention further provides a manufacturing method for manufacturing the wide-bandgap semiconductor trench MOSFET device structure as described in the first aspect, including the following steps:

[0040] S1. Epitaxially grow an epitaxial layer on a substrate;

[0041] S2. Etch a first-stage trench and retain a hard mask, and the bottom of the first-stage trench has a radian;

[0042] S3. Perform P-type and N-type ion implantation at the bottom of the first-stage trench to obtain a first-stage P-type shielding region and a first-stage N-type doping region;

[0043] S4. Prepare sidewalls at the first-stage trench and etch a second-stage trench;

[0044] S5. Horizontally etch a trench at the bottom of the first-stage P-type shielding region, and perform P-type ion implantation to form a second-stage P-type shielding region; the second-stage P-type shielding region overlaps with the first-stage P-type shielding region;

[0045] S6. Horizontally etch a trench at the bottom of the first-stage N-type doping region, and implant to form a second-stage N-type doping region, and the second-stage N-type doping region overlaps with the first-stage N-type doping region;

[0046] S7. Remove the sidewalls and the hard mask;

[0047] S8. Thermally oxidize to generate a gate oxide to obtain a gate dielectric layer, and deposit polysilicon to obtain gate polysilicon;

[0048] S9. Deposit metal to form an interlayer dielectric layer, a source electrode, and a drain electrode, thus obtaining.

[0049] Based on the above technical solutions, the present invention can also be improved as follows.

[0050] Further, in step S3, the concentration of P-type ion implantation is higher than that of N-type ion implantation, and the energy of N-type ion implantation is higher than that of P-type ion implantation.

[0051] Compared with the prior art, the technical solution of the present application has the following beneficial technical effects:

[0052] Compared with the prior art, the wide-bandgap semiconductor trench MOSFET device structure and its manufacturing method provided by the present invention have the following advantages:

[0053] (1) The device structure forms multi-level gate trenches and multi-level P-type shielding regions through self-aligned etching. Among them, the multi-level gate trenches and multi-level P-type shielding regions can introduce additional electric field concentration points, reducing the electric field intensity concentrated in the corners of the gate oxide. In an optional example, a P-type connection layer is set to ground the P-type shielding region.

[0054] (2) In the forward conduction current flow direction of the multi-level P-type shielding region, the width of the P-type shielding region gradually decreases, and the current path width of the forward conduction current increases. And through the self-aligned process, the multi-level stepped P-type shielding region is wrapped by multi-level N-type doped regions, and the concentration of the multi-level N-type doped regions is higher than that of the epitaxial layer. The multi-level N-type doped regions have the following advantages: The high-concentration N-type doping can prevent the P-type shielding region from forming an overly wide depletion region in the N-type doped region, reducing the influence of the P-type shielding region on the device conduction characteristics.

[0055] (3) The multi-level P-type shielding region is directly injected from the bottom after etching, using a lower injection energy on the premise of achieving the same depth of the P-type shielding region.

[0056] In summary, the wide-bandgap semiconductor trench MOSFET device structure provided by the present invention has the effects of high power density, low power consumption, and high breakdown voltage performance. Description of the Drawings

[0057] Figure 1 It is a three-dimensional structure schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided by Embodiment 1 of the present invention;

[0058] Figure 2 It is a structure schematic diagram at cross-section 1 and cross-section 2 of the wide-bandgap semiconductor trench MOSFET device structure provided by Embodiment 1 of the present invention;

[0059] Figures 3 - 6 It is an effect verification schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided by Embodiment 1 of the present invention;

[0060] Figure 7 It is a structure schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided by Embodiment 2 of the present invention;

[0061] Figure 8 It is a structure schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided by Embodiment 3 of the present invention;

[0062] Figure 9 It is a structure schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided by Embodiment 4 of the present invention;

[0063] Figure 10It is a schematic structural diagram of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 5 of the present invention;

[0064] Figure 11 It is a schematic structural diagram of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 6 of the present invention;

[0065] Figure 12 It is a schematic structural diagram of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 7 of the present invention;

[0066] Figures 13 - 21 It is a schematic diagram of the manufacturing method of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 8 of the present invention;

[0067] In the drawings, the list of components represented by each reference numeral is as follows:

[0068] 1. Substrate;

[0069] 2. Epitaxial layer;

[0070] 3. Multi-level P-type shielding region; 301. First-level P-type shielding region; 302. Second-level P-type shielding region;

[0071] 4. Multi-level N-type doping region; 401. First-level N-type doping region; 402. Second-level N-type doping region;

[0072] 5. Source P+ region;

[0073] 6. Source N+ region;

[0074] 7. Source;

[0075] 8. Drain;

[0076] 9. Gate structure; 901. Gate dielectric layer; 902. Gate polysilicon;

[0077] 10. P well region;

[0078] 11. P-type connection layer;

[0079] 12. Interlayer dielectric layer;

[0080] 13. P buried layer. Detailed implementation manners

[0081] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0082] The present invention provides a new trench MOSFET device structure for wide bandgap semiconductors and a manufacturing method thereof. The following further describes the embodiments of the present invention in detail in conjunction with the drawings and examples. The following examples are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0083] Example 1

[0084] As Figure 1 and Figure 2 shown, the embodiment of the present invention provides a trench MOSFET device structure for wide bandgap semiconductors. It should be noted that: the device structure includes a first cross-section (Cross-section 1) and a second cross-section (Cross-section 2), which specifically include: substrate 1, epitaxial layer 2, multi-level P-type shielding region 3, multi-level N-type doping region 4, source P+ region 5, source N+ region 6, P-type connection layer 11, source 7, drain 8 and gate structure 9.

[0085] The epitaxial layer 2 is grown on the substrate 1.

[0086] The multi-level P-type shielding region 3 is arranged vertically in the epitaxial layer 2, and the width dimension gradually decreases in the vertical direction.

[0087] The multi-level N-type doping region 4 is wrapped around the outer wall side of the multi-level P-type shielding region 3.

[0088] The source P+ region 5 and the source N+ region 6 are arranged in the epitaxial layer 2, and the source P+ region 5 is electrically connected to the multi-level P-type shielding region 3 through a P-well region.

[0089] The source 7 is arranged on the top of the source P+ region 5 and the source N+ region 6.

[0090] The drain 8 is arranged at the bottom of the substrate 1.

[0091] The gate structure 9 penetrates through the source P+ region 5 and the source N+ region 6 to the epitaxial layer 2, and the bottom contacts the multi-level P-type shielding region 3.

[0092] On the cross-section 2, multi-level P-type connection layers 11 are arranged. The P-type connection layers 11 are arranged on the outer wall side of part of the gate structure 9, and the bottom contacts the multi-level P-type shielding region 3 and the multi-level N-type doping region 4, and are used to realize the grounding of the multi-level P-type shielding region 3.

[0093] In an alternative embodiment, as Figure 1 shown, the device structure further includes multi-level gate trenches; the multi-level gate trenches are arranged vertically in the epitaxial layer 2, and the bottom of the multi-level gate trenches has a radian.

[0094] The multi-level P-type shielding region 3 is formed by implantation from the bottom of the multi-level gate trenches, and the width of the multi-level P-type shielding region 3 gradually decreases in the depth direction of the multi-level gate trenches.

[0095] Specifically, the multi-level gate trench includes a first-level gate trench and a second-level gate trench; the overall cross-section of the first-level gate trench and the second-level gate trench is stepped.

[0096] In a specific embodiment, as Figure 1 shown, the above-mentioned multi-level P-type shielding region 3 includes a first-level P-type shielding region 301 and a second-level P-type shielding region 302.

[0097] The first-level P-type shielding region 301 and the second-level P-type shielding region 302 are arranged in sequence along the vertical direction.

[0098] There is a first overlapping region between the first-level P-type shielding region 301 and the second-level P-type shielding region 302, and the P-type doping concentration in the first overlapping region is higher than that in the non-first overlapping region.

[0099] Correspondingly, as Figure 1 shown, the multi-level N-type doping region 4 includes a first-level N-type doping region 401 and a second-level N-type doping region 402.

[0100] The first-level N-type doping region 401 and the second-level N-type doping region 402 are arranged in sequence along the vertical direction, and are respectively arranged in a corresponding wrapping manner with the first-level P-type shielding region 301 and the second-level P-type shielding region 302.

[0101] There is a second overlapping region between the first-level N-type doping region 401 and the second-level N-type doping region 402, and the N-type doping concentration in the second overlapping region is higher than that in the non-second overlapping region.

[0102] It should be noted that the number of levels of the multi-level P-type shielding region 3, the multi-level gate trench, and the multi-level N-type doping region 4 is not limited to the above two levels. In actual operation, the number of levels can be set as required. Therefore, in the embodiments of the present invention, the number of levels of the multi-level P-type shielding region 3, the multi-level gate trench, and the multi-level N-type doping region 4 is defined as greater than or equal to 2.

[0103] In a specific embodiment, as Figure 1 shown, the gate structure 9 includes a gate dielectric layer 901 and a gate polysilicon 902.

[0104] The gate dielectric layer 901 is arranged on the inner wall side of the multi-level gate trench; the gate polysilicon 902 is filled in the trench inside the gate dielectric layer 901.

[0105] Furthermore, the device structure further includes an interlayer dielectric layer 12; the interlayer dielectric layer 12 is arranged on the top of the gate dielectric layer 901 and the gate polysilicon 902.

[0106] Effect description:

[0107] Regarding the technical defect 1 in the prior art: The device structure provided by this embodiment forms multi-level gate trenches and multi-level P-type shielding regions 3 (the first-level P-type shielding region 301 and the second-level P-type shielding region 302) through self-aligned etching. The multi-level gate trenches and multi-level P-type shielding regions 3 can introduce additional electric field concentration points, reducing the electric field intensity concentrated in the corners of the gate oxide; on cross-section 2, a P-type connection layer 11 is provided to ground the P-type shielding region.

[0108] The doping concentration distribution of the device simulation structure is as Figure 3 shown (the left figure is the ordinary gate / the right figure is the multi-level gate trench of this embodiment). Compared with the two structures, the structure proposed in this patent introduces a multi-level gate trench, a multi-level P-type shielding region 3 structure, and a multi-level N-type doping region 4 surrounding the multi-level P-type shielding region 3 (since the concentration of the multi-level N-type doping region 4 is not much different from that of the surrounding drift region, it is not shown in the figure).

[0109] The electric field distribution of the device in the blocking state is as Figure 4 shown (the left figure is the ordinary gate / the right figure is the multi-level gate trench of this embodiment). Compared with the two structures, due to the structure proposed in this patent introducing a multi-level gate trench and a multi-level P-type shielding region 3 structure, additional electric field concentration points are introduced, reducing the electric field of the gate oxide. The maximum electric field intensity of the gate oxide of the device structure proposed in this embodiment is 1.78 MV / cm (V ds = 1200 V, V gs = 0 V), which is 12.3% lower than that of the traditional structure.

[0110] Regarding the technical defect 2 in the prior art: In the current flow direction of the forward conduction current of the multi-level P-type shielding region 3, the width of the P-type shielding region gradually decreases, and the current path width of the forward conduction current increases. And through the self-aligned process, the multi-level stepped P-type shielding region is wrapped by the multi-level N-type doping region 4, and the concentration of the multi-level N-type doping region 4 is higher than that of the epitaxial layer 2. The multi-level N-type doping region 4 has the following advantages: The high-concentration N-type doping can prevent the P-type shielding region from forming an overly wide depletion region in the N-type epitaxial layer 2 region, reducing the influence of the P-type shielding region on the conduction characteristics of the device.

[0111] The current distribution of the device in the conduction state is as Figure 5 shown (the left figure is the ordinary gate / the right figure is the multi-level gate trench of this embodiment). The output characteristic curve of the device in the conduction state is as Figure 6 shown. Compared with the two structures, in the current flow direction of the forward conduction current of the multi-level P-type shielding region, the width of the P-type shielding region gradually decreases, the current path width of the forward conduction current increases, and the stepped high-doped N-type doping region around the P-type shielding region can minimize the influence of the new structure on the conduction energy of the device. The on-resistance of the device proposed in this embodiment and the traditional structure device is both 。

[0112] In summary, the structure provided by this embodiment can reduce the gate oxide electric field strength by 12.3% without affecting the device conduction ability.

[0113] Regarding the technical defect 3 in the prior art: A feasible process step for this structure is proposed for the device structure provided by this embodiment. In this process flow, the multi-level P-type shielding region 3 and the multi-level N-type doping region 4 are both implanted from the bottom of the trench. The advantage of doing this is to reduce the energy required for ion implantation.

[0114] Embodiment 2

[0115] Based on Embodiment 1, the difference from Embodiment 1 is that as Figure 7 shown, the multi-level trench may not be provided, and the stepped multi-level P-type shielding region 3 and the multi-level N-type doping region 4 are realized through multi-layer layout and by increasing the energy of N-type ion implantation.

[0116] Embodiment 3

[0117] Based on Embodiment 1, the difference from Embodiment 1 is that since Figure 1 the cross-section 1 can conduct current and the cross-section 2 cannot conduct current, by adjusting the ratio of the cross-section 1 and the cross-section 2 in the chip (as Figure 8 shown, only the layout setting of the P-type connection layer 11 in the trench extension direction is shown in the top view), the control of current and heat distribution can be achieved, and finally the purpose of improving the extreme stress reliability of the device can be realized.

[0118] Embodiment 4

[0119] Based on Embodiment 1, the difference from Embodiment 1 is that as Figure 9 shown, a P buried layer 13 can be provided in the epitaxial layer - the P buried layer 13 is provided in the epitaxial layer; the P buried layer 13 overlaps with the multi-level P-type shielding region in the vertical direction to ground the multi-level P-type shielding region.

[0120] The advantage of doing this is to further reduce the electric field strength of the gate oxide. As Figure 9 (cross-section 2) shown, the P buried layer 13 overlaps with the P-type shielding region in the vertical direction. The advantage of doing this is that the P buried layer 13 can ground the P-type shielding region through layout design, as shown in cross-section 2. And by adjusting the size and position of the opening of the P-type shielding region, the control of current and heat distribution can be achieved, and finally the purpose of improving the extreme stress reliability of the device can be realized.

[0121] Embodiment 5

[0122] Based on Embodiment 4, the difference from Embodiment 4 is that on the basis of the above solution, further, as Figure 10As shown, by adding a layout, deeper multi-level P-type shield region 3 ion implantation can be achieved in the cross-section, and the grounding of the P-buried layer 13 can be realized through the deeper multi-level P-type shield region 3.

[0123] Embodiment 6

[0124] Based on Embodiment 4, the difference from Embodiment 4 is that: on the basis of the above solution, further, as Figure 11 shown, the electrical connection between the P-buried layer 13 and the source (GND) can be achieved by increasing the ion implantation energy of the source P+ region 5.

[0125] Embodiment 7

[0126] Based on Embodiment 4, the difference from Embodiment 4 is that: on the basis of the above solution, further, as Figure 12 shown, by adding a layout, a deeper-level sub-trench can be achieved in some cross-sections - to obtain a deeper gate structure 9, and based on the deeper-level sub-trench, deeper multi-level P-type shield region 3 ion implantation can be achieved, and the grounding of the P-buried layer 13 can be realized through the deeper multi-level P-type shield region 3.

[0127] Embodiment 8

[0128] The embodiment of the present invention provides a manufacturing method for the wide-bandgap semiconductor trench MOSFET device structure corresponding to Embodiment 1. Refer to Figures 13 - 21 shown, the operations are as follows:

[0129] Step S1, ( Figure 13 shown) epitaxially grow an epitaxial layer on the substrate.

[0130] Step S2, ( Figure 14 shown) etch the first-level trench and retain the hard mask. The bottom of the first-level trench has a radian.

[0131] Step S3, ( Figure 15 shown) perform P-type and N-type ion implantation at the bottom of the first-level trench to obtain the first-level P-type shield region and the first-level N-type doped region.

[0132] Among them, the concentration of P-type ion implantation is higher than that of N-type ion implantation, and the energy of N-type ion implantation is higher than that of P-type ion implantation.

[0133] Due to the radian at the bottom of the trench, the N-type and P-type regions generated by ion implantation will not be completely at the bottom of the channel, and some ions will be implanted into both sides of the bottom of the trench and cause dispersion. The concentration of P-type ion implantation should be higher than that of N-type ion implantation (to avoid the compensation of P-type ion implantation by N-type ion implantation), and the energy of N-type ion implantation should be higher than that of P-type ion implantation (to achieve a deeper depth and lateral dispersion of N-type ion implantation).

[0134] Step S4. ( Figure 16 As shown in the figure) Prepare sidewalls at the first-level trenches and etch the second-level trenches.

[0135] Step S5. ( Figure 17 As shown in the figure) Horizontally etch trenches at the bottom of the first-level P-type shielding region, and perform P-type ion implantation to form the second-level P-type shielding region; there is an overlapping region between the second-level P-type shielding region and the first-level P-type shielding region, and the P-type doping concentration in this overlapping region is higher, and the protection ability for the gate oxide is better.

[0136] Step S6. ( Figure 18 As shown in the figure) Horizontally etch trenches at the bottom of the first-level N-type doping region, and implant to form the second-level N-type doping region. There is an overlapping region between the second-level N-type doping region and the first-level N-type doping region, and the N-type doping concentration in this overlapping region is higher, which can limit the influence of the depletion region of the high-concentration P-type shielding region on the current path.

[0137] Step S7. ( Figure 19 As shown in the figure) Remove the sidewalls and the hard mask.

[0138] Step S8. ( Figure 20 As shown in the figure) Thermally oxidize to generate the gate oxide to obtain the gate dielectric layer, and deposit polysilicon to obtain the gate polysilicon.

[0139] Step S9. ( Figure 21 As shown in the figure) Deposit metal to form the interlayer dielectric layer, the source electrode and the drain electrode, thus obtaining the device.

[0140] Since this manufacturing method is used for manufacturing the device structure of the wide-bandgap semiconductor trench MOSFET, the beneficial effects of the wide-bandgap semiconductor trench MOSFET device structure are equally applicable to this manufacturing method. For its beneficial effects, reference can be made to the above effect description, and no further elaboration will be made here.

[0141] In this specification, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A wide-bandgap semiconductor trench MOSFET device structure, characterized in that, Comprising: An epitaxial layer grown on a substrate; Multi-level P-type shielding regions disposed vertically in the epitaxial layer, and the width dimension gradually decreases vertically; Multi-level N-type doped regions wrapped on the outer wall side of the multi-level P-type shielding regions; A source P+ region and a source N+ region disposed side by side in contact in the epitaxial layer, and the source P+ region is electrically connected to the multi-level P-type shielding regions through a P-well region; A source electrode disposed on the top of the source P+ region and the source N+ region; A drain electrode disposed at the bottom of the substrate; A gate structure penetrating through the source P+ region and the source N+ region into the epitaxial layer, and the bottom is in contact with the multi-level P-type shielding regions; A P-type connection layer disposed on the outer wall side of a part of the gate structure, and the bottom is in contact with the multi-level P-type shielding regions and the multi-level N-type doped regions, for grounding the multi-level P-type shielding regions; The multi-level P-type shielding regions include a first-level P-type shielding region and a second-level P-type shielding region; The first-level P-type shielding region and the second-level P-type shielding region are arranged in sequence vertically; There is a first overlapping region between the first-level P-type shielding region and the second-level P-type shielding region, and the P-type doping concentration in the first overlapping region is higher than that in the non-first overlapping region; The multi-level N-type doped regions include a first-level N-type doped region and a second-level N-type doped region; The first-level N-type doped region and the second-level N-type doped region are arranged in sequence vertically and are respectively wrapped corresponding to the first-level P-type shielding region and the second-level P-type shielding region; There is a second overlapping region between the first-level N-type doped region and the second-level N-type doped region, and the N-type doping concentration in the second overlapping region is higher than that in the non-second overlapping region.

2. The wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that The device structure further includes multi-level gate trenches; The multi-level gate trenches are disposed vertically in the epitaxial layer, and the bottom of the multi-level gate trenches has a curvature; The multi-level P-type shielding regions are formed by implanting from the bottom of the multi-level gate trenches, and the width of the multi-level P-type shielding regions gradually decreases in the depth direction of the multi-level gate trenches.

3. The wide-bandgap semiconductor trench MOSFET device structure according to claim 2, characterized in that, The multi-level gate trenches include a first-level gate trench and a second-level gate trench; The overall cross-section of the first-level gate trench and the second-level gate trench is in a stepped shape.

4. The wide-bandgap semiconductor trench MOSFET device structure according to claim 2, wherein The gate structure includes a gate dielectric layer and gate polysilicon; The gate dielectric layer is disposed on the inner wall side of the multi-level gate trenches; The gate polysilicon is filled in the trenches inside the gate dielectric layer.

5. The wide bandgap semiconductor trench MOSFET device structure according to claim 4, characterized in that, The device structure further includes an interlayer dielectric layer; The interlayer dielectric layer is disposed on the top of the gate dielectric layer and the gate polysilicon.

6. The wide-bandgap semiconductor trench MOSFET device structure according to claim 1, wherein The device structure further includes a P buried layer; The P buried layer is disposed in the epitaxial layer; the P buried layer overlaps with the multi-level P-type shielding regions vertically to ground the multi-level P-type shielding regions.

7. A manufacturing method for fabricating a wide-bandgap semiconductor trench MOSFET device structure as described in any one of claims 1 to 6, characterized in that, Including the following steps: S1. Epitaxially grow an epitaxial layer on a substrate; S2. Etch a first-level trench and retain a hard mask, and the bottom of the first-level trench has a curvature; S3. Perform P-type and N-type ion implantation at the bottom of the first-level trench to obtain a first-level P-type shielding region and a first-level N-type doped region; S4. Prepare sidewalls at the first-level trenches and etch second-level trenches; S5. Horizontally etch trenches at the bottom of the first-level P-type shielding region, and perform P-type ion implantation to form a second-level P-type shielding region; there is an overlapping region between the second-level P-type shielding region and the first-level P-type shielding region; S6. Horizontally etch trenches at the bottom of the first-level N-type doping region, and implant to form a second-level N-type doping region. There is an overlapping region between the second-level N-type doping region and the first-level N-type doping region; S7. Remove the sidewalls and the hard mask; S8. Thermally oxidize to generate a gate oxide to obtain a gate dielectric layer, and deposit polysilicon to obtain gate polysilicon; S9. Deposit metal to form an interlayer dielectric layer, source electrodes, and drain electrodes, thus completing the process.

8. The manufacturing method according to claim 7, wherein In step S3, the concentration of P-type ion implantation is higher than that of N-type ion implantation, and the energy of N-type ion implantation is higher than that of P-type ion implantation.

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