A trench MOSFET device and its fabrication method

Abstract

This application discloses a trench MOSFET device and its fabrication method. The fabrication method includes: performing trench etching on the epitaxial layer of the device using a first preset process to etch a plurality of terminal ring trenches in at least the terminal region of the epitaxial layer, thereby defining a plurality of first platforms and a second platform in the terminal region; performing elemental doping and doping impurity activation treatments sequentially on all first platforms and the second platform using a second preset process, so that each first platform corresponds to a terminal ring working region; and sequentially fabricating the gate, source, and drain on the epitaxial layer using a third preset process to obtain the trench MOSFET device. Compared with the prior art, the trench MOSFET device fabricated by this solution allows for more precise control over the width and doping concentration of the terminal ring structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a trench MOSFET device and its fabrication method. Background Technology

[0002] Trench MOSFETs are widely used in the power semiconductor field due to their high integration and low on-resistance. The breakdown voltage of a trench MOSFET depends not only on the design of its cell region but also closely on the structure of its termination ring. This is because the termination ring, through a series of annular diffusion regions with the same doping type as the bulk region, gradually depletes and distributes the surface electric field, making it a key structure for achieving high breakdown voltage in trench MOSFETs.

[0003] In related technologies, the fabrication process of the termination ring structure of traditional trench MOSFET devices is usually carried out after the completion of the core cell region structure, such as the gate. This requires additional photolithography steps and supporting processes to define the termination ring region separately, which not only increases the complexity and manufacturing cost, but also makes it easy for the doping distribution of the termination ring region to change during subsequent high-temperature processes. In other words, it is difficult to achieve precise control over the width and doping concentration of the termination ring in the fabrication process of traditional trench MOSFET devices. Summary of the Invention

[0004] The purpose of this application is to provide a trench MOSFET device and its fabrication method, aiming to improve the traditional trench MOSFET device's terminal ring structure fabrication process, which makes it difficult to accurately control the width and doping concentration of the terminal ring structure.

[0005] To achieve this objective, embodiments of this application provide a method for fabricating a trench MOSFET device, the method comprising:

[0006] A trench etching process is performed on the epitaxial layer of the device using a first preset process to etch at least a number of terminal ring trenches in the terminal region of the epitaxial layer of the device, thereby defining a number of first platforms and a second platform in the terminal region. Each first platform is located between two adjacent terminal ring trenches, and the second platform is located between the cell region of the epitaxial layer of the device and the terminal ring trench adjacent to the cell region.

[0007] By performing element doping and doping impurity activation processes sequentially on all first and second platforms using a second preset process, each first platform forms a corresponding terminal ring working area.

[0008] The trench MOSFET device is obtained by sequentially fabricating the gate, source, and drain on the epitaxial layer of the device using a third preset process.

[0009] Optionally, in some embodiments of this application, the trench etching process performed on the device epitaxial layer using a first preset process to etch at least a plurality of terminal ring trenches in the terminal region of the device epitaxial layer includes:

[0010] A hard mask layer is deposited on the surface of the epitaxial layer of the device using a chemical vapor deposition process.

[0011] A first photoresist layer is spin-coated on the side of the hard mask layer away from the epitaxial layer of the device.

[0012] By combining photolithography and dry etching processes, the first photomask information containing terminal ring trench region information is sequentially transferred to the terminal region of the first photoresist layer, the hard mask layer, and the device epitaxial layer, so as to etch a plurality of terminal ring trenches in the terminal region of the device epitaxial layer.

[0013] Optionally, in some embodiments of this application, the first photomask information containing terminal ring trench region information is sequentially transferred to the terminal region of the first photoresist layer, the hard mask layer, and the device epitaxial layer through a combination of photolithography and dry etching processes, so as to etch a plurality of terminal ring trenches in the terminal region of the device epitaxial layer, including:

[0014] The information of the first photomask is transferred to the first photoresist layer using a photolithography process;

[0015] After transferring the first photomask information on the first photoresist layer to the hard mask layer using a dry etching process, the remaining portion of the first photoresist layer is removed.

[0016] The first photomask information on the hard mask layer is transferred to the terminal region of the device epitaxial layer by a dry etching process, and after etching a number of terminal ring trenches in the terminal region of the device epitaxial layer, the hard mask layer is removed.

[0017] Optionally, in some embodiments of this application, the depth of the terminal ring groove is 2 μm to 5 μm; and / or,

[0018] The width of the terminal annular groove is 1 μm to 3 μm; and / or,

[0019] The width of the first platform is 3μm to 15μm.

[0020] Optionally, in some embodiments of this application, the width of each of the first platforms is set to increase incrementally along the direction from the edge of the cell region to the edge of the device.

[0021] Optionally, in some embodiments of this application, the step of sequentially performing elemental doping and doping impurity activation processing on all first platforms and second platforms through a second preset process, so that each first platform forms a terminal ring structure, includes:

[0022] A second photoresist layer is spin-coated onto the surface of the epitaxial layer of the device;

[0023] Through photolithography, the second photomask information containing the terminal ring injection region information is transferred to the second photoresist layer, so that the corresponding terminal ring injection region is defined on the surface of each of the first platform and the surface of the second platform through the partial masking of the second photoresist layer;

[0024] After elemental doping is performed on each of the terminal ring implantation regions by ion implantation process so that each of the terminal ring implantation regions forms an inactive implantation region, the second photoresist layer is removed.

[0025] The epitaxial layer of the device is subjected to high-temperature annealing heat treatment to activate the doped impurities in each of the unactivated implanted regions. Under the action of high-temperature diffusion, the doped impurities in each of the unactivated implanted regions are broadened and the junction depth is advanced, so that each of the first platforms forms a terminal ring working region.

[0026] Optionally, in some embodiments of this application, the dopant is a P-type dopant or an N-type dopant.

[0027] Optionally, in some embodiments of this application, the step of sequentially fabricating the gate, source, and drain on the device epitaxial layer using a third preset process to obtain the trench MOSFET device includes:

[0028] By combining thermal oxidation and chemical vapor deposition processes, the epitaxial layer of the device is sequentially grown with a gate oxide layer and filled with a gate metal, so that the gate is fabricated in the cell region of the epitaxial layer of the device while the filling of several terminal ring trenches is completed.

[0029] By combining photolithography and ion implantation, a preset doping process is performed on a preset position of the cell region to define the bulk implantation region and the source region at the preset position.

[0030] By combining chemical vapor deposition, photolithography, dry etching, and physical vapor deposition, the intermediate dielectric layer and contact plug are deposited sequentially on the surface of the epitaxial layer of the device to achieve the extraction of the source region and the terminal ring working region.

[0031] After depositing metal layers on the surface of the intermediate dielectric layer and the surface of the contact plug using a physical vapor deposition process, passivation, device thinning, and back-side metallization are performed to complete the fabrication of the source and the drain, thus obtaining the trench MOSFET device.

[0032] Optionally, in some embodiments of this application, the process of filling several terminal ring trenches simultaneously with the fabrication of the gate in the cell region of the device epitaxial layer includes: growing a gate oxide layer on the sidewalls of several main trenches and several terminal ring trenches in the cell region by thermal oxidation; filling the interior of several main trenches and several terminal ring trenches with gate metal by chemical vapor deposition, so as to complete the filling of several terminal ring trenches simultaneously with the fabrication of the gate in the cell region of the device epitaxial layer; and / or,

[0033] The step of defining the body implantation region and the source region at the preset location includes: performing a first doping treatment on a first preset location of the cell region using a combination of photolithography and ion implantation processes to obtain the body implantation region; performing a second doping treatment on a second preset location of the cell region using a combination of photolithography and ion implantation processes to obtain the source region; and / or,

[0034] The method for extracting the source region and the terminal ring working region includes: depositing an intermediate dielectric layer on the surface of the device epitaxial layer using a chemical vapor deposition process; spin-coating a third photoresist layer on the surface of the intermediate dielectric layer; sequentially transferring third photomask information containing contact hole region information to the third photoresist layer, the intermediate dielectric layer, and the device epitaxial layer using a combination of photolithography and dry etching processes, thereby forming a plurality of source contact holes and a plurality of working region contact holes on the intermediate dielectric layer and the device epitaxial layer; and filling each of the source contact holes and each of the working region contact holes with metal using a physical vapor deposition process to form contact plugs, thereby extracting the source region and the terminal ring working region.

[0035] In addition, to achieve this objective, embodiments of this application also provide a trench MOSFET device, which is prepared by any of the above-described preparation methods.

[0036] The trench MOSFET device and its fabrication method provided in this application, through the above-described method steps, when performing elemental doping and dopant activation treatments on all first and second platforms sequentially through a second preset process to form a terminal ring working region on each first platform, can utilize the physical structure of the terminal ring trench to limit the thermal diffusion area (i.e., the diffusion range of dopant in the corresponding terminal ring working region) and the region concentration (i.e., the concentration of dopant in the corresponding terminal ring working region) of each terminal ring working region. Therefore, in the fabrication process of this trench MOSFET device, only the spacing between several terminal ring trenches during the terminal ring trench etching and the ion implantation process during elemental doping need to be adjusted to achieve precise control of the width and doping concentration of the terminal ring structure of this trench MOSFET device. It is evident that, compared to the prior art, the trench MOSFET device fabricated by this technical solution more easily achieves precise control of the width and doping concentration of the terminal ring structure. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0039] Figure 1 This is a flowchart illustrating the fabrication method of a trench MOSFET device according to an embodiment of this application.

[0040] Figure 2 This is a schematic diagram of the fabrication process of the trench MOSFET device according to an embodiment of this application. Figure 1 .

[0041] Figure 3 This is a schematic diagram of the fabrication process of the trench MOSFET device according to an embodiment of this application. Figure 2 .

[0042] Figure 4 This is a schematic diagram of the fabrication process of the trench MOSFET device according to an embodiment of this application. Figure 3 .

[0043] Figure 5 This is a schematic diagram of the fabrication process of the trench MOSFET device according to an embodiment of this application. Figure 4 .

[0044] Figure 6 This is a schematic diagram of the fabrication process of the trench MOSFET device according to an embodiment of this application. Figure 5 .

[0045] Figure 7 This is a schematic diagram of the fabrication process of the trench MOSFET device according to an embodiment of this application. Figure 6 .

[0046] Figure 8 This is a schematic diagram of the fabrication process of the trench MOSFET device according to an embodiment of this application. Figure 7 .

[0047] Figure 9 This is a schematic diagram of the fabrication process of the trench MOSFET device according to an embodiment of this application. Figure 8 .

[0048] Figure 10 This is a schematic diagram of the fabrication process of the trench MOSFET device according to an embodiment of this application. Figure 9 .

[0049] Figure 11 This is a schematic diagram of the fabrication process of the trench MOSFET device according to an embodiment of this application. Figure 10 .

[0050] Figure 12 This is a schematic diagram of the fabrication process of the trench MOSFET device according to an embodiment of this application. Figure 10 one.

[0051] Figure 13 This is a schematic diagram of the fabrication process of the trench MOSFET device according to an embodiment of this application. Figure 10 two.

[0052] Figure 14 for Figure 1 The flowchart shows the specific steps of the trench MOSFET device fabrication method, specifically step S110.

[0053] Figure 15 for Figure 1 The flowchart shows the specific steps of the trench MOSFET device fabrication method, specifically step S120.

[0054] Figure 16 for Figure 1 The flowchart shows the specific steps of the trench MOSFET device fabrication method, specifically step S130.

[0055] Figure label:

[0056] 10. Device epitaxial layer; 11. Termination ring trench; 12. First plateau; 13. Second plateau; 14. Termination ring injection region; 15. Termination ring working region; 20. Hard mask layer; 21. Second notch; 31. First photoresist layer; 311. First notch; 32. Second photoresist layer; 321. Third notch; 33. Third photoresist layer; 331. Fourth notch; 41. Gate oxide layer; 42. Gate metal; 50. Intermediate dielectric layer; 61. Working region contact hole; 62. Contact plug; 70. Metal layer. Detailed Implementation

[0057] To make the inventive objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0058] In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0059] The technical solution of this application will be further described below with reference to the accompanying drawings and specific embodiments.

[0060] It should be noted that the fabrication method of the trench MOSFET device in this application mainly focuses on the improvement of the fabrication process of the terminal region structure in the trench MOSFET device. The fabrication process of the cell region structure in the trench MOSFET device can be almost identical to the fabrication process of the cell region structure in a conventional trench MOSFET device. Therefore, in the accompanying drawings, Figures 2 to 15 The diagrams shown only illustrate the structure of the terminal region in this trench MOSFET device, and do not show the structure of the cell region in this trench MOSFET device.

[0061] Please see Figures 1 to 13 As shown, in one embodiment, this application provides a method for fabricating a trench MOSFET device, which specifically includes:

[0062] Step S110: Perform trench etching on the device epitaxial layer using a first preset process to etch at least a number of terminal ring trenches in the terminal region of the device epitaxial layer, thereby defining a number of first platforms and a second platform in the terminal region.

[0063] It should be noted that the trench MOSFET device fabrication method of this application embodiment is mainly used in the production and manufacturing of trench MOSFET devices, and the trench MOSFET device is not limited to an N-type trench MOSFET device, but can also be a P-type trench MOSFET device. Therefore, when fabricating a trench MOSFET device using this method, the substrate and epitaxial layer preparation can be performed according to whether the trench MOSFET device to be fabricated is an N-type trench MOSFET device or a P-type trench MOSFET device. Taking the fabrication of an N-type trench MOSFET device as an example, a heavily doped P+ type silicon wafer (e.g., boron doped) needs to be prepared, and then a lightly doped P- type silicon layer is epitaxially grown on the P+ substrate using a chemical vapor deposition (CVD) process to form the corresponding device epitaxial layer 10. If a P-type trench MOSFET device needs to be fabricated, a heavily doped N+ type silicon wafer (e.g., phosphorus or arsenic doped) needs to be prepared, and then a lightly doped N- type silicon layer is epitaxially grown on the N+ substrate using a chemical vapor deposition (CVD) process to form the corresponding device epitaxial layer 10.

[0064] After the corresponding device epitaxial layer 10 is obtained through the above-mentioned substrate and epitaxial layer, the main trench etching process and the terminal ring trench etching process can be performed in the cell region of the device epitaxial layer 10 and in the terminal region of the device epitaxial layer 10. The two can be performed separately or simultaneously. That is, the trench etching process is performed in the device epitaxial layer 10 through the first preset process. It can be that a number of main trenches (not shown) are etched at the corresponding positions in the cell region of the device epitaxial layer 10 and a number of terminal ring trenches 11 are etched at the corresponding positions in the terminal region of the device epitaxial layer 10 through the conventional trench etching process. Then, a number of first platforms 12 and a second platform 13 are defined in the terminal region. Each first platform 12 is located between two adjacent terminal ring trenches 11, and the second platform 13 is located between the cell region of the device epitaxial layer 10 and the terminal ring trenches 11 of the adjacent cell region. Alternatively, a number of terminal ring trenches 11 can be etched only at the corresponding positions of the terminal region of the device epitaxial layer 10 using a conventional trench etching process, thereby defining a number of first platforms 12 and a second platform 13 in the terminal region. In this case, the step of etching a number of main trenches at the corresponding positions of the cell region of the device epitaxial layer 10 can be performed before or after the steps of this method.

[0065] Generally, the number of termination ring trenches 11 is preferably six. The depth of the termination ring trenches 11 is preferably 2μm to 5μm, the width of the termination ring trenches 11 is preferably 1μm to 3μm, and the width of the first platform 12 is preferably 3μm to 15μm. In this way, a reasonable electric field distribution gradient can be formed in the termination ring region within a limited device area. At the same time, the structural design of the termination ring trenches 11 with a depth of 2μm to 5μm and a width of 1μm to 3μm helps to accurately control the curvature of the termination ring working region 15 and the expansion of the depletion region, while the first platform 12 with a width of 3μm to 15μm provides sufficient lateral space for the doped termination ring. This size combination achieves a balance between optimizing termination protection efficiency and improving the longitudinal breakdown voltage capability of the device, while avoiding the problems of overly complex structure or excessive area occupation. It is beneficial to improve the reliability of the device and ensure the feasibility of the manufacturing process.

[0066] Step S120: Perform element doping and doping impurity activation treatments sequentially on all first and second platforms using a second preset process, so that each first platform forms a terminal ring working area.

[0067] It should be noted that after the fabrication of several terminal ring trenches 11 is completed through the above-described method steps to define the corresponding multiple first platforms 12 and second platforms 13, element doping and doping impurity activation treatments can be performed sequentially on all first platforms 12 and second platforms 13 through a second preset process, so that each first platform region forms a corresponding terminal ring working region 15. The element doping treatment mentioned in this method step refers to introducing specific impurity atoms (such as boron, phosphorus, etc.) into the semiconductor material of all first platforms 12 and second platforms 13 through methods such as ion implantation to change their conductivity type or resistivity. The doping impurity activation treatment mentioned in this method step refers to the subsequent high-temperature annealing process, the purpose of which is to repair the lattice damage caused by ion implantation and to allow the doped impurity atoms to enter the lattice positions for electrical activation, ultimately forming a stable terminal ring working region 15 with the expected electrical characteristics.

[0068] Step S130: The gate, source and drain are fabricated sequentially on the device epitaxial layer through a third preset process to obtain a trench MOSFET device.

[0069] It should be noted that after each of the first platforms 12 has formed a corresponding terminal ring working region 15 through the above-described steps, the gate, source, and drain can be fabricated sequentially on the device epitaxial layer 10 using the third preset process to obtain a trench MOSFET device. The purpose of this method is to complete the main structure of the trench MOSFET device, namely the fabrication of the gate, source, and drain, on the device epitaxial layer 10. This process is roughly the same as that of a general trench MOSFET device, that is, the gate, source, and drain can be fabricated sequentially on the device epitaxial layer 10 using conventional processes to finally obtain the trench MOSFET device.

[0070] In this way, the trench MOSFET device fabrication method of this application embodiment, through the above-described method steps, when performing elemental doping and dopant activation treatments sequentially on all first platforms 12 and second platforms 13 through a second preset process, so that each first platform 12 corresponds to a terminal ring working region 15, can utilize the physical structure of the terminal ring trench 11 to limit the thermal diffusion region (i.e., the diffusion range of dopant in the corresponding terminal ring working region 15) and the region concentration (i.e., the concentration of dopant in the corresponding terminal ring working region 15). Therefore, in the fabrication process of this trench MOSFET device, only the spacing between several terminal ring trenches 11 during etching and the ion implantation process during elemental doping need to be adjusted to achieve precise control of the width and doping concentration of the terminal ring working region 15 of this trench MOSFET device. It is evident that, compared to the prior art, the trench MOSFET device fabricated by this technical solution more easily achieves precise control of the width and doping concentration of the terminal ring working region 15.

[0071] In some examples, such as Figure 2 , Figure 3 , Figure 4 as well as Figure 14 As shown, the specific process of performing the above method step "performing trench etching on the device epitaxial layer using a first preset process to etch at least a number of terminal ring trenches in the terminal region of the device epitaxial layer" can be as follows:

[0072] Step S121: Deposit a hard mask layer on the surface of the device epitaxial layer using a chemical vapor deposition process.

[0073] Step S122: Spin-coat the first photoresist layer on the side of the hard mask layer away from the device epitaxial layer.

[0074] Step S123: By combining photolithography and dry etching processes, the first photomask information containing the terminal ring trench region information is sequentially transferred to the terminal region of the first photoresist layer, the hard mask layer, and the device epitaxial layer, so as to etch a number of terminal ring trenches in the terminal region of the device epitaxial layer.

[0075] It should be noted that, in the above method steps, when depositing the hard mask layer 20 on the surface of the device epitaxial layer 10 using chemical vapor deposition, a hard mask layer 20 with a preferred thickness of 2 μm to 10 μm can be deposited on the upper surface of the device epitaxial layer 10 to ensure that the hard mask layer 20 can provide good etching protection in the subsequent etching process of the terminal ring trench 11. The first photomask information containing terminal ring trench region information mentioned in the above method steps specifically refers to the first photomask information that can accurately define the planar pattern, size, and position distribution of all terminal ring trenches 11 that need to be etched on the surface of the device epitaxial layer. This first photomask information, with the light-blocking / light-transmitting pattern on the photomask as a carrier, is the direct basis and spatial positioning template for the subsequent photolithography and etching processes to physically transfer the terminal ring trench 11 design blueprint sequentially to the first photoresist layer 31, the hard mask layer 20, and the device epitaxial layer 10.

[0076] It should be noted that the method steps in this example are only for etching a number of terminal ring trenches 11 in the terminal region of the device epitaxial layer 10. When a number of main trenches are also etched in the cell region of the device epitaxial layer 10 at the same time, only the first photomask information needs to be adjusted so that the first photomask information includes not only the terminal ring trench region information but also the main trench region information.

[0077] In this way, by using the above method and steps, the corresponding number and location of terminal ring trenches 11 can be etched on the device epitaxial layer 10.

[0078] In some examples, the specific process of performing the above method step "by combining photolithography and dry etching processes, the first photomask information containing the terminal ring trench region information is sequentially transferred to the first photoresist layer, the hard mask layer, and the device epitaxial layer, so as to etch several terminal ring trenches in the device epitaxial layer" can be as follows: First, the first photomask information is transferred to the first photoresist layer 31 through photolithography (that is, the first photoresist layer 31 is formed as shown in the figure). Figure 2 The structure shown has several first notches 311. Then, the first photomask information on the first photoresist layer 31 is transferred to the hard mask layer 20 using a dry etching process (so that the hard mask layer 20 is formed as shown). Figure 3After the structure shown (with several second notches 21) is completed, the remaining portion of the first photoresist layer 31 is removed. Finally, the first photomask information on the hard mask layer 20 is transferred to the terminal region of the device epitaxial layer 10 using a dry etching process, so that several terminal ring trenches 11 are etched in the terminal region of the device epitaxial layer 10, and then the hard mask layer 20 is removed. In this way, through the precise combination of photolithography and dry etching processes, the pattern of the first photomask information is first copied to the first photoresist layer 31 with high fidelity, and then the pattern is precisely transferred to the hard mask layer 20 using the first photoresist layer 31 as a mask. Finally, the hard mask layer 20 is used as a durable mask to complete the etching of the device epitaxial layer 10. This layer-by-layer transfer process, utilizing the excellent etching resistance of the hard mask layer 20, effectively ensures the uniformity of the etching depth of the terminal ring trenches 11 and the vertical regularity of the sidewall morphology, thereby providing a key process guarantee for the consistency and reliability of device performance.

[0079] It should be noted that after etching several terminal ring trenches 11 in the terminal region of the epitaxial layer 10 using the above method steps, the hard mask layer 20 can be removed specifically by wet etching during the removal process. This allows for rapid, uniform, and selective removal of the hard mask layer 20, while avoiding physical damage or erosion to the formed terminal ring trench 11 structure. This process is simple to operate and highly efficient, facilitating surface cleaning after the formation of critical structures. It provides a smooth, residue-free starting interface for the subsequent fabrication of the main structure, ensuring smooth process flow and stable device performance.

[0080] In some examples, such as Figures 2 to 4 As shown, the width of each first platform 12 is along the direction from the edge of the cell region to the edge of the device (i.e., Figure 2 The direction indicated by the middle arrow is progressively increased. This structural arrangement allows for a smoother, stepped distribution of the electric field within the termination ring region, gradually consuming the electric field strength and effectively mitigating electric field concentration at the device edges. This design optimizes the breakdown voltage efficiency of the termination ring operating region 15, achieving a higher breakdown voltage for the same area, while also enhancing the long-term reliability of this trench MOSFET device.

[0081] In some examples, such as Figure 5 , Figure 6 , Figure 7 as well as Figure 15 As shown, the specific process of performing the above method step "perform element doping and doping impurity activation treatment sequentially on all first and second platforms through a second preset process so that each first platform forms a corresponding terminal ring working area" can be described as follows:

[0082] Step S121: Spin-coat a second photoresist layer onto the surface of the device epitaxial layer.

[0083] Step S122: Using photolithography, the second photomask information containing the terminal ring injection region information is transferred to the second photoresist layer, so as to define the corresponding terminal ring injection region on the surface of each first platform and the surface of the second platform through the partial masking of the second photoresist layer.

[0084] Step S123: After doping each terminal ring implantation region with elements through ion implantation process so that each terminal ring implantation region forms an inactive implantation region, the second photoresist layer is removed.

[0085] Step S124: Perform high-temperature annealing heat treatment on the epitaxial layer of the device to activate the doped impurities in each unactivated implanted region, so that the doped impurities in each unactivated implanted region can be broadened and the junction depth can be advanced under the high-temperature diffusion effect, so that each first platform can form a terminal ring working region.

[0086] It should be noted that the second photomask information containing information about the terminal ring implantation region mentioned in the above method steps specifically refers to the planar pattern, size, and positional distribution of the regions (i.e., terminal ring implantation regions 14) that need to be ion implanted on each of the first platforms 12 and second platforms 13 of the device epitaxial layer 10, which can be precisely defined by the second photomask information. This second photomask information, using the light-blocking / light-transmitting pattern on the photomask as a carrier, serves as the direct basis and spatial positioning template for subsequent ion implantation of each terminal ring implantation region 14. The above method steps specifically involve transferring the second photomask information to the second photoresist layer 32 through photolithography, such that the second photoresist layer 32 forms as shown in the image. Figure 5 The structure shown has several third notches 321. In the above method steps, when elemental doping is performed on each terminal ring implantation region 14 using ion implantation, the specific dopant can be selected as either a P-type or N-type dopant depending on whether the trench MOSFET device to be fabricated is an N-type or P-type trench MOSFET. For example, if an N-type trench MOSFET device is to be fabricated, the dopant can be a P-type dopant, such as boron. If a P-type trench MOSFET device is to be fabricated, the dopant can be an N-type dopant, such as phosphorus (P) or arsenic (As). The above method steps involve high-temperature annealing of the device epitaxial layer 10 to activate the dopant in each unactivated implantation region. During the process of widening and deepening the junction under high-temperature diffusion, the dopant in each unactivated implantation region can, due to the physical barrier of the terminal ring trench 11, extend laterally to the sidewall of the adjacent terminal ring trench 11, thus forming the terminal ring working region 15.

[0087] Furthermore, the temperature range for the high-temperature annealing heat treatment mentioned in the above method steps is typically set between 900°C and 1200°C. This temperature range is chosen to provide sufficient energy to effectively activate the doped impurities, allowing them to occupy lattice sites and restore electrical activity. On the other hand, the high temperature also facilitates the diffusion of impurity atoms, thereby achieving the required junction depth widening and advancement, and precisely controlling the final doping distribution and electrical characteristics of the terminal ring working region 15.

[0088] In this way, through the above methods and steps, each first platform 12 can be effectively configured to form a terminal ring working area 15.

[0089] In some examples, such as Figures 8 to 13 , Figure 16 As shown, the specific process of performing the above method step "to sequentially fabricate the gate, source, and drain on the device epitaxial layer through a third preset process to obtain a trench MOSFET device" can be as follows:

[0090] Step S131: By combining thermal oxidation and chemical vapor deposition processes, gate oxide layer growth and gate metal filling processes are performed on several terminal ring trenches in sequence, so as to complete the gate fabrication in the cell region of the device epitaxial layer while simultaneously completing the filling process of several terminal ring trenches.

[0091] It should be noted that the purpose of this method is to complete the fabrication of the gate and the filling of the termination ring trenches 11. The specific process is as follows: First, a gate oxide layer 41 is grown on the sidewalls of several main trenches and several termination ring trenches 11 in the cell region using a thermal oxidation process. Then, a gate metal 42 is filled into the interior of several main trenches and several termination ring trenches 11 using a chemical vapor deposition process. This completes the fabrication of the gate (i.e., the gate metal 42 filling the main trenches) in the cell region of the device epitaxial layer 10 while simultaneously filling the several termination ring trenches 11. Since the thermal oxidation process lacks regional selectivity, the gate oxide layer 41 will also grow on the surface of the device epitaxial layer 10. Similarly, since the chemical vapor deposition process also lacks regional selectivity, a layer of gate metal 42 will also be deposited on the surface of the device epitaxial layer 10. After completing the corresponding processes, the gate metal 42 on the surface of the device epitaxial layer 10 can be removed by chemical mechanical polishing, ensuring that it exists only inside the main trenches and the termination ring trenches 11. After removing the gate metal 42 from the surface of the epitaxial layer 10, a wet etching process (e.g., using a diluted hydrofluoric acid solution) is then used to selectively remove the gate oxide layer 41 from the surface of the epitaxial layer 10. This is because the etching rate of hydrofluoric acid on silicon oxide (gate oxide) is much higher than that on single-crystal silicon carbide (epitaxy layer) or metal, thus enabling precise removal of the oxide layer on the surface of the epitaxial layer 10 without damaging the underlying substrate material or the gate structure within the trench.

[0092] Step S132: By combining photolithography and ion implantation processes, preset doping treatment is performed on preset positions of the cell region to define the bulk implantation region and the source region at the preset positions.

[0093] It should be noted that the purpose of this method is to define the body implantation region and the source region. The specific process is as follows: First, a first doping treatment is performed on the first predetermined position of the cell region of the epitaxial layer 10 using a combination of photolithography and ion implantation to obtain the body implantation region (not shown). Then, a second doping treatment is performed on the second predetermined position of the cell region of the epitaxial layer 10 using a combination of photolithography and ion implantation to obtain the source region (i.e., the heavily doped source region, not shown). Similarly, depending on whether the trench MOSFET device to be fabricated is an N-type trench MOSFET or a P-type trench MOSFET, the corresponding first doping treatment can be performed to obtain the body implantation region, and the corresponding second doping treatment can be performed to obtain the heavily doped source region. Taking an N-type trench MOSFET device as an example, the first doping process can be ion implantation of a P-type dopant (such as boron) to obtain a body implantation region, and the second doping process can be ion implantation of an N+ type dopant (such as phosphorus / arsenic) to obtain a heavily doped source region. If the trench MOSFET device to be fabricated is a P-type trench MOSFET device, the first doping process can be ion implantation of an N-type dopant (such as phosphorus / arsenic) to obtain a body implantation region, and the second doping process can be ion implantation of a P+ type dopant (such as boron) to obtain a heavily doped source region.

[0094] Step S133: By combining chemical vapor deposition, photolithography, dry etching and physical vapor deposition, the intermediate dielectric layer and contact plug are deposited sequentially on the surface of the device epitaxial layer to achieve the extraction of the source region and the terminal ring working region.

[0095] It should be noted that the purpose of this method is to achieve the deposition of the intermediate dielectric layer 50 and the filling of the contact plug 62. The specific process is as follows: First, an intermediate dielectric layer 50 is deposited on the surface of the device epitaxial layer 10 using chemical vapor deposition. Next, a third photoresist layer 33 is spin-coated onto the surface of the intermediate dielectric layer 50. Then, through a combination of photolithography and dry etching processes, the third photomask information containing the contact hole area information is sequentially transferred to the third photoresist layer 33 (thus ensuring that the third photoresist layer 33 forms a shape similar to...). Figure 11The structure shown has several fourth notches 331), an intermediate dielectric layer 50, and a device epitaxial layer 10, to form several source contact holes (not shown, each source contact hole can be similar to...) on the intermediate dielectric layer 50 and the device epitaxial layer 10. Figure 12 The working area contact hole 61 shown extends through the intermediate dielectric layer 50 and partially extends to the source region of the device epitaxial layer 10, and several working area contact holes 61 (i.e., each working area contact hole 61 is as shown) Figure 12 As shown, after penetrating the intermediate dielectric layer 50, it partially extends to the terminal ring working region 15 of the device epitaxial layer 10. Finally, through a physical vapor deposition process, metal is filled at each source contact hole and each working region contact hole 61 to form contact plugs 62, so as to realize the lead-out of the source region and the terminal ring working region 15.

[0096] Generally, when filling the source contact holes and working area contact holes 61 with metal in the above-described method steps, tungsten is preferred. This allows for seamless filling of the high aspect ratio source contact holes and working area contact holes 61, ensuring the continuity and reliability of electrical contact. Furthermore, tungsten has a high melting point and good thermal stability, enabling it to withstand subsequent process temperatures. Its low resistivity also helps reduce source contact resistance and working area contact resistance, thereby improving the overall current conduction capability of the trench MOSFET device.

[0097] Step S134: After depositing metal layers on the surface of the intermediate dielectric layer and the contact plug through physical vapor deposition, passivation, device thinning and back metallization are carried out to complete the fabrication of the source and drain, and obtain the trench MOSFET device.

[0098] It should be noted that the method first deposits a metal layer 70, preferably 4μm to 10μm thick, on the surface of the intermediate dielectric layer 50 and the contact plug 62 using a physical vapor deposition process, so as to form a metal layer 70 on the front side of the device (i.e., Figure 13 The source electrode (i.e., the portion of the cell region corresponding to metal layer 70) is fabricated on the upper surface shown. Subsequently, conventional passivation is performed to protect the device surface from environmental influences, and conventional device thinning is used to optimize device thickness and thermal resistance. Then, low-resistance, reliable drain ohmic contacts are formed on the back side of the device (i.e., on the back side). Figure 13 The drain electrode (not shown) is fabricated on the lower surface shown. This series of processes fully constructs the electrode system and physical structure of the device, ensuring that the trench MOSFET device has good heat dissipation, electrical performance, and long-term operational reliability.

[0099] In this way, through the above-described steps, precise gate shaping and ensuring gate insulation quality and trench control capabilities can be achieved. Simultaneously, the source and drain interconnections and contacts are completed through controllable implantation and deposition etching processes to form a stable device structure. The entire process is highly compatible and controllable, effectively guaranteeing the performance and reliability of the key electrodes in this trench MOSFET device.

[0100] In one embodiment, such as Figure 13 As shown, this application embodiment also provides a trench MOSFET device, which is prepared by the preparation method of the above embodiment. Therefore, since the trench MOSFET device of this application embodiment is prepared by the preparation method of the above embodiment, it makes it easier to achieve precise control over the width and doping concentration of the terminal ring working region 15.

[0101] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a trench MOSFET device, characterized in that, The preparation method includes: A trench etching process is performed on the epitaxial layer of the device using a first preset process to etch at least a number of terminal ring trenches in the terminal region of the epitaxial layer of the device, thereby defining a number of first platforms and a second platform in the terminal region. Each first platform is located between two adjacent terminal ring trenches, and the second platform is located between the cell region of the epitaxial layer of the device and the terminal ring trench adjacent to the cell region. The second preset process is used to sequentially perform element doping and doping impurity activation processes on all the first and second platforms, so that each of the first platforms forms a corresponding terminal ring working area. The trench MOSFET device is obtained by sequentially fabricating the gate, source, and drain on the epitaxial layer of the device using a third preset process.

2. The preparation method according to claim 1, characterized in that, The process of performing trench etching on the epitaxial layer of the device using a first preset process to etch at least a plurality of terminal ring trenches in the terminal region of the epitaxial layer of the device includes: A hard mask layer is deposited on the surface of the epitaxial layer of the device using a chemical vapor deposition process. A first photoresist layer is spin-coated on the side of the hard mask layer away from the epitaxial layer of the device. By combining photolithography and dry etching processes, the first photomask information containing terminal ring trench region information is sequentially transferred to the terminal region of the first photoresist layer, the hard mask layer, and the device epitaxial layer, so as to etch a plurality of terminal ring trenches in the terminal region of the device epitaxial layer.

3. The preparation method according to claim 2, characterized in that, The method involves combining photolithography and dry etching processes to sequentially transfer first photomask information, including information about the terminal ring trench region, to the first photoresist layer, the hard mask layer, and the terminal region of the device epitaxial layer, thereby etching a plurality of terminal ring trenches in the terminal region of the device epitaxial layer, including: The information of the first photomask is transferred to the first photoresist layer using a photolithography process; After transferring the first photomask information on the first photoresist layer to the hard mask layer using a dry etching process, the remaining portion of the first photoresist layer is removed. The first photomask information on the hard mask layer is transferred to the terminal region of the device epitaxial layer by a dry etching process, and after etching a number of terminal ring trenches in the terminal region of the device epitaxial layer, the hard mask layer is removed.

4. The preparation method according to claim 1, characterized in that, The depth of the terminal ring groove is 2μm to 5μm; and / or, The width of the terminal annular groove is 1 μm to 3 μm; and / or, The width of the first platform is 3μm to 15μm.

5. The preparation method according to claim 1, characterized in that, The width of each of the first platforms increases progressively from the edge of the cell region to the edge of the device.

6. The preparation method according to claim 1, characterized in that, The process involves sequentially performing elemental doping and doping impurity activation treatments on all first and second platforms using a second preset process, so that each first platform forms a terminal ring working area, including: A second photoresist layer is spin-coated onto the surface of the epitaxial layer of the device; Through photolithography, the second photomask information containing the terminal ring injection region information is transferred to the second photoresist layer, so that the corresponding terminal ring injection region is defined on the surface of each of the first platforms and the surface of the second platform through the partial masking of the second photoresist layer; After elemental doping is performed on each of the terminal ring implantation regions by ion implantation process so that each of the terminal ring implantation regions forms an inactive implantation region, the second photoresist layer is removed. The epitaxial layer of the device is subjected to high-temperature annealing heat treatment to activate the doped impurities in each of the unactivated implanted regions. Under the action of high-temperature diffusion, the doped impurities in each of the unactivated implanted regions are broadened and the junction depth is advanced, so that each of the first platforms forms a terminal ring working region.

7. The preparation method according to claim 6, characterized in that, The doping impurities are P-type doping elements or N-type doping elements.

8. The preparation method according to any one of claims 1-7, characterized in that, The process of sequentially fabricating the gate, source, and drain electrodes on the epitaxial layer of the device using a third preset process to obtain the trench MOSFET device includes: By combining thermal oxidation and chemical vapor deposition processes, the epitaxial layer of the device is sequentially grown with a gate oxide layer and filled with a gate metal, so that the gate is fabricated in the cell region of the epitaxial layer of the device while the filling of several terminal ring trenches is completed. By combining photolithography and ion implantation, a preset doping process is performed on a preset position of the cell region to define the bulk implantation region and the source region at the preset position. By combining chemical vapor deposition, photolithography, dry etching, and physical vapor deposition, the intermediate dielectric layer and contact plug are deposited sequentially on the surface of the epitaxial layer of the device to achieve the extraction of the source region and the terminal ring working region. After depositing metal layers on the surface of the intermediate dielectric layer and the surface of the contact plug using a physical vapor deposition process, passivation, device thinning, and back-side metallization are performed to complete the fabrication of the source and the drain, thus obtaining the trench MOSFET device.

9. The preparation method according to claim 8, characterized in that, While fabricating the gate in the cell region of the device epitaxial layer, the filling process of several terminal ring trenches is completed, including: growing a gate oxide layer on the sidewalls of several main trenches and several terminal ring trenches in the cell region by thermal oxidation; filling the interior of several main trenches and several terminal ring trenches into the interior by chemical vapor deposition, so as to complete the filling process of several terminal ring trenches while fabricating the gate in the cell region of the device epitaxial layer; and / or, The step of defining the body implantation region and the source region at the preset positions includes: performing a first doping treatment on a first preset position of the cell region using a combination of photolithography and ion implantation processes to obtain the body implantation region; performing a second doping treatment on a second preset position of the cell region using a combination of photolithography and ion implantation processes to obtain the source region; and / or, The method for extracting the source region and the terminal ring working region includes: depositing an intermediate dielectric layer on the surface of the device epitaxial layer using a chemical vapor deposition process; spin-coating a third photoresist layer on the surface of the intermediate dielectric layer; sequentially transferring third photomask information containing contact hole region information to the third photoresist layer, the intermediate dielectric layer, and the device epitaxial layer using a combination of photolithography and dry etching processes, thereby forming a plurality of source contact holes and a plurality of working region contact holes on the intermediate dielectric layer and the device epitaxial layer; and filling each of the source contact holes and each of the working region contact holes with metal using a physical vapor deposition process to form contact plugs, thereby extracting the source region and the terminal ring working region.

10. A trench MOSFET device, characterized in that, The trench MOSFET device is prepared by the preparation method according to any one of claims 1-9.

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