A trench MOSFET device and a method of fabricating the same

Abstract

The application relates to the technical field of semiconductors, and particularly discloses a trench MOSFET device and a preparation method thereof, wherein the device comprises an N-type substrate, the N-type substrate sequentially has an N-type epitaxial layer, two Pwell regions and two inverted-trapezoidal trenches between the two Pwell regions from bottom to top; the Pwell region has an N+ region and a first P+ region, the N+ region and the first P+ region are located at the top of the Pwell region; one inclined edge of the inverted-trapezoidal trench is in contact with the corresponding Pwell region and N+ region; a gate oxide layer is deposited in the inverted-trapezoidal trench; the inverted-trapezoidal trench further has a polysilicon gate region, the polysilicon gate region is close to the corresponding Pwell region and N+ region; the inverted-trapezoidal trench further has a second P+ region; the second P+ regions have a Schottky contact region; the first P+ region and the top of the N+ region have a source ohmic contact region; the bottom of the N-type substrate has a drain ohmic contact region. The technical scheme can improve the reliability of the device and reduce power consumption.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench MOSFET device and a preparation method thereof. Background Art

[0002] Power devices boast a range of advantages, including high switching speeds, high withstand voltages, and excellent thermal stability. They are currently widely used in diverse and complex operating environments, including industrial control, power supplies, portable appliances, consumer electronics, automotive electronics, aviation, and aerospace. However, high power often results in higher operating temperatures, which can cause device electrical characteristics to deteriorate, compromising performance and reliability.

[0003] For example, traditional SiCMOSFET power devices control the switching of the device by changing the voltage applied to the gate. Currently, SiCMOSFETs mainly have two structures: planar gate and trench gate. Planar gate has JFET resistance, which results in a higher on-resistance than trench gate. To reduce energy loss, trench gate MOSFETs have become the main development target of major manufacturers. However, the gate oxide near the corners of the polysilicon gate of traditional trench structure SiCMOSFETs will break down under high withstand voltage conditions, resulting in reduced device reliability. Internationally, SiCMOSFETs with integrated SBDs have also been introduced. The integrated SBD is mainly embedded between two cells to increase the continuous current capability of the SiCMOSFET. However, this solution will increase Ids (drain-source current) when withstanding high voltage, resulting in higher overall energy consumption.

[0004] Therefore, a trench MOSFET device with high reliability and low power consumption and a preparation method thereof are needed. Summary of the Invention

[0005] One of the objectives of the present invention is to provide a trench MOSFET device that can improve device reliability and reduce power consumption.

[0006] In order to solve the above technical problems, this application provides the following technical solutions:

[0007] A trench MOSFET device includes an N-type substrate, wherein the N-type substrate has, from bottom to top, an N-type epitaxial portion and two Pwell regions, the two Pwell regions being located on either side of a top portion of the N-type epitaxial portion; the Pwell region having an N+ region and a first P+ region, the N+ region and the first P+ region being located on top of the Pwell region;

[0008] There are two inverted trapezoidal trenches between the two Pwell regions, one oblique side of the inverted trapezoidal trench contacts the corresponding Pwell region and N+ region; a gate oxide layer is deposited in the inverted trapezoidal trench; there is also a polysilicon gate region in the inverted trapezoidal trench, and the polysilicon gate region is close to the corresponding Pwell region and N+ region;

[0009] A second P+ region is provided outside the inverted trapezoidal trench, and the second P+ region wraps around the bottom edge of the inverted trapezoidal trench and the oblique edge away from the corresponding Pwell region and N+ region;

[0010] There is a Schottky contact region between the second P+ regions;

[0011] The first P+ region and the top of the N+ region have a source ohmic contact region, and the bottom of the N-type substrate has a drain ohmic contact region.

[0012] The beneficial effects of the program are as follows:

[0013] Traditional trench-gate MOSFETs have a gate oxide electric field concentration problem near the polysilicon gate corners. The gate oxide electric field can easily exceed 3MV / cm, which does not meet long-term reliability requirements. This solution can use a second P+ region to surround the gate oxide in the trench, thereby reducing the electric field at the corner to 2MV / cm.

[0014] In this solution, when the device is turned off, the depletion layer formed by the second P+ region and the Pwell region in the epitaxial growth not only protects the polysilicon gate region, but also stabilizes the potential at the N-channel, preventing gate oscillation caused by instantaneous shutdown and improving the reliability of the trench silicon carbide MOSFET. The second P+ region wraps around the bottom edge of the inverted trapezoidal trench and its oblique edges away from the corresponding Pwell and N+ regions, which can reduce leakage of the integrated SBD and reduce energy consumption.

[0015] Traditional SiC MOSFETs require an external anti-parallel Schottky diode in applications such as motor drive and traction inverters. This diode's low forward voltage drop allows for reverse freewheeling, but this increases the overall module footprint.

[0016] The SBD formed by the integrated Schottky contact area in this solution can greatly reduce the package area compared to external anti-parallel SBDs. The integrated SBD not only provides stronger reverse freewheeling capability, but also reduces electromagnetic interference caused by the loop. The instantaneous high current caused by the loop during shutdown can be freewheeled through the SBD, reducing the risk of MOSFET performance degradation.

[0017] In summary, this solution not only solves the gate oxide reliability problem of trench MOSFET, but also optimizes the freewheeling capability of the internal diode by integrating SBD. Compared with traditional trench MOSFET, the single-channel structure can reduce Cgs, thereby increasing the switching frequency of the MOSFET and reducing the input power consumption.

[0018] Furthermore, the inverted trapezoidal groove is also filled with insulating material.

[0019] A second object of the present invention is to provide a method for preparing a trench MOSFET device, comprising the following steps:

[0020] S1. Setting an N-type substrate;

[0021] S2, growing N-type epitaxy on an N-type substrate;

[0022] S3, implanting ions into the Pwell regions on both sides of the N-type epitaxial region, implanting ions into the first P+ region in the Pwell region, and implanting ions into the N+ region in the Pwell region;

[0023] S4, depositing a carbon film, and removing the carbon film after annealing;

[0024] S5, etching an inverted trapezoidal trench along a set angle; implanting ions at the bottom of the inverted trapezoidal trench and at a position away from the oblique edge of the Pwell region to form a second P+ region, annealing at a high temperature to activate the ions in the second P+ region, then removing the sacrificial oxide layer on the surface, and then depositing a gate oxide layer on the surface of the inverted trapezoidal trench;

[0025] Using a mask and photoresist, the portion of the inverted trapezoidal trench encompassed by the second P+ region is blocked, and then a layer of polysilicon gate region is deposited in the inverted trapezoidal trench; the remaining portion of the inverted trapezoidal trench is filled with an insulating layer;

[0026] S6, sputtering metal Ti or Ni on the top of the first P+ region and the N+ region to form a source ohmic contact region;

[0027] Metal Ti, Ni, W or Pt is deposited on the N-type epitaxial layer between the two inverted trapezoidal trenches to form a Schottky contact region.

[0028] Traditional MOSFET designs with integrated SBDs primarily embed the integrated SBDs between cells, but this can lead to high source leakage in the off state. This solution embeds the SBDs in two second P+ regions. When the MOSFET is off, the depletion regions formed by the two second P+ regions can effectively prevent electrons from crossing the depletion layer and reaching the source.

[0029] In summary, this solution can successfully increase the MOS switching frequency, reduce the risk of source leakage and gate degradation, and improve gate oxide reliability. The integrated SBD can greatly enhance the reverse freewheeling capability, preventing the MOSFET device from suffering from instantaneous high current when it is turned off and causing performance degradation.

[0030] Furthermore, the method further includes step S7, thinning the substrate at the bottom of the N-type substrate, and then sputtering metal Ti or Ni to form a drain ohmic contact region.

[0031] Furthermore, in step S2, the doping concentration of the N-type epitaxial layer is 5e15-2e16, and the thickness is 5-30 um.

[0032] Furthermore, in step S3, the ion implantation dose in the Pwell region is 1e12-1e14 cm -2 The injection energy is 400-1500 KeV, the junction depth is 0.6-1.8 μm, and the doping concentration range is 5e16-5e18 cm -3 ;

[0033] The ion implantation dose of the first P+ region is 1e14~1e16cm -2 The injection energy is 50-300 KeV, the junction depth is 0.1-0.8 μm, and the doping concentration range is 1e16-1e18 cm -3 ;

[0034] The ion implantation dose in the N+ region is 1e14~1e16cm -2 The injection energy is 50-300 KeV, the junction depth is 0.1-0.8 μm, and the doping concentration range is 1e16-1e18 cm -3 .

[0035] Furthermore, in step S4, the thickness of the carbon film is 0.1-2 μm, the annealing temperature is 1000° C.-2000° C., and the annealing time is 0.1-1 h.

[0036] Furthermore, in step S5, the depth of the inverted trapezoidal trench is 0.8-2 um, and the width is 1-3 um; the thickness of the gate oxide layer is 0.5-3 um; and the thickness of the polysilicon gate region is 0.5-3 um, and the width is 1-2 um.

[0037] Furthermore, in step S5, the ion implantation dose of the second P+ region is 1e14-1e16 cm -2 The injection energy is 800-2000 KeV, the junction depth is 1-2.2 μm, and the doping concentration range is 5e18-1e20 cm -3 .

[0038] Furthermore, in step S1, the doping concentration of the N-type substrate is 1e19-1e21 cm -3 , thickness is 100~500um. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of the structure of a trench MOSFET device according to an embodiment;

[0040] Figure 2 This is a schematic cross-sectional view after ion implantation in step S3 of a method for preparing a trench MOSFET device according to an embodiment;

[0041] Figure 3Schematic cross-sectional view of etching an inverted trapezoidal trench in step S5 of a method for preparing a trench MOSFET device according to an embodiment;

[0042] Figure 4 Schematic cross-sectional view of a method for preparing a trench MOSFET device in accordance with an embodiment after depositing a polysilicon gate region in step S5;

[0043] Figure 5 Schematic cross-sectional view of a method for preparing a trench MOSFET device according to an embodiment after forming a Schottky contact region and a drain ohmic contact region in steps S6 and S7. DETAILED DESCRIPTION

[0044] The following is further described in detail through specific implementation methods:

[0045] The symbols in the drawings of the specification include: N-type substrate 1, N-type epitaxial 2, second P+ region 3, Pwell region 4, N+ region 5, first P+ region 6, gate oxide layer 7, polysilicon gate region 8, source ohmic contact region 9, drain ohmic contact region 10, and Schottky contact region 11.

[0046] Example 1

[0047] A trench MOSFET device in this embodiment includes an N-type substrate 1. The N-type substrate 1 has, from bottom to top, an N-type epitaxial extension 2 and two Pwell regions 4, one located on either side of the top of the N-type epitaxial extension 2. The Pwell region 4 includes an N+ region 5 and a first P+ region 6, which are located on top of the Pwell region 4. In this embodiment, the N-type substrate 1 is a SiC substrate. The provision of the first P+ region 6 prevents conduction between the gate and the source.

[0048] Two inverted trapezoidal trenches 7 are further provided between the two Pwell regions 4. A first P+ region 6 is located at the top of the Pwell region 4, away from the inverted trapezoidal trench 7. One oblique side of the inverted trapezoidal trench 7 contacts the corresponding Pwell region 4 and N+ region 5. A gate oxide layer is deposited in the inverted trapezoidal trench 7. A polysilicon gate region 8 is further provided in the inverted trapezoidal trench 7, and the polysilicon gate region 8 is close to the corresponding Pwell region 4 and N+ region 5.

[0049] A second P+ region 3 is provided outside the inverted trapezoidal trench 7 . The second P+ region 3 wraps around the bottom edge of the inverted trapezoidal trench 7 and the oblique edges away from the corresponding Pwell region 4 and N+ region 5 .

[0050] An integrated SBD formed by a Schottky contact region 11 is provided between the two inverted trapezoidal trenches 7 . The Schottky contact region 11 is also located on the portions of the two second P+ regions 3 that wrap around the oblique sides of the inverted trapezoidal trenches 7 .

[0051] The inverted trapezoidal groove is also filled with insulating material.

[0052] A source ohmic contact region 9 is formed on the top of the first P+ region 6 and the N+ region 5 ; and a drain ohmic contact region 10 is formed on the bottom of the N-type substrate 1 .

[0053] This embodiment also provides a method for preparing a trench MOSFET device, comprising the following steps:

[0054] S1, set the doping concentration to 1e19~1e21cm -3 , an N-type substrate 1 having a thickness of 100 to 500 μm;

[0055] S2, growing an N-type epitaxial layer 2 on the N-type substrate 1, wherein the doping concentration of the N-type epitaxial layer 2 is 5e15-2e16 and the thickness is 5-30 μm;

[0056] S3, such as Figure 2 As shown, ions are implanted into the Pwell region 4 on both sides of the N-type epitaxial 2, and the ion implantation dose is 1e12~1e14cm -2 The injection energy is 400-1500 KeV, the junction depth is 0.6-1.8 μm, and the doping concentration range is 5e16-5e18 cm -3 ;

[0057] Ions are implanted into the N+ region 5 in the Pwell region 4, with an ion implantation dose of 1e14 to 1e16 cm -2 The injection energy is 50-300 KeV, the junction depth is 0.1-0.8 μm, and the doping concentration range is 1e16-1e18 cm -3 .

[0058] Ions are implanted into the first P+ region 6 in the Pwell region 4, with an ion implantation dose of 1e14-1e16 cm -2 The injection energy is 50-300 KeV, the junction depth is 0.1-0.8 μm, and the doping concentration range is 1e16-1e18 cm -3 .

[0059] S4. Deposit a carbon film on the surface of the N-type epitaxial 2 to prevent high-temperature annealing from oxidizing SiC into SiO2. The thickness of the carbon film is 0.1 to 2 μm, the annealing temperature is 1000°C-2000°C, and the annealing time is 0.1 to 1 hour. After annealing, remove the carbon film.

[0060] S5, such as Figure 3 As shown, an inverted trapezoidal groove is etched along a set angle, the depth of the inverted trapezoidal groove is 0.8 to 2 μm, and the width is 1 to 3 μm; the set angle is 60 to 80 degrees, that is, the angle between the bottom edge and the hypotenuse.

[0061] Ions are implanted at the bottom of each inverted trapezoidal trench and at the oblique edge of the inverted trapezoidal trench away from the Pwell region 4 to form a second P+ region 3. The ion implantation dose is 1e14-1e16 cm -2 The injection energy is 800-2000 KeV, the junction depth is 1-2.2 μm, and the doping concentration range is 5e18-1e20 cm -3 ;

[0062] High temperature annealing activates the ions in the second P+ region and then removes the sacrificial oxide layer on the surface.

[0063] like Figure 4 As shown, a gate oxide layer is then deposited on the surface of the inverted trapezoidal trench using ALD (atomic layer deposition) technology, with a thickness of 0.5 to 3 μm.

[0064] The inverted trapezoidal trench wrapped by the second P+ region 3 is blocked by a mask and photoresist, and then a layer of polysilicon gate region 8 is deposited in the inverted trapezoidal trench. The thickness of the polysilicon gate region 8 is 0.5-3 μm and the width is 1-2 μm.

[0065] The remaining portion of the inverted trapezoidal trench is filled with an insulating layer.

[0066] S6 , sputtering metal Ti or Ni on the top of the first P+ region 6 and the N+ region 5 to form a source ohmic contact region 9 , wherein the thickness of the source ohmic contact region 9 is 0.05-0.5 μm.

[0067] like Figure 5 As shown, metal Ti, Ni, W or Pt is deposited on the N epitaxial layer between the two inverted trapezoidal trenches to form a Schottky contact region 11. The thickness of the Schottky contact region 11 is 0.05-0.5 μm, and the annealing temperature is 1000-2000°C.

[0068] S7 , thinning the bottom of the N-type substrate 1 , and then sputtering metal Ti or Ni to form a drain ohmic contact region 10 .

[0069] Compared with existing MOSFET devices, this solution has the following advantages:

[0070] 1. Existing trench SiC MOSFETs are prone to gate oxide breakdown at the corners of the trench. However, the present invention forms a second P+ region 3 by implanting ions at the bottom and sides of the inverted trapezoidal trench, which can protect the gate oxide layer and greatly enhance the gate oxide reliability of the SiC device.

[0071] 2. Compared with the existing SiC MOSFET with integrated SBD, the SBD of the present invention is integrated between two second P+ regions 3. When withstanding high voltage, the depletion layer formed by the second P+ region 3 can effectively suppress source leakage.

[0072] 3. The existing trench SiC MOSFET has interface charges due to defects at the bottom of the trench, which easily causes threshold electrical drift. This solution effectively shields the influence of the interface charges by forming the second P+ region 3 through ion implantation.

[0073] 4. The body diode of the existing trench SiC MOSFET has low surge resistance. This solution can greatly increase the surge resistance by integrating SBD.

[0074] 5. Compared with existing trench SiC MOSFETs, this solution integrates SBDs, eliminating the need for additional parallel SBDs and significantly reducing the package area.

[0075] 6. Compared with other integrated SBDMOSFET solutions, Cgs (gate-source capacitance) is lower, the switching frequency is higher, and the input power consumption is also reduced.

[0076] The above are only embodiments of the present invention. The invention is not limited to the fields involved in this implementation case. Common knowledge such as the known specific structures and characteristics in the scheme is not described in detail here. Ordinary technicians in the relevant field are aware of all common technical knowledge in the technical field to which the invention belongs before the application date or priority date, can obtain all existing technologies in the field, and have the ability to apply conventional experimental means before that date. Ordinary technicians in the relevant field can improve and implement this scheme in combination with their own abilities under the inspiration given by this application. Some typical known structures or known methods should not become obstacles for ordinary technicians in the relevant field to implement this application. It should be pointed out that for those skilled in the art, without departing from the structure of the present invention, several variations and improvements can be made, which should also be regarded as the scope of protection of the present invention. These will not affect the effect of the implementation of the present invention and the practicality of the patent. The scope of protection required by this application shall be based on the content of its claims, and the specific implementation methods and other records in the specification can be used to interpret the content of the claims.

Claims

1. A trench MOSFET device, characterized in that: The N-type substrate comprises an N-type epitaxial layer and two Pwell regions from bottom to top, wherein the two Pwell regions are respectively located on both sides of the top of the N-type epitaxial layer; The Pwell region comprises an N+ region and a first P+ region, wherein the N+ region and the first P+ region are located on top of the Pwell region; There are two inverted trapezoidal trenches between the two Pwell regions, one oblique side of the inverted trapezoidal trench contacts the corresponding Pwell region and N+ region; a gate oxide layer is deposited in the inverted trapezoidal trench; there is also a polysilicon gate region in the inverted trapezoidal trench, and the polysilicon gate region is close to the corresponding Pwell region and N+ region; A second P+ region is provided outside the inverted trapezoidal trench, and the second P+ region wraps around the bottom edge of the inverted trapezoidal trench and the oblique edge away from the corresponding Pwell region and N+ region; There is a Schottky contact region between the second P+ regions; The first P+ region and the top of the N+ region have a source ohmic contact region, and the bottom of the N-type substrate has a drain ohmic contact region.

2. The trench MOSFET device according to claim 1, wherein: The inverted trapezoidal trench is further filled with insulating material.

3. A method for preparing a trench MOSFET device, characterized in that: The steps include: S1. Setting an N-type substrate; S2, growing N-type epitaxy on an N-type substrate; S3, implanting ions into the Pwell regions on both sides of the N-type epitaxial growth, and implanting ions into the first P+ region in the Pwell region; and implanting ions into the N+ region in the Pwell region; S4, depositing a carbon film, and removing the carbon film after annealing; S5, etching an inverted trapezoidal trench along a set angle; implanting ions at the bottom of the inverted trapezoidal trench and at a position away from the oblique edge of the Pwell region to form a second P+ region, annealing at a high temperature to activate the ions in the second P+ region, then removing the sacrificial oxide layer on the surface, and then depositing a gate oxide layer on the surface of the inverted trapezoidal trench; Using a mask and photoresist, the portion of the inverted trapezoidal trench encompassed by the second P+ region is blocked, and then a layer of polysilicon gate region is deposited in the inverted trapezoidal trench; the remaining portion of the inverted trapezoidal trench is filled with an insulating layer; S6, sputtering metal Ti or Ni on the top of the first P+ region and the N+ region to form a source ohmic contact region; Metal Ti, Ni, W or Pt is deposited on the N-type epitaxial layer between the two inverted trapezoidal trenches to form a Schottky contact region.

4. The method for preparing a trench MOSFET device according to claim 3, wherein: The method further includes step S7 , thinning the substrate at the bottom of the N-type substrate, and then sputtering metal Ti or Ni to form a drain ohmic contact region.

5. The method for preparing a trench MOSFET device according to claim 4, wherein: In the step S2, the doping concentration of the N-type epitaxial layer is 5e15-2e16, and the thickness is 5-30 um.

6. The method for preparing a trench MOSFET device according to claim 5, wherein: In step S3, the ion implantation dose in the Pwell region is 1e12-1e14 cm -2 The injection energy is 400-1500 KeV, the junction depth is 0.6-1.8 μm, and the doping concentration range is 5e16-5e18 cm -3 ; The ion implantation dose of the first P+ region is 1e14~1e16cm -2 The injection energy is 50-300 KeV, the junction depth is 0.1-0.8 μm, and the doping concentration range is 1e16-1e18 cm -3 ; The ion implantation dose in the N+ region is 1e14~1e16cm -2 The injection energy is 50-300 KeV, the junction depth is 0.1-0.8 μm, and the doping concentration range is 1e16-1e18 cm -3 .

7. The method for preparing a trench MOSFET device according to claim 6, wherein: In step S4, the thickness of the carbon film is 0.1-2 μm, the annealing temperature is 1000° C.-2000° C., and the annealing time is 0.1-1 h.

8. The method for preparing a trench MOSFET device according to claim 7, wherein: In step S5, the depth of the inverted trapezoidal trench is 0.8-2 μm, and the width is 1-3 μm; the thickness of the gate oxide layer is 0.5-3 μm; and the thickness of the polysilicon gate region is 0.5-3 μm, and the width is 1-2 μm.

9. The method for preparing a trench MOSFET device according to claim 8, wherein: In step S5, the ion implantation dose of the second P+ region is 1e14-1e16 cm -2 The injection energy is 800-2000 KeV, the junction depth is 1-2.2 μm, and the doping concentration range is 5e18-1e20 cm -3 .

10. The method for preparing a trench MOSFET device according to claim 3, wherein: In step S1, the doping concentration of the N-type substrate is 1e19-1e21 cm -3 , thickness is 100~500um.

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