SEMICONDUCTOR COMPONENT

Abstract

A semiconductor device 1 is implemented in which the design degrees of freedom of the width of a channel region 5 and the width of a JFET region 8 in a trench MOSFET with a vertical channel-fin structure are high. The semiconductor device 1 is a trench MOSFET with the vertical channel-fin structure. End parts in a lateral direction of the bottom surfaces of a plurality of trenches 2 are arranged in body regions 9. The channel region 5 is connected to the body regions 9. A channel current flows in the channel region 5 in the vertical direction. The JFET region 8 comprises a first JFET region 8A and a second JFET region 8B, which is arranged closer to one side of the channel region 5 than the first JFET region 8A, and the width of the second JFET region 8B is greater than the width of the first JFET region 8A.

Description

Technical field

[0001] The present invention relates to a semiconductor device. State of the art

[0002] A trench MOSFET with a vertical channel-fin structure has been proposed as one type of trench MOSFET.

[0003] Fig. Figure 17 shows a perspective view that schematically describes the structure of a trench MOSFET with a conventional vertical channel fin structure. It should be noted that in Fig. 17 illustrations of gate electrodes, a gate insulating film, an interlayer insulating film, source electrodes and a drain electrode have been omitted.

[0004] A in Fig. Figure 17 shows a conventional semiconductor device 1 comprising a plurality of grooves 2 which, in plan view, have a longitudinal direction in a first direction and a transverse direction in a second direction and are oriented in the second direction. It should be noted that the groove is defined by a dotted line in the front cross-section in Fig. 17 indicated trenches 2 virtually show positions corresponding to trenches 2 to describe the positional relationship between other components and trenches 2.

[0005] A source region 3 of the first conductivity type comprises a region having a fin structure that is at least partially subdivided by the plurality of trenches 2. A channel region 5 of the second conductivity type, also with a fin structure subdivided by the plurality of trenches 2, is formed on a lower surface of the source region 3 and in contact with the source region 3. A JFET region 8 of the first conductivity type is formed below the channel region 5, and body regions 9 of the second conductivity type are formed on the lateral sides of the JFET region 8. End parts in the first direction of the bottom surfaces of the plurality of trenches 2 are arranged in the body regions 9. The channel region 5 is connected to the body regions 9. A drift region 10 of the first conductivity type is formed below the JFET region 8, and a drain region 11 of the first conductivity type is formed below the drift region 10.

[0006] Furthermore, the in Fig. Figure 17 shows a conventional semiconductor device 1 comprising a gate insulating film located inside the trenches 2 and a gate electrode comprising a region located at least partially within the trenches 2, and a channel current flowing in the vertical direction (depth direction) in the channel region 5. It should be noted that the gate electrodes buried inside the trenches 2 are interconnected outside the trenches 2.

[0007] It should be noted that patent literature relating to such a technique includes, for example, patent literature 1, and, although the names and detailed structures of components differ, paragraphs 0048 to 0052, as well as the Fig. 3 and 14 to 18 of patent literature 1 describe a configuration similar to the one described above. Fig. 17 is similar. Citation list for patent literature

[0008] Patent Literature 1: JP 2004-207289 A Summary of the invention: Technical problem

[0009] This structure of the in Fig. In the conventional semiconductor device 1 shown in Figure 1, the number of channels can be increased by shortening a trench distance (pitch) and increasing a channel density, and a turn-on resistance can be reduced when viewed from the perspective of an entire semiconductor chip.

[0010] Furthermore, the JFET region 8 is formed between the body regions 9; a depletion layer extends from the body regions 9 to the JFET region 8 at the time of a short circuit and pinches off, and therefore a short-circuit withstand time is large.

[0011] Furthermore, in this structure, end sections in the first direction of the bottom surfaces of the plurality of trenches 2 are arranged in the body regions 9, and therefore three-dimensional corners of the trenches 2 are present in the body regions 9. Consequently, at the three-dimensional corner sections of the trenches 2, where the electric field is likely to be concentrated and a breakdown of the gate insulating film is likely to occur, a concentration of an electric field is released even at the point of application of a high voltage, so that it is possible to suppress a breakdown of the gate insulating film.

[0012] It is also possible to reduce the on-resistance by increasing the width of channel area 5 (the length in the first direction of channel area 5) and decreasing a channel resistance.

[0013] However, the structure of the in Fig. In the conventional semiconductor device 1 shown in Figure 1, the channel area 5 has a fin structure subdivided by the plurality of trenches 2. The end parts in the first direction of the bottom surfaces of the plurality of trenches 2 are arranged in the body areas 9. In this structure, the channel area 5 is connected to the body areas 9. The width of the channel area 5 is a width obtained by subtracting the overlap widths of the trenches 2 and the body areas 9 from the width in a longitudinal direction of the trenches 2 (the length in the first direction of the trenches 2). The width of the channel area 5 and the width of the JFET area 8 (the length in the first direction of the JFET area 8) immediately below the channel area 5 are equal.Accordingly, there is a problem that the width of channel area 5 and the width of JFET area 8 immediately below channel area 5 cannot be designed independently, and if the width of channel area 5 is increased and the on-resistance is decreased to improve performance, the width of JFET area 8 will become large, the short-circuit withstand time and breakdown voltage will decrease, and the reliability will decrease, and performance and reliability are in a trade-off relationship.

[0014] One problem to be solved by the present invention is to implement a semiconductor device in which the degree of freedom of a design of the width of a channel region and the width of a JFET region in a trench MOSFET with a vertical channel fin structure is high. Solution to the problem

[0015] To solve the above problem, a semiconductor device according to the present invention comprises: a plurality of trenches having a longitudinal direction in a first direction and a transverse direction in a second direction in a top view, and oriented in the second direction; a source region of a first conductivity type comprising a region with a fin structure that is at least partially subdivided by the plurality of trenches; a channel region of a second conductivity type that is in contact with a lower surface of the source region and has a fin structure that is subdivided by the plurality of trenches; a gate insulating film arranged inside the trenches; a gate electrode comprising a region that is at least partially arranged inside the trenches; a JFET region of the first conductivity type arranged below the channel region;and a body region of the second conductivity type, which is arranged on a lateral side of the JFET region, wherein end parts are arranged in the first direction of bottom surfaces of the plurality of trenches in the body region, the channel region is connected to the body region and a channel current flows in the channel region in a vertical direction, the JFET region comprises a first JFET region and a second JFET region which is arranged closer to a side of the channel region than the first JFET region, and a length in the first direction of the second JFET region is longer than a length in the first direction of the first JFET region.; Advantageous effects of the invention

[0016] According to the present invention, it is possible to implement a semiconductor device in which the degree of freedom of a design of the width of a channel region and the width of a JFET region in a trench MOSFET with a vertical channel fin structure is high. Brief description of the drawings [ Fig. 1] Fig. Figure 1 shows a perspective view representing a schematic configuration of a semiconductor device according to embodiment 1. [ Fig. 2] Fig. Figure 2 shows a cross-sectional view along the line X1-X1' in Fig. 1. [ Fig. 3] Fig. Figure 3 shows a cross-sectional view along the line X2-X2' in Fig. 1. [ Fig. 4] Fig. Figure 4 shows a cross-sectional view along the line Y1-Y1' in Fig. 1. [ Fig. 5] Fig. Figure 5 shows a cross-sectional view along the line X1-X1', which Fig. 2 corresponds and represents another example of the schematic configuration of the semiconductor device according to embodiment 1. [ Fig. 6] Fig. Figure 6 shows a cross-sectional view along the line X1-X1', which represents the schematic configuration of the semiconductor device according to embodiment 2, and is a diagram that schematically represents the extent of a depletion layer at a time of normal operation. [ Fig. 7] Fig. Figure 7 shows a cross-sectional view along the line X1-X1', which represents the schematic configuration of the semiconductor device according to embodiment 2, and is a diagram that schematically represents the extent of the depletion layer at a time of short circuit or at a time of blocking. [ Fig. 8] Fig. Figure 8 shows a diagram illustrating a trade-off between performance and reliability in a case of a design that focuses on the reliability of the semiconductor device according to embodiment 2. [ Fig. 9] Fig. Figure 9 shows a diagram illustrating a trade-off between performance and reliability in a case of a design that focuses on the performance of the semiconductor device according to embodiment 2. [ Fig. 10] Fig. Figure 10 shows a cross-sectional view along the line X1-X1', which represents the schematic configuration of the semiconductor device according to embodiment 3, and is a diagram that schematically represents the extent of the depletion layer at a time of short circuit or at a time of blocking. [ Fig. 11] Fig. Figure 11 shows a cross-sectional view along the line X1-X1', which represents the schematic configuration of the semiconductor device according to embodiment 4. [ Fig. 12] Fig. Figure 12 shows a diagram depicting a fault concentration profile in a depth direction along the line Z1-Z1' in Fig. 11 represents. [ Fig. 13] Fig. Figure 13 shows a cross-sectional view along the line X1-X1', which represents the schematic configuration of the semiconductor device according to embodiment 5. [ Fig. 14] Fig. Figure 14 shows a diagram describing a relationship between an integration value of a dose quantity of a JFET region and the electric field of a gate insulating film in the semiconductor device according to embodiment 6. [ Fig. 15] Fig. Figure 15 shows a cross-sectional view along the line X1-X1', which describes a manufacturing process of the semiconductor device according to embodiment 7. [ Fig. 16] Fig. Figure 16 shows a diagram describing the manufacturing process of the semiconductor device according to embodiment 7 and a defect concentration profile in the depth direction along the line Z2-Z2' in Fig. 15 represents. [ Fig. 17] Fig. Figure 17 shows a perspective view that schematically describes the structure of a trench MOSFET with a conventional vertical channel fin structure. Description of embodiments

[0017] Embodiments of the present invention are described below with reference to the drawings. In each drawing and in each embodiment, identical or similar components are assigned identical reference numerals, and any duplicate description of the same is omitted. Design 1

[0018] Fig. Figure 1 shows a perspective view representing a schematic configuration of a semiconductor device according to embodiment 1. Fig. Figure 2 shows a cross-sectional view along the line X1-X1' in Fig. 1. Fig. Figure 3 shows a cross-sectional view along the line X2-X2' in Fig. 1. Fig. Figure 4 shows a cross-sectional view along the line Y1-Y1' in Fig. 1. It should be noted that in Fig. 1 Representations of a gate electrode 7, a gate insulating film 6, an intermediate layer insulating film 14, a source electrode 12 and a drain electrode 13 have been omitted.

[0019] A semiconductor device 1 according to the present embodiment comprises a plurality of trenches 2, a source region 3 of a first conductivity type, a channel region 5 of a second conductivity type, the gate insulating film 6, the gate electrode 7, a JFET region 8 of the first conductivity type and body regions 9 of the second conductivity type.

[0020] The present embodiment describes an example in which the first conductivity type is an n-type and the second conductivity type is a p-type, but is not limited thereto, and the first conductivity type can be the p-type and the second conductivity type can be the n-type.

[0021] The multitude of trenches 2 exhibits a longitudinal direction in a first direction (a direction along the line X1-X1' in plan view). Fig. 1) and a transverse direction in a second direction (a direction along the line Y1-Y1' in Fig. 1) on and is oriented in the second direction. It should be noted that the dotted line in the cross-sections indicates the Fig. 1 and Fig. The indicated trench 2 virtually shows a position corresponding to the trenches 2 in order to describe the positional relationship between other components and the trenches 2.

[0022] The source region 3 of the first conductivity type comprises a region with a fin structure that is at least partially subdivided by the plurality of trenches 2. The channel region 5 of the second conductivity type, with the fin structure subdivided by the plurality of trenches 2, is located on a lower surface of the source region 3 and in contact with the source region 3. The JFET region 8 of the first conductivity type is located below the channel region 5, and the body regions 9 of the second conductivity type are located on the lateral sides of the JFET region 8. The channel region 5 is connected to the body regions 9. Accordingly, the width of the channel region 5 is a width obtained by subtracting an overlap width of the trenches 2 and the body regions 9 from the width in the longitudinal direction of the trench 2.

[0023] The gate insulating film 6 is located inside the grooves 2. Furthermore, at least part of a region of the gate electrode 7 is located inside the grooves 2. It should be noted that the gate electrode 7 located inside the grooves 2 is interconnected outside the grooves 2. The gate electrode 7 can, for example, be made of polysilicon.

[0024] In the semiconductor device 1 according to the present embodiment, a gate drive signal is applied to the gate electrode 7 inside the trench 2 to control the flow of a channel current in the channel region 5 of the fin structure in a vertical direction (depth direction). That is, the trench MOSFET has a vertical channel fin structure. Consequently, the number of channels can be increased by reducing the trench spacing and increasing the channel density, thus reducing the on-resistance when considering the entire semiconductor chip. Furthermore, the JFET region 8 is formed between the body regions 9. A depletion layer extends from the body regions 9 to the JFET region 8 and pinches off during a short circuit, resulting in a long short-circuit withstand time.

[0025] It should be noted that, according to the present embodiment, the semiconductor device 1 additionally comprises a first-type conductivity drift region 10 located below the JFET region 8, a first-type conductivity drain region 11 located below the drift region 10, the source electrode 12 located on the front surface, the drain electrode 13 located on a rear surface, and the interlayer insulating film 14.

[0026] The source electrode 12 is an electrode formed, for example, from a metal such as aluminum and electrically connected to the source region 3. The present embodiment is described using an example in which the source electrode 12 is electrically connected to the body regions 9, with the contact region 4 of the second conductivity type being arranged between them and having a higher, but not limited to, impurity concentration than that of the body regions 9, and the source electrode 12 can be directly connected to the body regions 9.

[0027] The drain electrode 13 is an electrode that is made, for example, of a metal such as aluminium and is electrically connected to the drain area 11.

[0028] The interlayer insulating film 14 is formed between the interconnected sections of the gate electrode 7 and the source region 3. Furthermore, the interlayer insulating film 14 is also configured to cover the upper and side parts of the interconnected sections of the gate electrode 7.

[0029] In the semiconductor device 1 according to the present embodiment, the end parts are arranged in the first direction of the bottom surfaces of the plurality of grooves 2 in the body regions 9. Consequently, three-dimensional corners of the grooves 2 in the body regions 9 are present in this structure. Accordingly, at the three-dimensional corner sections of the grooves 2, where the electric field is likely to be concentrated and a break in the gate insulating film 6 is likely to occur, a concentration of an electric field is released even when a high voltage is applied, so that it is possible to suppress a break in the gate insulating film 6.

[0030] Furthermore, in the semiconductor device 1 according to the present embodiment, the JFET region 8 comprises a first JFET region 8A and a second JFET region 8B, which is located closer to one side of the channel region 5 than the first JFET region 8A, and the width of the second JFET region 8B (the length in the first direction of the second JFET region 8B) is greater than the width of the first JFET region 8A (the length in the first direction of the first JFET region 8A). Consequently, even in a condition where the width of the channel region 5 and the width of the second JFET region 8B are equal immediately below the channel region 5, the width of the channel region 5 and the width of the first JFET region 8A are not affected by this constraint, and both can be designed independently of each other.Furthermore, the smaller the width of the JFET region 8, the more likely it is that the depletion layer, which extends from the body regions 9 to the JFET region 8 at the time of a short circuit, will close and pinch off in the JFET region 8, thus increasing the short-circuit withstand time.Accordingly, by increasing the width of channel 5 and decreasing the on-resistance, and conversely by decreasing the width of the first JFET region 8A relative to channel 5 to improve performance, sufficient short-circuit withstand time and breakdown voltage can be ensured, thus also guaranteeing reliability. Compared to a case where there is only one type of JFET region 8 width, as in conventional techniques, it is possible to increase the design's degree of freedom, improve the trade-off between performance and reliability, and make both performance and reliability compatible. Furthermore, the width of the first JFET region 8A can be changed independently of the width of channel 5 according to the required breakdown voltage, thus simplifying design modifications.

[0031] As described above, according to the present embodiment it is possible to implement the semiconductor device 1 in the trench MOSFET with the vertical channel fin structure, in which the degree of freedom of a design is high in terms of the width of the channel area 5 and the width of the JFET area 8.

[0032] It should be noted that the position in the depth direction of a lower end of the gate electrode 7, which is located inside the grooves 2, should desirablely overlap with the position in the depth direction of the second JFET region 8B. While the position in the depth direction of the lower end of the gate electrode 7 may be the same as the position in the depth direction of an upper end or the lower end of the second JFET region 8B, the position in the depth direction of the lower end of the gate electrode 7 is desirablely deeper than the position in the depth direction of the upper end of the second JFET region 8B and, taking into account manufacturing variations, is located in a shallower position than the position in the depth direction of the lower end of the second JFET region 8B.

[0033] Furthermore, the width of the first JFET region 8A is desirable to be 0.1 µm or more and the width of the second JFET region 8B is desirable to be 5 µm or less, but these widths are not limited thereto.

[0034] The impurity concentration of the first JFET region 8A can be equal to or different from the impurity concentration of the second JFET region 8B.

[0035] It should be noted that, with regard to the impurity concentration in the present embodiment, for example, the first JFET region 8A and the second JFET region 8B are represented as n, the body regions 9 and the channel region 5 are represented as p, the drift region 10 is represented as n- of a low concentration, the source region 3 and the drain region 11 are represented as n+ of a high concentration, and the contact region 4 is represented as p+ of a high concentration, but are not limited to these, as long as an operation intended by the present embodiment can be implemented. For example, the first JFET region 8A and the second JFET region 8B can be n- of a low concentration.

[0036] The semiconductor device 1 according to the present embodiment can, for example, be formed using an n+-type SiC substrate, but is not limited to this, and the Si substrate or the like can be used. Furthermore, sections not specifically described for a fabrication method in this description can be formed by a general semiconductor device fabrication method, for example by forming the n+-type drain region 11 using the n+-type SiC substrate and forming the n-type drift region 10 by epitaxial growth, and therefore a detailed description is omitted.

[0037] Fig. Figure 5 shows a cross-sectional view along the line X1-X1', which Fig. 2 corresponds and represents another example of the schematic configuration of the semiconductor device according to embodiment 1.

[0038] Although Fig. 2. While the shapes of the JFET region 8 and the body regions 9 are represented as simple shapes such as rectangular forms, the respective regions are actually produced by ion implantation or epitaxial growth, and therefore the JFET region 8 and the body regions 9 can have such a shape that boundary sections are smoothly connected without corners, as in Fig. Figure 5 shows that there may not be a defined boundary between the first JFET region 8A and the second JFET region 8B. This case is also the same as the one in Figure 5. Fig. 2, by making the width of the second JFET region 8B larger than the width of the first JFET region 8A.

[0039] The following embodiments are based on the one described in Fig. 5 described in the form shown. Design 2

[0040] Embodiment 2 is a variation of embodiment 1 and is an embodiment in which the impurity concentration of the first conductance type of the second JFET region 8B is lower than the impurity concentration of the first conductance type of the first JFET region 8A. It should be noted that, ideally, the impurity concentration of the first conductance type of the second JFET region 8B should be 1 × 10 15 cm -3 or more, and the impurity concentration of the first conductivity type of the first JFET region is 8A 1×10 20 cm- 3 or less, but are not limited to that.

[0041] Fig. Figure 6 shows a cross-sectional view along the line X1-X1', which represents the schematic configuration of the semiconductor device according to embodiment 2, and is a diagram that schematically represents the extent of a depletion layer at a time of normal operation. Fig. Figure 7 is a cross-sectional view along the line X1-X1', representing the schematic configuration of the semiconductor device according to embodiment 2, and is a diagram schematically illustrating the extent of the depletion layer at a time of short circuit or blocking. The lower the impurity concentration, the more readily the depletion layer 17 expands. It should be noted that, since the extent of the depletion layer 17 varies depending on the applied drain voltage and the impurity concentration in each region, the Fig. 6 and Fig. These 7 are merely examples.

[0042] As in Fig. As shown in Figure 6, during normal operation, while the depletion layer 17 likely expands in the second JFET region 8B with its low concentration, the width of the second JFET region 8B is wide, and therefore the resistance in the second JFET region 8B is sufficiently low. Furthermore, the first JFET region 8A, although narrow, has a high concentration, and therefore the depletion layer 17 barely extends from the body regions 9, and the resistance is sufficiently low for high power output.

[0043] As in Fig. As shown in Figure 7, since the second JFET region 8B has a low concentration at the time of a short circuit or when the circuit is off, the depletion layer 17 closes and pinches off in the second JFET region 8B to saturate the current. The depletion layer 17 pinches off in the second JFET region 8B, thus reducing the electric field of the gate insulating film 6 at the bottom surfaces of the trenches 2.

[0044] Furthermore, the structure, in which the width of the second JFET region 8B is greater than the width of the first JFET region 8A and the impurity concentration of the first conductivity type of the second JFET region 8B is lower than the impurity concentration of the first conductivity type of the first JFET region 8A, as in the present embodiment, also offers the advantage that the electrical properties of the semiconductor device 1 are hardly affected by manufacturing variations within a wafer layer or between wafers. More precisely, the width of the second JFET region 8B is wide, so that even if the width varies during manufacturing, the change in the resistance of the JFET region 8 is small. Furthermore, the depletion layer 17 extends only slightly because the first JFET region 8A has a high concentration, and therefore, even if the width varies during manufacturing, the change in the resistance of the JFET region 8 is small.Furthermore, although the first JFET region 8A requires a width such that the depletion layer 17 is not closed during normal operation, even if the width varies during manufacturing, this is because the first JFET region 8A has a high concentration, while the depletion layer 17 has a low concentration. Therefore, the effect of a variation in width is minimal. Regarding the short-circuit withstand time, the width of the second JFET region 8B, which is intended to be pinched off at the time of a short circuit, is wider, so the effect of a variation in width is minimal. Furthermore, it is possible to reduce the need for precise exposure quantity adjustment in a photographic process during manufacturing.

[0045] Next, the properties of the semiconductor device 1 according to the present embodiment will be described.

[0046] The design window of the semiconductor device 1 according to the present embodiment can be made wider than that of conventional techniques. An example is given with reference to the Fig. 8 and Fig. 9 described.

[0047] Fig. Figure 8 shows a diagram illustrating a trade-off between performance and reliability in a case of a design that focuses on the reliability of the semiconductor device according to embodiment 2. Fig. Figure 9 shows a diagram illustrating a trade-off between performance and reliability in a design focused on the performance of the semiconductor device according to embodiment 2. In the Fig. 8 and Fig. Figure 9 shows the horizontal axis as the width of the first JFET region 8A, the vertical axis on the left shows a saturation current at the time of a short circuit as an example of reliability, and the vertical axis on the right shows the resistance of JFET region 8 as an example of performance. It should be noted that other indices can be used for performance and reliability.

[0048] In Fig. 8 denotes 101 properties of a saturation current at the time of a short circuit in a conventional specification, and 102 denotes properties of a resistance of the JFET region 8 in the conventional specification. Here, the conventional specification is one in which the second JFET region 8B does not exist, and the entire JFET region 8 is formed solely by the first JFET region 8A. It should be noted that the properties vary depending on the depth and impurity concentration of the first JFET region 8A, and those in Fig. The properties shown in Figure 8 are an example. Since the saturation current at the time of a short circuit increases in the conventional specification as the width of the first JFET region 8A increases, a threshold point 103, which is equal to a threshold value of the saturation current to be allowed at the time of a short circuit, becomes an upper limit of the design width of the first JFET region 8A. The resistance of the JFET region 8 in the conventional specification increases as the width of the first JFET region 8A decreases, and increases rapidly as the width of the first JFET region 8A becomes less than a threshold point 104 at which the depletion layer 17 in the JFET region 8 pinches off at the time of normal operation. Accordingly, the threshold point 104 is the lower limit of the design width of the first JFET region 8A. The area between the upper and lower limits of the design is the design window.A design window 105 of the width of the first JFET region 8A in the conventional specification has a . Fig. 8 shown size.

[0049] In contrast, 111 refers to properties of a saturation current at the time of a short circuit in the specification, which focuses on reliability in the present embodiment, and 112 refers to properties of a resistance of the JFET area 8 in the specification, which focuses on reliability in the present embodiment.

[0050] In the specification focusing on reliability and the specification focusing on performance, according to the present embodiment, a second JFET region 8B is added, which has a wider width than the first JFET region 8A and a lower impurity concentration of the first conductivity type. An example is used and described in which the impurity concentration of the second JFET region 8B is set to a lower concentration than that of JFET region 8 in the conventional specification, and the impurity concentration of the first JFET region 8A is set to a higher concentration than that of JFET region 8 in the conventional specification, but the impurity concentrations are not limited thereto.

[0051] The specification focusing on reliability in the present embodiment is implemented, for example, in a case where the impurity concentration of the second JFET region 8B is relatively low, a case where the width of the second JFET region 8B is relatively narrow, or a case where the impurity concentration of the first JFET region 8A is close to that of the impurity concentration of the second JFET region 8B, but is not limited to these cases. It should be noted that the properties change depending on the depth and impurity concentration of the first JFET region 8A and the width, depth, and impurity concentration of the second JFET region 8B, and therefore the properties described in Fig. The 8 properties shown are an example.

[0052] Regarding the reliability index, according to the reliability-focused specification's saturation current characteristic (111), the depletion layer (17) closes and pinches off earlier in the second JFET region (8B) than in the first JFET region (8A) at a high voltage. This prevents a large current (short-circuit current) from flowing, so that even if the width of the first JFET region (8A) is the same, the saturation current at the time of a short circuit can be reduced compared to the saturation current characteristic (101) in the conventional specification. Accordingly, a threshold (113) corresponding to threshold (103) is positioned further to the right than threshold (103), and the upper limit of the design's width of the first JFET region (8A) is widened.

[0053] Regarding the performance index, according to the resistance characteristics 112 of JFET region 8 in the specification, which focuses on reliability, although there is also a region where the resistance is more or less higher than that of characteristics 102 of JFET region 8 in the conventional specification, since the second JFET region 8B has a wider width than the first JFET region 8A and the first JFET region 8A has a higher concentration than in the conventional specification, the threshold point 114 (pinch-off point), at which the depletion layer 17 in the first JFET region 8A pinches off at the time of normal operation, can be placed closer to the left than the threshold point 104 in the conventional specification.As described above, threshold point 114 moves further to the left than threshold point 104, thus widening the lower limit of the design width of the first JFET area 8A.

[0054] Accordingly, a design window 115 of the width of the first JFET area 8A in the specification which focuses on reliability according to the present embodiment can be made wider than the design window 105 of the width of the first JFET area 8A in the conventional specification.

[0055] It should be noted that, although Fig. Figure 8 provides an example where the impurity concentration of the first JFET region 8A in the reliability-focused specification is made higher than the impurity concentration of the first JFET region 8A in the conventional specification. In this case, the threshold 114 is close to the threshold 104, and therefore, although the lower limit of the design width of the first JFET region 8A does not change significantly, the saturation current at the time of a short circuit decreases compared to... Fig. 8 further, thus extending the upper limit of the design. Accordingly, it is also possible in this case to make design window 115 wider than design window 105.

[0056] The design, which focuses on performance in Fig. 9 focuses on such a specification that the resistance of the JFET area 8 is reduced and the current at the time of normal operation is lower compared to the design that focuses on reliability in Fig. 8 concentrated, increased.

[0057] In Fig. 9. The properties 101 of the saturation current at the time of a short circuit in the conventional specification and the properties 102 of the resistance of the JFET region 8 in the conventional specification are the same as those in Fig. 8.

[0058] In contrast, 121 refers to characteristics of a saturation current at the time of a short circuit in the specification, which focuses on the performance according to the present embodiment, and 122 refers to characteristics of a resistance of the JFET area 8 in the specification, which focuses on the performance according to the present embodiment.

[0059] The specification focusing on performance according to the present embodiment can, for example, be implemented by making the impurity concentration of the second JFET region 8B much higher than the impurity concentration of the second JFET region 8B in the specification focusing on reliability, while fulfilling the condition that the second JFET region 8B has a lower concentration than that of the first JFET region 8A. It should be noted that the present invention is not limited to this, and it is possible to make at least one of the impurity concentrations of the first JFET region 8A and the impurity concentration of the second JFET region 8B higher than that in the specification focusing on reliability, while fulfilling the condition that the second JFET region 8B has a lower concentration than that of the first JFET region 8A.It should be noted that the properties change depending on the depth and impurity concentration of the first JFET region 8A and the width, depth and impurity concentration of the second JFET region 8B, and therefore the values ​​in . Fig. The 9 properties shown are an example.

[0060] Regarding the power index, the resistance in feature 122 of JFET region 8 in the power-focused specification is lower than that in feature 102 of JFET region 8 in the conventional specification. Consequently, it is possible to increase the current during normal operation and improve performance. The first JFET region 8A has a high concentration and therefore does not pinch off, even when its width is reduced to a narrower width than in the conventional specification. Accordingly, the threshold point 124, at which the depletion layer 17 in the first JFET region 8A pinches off during normal operation, is located further to the left than the threshold point 104. It should be noted that the second JFET region 8B has a wide width and does not pinch off during normal operation.

[0061] Regarding the reliability index, the saturation current at the time of a short circuit in feature 121 of the saturation current at the time of a short circuit in the performance-focused specification is greater than the saturation current at the time of a short circuit in feature 101 of the conventional specification, and while a threshold point 123, corresponding to threshold point 103, moves further to the left than threshold point 103, a threshold point 124, corresponding to threshold point 104, also moves to the left, a design window 125 of the width of the first JFET range 8A in the performance-focused specification is wider than the design window 105 of the width of the first JFET range 8A in the conventional specification.Furthermore, at the time of high voltage, the depletion layer 17 is closed and pinched off in the second JFET region 8B, so that it is possible to prevent a large current (short-circuit current) from flowing, and consequently it is also possible to ensure reliability while improving performance. embodiment 3

[0062] Embodiment 3 is a variation of embodiment 1 and is an embodiment in which the impurity concentration of the first conductance type of the second JFET region 8B is higher than the impurity concentration of the first conductance type of the first JFET region 8A. It should be noted that, ideally, the impurity concentration of the first conductance type of the first JFET region 8A should be 1 × 10 15 cm -3 or more, and the impurity concentration of the first conductivity type of the second JFET region 8B 1×10 20 cm -3or less, but the concentrations of impurities are not limited to this.

[0063] Fig. Figure 10 shows a cross-sectional view along the line X1-X1', which represents the schematic configuration of the semiconductor device according to embodiment 3, and is a diagram that schematically represents the extent of the depletion layer at the time of a short circuit or at the time of blocking.

[0064] Embodiment 3 differs from embodiment 2 in that the depletion layer 17 is closed and pinches off in the first JFET region 8A and part of the drift region 10. The location where the depletion layer 17 closes and pinches off differs from that in embodiment 2; however, the width of the channel region 5 and the width of the first JFET region 8A can also be designed independently in the present embodiment. Furthermore, compared to embodiment 2, it is possible to enlarge the path where the depletion layer 17 pinches off, thus increasing the resistance in the path through which the saturation current flows and making it possible to suppress the saturation current.

[0065] Furthermore, although not shown, the second JFET area 8B also exhibits a high impurity concentration at the time of normal operation, so that the resistance becomes low. Design 4

[0066] Embodiment 4 is a variation of embodiment 1 and is an embodiment in which part of the second JFET region 8B comprises a channel punch-back region 15 which has a higher impurity concentration of the first conductivity type than that of the other part of the second JFET region 8B.

[0067] Fig. Figure 11 shows a cross-sectional view along the line X1-X1', which represents the schematic configuration of the semiconductor device according to embodiment 4. Fig. 12 is a diagram showing a fault concentration profile in the depth direction along the line Z1-Z1' in Fig. 11 represents. In Fig. Figure 12 shows the depth on the horizontal axis and the concentration of defects on the vertical axis. It should be noted that Fig. 12 is an example where the channel punch-back area 15 is provided in comparison to embodiment 2; the channel punch-back area 15 is not limited to this and can be applied to embodiment 1 or embodiment 3.

[0068] According to the present embodiment, in addition to the effects according to embodiment 1 and embodiment 3, it is possible to prevent the expansion of an area of ​​the impurity concentration of the second conductivity type of the channel area 5 through the channel punch-back area 15, as shown in Fig. 12 shown. Design 5

[0069] Embodiment 5 is a variation of embodiment 1 and is an embodiment in which the impurity concentration of the first conductivity type of the first JFET region 8A and the impurity concentration of the first conductivity type of the second JFET region 8B are different, and a JFET region with a higher impurity concentration of the first conductivity type under the first JFET region 8A and the second JFET region 8B between this JFET region and the body regions 9 comprises a region of low concentration in which the impurity concentration of the first conductivity type is lower than that of the other part, or an intrinsic region 16 that is not doped with an impurity of the first conductivity type.

[0070] Fig. Figure 13 shows a cross-sectional view along the line X1-X1', which represents the schematic configuration of the semiconductor device according to embodiment 5.

[0071] Fig. Figure 13 provides an example where, if the first JFET region 8A has a higher concentration than the second JFET region 8B, as in embodiment 2, the intrinsic region 16 is provided for the first JFET region 8A with the high concentration. It should be noted that the present invention is not limited to this, and a low-concentration region with a defect concentration of the first conductivity type that is lower than that of the other region can be provided instead of the intrinsic region 16. The low-concentration region preferably has a sufficiently low concentration.

[0072] In a case where, for example, the second JFET region 8B has a very low concentration, the first JFET region 8A must have a certain level of high concentration to reduce the resistance of JFET region 8. However, in this case, an electric field at the junction at the boundary between the first JFET region 8A and the body region 9 becomes high, and undesirable behavior such as avalanche multiplication and hot-carrier effects can occur. Therefore, by providing the intrinsic region 16 (i-layer), as in Fig. As shown in Figure 13, it is possible to reduce the maximum electric field by the following equation.

[0073] Emax (with the i-layer) / Emax (without the i-layer) = (1+d2 / Wd2) 0,5 -d / Wd applies, where Wd represents the width of a depletion layer at a pn junction and d represents the width of the i-layer.

[0074] It should be noted that in a case where the second JFET area 8B has a higher concentration than that of the first JFET area 8A, as in embodiment 3, the area of ​​low impurity concentration or the intrinsic area 16 can be provided for the second JFET area 8B with the high concentration. Design 6

[0075] Design 6 is a variation of design 1.

[0076] In the semiconductor device 1 according to the present embodiment, at least some of the parameters of the width, depth, and impurity concentration of the first conductivity type of the first JFET region 8A and the width, depth, and impurity concentration of the first conductivity type of the second JFET region 8B are set such that (1) the integration value of the dose quantity of the JFET region 8 is minimized, (2) the maximum value of the quasi-Fermi level of the JFET region 8 at the time of applying a voltage during normal operation is minimized, and (3) the depth of the depletion layer 17, which extends to the drift region 10 at the time of a short circuit, is maximized.

[0077] Fig. Figure 14 shows a diagram describing a relationship between an integration value of a dose quantity of a JFET region and the electric field of a gate insulating film in the semiconductor device according to embodiment 6. Fig. Figure 14 shows the horizontal axis as an integration value of the dose quantity of JFET region 8, and the vertical axis shows the electric field of the gate insulating film 6 at the time of turn-off. It should be noted that the integration value of the dose quantity of JFET region 8 on the horizontal axis is an integration value of the dose quantity of the entire JFET region 8, which is a combination of the first JFET region 8A and the second JFET region 8B.

[0078] According to condition (1), the electric field of the gate insulating film 6 can be reduced at the time of blocking. It should be noted that, although an example has been described where the relationship between the two is essentially linear in the domain of the design according to the present embodiment, as in Fig. 14 shows that the present invention is not limited thereto.

[0079] According to condition (2) it is possible to reduce the on-resistance of the entire JFET area 8 at the time of normal operation.

[0080] According to condition (3) it is possible to minimize the current flowing in the JFET region 8 at the time of a short circuit and to reduce the saturation current.

[0081] Furthermore, (4) the design windows 115 and 125 (see Fig. 8 and Fig. 9) the width of the first JFET area 8A is adjusted so that the design windows 115 and 125 have a predetermined width or more, or can be a maximum in combination with embodiment 2.

[0082] An example of a design procedure might involve: using at least some of the parameters of the width, depth, and impurity concentration of the first conductance type of the first JFET region 8A and the width, depth, and impurity concentration of the first conductance type of the second JFET region 8B as variables, fixing the remaining parameters, and finding a numerical value that satisfies the requirement of conditions (1) to (3) or conditions (1) to (4). It should be noted that this design can be conceived by humans or created using an artificial intelligence (AI) optimization system.

[0083] According to the present embodiment, it is possible to implement the semiconductor device that can achieve both performance and reliability. Model 7

[0084] Embodiment 7 is a variation of embodiment 1.

[0085] Fig. Figure 15 shows a cross-sectional view along X1-X1', which describes a manufacturing process of the semiconductor device according to embodiment 7. Fig. Figure 16 is a diagram describing the manufacturing process of the semiconductor device according to embodiment 7, and is a diagram showing a defect concentration profile in the depth direction along the line Z2-Z2' in Fig. 15 represents. In Fig. 16. The horizontal axis indicates depth, and the vertical axis indicates a concentration of defects.

[0086] In the present embodiment, when the body regions 9 are formed using a resist 18 as a mask, ions are implanted such that a peak position in the depth direction of the impurity concentration of the second conductivity type is located at a position in the depth direction of the first JFET region 8A in order to form such a shape that part of the body regions 9 protrudes, so that it is possible to form the body regions 9 with such a shape that the width of the second JFET region 8B is greater than the width of the first JFET region 8A by implanting ions once.

[0087] Consequently, according to the present embodiment, the semiconductor device 1 has a structure such that the tip position in the depth direction of the impurity concentration of the second conductivity type of the body regions 9 overlaps with the position in the depth direction of the first JFET region 8A.

[0088] It should be noted that the present invention is not limited to such a manufacturing process and such a structure, and the body region 9, with a shape such that the width of the second JFET region 8B is greater than the width of the first JFET region 8A, can be formed in two steps. In this case, the impurity concentration of the second conductivity type of the body region 9 may not exhibit a peak in the depth direction.

[0089] While the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in those embodiments, and various variations can be made within the scope of the technical concepts of the present invention. Furthermore, some or all of the configurations described in the embodiments can be used in combination. Reference symbol list 1 Semiconductor device 2 trenches 3 Source area 4 Contact area 5 channel area 6 Gate insulating film 7 Gate electrode 8 JFET area 8A First JFET section 8B Second JFET area 9 Body Area 10 Drift range 11 Drain area 12 Source electrode 13 Drain electrode 14 Interlayer insulating film 15-channel punch-back area 16 Intrinsic area 17th impoverishment layer 18 Resist QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2004-207289 A

[0008]

Claims

[1] Semiconductor device, comprising: a multitude of trenches which, in plan view, have a longitudinal direction in a first direction and a transverse direction in a second direction and are oriented in the second direction; a source area of ​​a first conductivity type, comprising an area with a fin structure that is at least partially subdivided by the multitude of trenches; a channel area of ​​a second conductivity type that is in contact with a lower surface of the source area and has a fin structure subdivided by the multitude of trenches; a gate insulating film that is arranged inside the trenches; a gate electrode that includes an area located at least partially inside the trenches; a JFET region of the first conductivity type, located below the channel region; and a body region of the second conductivity type, which is located on a lateral side of the JFET region, wherein End parts in the first direction of ground surfaces of the multitude of trenches in the body area are arranged, the channel area is connected to the body area and a channel current flows in the channel area in a vertical direction, the JFET area comprises a first JFET area and a second JFET area, which is located closer to one side of the channel area than the first JFET area, and a length in the first direction of the second JFET region is longer than a length in the first direction of the first JFET region. [2] Semiconductor device according to claim 1, wherein the impurity concentration of the first conductivity type of the second JFET region is lower than the impurity concentration of the first conductivity type of the first JFET region. [3] Semiconductor device according to claim 2, wherein the impurity concentration of the first conductivity type of the second JFET region is 1×10 15 cm -3 or more, and the impurity concentration of the first conductance type of the first JFET region is 1×10 20 cm -3 or less. [4] Semiconductor device according to claim 1, wherein the impurity concentration of the first conductivity type of the second JFET region is higher than the impurity concentration of the first conductivity type of the first JFET region. [5] Semiconductor device according to claim 4, wherein the impurity concentration of the first conductivity type of the first JFET region 1×10 15 cm -3 or more, and The impurity concentration of the first conductivity type of the second JFET region is 1×10 20 cm -3 or less. [6] Semiconductor device according to claim 1, wherein a tip position in a depth direction of a defect concentration of the second conductivity type of the body region overlaps with a position in the depth direction of the first JFET region. [7] Semiconductor device according to claim 1, wherein a position in a depth direction of a lower end of the gate electrode, which is arranged inside the trenches, overlaps with a position in the depth direction of the second JFET region. [8] Semiconductor device according to claim 1, wherein a part of the second JFET region comprises a channel punch-back region having a higher impurity concentration of the first conductivity type than that of another section of the second JFET region. [9] Semiconductor device according to claim 1, further comprising: a contact area provided on a front surface side of the body area and exhibiting a higher concentration of the second conductivity type of defect than that of the body area; and a source electrode that is connected to the contact area and the source area. [10] Semiconductor device according to claim 1, wherein a length in the first direction of the first JFET region is 0.1 µm or more, and a length in the first direction of the second JFET region is 5 µm or less. [11] Semiconductor device according to claim 1, wherein a defect concentration of the first conductivity type of the first JFET region and a defect concentration of the first conductivity type of the second JFET region are different, and a JFET region with a higher impurity concentration of the first conductivity type below the first JFET region and the second JFET region, a low concentration region, or an intrinsic region between the JFET region and the body region, wherein the low concentration region has a lower impurity concentration of the first conductivity type than that of any other region, or the intrinsic region is not doped with an impurity of the first conductivity type. [12] Semiconductor device according to claim 1, further comprising: a first-type conductivity drift region located below the JFET region; and a drain region of the first conductivity type, which is located below the drift region. [13] Semiconductor device according to claim 12, wherein at least some of the parameters of a length in the first direction, a depth and a defect concentration of the first conductivity type of the first JFET region and a length in the first direction, a depth and the defect concentration of the first conductivity type of the second JFET region are set such that an integration value of a dose quantity of the JFET region is minimized, a maximum value of a quasi-Fermi level of the JFET region at a time of application of a voltage at a time of normal operation is minimized, and a depth of a depletion layer extending to the drift region at a time of short circuit is maximized. [14] Semiconductor device according to claim 1, wherein The length in the first direction of the trenches is longer than the length in the first direction of the second JFET region.

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