A gallium nitride trench MOSFET device and its fabrication method

Abstract

This invention provides a gallium nitride trench MOSFET device and its fabrication method. The device includes a drain metal, a GaN substrate, and an n-type MOSFET arranged sequentially from bottom to top. ‑ A GaN drift layer, a current blocking layer, and an n-type wide bandgap conductive layer are included. An source metal is deposited on the upper surface of the n-type wide bandgap conductive layer. The upper surface of the n-type wide bandgap conductive layer is etched downwards with a penetration layer reaching the n-type wide bandgap conductive layer. ‑ - Trenches in contact with the GaN drift layer, wherein protrusions protruding from the n ‑ The gate metal on the upper surface of the GaN drift layer is provided, and a gate dielectric layer is disposed between the gate metal and the trench. By replacing the traditional p-GaN layer with a current blocking layer and an n-type wide bandgap conductive layer, the doping activation problem, substrate mismatch defect problem and Mg secondary passivation risk in the p-GaN growth process can be avoided from the root. This provides a key solution for overcoming the bottlenecks of existing technologies and improving the performance stability and mass production yield of enhancement-mode GaN MOSFETs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a gallium nitride trench MOSFET device and its fabrication method. Background Technology

[0002] With the explosive growth in demand for high-power-density, high-efficiency power electronic devices in fields such as new energy vehicles, 5G base stations, and smart grids, gallium nitride (GaN) materials are gradually replacing traditional silicon-based IGBTs as the mainstream solution due to their advantages such as high breakdown field strength (approximately 3.3 MV / cm), high electron mobility (approximately 2000 cm² / (V·s)), and fast switching speed. Among them, enhancement-mode GaN MOSFETs, due to their ability to turn off without a negative gate voltage, are in urgent demand in safety-sensitive scenarios such as automotive inverters, server power supplies, and photovoltaic inverters. However, the core structure of such devices consists of two parts: first, a MOS structure trench formed by the gate, oxide, and semiconductor, which attracts / relocates charge carriers through the field effect at the trench to form a conductive channel; second, the key device substrate and epitaxial structure, which is generally a functional region formed by three layers of npn-type semiconductors. Existing gallium nitride MOSFET products primarily achieve switching functionality through channel electronic control and gate electric field coupling. They are categorized into enhancement-mode (currently mainstream) and depletion-mode, with enhancement-mode being more widely used in safety-sensitive applications. The conduction mechanism (when the gate voltage V...) gs Threshold voltage V th In this case, the positive gate voltage attracts electrons to accumulate at the interface through the field effect of the gate dielectric layer, forming a conductive channel. In addition to the inherent advantages of the trench structure, the key focus is on the two semiconductor pn junctions formed by the p-GaN layer and the n-GaN at the bottom and top layers of the functional region. The hole concentration and resistivity of the p-GaN layer directly determine the gate's control over the channel, which is crucial for achieving the device's performance targets.

[0003] Based on this, in the current growth of gallium nitride MOSFET npn epitaxial structures, the preparation of p-GaN and its low activation rate have gradually become the core bottleneck and a huge challenge restricting device performance and yield. The difficulties stem primarily from the high-quality p-GaN epitaxial growth and the complex coupling of different elements during epitaxial growth in the npn structure, which is detailed in this patent: First, magnesium (Mg), as the most commonly used p-type dopant, has a deep acceptor level (ionization energy of approximately 250 meV), resulting in extremely low hole ionization at room temperature. Even if magnesium is successfully incorporated into the lattice, the traditional thermal annealing process (usually performed in an N2 atmosphere) is not very efficient at breaking Mg-H bonds, resulting in an overall activation efficiency of magnesium acceptors generally below 1%. Simultaneously, there is a significant lattice mismatch and thermal mismatch between the heterostructure substrate (such as silicon, sapphire, or silicon carbide) and GaN, resulting in a high dislocation density in the epitaxial layer (typically exceeding 10⁹ cm⁻¹). -2These defects compensate for acceptor doping, further reducing the effective hole concentration. Secondly, in growth processes such as metal-organic chemical vapor deposition (MOCVD), hydrogen atoms in the reaction atmosphere readily form stable Mg-H complexes with magnesium. This passivation effect causes a large number of dopants to lose their electroactivity. Current mainstream MOCVD equipment suitable for mass production of power devices (such as equipment with reaction chambers composed of graphite components) cannot utilize the memory effect of magnesium to improve doping efficiency, which exacerbates the doping challenge. Thirdly, the complex coupling of different elements during epitaxial growth in npn structures, when regrowing n... + When using a p-GaN layer, the problem of Mg re-passivation always occurs. This makes it difficult to effectively activate the p-GaN layer, making it difficult for p-GaN-based device designs to achieve the expected performance indicators, increasing process complexity and cost, and reducing product yield and reliability.

[0004] The existing methods for preparing gallium nitride MOSFET devices have the following problems: (1) The preparation of gallium nitride MOSFETs involves multiple epitaxial growths, which have high time and economic costs; (2) Due to the high acceptor ionization energy, significant self-compensation effect, and solid solubility limitation of p-GaN, p-GaN grown by epitaxy currently has the problem of low doping activation rate, and there will be a tailing effect after p-GaN epitaxy, which affects the subsequent epitaxial quality. Summary of the Invention

[0005] The purpose of this invention is to provide a gallium nitride trench MOSFET device and its fabrication method to solve the problem of low doping rate and activation rate in p-GaN, thereby improving gate control capability, enhancing device stability and electrical performance.

[0006] The first aspect of this invention provides a gallium nitride trench MOSFET device, comprising, from bottom to top, a drain metal, a GaN substrate, and an n... - - A GaN drift layer, a current blocking layer, and an n-type wide bandgap conductive layer, wherein an source metal is deposited on the upper surface of the n-type wide bandgap conductive layer, and the upper surface of the n-type wide bandgap conductive layer is etched downwards to penetrate to the n-type wide bandgap conductive layer. - -A trench in contact with the GaN drift layer, wherein protrusions protruding from n are deposited within the trench. - - Gate metal on the upper surface of the GaN drift layer, with a gate dielectric layer between the gate metal and the trench.

[0007] Furthermore, the current blocking layer is a He ion implantation layer.

[0008] Furthermore, the n-type wide bandgap conductive layer is n + -SiC thin film layer.

[0009] Furthermore, the n -- The upper surface of the GaN drift layer is provided with a step, and the current blocking layer is disposed on the step.

[0010] A second aspect of the present invention provides a method for fabricating a gallium nitride trench MOSFET device, comprising: Epitaxial growth on the surface of a GaN substrate - -GaN drift layer; In n - -Inject a current blocking layer onto the upper surface of the GaN drift layer; An n-type wide bandgap conductive layer is formed on the surface of the current blocking layer; Starting from the upper surface of the n-type wide bandgap conductive layer, an etch is made downwards to penetrate to the n-type wide bandgap conductive layer. - - Grooves in GaN drift layer contact; A gate dielectric layer is deposited on the surface of the n-type wide bandgap conductive layer and within the trench, avoiding the source metal deposition region. Deposit source metal in the source metal deposition region of the n-type wide bandgap conductive layer; Deposit gate metal within the trench; Drain metal is deposited on the lower surface of the GaN substrate.

[0011] Furthermore, the statement in n - -Implanting a current-blocking layer on the upper surface of the GaN drift layer, including: using an ion implanter on n - - He ions are implanted into the upper surface of the GaN drift layer to form the current blocking layer.

[0012] Furthermore, forming an n-type wide bandgap conductive layer on the surface of the current blocking layer includes: Using a Si carrier as a temporary substrate, a SiO2 release layer is formed on its surface. Then, a SiC thin film is deposited on the SiO2. Nitrogen- or phosphorus-containing gases are added to the reaction gas as doping sources to obtain n-banded SiC. + -A composite structure of SiC thin film layers; n of the composite structure + - The surface of the SiC thin film layer is aligned and bonded to the upper surface of the current blocking layer; After bonding is complete, the temporary substrate is released and the SiO2 release layer is etched away.

[0013] Furthermore, the etching process begins from the upper surface of the n-type wide bandgap conductive layer and extends downwards to penetrate to the n-type wide bandgap conductive layer. - -After the GaN drift layer contacts the trench, the process also includes: placing the sample in a tetramethylammonium hydroxide solution for wet processing to remove micro-masking residues and local spikes formed during the etching process and improve the morphology of the trench sidewalls / bottom.

[0014] Furthermore, the deposition of the gate dielectric layer on the surface of the n-type wide bandgap conductive layer and within the trench, avoiding the source metal deposition region, includes: Aluminum oxide is deposited on the surface of the n-type wide bandgap conductive layer and in the trenches as a gate dielectric layer; Alumina is removed from the source metal deposition area by wet etching.

[0015] Furthermore, the preparation method also includes: in the n - - The GaN drift layer is etched on both sides to form a raised step in the middle, so that the current blocking layer is placed on the step.

[0016] The beneficial effects of this plan are as follows: By replacing the traditional p-GaN layer with a current blocking layer and an n-type wide bandgap conductive layer, the doping activation problem, substrate mismatch defect problem and Mg secondary passivation risk in the p-GaN growth process can be avoided from the root. This provides a key solution for breaking through the existing technical bottlenecks and improving the performance stability and mass production yield of enhancement-mode GaN MOSFETs. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a gallium nitride trench MOSFET device. Figure 2 This is a schematic diagram of step one in the fabrication method of a gallium nitride trench MOSFET device; Figure 3 This is a schematic diagram of step two in the fabrication method of a gallium nitride trench MOSFET device; Figure 4 This is a schematic diagram of step three in the fabrication method of a gallium nitride trench MOSFET device. Figure 1 ; Figure 5 This is a schematic diagram of step three in the fabrication method of a gallium nitride trench MOSFET device. Figure 2 ; Figure 6 This is a schematic diagram of step three in the fabrication method of a gallium nitride trench MOSFET device. Figure 3 ; Figure 7 This is a schematic diagram of step four in the fabrication method of a gallium nitride trench MOSFET device. Figure 8 This is a schematic diagram of step six in the fabrication method of a gallium nitride trench MOSFET device. Figure 1 ; Figure 9 This is a schematic diagram of step six in the fabrication method of a gallium nitride trench MOSFET device. Figure 2 ; Figure 10This is a schematic diagram of step seven in the fabrication method of a gallium nitride trench MOSFET device. Figure 11 This is a schematic diagram of step eight in the fabrication method of a gallium nitride trench MOSFET device.

[0018] Explanation of reference numerals in the attached figures: 1. Drain metal; 2. GaN substrate; 3. n - - GaN drift layer; 4. Current blocking layer; 5. n-type wide bandgap conductive layer; 6. Source metal; 7. Gate metal; 8. Gate dielectric layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0020] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "front," "rear," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention; the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; furthermore, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "joined" should be interpreted broadly, for example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal communication of two components. For those skilled in the art, the specific meaning of the terms in this invention can be understood according to the specific circumstances.

[0021] See Figure 1 This embodiment also discloses a gallium nitride trench MOSFET device, including a drain metal 1, a GaN substrate 2, and an n-type substrate arranged sequentially from bottom to top. - -GaN drift layer 3, current blocking layer 4, and n-type wide bandgap conductive layer 5. An source metal 6 is deposited on the upper surface of the n-type wide bandgap conductive layer 5. The upper surface of the n-type wide bandgap conductive layer 5 is etched downwards to penetrate to the n-type wide bandgap conductive layer. - -GazN drift layer 3 contact trench, the trench contains deposits protruding from n - - Gate metal 7 on the upper surface of GaN drift layer 3, with gate dielectric layer 8 between gate metal 7 and trench, n - - The upper surface of the GaN drift layer 3 has steps for device isolation.

[0022] Specifically: Drain metal 1 is a metal layer located at the bottom of the device, used to collect charge carriers and provide external electrical connections. It uses a Ti / Al / Ni / Au stacked structure with thicknesses of 25nm / 100nm / 20nm / 60nm.

[0023] A high-concentration Si-doped GaN substrate 2 serves as the basic support structure for the device, providing the crystal growth interface. It has a thickness of 400 μm and a doping concentration of 5 × 10⁻⁶. 18 cm -3 .

[0024] n - The GaN drift layer 3 is one of the core functional regions of the device. It has a low doping concentration and is mainly used to withstand high voltages and provide channels for carrier drift. It has a thickness of 20 μm and a doping concentration of 5 × 10⁻⁶. 16 cm -3 .

[0025] CBL current blocking layer 4 is used to limit the current path and improve the breakdown voltage and switching characteristics of the device. It can be achieved through localized doping, ion implantation, or the formation of insulating regions to create a high-resistivity region in a specific area. The thickness is 400 nm, and it was created by He ion implantation.

[0026] n-type wide bandgap conductive layer 5 (n + The SiC layer is a semiconductor layer with high electron concentration and wide bandgap characteristics, used to provide a low-resistance current path. It is integrated into the device by bonding and has a thickness of 400 nm.

[0027] Source metal 6 is used to provide a pathway for charge carriers to enter the device. It uses a Ti / Al / Ni / Au stacked structure with thicknesses of 25nm / 100nm / 20nm / 60nm.

[0028] Gate metal 7 is a key electrode for forming the MOS structure. It is used to apply gate voltage to control the channel to turn on or off. It uses a Ti / Al / Ni / Au stacked structure with a thickness of 25nm / 100nm / 20nm / 60nm.

[0029] The gate dielectric layer 8 (gate oxide layer Al2O3) is an insulating material disposed between the gate metal 7 and the semiconductor material. It is used to isolate the gate metal 7 from the channel and withstand the gate voltage. It is formed by PECVD or ALD and has a thickness of 70-100nm.

[0030] n +SiC thin films, with their extremely high carrier concentration and excellent electron mobility, can effectively reduce the on-resistance of devices, thereby reducing power loss and improving the current carrying capacity. Simultaneously, SiC itself possesses excellent thermal conductivity, efficiently dissipating heat generated during device operation, effectively improving heat dissipation performance, lowering junction temperature, and thus enhancing the stability and reliability of devices under high-power, high-frequency operating conditions. Furthermore, SiC and GaN exhibit good compatibility in lattice matching and thermal expansion coefficients, facilitating the realization of high-quality heterojunction interfaces, further optimizing the overall device performance and manufacturing yield.

[0031] The core of this MOSFET device design in this patent lies in the fact that the electron blocking layer, by introducing a significant band shift, constructs an energy barrier in real space, thereby controlling electron transport. When no voltage is applied to the gate, this natural conduction band barrier acts like a dam, effectively blocking the flow of electrons from the source to the drain. Even if a large number of electrons exist in the channel layer, they cannot overcome this high-energy barrier, thus ensuring reliable turn-off of the device in the default state with extremely small current. When a sufficient forward voltage is applied to the gate, the gate electric field modulates the energy band of the channel layer, causing it to bend downwards. This is equivalent to lowering the barrier height in front of the electron blocking layer. Once the barrier is lowered sufficiently, electrons in the channel can cross or pass through this lowered barrier through thermionic emission or tunneling mechanisms, forming a current from the source to the drain, and the device then turns on.

[0032] The advantages of this invention lie in the key innovation of the device: the current blocking layer 4 formed by He ion implantation in the middle. High-energy He ions bombard the GaN lattice, generating deep-level defects. These defects can effectively trap charge carriers, thereby locally forming a high-resistance region. This CBL layer can effectively modulate the electric field distribution, preventing premature breakdown of current under high voltage and improving the device's blocking voltage capability; more importantly, it avoids many problems existing in the mass production of p-GaN layers. Simultaneously, this patent uses a bonding method to connect the n... + -SiC is used as the top contact layer. The entire process is controlled by the gate voltage and belongs to the unipolar field effect conduction mechanism. Therefore, the switching speed is fast and there is no minority carrier storage effect.

[0033] Alternative options include: the current blocking layer 4 (CBL) is not limited to He ion implantation; it can also be formed by inert ion implantation such as Ne / Ar or compensating / charge-controlled ion implantation such as F, N, and O. The desired high-resistivity controlled distribution can also be obtained through multiple implantations, different energy combinations, or partitioned mask implantation. The material used for the top conductive / contact layer is not limited to n... +-SiC, or ITO, ZnO, Ga2O3 and other n-type wide bandgap conductive layers 5, can be prepared by bonding, or by ALD, PLD, CVD or isomagnetron sputtering.

[0034] The working principle of this gallium nitride trench MOSFET device is as follows: In the off state, when the gate voltage is zero or negative, the conductive channel in the trench region does not form. At this time, the He ion implantation layer acts as a current blocking layer 4, effectively preventing current flow from the source to the drain, ensuring the device's turn-off performance. Compared to traditional p-GaN devices, this He ion implantation layer avoids the leakage current problem caused by the low activation rate of p-GaN layers, improving the device's blocking capability and reliability.

[0035] In the on state, when a positive voltage is applied to the gate metal 7, the gate electric field passes through the gate dielectric layer 8,n. + -SiC and n on the trench sidewall - -Electrons in GaN drift layer 3 (in n + (SiC region as the main component) Under the influence of the gate electric field, electrons enter the sidewall surface channel, forming a conductive channel. Electrons originate from the source metal 6, pass through the body metal layer and n in the barrier layer contact hole. + -SiC thin film layer, and then through the conductive channel formed in the trench, finally flows to the drain metal 1. + -The SiC thin film layer serves as a low-resistance conductive path, ensuring that electrons can efficiently enter the channel from the source.

[0036] The method for fabricating a gallium nitride trench MOSFET device disclosed in this embodiment includes the following steps: S1, Epitaxial growth of n on the surface of a GaN substrate - -GaN drift layer; Specifically, prepare a highly Si-doped gallium nitride substrate (thickness 400±100 μm) with a surface roughness <0.5 nm. Epitaxially grow a low-concentration Si-doped GaN (thickness 20±5 μm, epitaxial methods include but are not limited to HVPE, MOCVD, MBE, etc.) on this substrate. See [link to relevant documentation]. Figure 2 .

[0037] S2, in n - -Inject a current blocking layer onto the upper surface of the GaN drift layer; He ions were implanted into the epitaxial substrate to a depth of 400 nm (range 300-500 nm) using an ion implanter to form a current blocking layer (CBL layer). See [link to documentation]. Figure 3 .

[0038] It should be noted that the current blocking layer (CBL) is not limited to He ion implantation. It can also be formed by inert ion implantation such as Ne / Ar or by compensation / charge-controlled ion implantation such as F, N, and O. The desired high resistance control distribution can also be obtained by multiple implantations, different energy combinations, or partitioned mask implantation.

[0039] After ion implantation, the bonding surface of the GaN wafer with He implanted CBL is cleaned.

[0040] The cleaning process includes the following steps: sequentially cleaning with organic solvents to remove organic contaminants (including but not limited to acetone and isopropanol cleaning), followed by rinsing with deionized water and drying with nitrogen; acid washing to remove metal ions and oxidation residues (such as piranha solution), followed by thorough rinsing with deionized water and drying; and plasma treatment to activate the surface (including but not limited to O2 plasma, Ar plasma, or a combination thereof) to improve surface cleanliness and surface energy and enhance the reliability of subsequent bonding interfaces.

[0041] S3. An n-type wide bandgap conductive layer is generated on the surface of the current blocking layer; S31. Using a Si carrier as a temporary substrate, a 200 nm thick SiO2 release layer is formed on its surface (PECVD / ALD / sputtering are all acceptable). Then, a SiC thin film is deposited on the SiO2 (PECVD / LPCVD, etc.). A nitrogen- or phosphorus-containing gas is added to the reaction gas as a doping source, for example, N2 or NH3 is added to provide a nitrogen source, or PH3 is added to provide a phosphorus source; thereby obtaining n + -SiC composite structure. Film thickness 400 nm (300 nm-500 nm, optimal 400 nm). See also Figure 4 .

[0042] S32, change "Si / SiO2 / n" + The "-SiC" composite structure is bonded to the GaN wafer with the He-implanted CBL to complete the wafer release. Specifically, this includes: bonding the n... + - The SiC thin film surface and the GaN wafer surface to be bonded are cleaned and then activated by plasma (including but not limited to O2 plasma or Ar plasma activation).

[0043] Then “Si / SiO2 / n” + n in the "-SiC" composite structure + - The SiC thin film is aligned and bonded to the GaN wafer. Bonding methods include, but are not limited to, surface activation bonding or oxide bonding. After bonding, post-annealing is performed to enhance bonding strength and stabilize the interface. See [link to relevant documentation]. Figure 5 .

[0044] S33. After bonding is complete, release the temporary substrate and etch away the SiO2 release layer.

[0045] After bonding is complete, without damaging the SiC and GaN host materials, the SiO2 sacrificial layer is selectively etched away using a buffered oxide etchant (BOE) (etching methods include, but are not limited to, BOE, HF solution, or vapor-phase HF etching), thereby releasing and removing the SiO2 sacrificial layer. See also Figure 6 .

[0046] It should be noted that the materials used for the top conductive / contact layer are not limited to n + -SiC can also be ITO, ZnO, Ga2O3 and other n-type wide bandgap conductive layers. The preparation method is not limited to bonding, but can also be ALD, PLD, CVD or isor magnetron sputtering.

[0047] S4. Starting from the upper surface of the n-type wide bandgap conductive layer, etch a step downwards, penetrating to the contact hole of the barrier layer that contacts the current barrier layer, and penetrating to the contact hole of the n-type wide bandgap conductive layer. - - Trenches at the GaN drift layer contact; dry etching is performed using photolithography and reactive ion etching (RIE) techniques to etch trenches and steps (MESA), respectively. The MESA step is located at n... - -Outer periphery of the GaN drift layer and not penetrated n - - A stepped layer of GaN drift layer used to achieve device isolation. See also Figure 7 .

[0048] S5. Place the sample in a tetramethylammonium hydroxide solution for wet treatment to remove micro-masking residues and local spikes formed during the etching process and improve the morphology of the trench sidewalls / bottom.

[0049] After etching, the sample is placed in a tetramethylammonium hydroxide (TMAH) solution for wet treatment to remove micro-masking residues and local spikes formed during the etching process and improve the morphology of the trench sidewalls / bottom. The treatment temperature is 80–90 °C, preferably 85 °C, and the treatment time is 30–90 min, preferably 60 min.

[0050] S6. Deposit a gate dielectric layer on the surface of the n-type wide bandgap conductive layer and in the trench, avoiding the source metal deposition region. S61. After TMAH processing, deposit 70 nm (optional range 70-100 nm, preferably 70 nm) aluminum oxide as the gate dielectric layer using plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). See Figure 8 In this process, gate dielectric layers are deposited on the steps, in the trenches, and on the surface of the n-type wide bandgap conductive layer.

[0051] S62. After deposition, wet etching using photolithography and BOE solution is performed to remove the oxide from the source metal deposition area. See also Figure 9 .

[0052] S7. Deposit source metal in the source metal deposition area and deposit gate metal in the trench; Metals Ti / Al / Ni / Au (25 / 100 / 20 / 60 nm) were deposited on the front side of the sample via thermal evaporation or electron beam evaporation to form the gate (G) and source (S) metals of the GaN MOSFET, respectively. See also... Figure 10 .

[0053] S8. Deposit drain metal on the lower surface of the GaN substrate.

[0054] Metallic Ti / Al / Ni / Au (25 / 100 / 20 / 60 nm) was deposited on the back side of the sample via thermal evaporation or electron beam evaporation to form the drain metal (D) of the GaN MOSFET. See also Figure 11 .

[0055] This scheme proposes a current blocking layer (CBL) formed by He ion implantation in the drift region / channel-related region of a trench-type GaN MOSFET. High-energy He implantation introduces defects and deep-level trapping centers into the GaN lattice, reducing the local effective carrier concentration and forming a high-resistance control region. This suppresses unwanted leakage channels under turn-off and high-voltage operating conditions. The top layer of the device uses n... + -SiC serves as an n-type conductive / contact layer, achieving the top-level conductive channel through bonding. Therefore, the scope of protection of this invention should cover the material and structural characteristics of CBLs formed by He (and equivalent substitution ions or combinations of ions) implantation, their placement and distribution depth / thickness in the device, the implantation process window and mask selectivity implementation methods, and the relationship with n-type conductive / contact layers. + - Various equivalent replacement and modification schemes for blocking enhancement are achieved by combining the SiC top conductive contact layer, gate dielectric and gate metal system and terminal electric field management structure.

[0056] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A gallium nitride trench MOSFET device, characterized in that, Including, from bottom to top, the drain metal, GaN substrate, and n - - A GaN drift layer, a current blocking layer, and an n-type wide bandgap conductive layer, wherein an source metal is deposited on the upper surface of the n-type wide bandgap conductive layer, and the upper surface of the n-type wide bandgap conductive layer is etched downwards to penetrate to the n-type wide bandgap conductive layer. - -A trench in contact with the GaN drift layer, wherein protrusions protruding from n are deposited within the trench. - - Gate metal on the upper surface of the GaN drift layer, with a gate dielectric layer between the gate metal and the trench.

2. The gallium nitride trench MOSFET device according to claim 1, characterized in that, The current blocking layer is a He ion implantation layer.

3. The gallium nitride trench MOSFET device according to claim 1, characterized in that, The n-type wide bandgap conductive layer is n + -SiC thin film layer.

4. The gallium nitride trench MOSFET device according to claim 1, characterized in that, The n - - The upper surface of the GaN drift layer is provided with a step, and the current blocking layer is disposed on the step.

5. A method for fabricating a gallium nitride trench MOSFET device, characterized in that, include: Epitaxial growth on the surface of a GaN substrate - -GaN drift layer; In n - -Inject a current blocking layer onto the upper surface of the GaN drift layer; An n-type wide bandgap conductive layer is formed on the surface of the current blocking layer; Starting from the upper surface of the n-type wide bandgap conductive layer, an etch is made downwards to penetrate to the n-type wide bandgap conductive layer. - - Grooves in GaN drift layer contact; A gate dielectric layer is deposited on the surface of the n-type wide bandgap conductive layer and in the trench, avoiding the source metal deposition region; Deposit source metal in the source metal deposition region of the n-type wide bandgap conductive layer; Deposit gate metal within the trench; Drain metal is deposited on the lower surface of the GaN substrate.

6. The method for fabricating a gallium nitride trench MOSFET device according to claim 5, characterized in that, The in n - -Implanting a current-blocking layer on the upper surface of the GaN drift layer, including: using an ion implanter on n - - He ions are implanted into the upper surface of the GaN drift layer to form the current blocking layer.

7. The method for fabricating a gallium nitride trench MOSFET device according to claim 5, characterized in that, The formation of an n-type wide bandgap conductive layer on the surface of the current blocking layer includes: Using a Si carrier as a temporary substrate, a SiO2 release layer is formed on its surface. Then, a SiC thin film is deposited on the SiO2. Nitrogen- or phosphorus-containing gases are added to the reaction gas as doping sources to obtain n-banded SiC. + -A composite structure of SiC thin film layers; n of the composite structure + - The surface of the SiC thin film layer is aligned and bonded to the upper surface of the current blocking layer; After bonding is complete, the temporary substrate is released and the SiO2 release layer is etched away.

8. The method for fabricating a gallium nitride trench MOSFET device according to claim 7, characterized in that, The etching process begins from the upper surface of the n-type wide bandgap conductive layer and extends downwards to penetrate to the n-type wide bandgap conductive layer. - -After the GaN drift layer contacts the trench, the process also includes: placing the sample in a tetramethylammonium hydroxide solution for wet processing to remove micro-masking residues and local spikes formed during the etching process and improve the morphology of the trench sidewalls / bottom.

9. The method for fabricating a gallium nitride trench MOSFET device according to claim 7, characterized in that, The deposition of the gate dielectric layer on the surface of the n-type wide bandgap conductive layer and within the trench, avoiding the source metal deposition region, includes: Aluminum oxide is deposited on the surface of the n-type wide bandgap conductive layer and in the trenches as a gate dielectric layer; Alumina is removed from the source metal deposition area by wet etching.

10. The method for fabricating a gallium nitride trench MOSFET device according to claim 7, characterized in that, The preparation method further includes: in the n - - The GaN drift layer is etched on both sides to form a raised step in the middle, so that the current blocking layer is placed on the step.

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