Low-threshold-voltage Trench MOSFET device and preparation method thereof
By introducing a P+/N- structure into low threshold voltage Trench MOSFET devices, the breakdown point location is changed, solving the problems of easy breakdown and poor reliability of the devices, and achieving lower threshold voltage and longer service life.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN SHANGDINGXIN TECH CO LTD
- Filing Date
- 2026-02-06
- Publication Date
- 2026-05-01
AI Technical Summary
Existing low threshold voltage Trench MOSFET devices are prone to breakdown, have short lifespans and poor reliability, mainly due to the high electric field that the gate oxide layer withstands, leading to breakdown and increased leakage current.
Introducing a P+/N- structure into a low threshold voltage Trench MOSFET device, with the P+ region located outside the trench and extending below it, changes the breakdown point location, causing the high electric field location to break down earlier at the P+/N- structure, thereby reducing the electric field strength of the gate oxide layer and further reducing the gate oxide layer thickness at the same P-body region concentration.
It improves device lifetime and gate oxide reliability, reduces threshold voltage by 0.1-0.15V, extends device lifespan, and enhances reliability.
Smart Images
Figure CN121968649A_ABST
Abstract
Description
A low threshold voltage Trench MOSFET device and its fabrication method Technical Field
[0001] This invention relates to low-voltage trench MOSFET devices, specifically to a low-threshold-voltage trench MOSFET device and its fabrication method. Background Technology
[0002] Low-voltage trench MOSFETs are designed for low-voltage (typically <200V, with the main market segment at 12V-150V), high-current, high-frequency switching applications. The trench is the core structural feature of a low-voltage trench MOSFET. Unlike traditional planar MOSFETs, its gate is not laid flat on the chip surface but vertically etched into the silicon wafer, forming a three-dimensional trench structure. The gate oxide layer and gate polysilicon are formed within these trenches. The cell width of a low-voltage trench MOSFET is significantly reduced compared to a planar MOSFET, increasing channel density and improving chip power density.
[0003] Low threshold voltage (Vth) Trench MOSFETs are a type of low-voltage Trench MOSFET that allow direct driving at lower mains supply voltages, such as in battery protection switches in laptops. Directly driving the Trench MOSFET with the battery voltage eliminates the need for a charge pump, simplifying design and saving space and cost. A low threshold voltage (Vth) is typically achieved by reducing the boron ion doping concentration in the channel region (P-body) and thinning the gate oxide layer. Insufficient boron ion doping concentration can severely reduce the breakdown voltage, meaning the device may experience punch-through breakdown at low drain voltages, significantly sacrificing breakdown voltage. Even slight reductions may not affect the breakdown voltage but can increase the drain-source leakage current. A thinner gate oxide layer withstands a higher electric field, making it more susceptible to gate oxide breakdown, reducing device lifespan and reliability. Figure 12 is a schematic diagram of the existing Trench MOSFET structure. When the device breaks down, the breakdown point is located at the bottom of the gate oxide layer of the trench. At this time, the gate oxide layer at the bottom of the trench is subjected to a high electric field, which can easily reduce the gate oxide reliability and reduce the device lifetime and reliability. Summary of the Invention
[0004] This invention provides a low threshold voltage Trench MOSFET device and its fabrication method, which can solve the technical problems of easy breakdown, low lifespan and poor reliability of low threshold voltage Trench MOSFET devices in the prior art.
[0005] To achieve the above objectives, in one aspect, embodiments of the present invention provide a low threshold voltage Trench MOSFET device, including a gate oxide layer, a gate polysilicon, a P+ / N- structure, and a plurality of trenches; the plurality of trenches are arranged side by side on the cross-section of the low threshold voltage Trench MOSFET device; the gate oxide layer is located on the inner wall of the trenches; the gate polysilicon fills the trenches above the gate oxide layer; the P+ / N- structure is located in the lower section outside the trenches and extends below the trenches, and the P+ / N- structure is connected to the outer wall of two adjacent trenches.
[0006] Preferably, the P+ / N- structure includes a P+ region and an N-elongation region, wherein the P+ region is located above the N-elongation region; the P+ region is located between two adjacent trenches and extends downward below the two adjacent trenches, and the P+ region is connected to the outer wall of the two adjacent trenches; the N-elongation region is located below the P+ region.
[0007] Preferably, the N-elongation region is located below the P+ region and extends below all the trenches, and the N-elongation region is connected to the outer wall of the trenches to which the P+ region is not connected.
[0008] Preferably, the low threshold voltage Trench MOSFET device further includes a P-body region; the P-body region is located between two adjacent trenches and disposed on the P+ / N- structure; the P-body region is connected to the outer wall of the two trenches.
[0009] Preferably, the low threshold voltage Trench MOSFET device further includes an ILD region and multiple contact holes; the ILD region is disposed above the top of all the trenches and connected to the top of all the trenches; the contact holes penetrate the ILD region into the P-body region, and the contact holes are located between adjacent trenches; the low threshold voltage Trench MOSFET device further includes a source electrode and a drain electrode; the source electrode is disposed above the ILD region, and the drain electrode is disposed below the P+ / N- structure.
[0010] Preferably, in this low threshold voltage Trench MOSFET device, the thickness of the gate oxide layer is 15~30nm.
[0011] On the other hand, embodiments of the present invention provide a method for fabricating a low threshold voltage Trench MOSFET device, comprising: forming a P+ / N- structure on an N+ substrate; forming a trench with an upper opening by etching on the upper section of the P+ / N- structure, wherein two adjacent trenches are arranged side by side; growing a gate oxide layer on the inner wall of the trench; and depositing and etching back in the trench on the gate oxide layer to form a gate polysilicon.
[0012] Preferably, forming a P+ / N- structure on an N+ substrate includes: depositing an N- epitaxial region on the N+ substrate; performing photolithography on a section perpendicular to the N- epitaxial region, implanting boron ions, and annealing to form a P+ region; using the N- epitaxial region and the P+ region as a P+ / N- structure; forming an open-top trench in the upper section of the P+ / N- structure by etching, with two adjacent trenches arranged side by side, including: forming open-top trenches at both ends of the P+ region by etching, a portion of the bottom end of the trench passing through the upper corner of the P+ region and contacting the P+ region, and another portion of the bottom end of the trench contacting the N- epitaxial region.
[0013] Preferably, the fabrication method of the low threshold voltage Trench MOSFET device further includes: implanting boron ions into all the N-epitaxial regions above the upper plane of the P+ region and annealing to form a P-body region; photolithography at the upper end of the P-body region outside the trench, implanting arsenic ions and annealing to obtain an N+ region; depositing an ILD region above the top of the trench; etching the ILD through the ILD region and etching Si into the P-body region, and filling the space formed by the ILD and Si in the etched ILD region with metal to form a contact hole.
[0014] Preferably, the fabrication method of the low threshold voltage Trench MOSFET device further includes: sputtering metal on the upper surface of the ILD region to form a source electrode; thinning the lower surface of the N+ substrate and evaporating metal on the thinned lower surface of the N+ substrate to form a drain electrode.
[0015] The above technical solution has the following beneficial effects: In the low threshold voltage Trench MOSFET device of this embodiment, a P+ / N- structure is formed under the trench. The P+ / N- structure is located in the lower section outside the trench and extends below the trench, that is, the depth of the P+ region is higher than the depth of the trench. When the source electrode is connected to a low potential and the drain electrode is connected to a high potential, and a high voltage is applied between the drain and source, the structure corresponding to the high electric field is prone to breakdown. If the low threshold voltage Trench MOSFET device breaks down, because the electric field of the P+ / N- structure is higher than the electric field of the gate oxide layer 105, its breakdown point is located at the P+ / N- structure, and breakdown occurs earlier at the P+ / N- structure. This changes the location of the highest electric field when the low threshold voltage Trench MOSFET device breaks down, as shown at position B in Figure 10, rather than position A at the bottom of the trench. This improves the lifetime of the low threshold voltage Trench MOSFET device and the reliability of the gate oxide layer.
[0016] Compared to existing trench MOSFETs, by introducing a P+ region, the electric field borne by the gate oxide layer at the bottom of the trench is reduced. This allows for a further reduction in gate oxide layer thickness at the same P-body region concentration, resulting in a lower threshold voltage. Compared to existing technologies, the gate oxide layer thickness in this embodiment can be further reduced by 5nm, thereby further reducing the threshold voltage by 0.1-0.15V. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figures 1-9 show the structural state of a low threshold voltage Trench MOSFET device according to an embodiment of the present invention after each step in the fabrication process; Figure 10 shows a complete low threshold voltage Trench MOSFET device according to an embodiment of the present invention; Figure 11 is a flowchart of a fabrication method for a low threshold voltage Trench MOSFET device according to an embodiment of the present invention; Figure 12 is a schematic diagram of a prior art Trench MOSFET structure.
[0019] The reference numerals in the attached figures are as follows: 101, N+ substrate; 102, N- epitaxial region; 103, P+ region; 104, trench; 105, gate oxide layer; 106, gate polysilicon; 107, P-body region; 108, N+ region; 109, ILD region; 110, contact hole; 111, source electrode; 112, drain electrode. Detailed Implementation
[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0021] As shown in Figure 10, in conjunction with an embodiment of the present invention, a low threshold voltage Trench MOSFET device is provided, including a gate oxide layer 105, a gate polysilicon 106, a P+ / N- structure, and a plurality of trenches 104; the plurality of trenches 104 are arranged side by side on the cross-section of the low threshold voltage Trench MOSFET device; the gate oxide layer 105 is located on the inner wall of the trenches 104; the gate polysilicon 106 fills the trenches 104 above the gate oxide layer 105; the P+ / N- structure is located in the lower section outside the trenches 104 and extends below the trenches 104, and the P+ / N- structure is connected to the outer walls of two adjacent trenches 104.
[0022] In this embodiment of the invention, a low threshold voltage Trench MOSFET device forms a P+ / N- structure below a trench 104. The P+ / N- structure is located in the lower section outside the trench 104 and extends below it, meaning the depth of the P+ region is greater than the depth of the trench 104. Therefore, when the source electrode 111 is connected to a low potential and the drain electrode 112 is connected to a high potential, a high voltage is applied between the drain and source. The structure corresponding to the location with the high electric field is prone to breakdown. If the low threshold voltage Trench MOSFET device breaks down, because the electric field of the P+ / N- structure is higher than the electric field of the gate oxide layer 105, its breakdown point is located in the P+ / N- structure. This causes premature breakdown in the P+ / N- structure, thus changing the location of the highest electric field at the time of breakdown of the low threshold voltage Trench MOSFET device, as shown at position B in Figure 10, rather than position A at the bottom of the trench 104. This improves the lifetime of the low threshold voltage Trench MOSFET device and the reliability of the gate oxide layer 105.
[0023] Compared to existing trench MOSFETs, by introducing the P+ region 103, the electric field borne by the gate oxide layer 105 at the bottom of the trench is reduced. This allows for a further reduction in the gate oxide layer 105 thickness while maintaining the same P-body region 107 concentration, resulting in a lower threshold voltage. Compared to existing technologies, the thickness of the gate oxide layer 105 in this embodiment can be further reduced by 5 nm, thereby further reducing the threshold voltage by 0.1-0.15 V.
[0024] Preferably, the P+ / N- structure includes a P+ region 103 and an N-elongation region 102, wherein the P+ region 103 is disposed above the N-elongation region 102; the P+ region 103 is located between two adjacent trenches 104 and extends downward below the two adjacent trenches 104, and the P+ region 103 is connected to the outer wall of the two adjacent trenches 104; the N-elongation region 102 is disposed below the P+ region 103.
[0025] In the low threshold voltage Trench MOSFET device of the present invention, a P+ region 103 is added below the trench 104. The P+ region 103 is located in the lower section outside the trench 104 and extends below the trench 104, that is, the depth of the P+ region 103 is greater than the depth of the trench 104. When the source electrode 111 is connected to a low potential and the drain electrode 112 is connected to a high potential, and a high voltage is applied between the drain and the source, the structure corresponding to the location with the high electric field is prone to breakdown. If the low threshold voltage Trench MOSFET device breaks down, because the electric field of the P+ region 103 is higher than the electric field of the gate oxide layer 105, its breakdown point is located at the bottom of the P+ region 103, and the breakdown occurs prematurely at the P+ region 103. That is, the P+ / N- structure formed by the P+ region 103 and the N- epitaxial region 102 is broken down prematurely. The location of the highest electric field is optimized from the bottom of the trench 104 to the bottom of the P+ region 103; thereby changing the low threshold voltage Trench MOSFET device. The location of the highest electric field during MOSFET device breakdown is shown at position B in Figure 10, rather than position A at the bottom of trench 104. This improves the lifetime of low threshold voltage Trench MOSFET devices and the reliability of gate oxide layer 105.
[0026] Preferably, the N-epipolar region 102 is located below the P+ region 103 and extends below all the trenches 104, and the N-epipolar region 102 is connected to the outer wall of the trenches 104 to which the P+ region 103 is not connected.
[0027] The N-epipolar region 102 is connected to the outer wall of the P+ region 103, which is not connected to the trench 104. Through the P+ / N- structure formed by the N-epipolar region 102 and the P+ region 103, the depth of the P+ region 103 is greater than the depth of the trench 104, and it also extends below all the trenches 104. Therefore, when the source electrode 111 is connected to a low potential and the drain electrode 112 is connected to a high potential, and a high voltage is applied between the drain and source, if the low threshold voltage Trench MOSFET device breaks down, its breakdown point is located at the bottom of the P+ region 103. This premature breakdown at the bottom of the P+ region 103 changes the location of the highest electric field at the breakdown point of the low threshold voltage Trench MOSFET device, as shown at position B in Figure 10, rather than position A at the bottom of the trench 104. This improves the lifespan and reliability of the low threshold voltage Trench MOSFET device.
[0028] Preferably, the low threshold voltage Trench MOSFET device further includes a P-body region 107; the P-body region 107 is located between two adjacent trenches 104 and is disposed on the P+ / N- structure; the P-body region 107 is connected to the outer wall of the two trenches 104.
[0029] Because of the presence of the P+ region 103, the P-body region 107 above the P+ region 103 cannot provide an electronic current path, i.e., there is no current. Therefore, compared to the existing structure, there is no N+ region above the P-body region 107 between the trenches 104 in this embodiment of the invention. In the prior art, the current is collected from the N+ region above the P-body region 107 to the source point 111. In this embodiment of the invention, the P+ region 103 is introduced, and no current path is formed here, so there is no need to set an N+ region above the P-body region 107.
[0030] Preferably, the low threshold voltage Trench MOSFET device further includes an ILD region 109 and a plurality of contact holes 110; the ILD region 109 is disposed above the top of all the trenches 104 and connected to the top of all the trenches 104; the contact holes 110 penetrate the ILD region 109 and enter into the P-body region 107, and the contact holes 110 are located between adjacent trenches 104; the low threshold voltage Trench MOSFET device further includes a source electrode 111 and a drain electrode 112; the source electrode 111 is disposed above the ILD region 109, and the drain electrode 112 is disposed below the P+ / N- structure.
[0031] Preferably, the thickness of the gate oxide layer 105 is 15~30nm.
[0032] As shown in Figure 11, in conjunction with an embodiment of the present invention, a method for fabricating a low threshold voltage Trench MOSFET device is provided, comprising: S210: forming a P+ / N- structure on an N+ substrate 101; S220: forming a trench 104 with an upper opening by etching on the upper section of the P+ / N- structure, wherein two adjacent trenches 104 are arranged side by side; S230: growing a gate oxide layer 105 on the inner wall of the trench 104; S240: depositing and etching back within the trench 104 on the gate oxide layer 105 to form a gate polysilicon 106.
[0033] The fabrication method of the low threshold voltage Trench MOSFET device according to this invention forms a P+ / N- structure below the trench 104. The P+ / N- structure is located in the lower section outside the trench 104 and extends below it, meaning the depth of the P+ / N- structure is greater than the depth of the trench 104. Therefore, when the source electrode 111 is connected to a low potential and the drain electrode 112 is connected to a high potential, a high voltage is applied between the drain and source. The structure corresponding to the high electric field is prone to breakdown. If the low threshold voltage Trench MOSFET device breaks down, because the electric field of the P+ / N- structure is higher than the electric field of the gate oxide layer 105, its breakdown point is located in the P+ / N- structure. This causes premature breakdown of the P+ / N- structure, thus changing the location of the highest electric field at the time of breakdown of the low threshold voltage Trench MOSFET device, as shown at position B in Figure 10, rather than position A at the bottom of the trench 104. This improves the lifespan and reliability of the low threshold voltage Trench MOSFET device.
[0034] Compared to existing trench MOSFETs, by introducing the P+ region 103, the electric field borne by the gate oxide layer 105 at the bottom of the trench is reduced. This allows for a further reduction in the gate oxide layer 105 thickness while maintaining the same P-body region 107 concentration, resulting in a lower threshold voltage. Compared to existing technologies, the thickness of the gate oxide layer 105 in this embodiment can be further reduced by 5 nm, thereby further reducing the threshold voltage by 0.1-0.15 V.
[0035] Preferably, S210: forming a P+ / N- structure on the N+ substrate 101 includes: S210-1: depositing an N- epitaxial region 102 on the N+ substrate 101; S210-2: performing photolithography on a cross section perpendicular to the N- epitaxial region 102, implanting boron ions and annealing to form a P+ region 103; S210-3: using the N- epitaxial region 102 and the P+ region 103 as a P+ / N- structure; S220: forming a trench 104 with an open top end by etching on the upper section of the P+ / N- structure, with two adjacent trenches 104 arranged side by side, including: forming trenches 104 with open top ends by etching at both ends of the P+ region 103, a portion of the bottom end of the trench 104 passing through the upper corner of the P+ region 103 and contacting the P+ region 103, and another portion of the bottom end of the trench 104 contacting the N- epitaxial region 102.
[0036] In the low threshold voltage Trench MOSFET device of the present invention, a P+ region 103 is added below the trench 104. The P+ region 103 is located in the lower section outside the trench 104 and extends below the trench 104, that is, the depth of the P+ region 103 is greater than the depth of the trench 104. When the source electrode 111 is connected to a low potential and the drain electrode 112 is connected to a high potential, and a high voltage is applied between the drain and the source, the structure corresponding to the location with the high electric field is prone to breakdown. If the low threshold voltage Trench MOSFET device breaks down, because the electric field of the P+ region 103 is higher than the electric field of the gate oxide layer 105, its breakdown point is located at the bottom of the P+ region 103, and the breakdown occurs prematurely at the P+ region 103. That is, the P+ / N- structure formed by the P+ region 103 and the N- epitaxial region 102 is broken down prematurely, thus optimizing the location of the highest electric field from the bottom of the trench 104 to the bottom of the P+ region 103; thereby changing the low threshold voltage Trench MOSFET device. The location of the highest electric field during MOSFET device breakdown is shown at position B in Figure 10, rather than position A at the bottom of trench 104. This improves the lifetime and reliability of low threshold voltage Trench MOSFET devices.
[0037] Preferably, the fabrication method of the low threshold voltage Trench MOSFET device further includes: S250: implanting boron ions into all the N-epipolar regions 102 above the upper plane of the P+ region 103 and annealing to form a P-body region 107; S260: photolithography on the upper end of the P-body region 107 outside the trench 104, implanting arsenic ions and annealing to obtain an N+ region 108; S270: depositing an ILD region 109 on the top of the trench 104; the ILD is an insulating material layer.
[0038] S280: The ILD is etched through the ILD region 109 and the Si is etched into the P-body region 107, and the space formed by the ILD and Si in the etched ILD region 109 is filled with metal to form a contact hole 110.
[0039] Because of the presence of the P+ / N- structure, i.e., the presence of the P+ region 103, the P-body region 107 above the P+ region 103 cannot provide an electronic current path, i.e., there is no current.
[0040] Therefore, compared to existing structures, there is no N+ region above the P-body region 107 between the trenches 104 in this embodiment of the invention.
[0041] Preferably, the method for fabricating the low threshold voltage Trench MOSFET device further includes: S290: sputtering metal on the upper surface of the ILD region 109 to form a source electrode 111; S300: thinning the lower surface of the N+ substrate 101 and evaporating metal on the thinned lower surface of the N+ substrate 101 to form a drain electrode 112.
[0042] The technical solutions of the present invention will be described in detail below with reference to specific application examples. For technical details not described in the implementation process, please refer to the relevant descriptions above.
[0043] As shown in Figures 1-10, the sequential steps of a method for fabricating a low threshold voltage Trench MOSFET device according to an embodiment of the present invention are as follows: 1. Select an N+ substrate 101 and deposit an N- epitaxial region 102, as shown in Figure 1; 2. Photolithographically ... -2 Further boron ion annealing is performed at a temperature of 1100~1150℃ for 60~90 min; a P+ region 103 is formed in the N-epitaxial region 102, as shown in Figure 2; preferably, the implantation energy is 200 keV and the dose is 1e13cm. -2 Preferably, the annealing temperature is 1100℃ and the annealing time is 60 min; 3. The trench area is formed by photolithographic etching to form trench 104, the depth of trench 104 is 0.8~1.5μm and the width of trench is 0.25~0.45μm, as shown in Figure 3; preferably, the depth of trench 104 is 1μm and the width of trench 104 is 0.35μm; the depth of P+ region 103 is at least 0.2μm greater than the depth of trench 104.
[0044] 4. Grow a gate oxide layer 105 with a thickness of 15-30 nm, as shown in Figure 4; preferably, the thickness of the gate oxide layer 105 is 20 nm; 5. Deposit and etch back the gate polysilicon 106 to form the gate polysilicon 106, as shown in Figure 5; 6. Construct the P-body region 107 by boron ion implantation, with a boron ion implantation energy of 100 keV-150 keV and a dose of 8e12-1.2e13 cm⁻¹. -2 Further boron ion annealing is performed at a temperature of 1050~1150℃ for 30~60 min to form a P-body region 107, as shown in Figure 6; wherein, the P+ region 103 is located below the P-body region 107 between the trenches 104; preferably, the implantation energy is 120 keV and the dose is 8e12cm. -2 Preferably, the annealing temperature is 1050℃ and the annealing time is 60 min; 7. Source N+ photolithography, arsenic ion implantation and annealing, the implantation energy is 60 keV and the dose is 5e15cm. -2 Further arsenic ion annealing is performed at a temperature of 950℃ for 30 seconds to form N+ region 108, as shown in Figure 7; 8. ILD deposition is performed to form ILD region 109, as shown in Figure 8; 9. Contact hole photolithography is performed to etch Si and fill it with metal to form contact hole 110, as shown in Figure 9; 10. Front metal is sputtered to form source electrode 111; back side thinning and back side metal evaporation are performed to form drain electrode 112, as shown in Figure 10.
[0045] The beneficial technical effects achieved by the embodiments of the present invention are as follows: In the low threshold voltage Trench MOSFET device of the present invention, a P+ region 103 is added below the trench 104. The P+ region 103 is located in the lower section outside the trench 104 and extends below the trench 104, that is, the depth of the P+ region 103 is greater than the depth of the trench 104. When the source electrode 111 is connected to a low potential and the drain electrode 112 is connected to a high potential, and a high voltage is applied between the drain and the source, the structure corresponding to the location with a high electric field is prone to breakdown. If the low threshold voltage Trench MOSFET device breaks down, because the electric field of the P+ region 103 is higher than the electric field of the gate oxide layer 105, its breakdown point is located at the bottom of the P+ region 103, and the breakdown occurs prematurely at the P+ region 103. That is, the P+ / N- structure formed by the P+ region 103 and the N- epitaxial region 102 is broken down prematurely, optimizing the location of the highest electric field from the bottom of the trench 104 to the bottom of the P+ region 103; thereby changing the low threshold voltage Trench MOSFET device. The location of the highest electric field during MOSFET device breakdown is shown at position B in Figure 10, rather than position A at the bottom of trench 104. This improves the lifetime of low threshold voltage Trench MOSFET devices and the reliability of gate oxide layer 105.
[0046] Compared to existing trench MOSFETs, by introducing the P+ region 103, the electric field borne by the gate oxide layer 105 at the bottom of the trench is reduced. This allows for a further reduction in the gate oxide layer 105 thickness while maintaining the same P-body region 107 concentration, resulting in a lower threshold voltage. Compared to existing technologies, the thickness of the gate oxide layer 105 in this embodiment can be further reduced by 5 nm, thereby further reducing the threshold voltage by 0.1-0.15 V.
[0047] Since the P+ region 103 exists, the P-body region 107 above the P+ region 103 cannot provide an electronic current path, that is, there is no current. Therefore, compared with the existing structure, there is no N+ region above the P-body region 107 between the trenches 104 in this embodiment of the invention.
[0048] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to the specific order or hierarchy described.
[0049] In the above detailed description, various features are combined together in a single embodiment to simplify this disclosure. This approach to disclosure should not be construed as reflecting an intention that embodiments of the claimed subject matter require more features than are explicitly stated in each claim. Rather, as reflected in the appended claims, the invention is presented with fewer features than all of the features of the single disclosed embodiment. Therefore, the appended claims are hereby explicitly incorporated into the detailed description, wherein each claim stands alone as a preferred embodiment of the invention.
[0050] The disclosed embodiments have been described above to enable any person skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments without departing from the spirit and scope of this disclosure. Therefore, this disclosure is not limited to the embodiments given herein, but is consistent with the broadest scope of the principles and novel features disclosed in this application.
[0051] The foregoing description includes examples of one or more embodiments. It is certainly impossible to describe all possible combinations of components or methods in order to describe the above embodiments, but those skilled in the art will recognize that further combinations and arrangements of the various embodiments are possible. Therefore, the embodiments described herein are intended to cover all such changes, modifications, and variations that fall within the scope of the appended claims. Furthermore, the term "comprising" as used in the specification or claims is interpreted in a manner similar to the term "including," as interpreted when used as a conjunction in the claims. Additionally, the use of any term "or" in the specification of the claims is intended to mean "non-exclusive or."
[0052] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A low threshold voltage Trench MOSFET device, characterized in that, The device includes a gate oxide layer (105), a gate polysilicon layer (106), a P+ / N- structure, and a plurality of trenches (104); the plurality of trenches (104) are arranged side by side on the cross section of the low threshold voltage Trench MOSFET device; the gate oxide layer (105) is located on the inner wall of the trenches (104); the gate polysilicon layer (106) fills the trenches (104) above the gate oxide layer (105); the P+ / N- structure is located outside the lower section of the trenches (104) and extends below the trenches (104), and the P+ / N- structure is connected to the outer wall of two adjacent trenches (104).
2. The low threshold voltage Trench MOSFET device according to claim 1, characterized in that, The P+ / N- structure includes a P+ region (103) and an N-elongation region (102). The P+ region (103) is located above the N-elongation region (102). The P+ region (103) is located between two adjacent trenches (104) and extends downward below the two adjacent trenches (104). The P+ region (103) is connected to the outer wall of the two adjacent trenches (104). The N-elongation region (102) is located below the P+ region (103).
3. The low threshold voltage Trench MOSFET device according to claim 2, characterized in that, The N-elongation region (102) is located below the P+ region (103) and extends below all the trenches (104), and the N-elongation region (102) is connected to the outer wall of the trenches (104) to which the P+ region (103) is not connected.
4. The low threshold voltage Trench MOSFET device according to claim 1, characterized in that, It also includes a P-body region (107); the P-body region (107) is located between two adjacent grooves (104) and is disposed on the P+ / N- structure; the P-body region (107) is connected to the outer wall of the two grooves (104).
5. The low threshold voltage Trench MOSFET device according to claim 4, characterized in that, It also includes an ILD region (109) and multiple contact holes (110); the ILD region (109) is located above the top of all the trenches (104) and connected to the top of all the trenches (104); the contact holes (110) penetrate the ILD region (109) and enter into the P-body region (107), and the contact holes (110) are located between adjacent trenches (104); the low threshold voltage Trench MOSFET device also includes a source electrode (111) and a drain electrode (112); the source electrode (111) is located above the ILD region (109), and the drain electrode (112) is located below the P+ / N- structure.
6. The low threshold voltage Trench MOSFET device according to claim 4, characterized in that, The thickness of the gate oxide layer (105) is 15~30nm.
7. A method for fabricating a low threshold voltage Trench MOSFET device, characterized in that, include: A P+ / N- structure is formed on an N+ substrate (101); A trench (104) with an upper opening is formed by etching in the upper section of the P+ / N- structure, and two adjacent trenches (104) are arranged side by side; a gate oxide layer (105) is grown on the inner wall of the trench (104); a gate polysilicon (106) is formed by deposition and etch-back in the trench (104) on the gate oxide layer (105).
8. The method for fabricating a low threshold voltage Trench MOSFET device according to claim 7, characterized in that, Forming a P+ / N- structure on an N+ substrate (101) includes: depositing an N- epitaxial region (102) on the N+ substrate (101); performing photolithography on a cross section perpendicular to the N- epitaxial region (102), implanting boron ions and annealing to form a P+ region (103); using the N- epitaxial region (102) and the P+ region (103) as a P+ / N- structure; forming a trench (104) with an upper opening by etching on the upper section of the P+ / N- structure, with two adjacent trenches (104) arranged side by side, including: forming trenches (104) with an upper opening at both ends of the P+ region (103) by etching, a portion of the bottom end of the trench (104) passing through the upper corner of the P+ region (103) and contacting the P+ region (103), and another portion of the bottom end of the trench (104) contacting the N- epitaxial region (102).
9. The method for fabricating a low threshold voltage Trench MOSFET device according to claim 8, characterized in that, Also includes: Boron ions are implanted and annealed in all the N-epipolar regions (102) above the upper plane of the P+ region (103) to form a P-body region (107); arsenic ions are implanted and annealed at the upper end of the P-body region (107) outside the trench (104) to obtain an N+ region (108); an ILD region (109) is obtained by deposition above the top of the trench (104); the ILD of the ILD region (109) is etched through the ILD region (109) and Si is etched into the P-body region (107), and the space formed by the ILD and Si of the etched ILD region (109) is filled with metal to form a contact hole (110).
10. The method for fabricating a low threshold voltage Trench MOSFET device according to claim 9, characterized in that, Also includes: Metal is sputtered onto the upper surface of the ILD region (109) to form a source electrode (111). The lower surface of the N+ substrate (101) is thinned, and metal is evaporated on the thinned lower surface of the N+ substrate (101) to form a drain electrode (112).